Flexible cache allocation technology priority-based cache line eviction algorithm

Abstract

To provide a system equipped with a cache line eviction algorithm.SOLUTION: A system includes a last level cache (LLC) and a cache control circuit, the LLC having multiple ways, each allocated to one of multiple priorities, each priority having specified minimum and maximum ways to occupy. The cache control circuit is configured to store an incoming CL having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technical field of the present invention relates generally to computer processor architecture, and more particularly to an improved flexible cache allocation technique (Flex-CAT) priority-based eviction algorithm for cache partitioning. [Background technology]

[0002] Multitenancy has been identified as a solution that achieves high system utilization and reduced costs through space sharing. Multitenancy is possible in cloud environments through virtualization, where each core hosts a virtual machine (VM) that runs user applications. New computing paradigms, such as Function as a Service (FaaS), utilize container-based virtualization to run many individual lightweight functions within containers. In a typical multitenant environment, high-priority (HP) jobs coexist with low-priority (LP) jobs on the same computing resource, such as a multicore processor or core. HP jobs are latency-sensitive, while LP jobs often have loose deadlines. Some HP jobs require deterministic performance in addition to low latency. Users who submit jobs enter into quality-of-service (QoS) service-level agreements (SLAs) with cloud service providers (CSPs) and accordingly adhere to these with guarantees of latency or performance determinism. CSPs must meet the SLAs by limiting performance fluctuations or degradation of QoS of HP jobs caused by other colocated LP jobs. [Brief explanation of the drawings]

[0003] The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like reference symbols refer to similar elements and in which:

[0004] [Figure 1]FIG. 2 is a block diagram illustrating processing components that execute instructions according to some embodiments.

[0005] [Figure 2] FIG. 1 is a block diagram illustrating a system including a multi-core system running virtual machines, according to some embodiments.

[0006] [Figure 3] 1 illustrates an exemplary cache partitioning scheme according to some embodiments.

[0007] [Figure 4] FIG. 1 is a block diagram illustrating cache line eviction according to some embodiments.

[0008] [Figure 5] FIG. 1 is a block flow diagram illustrating processing performed by a cache control circuit in response to a cache fill request, according to some embodiments.

[0009] [Figure 6] FIG. 1 is a flow diagram illustrating cache control circuitry for processing cache fill requests according to some embodiments.

[0010] 7A and 7B are block diagrams illustrating a generic vector friendly instruction format and its instruction templates according to some embodiments of the present invention.

[0011] [Figure 7A] FIG. 1 is a block diagram illustrating a generic vector friendly instruction format and its class A instruction templates according to some embodiments of the present invention.

[0012] [Figure 7B] FIG. 1 is a block diagram illustrating a generic vector friendly instruction format and its class B instruction templates according to some embodiments of the present invention.

[0013] [Figure 8A] FIG. 1 is a block diagram illustrating an exemplary vector-specific instruction format according to some embodiments of the present invention.

[0014] [Figure 8B] FIG. 1 is a block diagram illustrating the fields that make up the full opcode field of a vector-specific instruction format, according to one embodiment.

[0015] [Figure 8C] FIG. 1 is a block diagram illustrating the fields that make up the register index field of a vector-specific instruction format, according to one embodiment.

[0016] [Figure 8D] FIG. 1 is a block diagram illustrating the fields that make up the extended operation field of a vector-specific instruction format, according to one embodiment.

[0017] [Figure 9] FIG. 2 is a block diagram of a register architecture, according to one embodiment.

[0018] [Figure 10A] 1A-1C are block diagrams illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, according to some embodiments.

[0019] [Figure 10B] 1 is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core included in a processor according to some embodiments.

[0020] 11A and 11B are block diagrams of a more specific exemplary in-order core architecture, in which the core is one of several logic blocks (including other cores of the same and / or different types) within a chip.

[0021] [Figure 11A] FIG. 1 is a block diagram of a single processor core with a connection to an on-die interconnect network and with a local subset of a level 2 (L2) cache, according to some embodiments.

[0022] [Figure 11B] FIG. 11B is an expanded view of a portion of the processor core of FIG. 11A, according to some embodiments.

[0023] [Figure 12] FIG. 1 is a block diagram of a processor, according to some embodiments, which may have two or more cores, may have an integrated memory controller, and may have integrated graphics.

[0024] 13 through 16 are block diagrams of exemplary computer architectures.

[0025] [Figure 13] FIG. 1 is a block diagram of a system according to some embodiments.

[0026] [Figure 14] FIG. 1 is a block diagram of a first, more specific, exemplary system according to some embodiments.

[0027] [Figure 15] FIG. 2 is a block diagram of a second, more specific, exemplary system according to some embodiments.

[0028] [Figure 16] FIG. 1 is a block diagram of a system on a chip (SoC) according to some embodiments.

[0029] [Figure 17] 1 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0030] In the following description, numerous specific details are set forth. However, it will be understood that some embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail in order not to obscure an understanding of this description.

[0031] The use of phrases such as "one embodiment," "an embodiment," "an example embodiment," and the like in this specification indicates that a feature, structure, or characteristic may be included in the described embodiment, but not all embodiments necessarily include that feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a feature, structure, or characteristic is described with respect to one embodiment, it indicates that it is obvious to one skilled in the art that the feature, structure, or characteristic also affects other embodiments where explicitly stated.

[0032] As mentioned above, cloud service providers (CSPs) need to meet their service level agreements (SLAs) by limiting performance fluctuations or degradation of the quality of service (QoS) of high-performance (HP) jobs caused by other low-performing co-located LP jobs. Specifically, the disclosed embodiments describe Flexible Cache Allocation Technology (Flex-CAT), an architectural solution to limit HP last-level cache (LLC) evictions by LP jobs. The Flex-CAT approach dynamically determines the optimal number of ways for each cache set depending on the utilization of cache lines (CLs) within each set according to various priorities. The bounds (minimum and maximum number of ways) are specified in model-specific registers (MSRs) that provide hints for selecting eviction victims during LLC cache fills.

[0033] Flex-CAT has the advantage of providing an easily configurable yet flexible interface for specifying cache partitions. Flex-CAT supports a dynamic cache partitioning scheme with priority-based LLC eviction decisions based on real-time data to manage partitions at a fine granularity. Flex-CAT helps meet cloud service providers' requirements for performance determinism and architectural features that meet QoS guarantees, such as separation of high- and low-performing jobs. Low-performing jobs are sometimes referred to herein as "noisy neighbors."

[0034] Lesser alternative approaches have attempted to resolve the imbalance between HP and LP jobs sharing resources by assigning distinct sets of ways to cores and restricting HP and LP jobs to specific cores. However, such approaches have several problems. For example, the mechanism lacks a concept of priority. Some of these approaches isolate HP jobs from LP jobs by assigning unique sets of ways to all cache sets and HP cores, but these unique resources are unavailable to LP workloads when not being utilized by HP workloads. Furthermore, some of these approaches saturate certain limited cache sets (e.g., x sets) more than others (e.g., Nx sets, where N is the total number of cache sets). Due to the saturation of these x sets, equal way allocation to HP jobs can lead to over-provisioning across the Nx sets and under-utilization of these Nx sets. Furthermore, allocating fewer than the maximum number of ways to a core results in poor associativity, increased conflict misses, and reduced performance. Static allocation approaches that assign fixed cache ways to cores do not allow for flexibility during cache eviction and fill.

[0035] However, the disclosed embodiments provide a flexible interface for dynamically specifying priorities and cache partitions. Priorities are listed in ascending order. Flexible cache partitions can be specified with a minimum and maximum number of ways per priority. Unlike some other approaches, Flex-CAT does not require software to specify the exact cache ways allocated to each partition.

[0036] Such dynamic priority and cache partitioning specifications are supported by Class of Service (CLOS) registers, which hold the following values for each CLOS: CLOS priority P:Pn bit Maximum number of ways occupied by priority P: mxwn bits Minimum number of ways occupied by priority P: mnwn bits

[0037] For example, if the maximum number of priorities is 4, then Pn = log(4) = 2. If the maximum number of ways is 16, then mxwn = mnwn = log(16) = 4. [Table 1]

[0038] According to the embodiment disclosed herein, the requester is the owner of the CL to be filled in the LLC. Let PF be the priority of the requester. In the system, PL is the lowest priority and PH is the highest priority. Let loc be the final storage location for the requester's CL determined by Flex-CAT. The occupancy count O[PF] of the requester is the number of CLs the requester occupies in the indexed cache set.

[0039] Flex-CAT is a new eviction algorithm that performs priority-based cache partitioning at the cache set granularity. LP CLs are prioritized for eviction as long as the requester's occupancy does not exceed the maximum way allocation (mxw). Once the requester's occupancy reaches the maximum allocation, Flex-CAT prioritizes self-eviction over other-priority eviction to stay within the partition boundary. In the limited circumstances where these previous two steps fail to find a victim, Flex-CAT selects HP CLs for eviction to make room for subsequent cache fills. The basic concept of Flex-CAT is shown in Figure 4.

[0040] The detailed algorithm is illustrated in the flowcharts of Figures 4-6 and described below: During an LLC fill, the disclosed embodiments use a conventional hashing algorithm to determine the cache set index for the requestor's subsequent cache line.

[0041] After indexing into the appropriate cache set, Flex-CAT first searches for invalid LLC entries within the indexed cache set. If the cache set is full and no invalid storage location is found, Flex-CAT determines the victim CL that needs to be evicted from the LLC. This ensures that Flex-CAT is enabled only for saturated cache sets and that no unnecessary workload is imposed in the absence of contention. Flex-CAT scans the entire cache set and determines the index of the LRU CL, its elapsed time, and the occupancy count for each priority of the system.

[0042] If the claimant's occupancy count is less than the minimum allocation (O[PF] < PF[mnw]), Flex-CAT preferentially evicts the LP LRU CL to increase its occupancy count. If the claimant's occupancy count reaches the minimum allocation and is less than the maximum allocation (PF[mnw] ≤ O[PF] < PF[mxw]), Flex-CAT searches for the LRU victim among the priorities and further adds that LRU CL to the candidate list. When the claimant's occupancy count reaches the maximum allocation, Flex-CAT ignores the LP LRU candidates and selects the claimant's LRU (LRUF) as the victim CL, ensuring that the claimant's occupancy count never exceeds the upper limit (PF[mxw]). If no victim is found in the previous stage (if all lines belong to owners of higher priorities), Flex-CAT performs a HP eviction.

[0043] Figures 5 and 6 and the flowchart described below show the steps that Flex-CAT goes through after indexing into the appropriate cache set.

[0044] 1 is a block diagram illustrating processing components for executing instructions, according to some embodiments. As shown, storage 101 stores instruction(s) to be executed 103. As described further below, in some embodiments, system 100 (also referred to herein as a "computing system") is a SIMD processor that simultaneously processes multiple elements of packed data vectors, including matrices.

[0045] In operation, instruction(s) 103 are fetched from storage 101 by fetch circuitry 105. The instructions are decoded by decode circuitry 109. Decode circuitry 109 decodes the fetched instructions 107 into one or more operations. In some embodiments, this decoding includes generating multiple micro-operations that are executed by execution circuitry (such as execution circuitry 117). Decode circuitry 109 also decodes instruction suffixes and prefixes (if used).

[0046] In some embodiments, the register renaming, register allocation, and / or scheduling circuitry 113 provides functionality for one or more of the following: 1) renaming logical operand values to physical operand values (e.g., register alias tables in some embodiments), 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions 111 from an instruction pool for execution on the execution circuitry 117 (e.g., using reservation stations in some embodiments).

[0047] Registers (register file) and / or memory 115 store data as operands for instructions 111 executed by execution circuitry 117. Exemplary register types include write mask registers, packed data registers, general purpose registers, and floating point registers, as further described and shown below with reference to at least FIG.

[0048] In some embodiments, writeback circuitry 119 commits instruction execution results. Execution circuitry 117 and system 100 are further illustrated in and described with reference to Figures 2-4, 10A, 10B, 11A, and 11B.

[0049] FIG. 2 is a block diagram illustrating a system including a multi-core processor running virtual machines, according to some embodiments. As shown, computing system 200 includes multi-core processor 202 including core 0 206A, core 1 206B, ... through core N 206N that share a last-level cache LLC 204. Together, the resources of processor 202 can function as part of a cloud service provider's (CSP's) computing platform to provide network services to one or more clients. For example, as shown, cores 0, 1, through N support VM0 210A, VM1 210B, ... through VMN 210N. VM0 210A supports VNF application 0 212A (a virtual network function application) and guest OS0 214A. Similarly, VM1 210B supports VNF application 1 212B and guest OS1 214B. Similarly, the VMN 210N supports a VNF application 212N and a guest OS N 214N. In operation, the virtual machines are launched and managed using the hypervisor / VMM 208. An operating system 214 may be invoked to further manage the system.

[0050] In some embodiments, cache control circuitry 201 cooperates with hypervisor / VMM 208 to implement the cache partitioning scheme described herein.

[0051] In some embodiments, cache monitor circuitry 203 maintains statistics and heuristics regarding cache access requests, such as the percentage of low priority cache fill requests that result in the eviction of high priority cache lines. Cache monitor circuitry 203 is optional, as indicated by the dashed box, as it could alternatively be incorporated into processor 202. In some examples, computing system 200 is a standalone computing platform, while in other examples it is coupled to another computing platform via a network (not shown).

[0052] In some embodiments, computing system 200 is a node in a data center and supports VMs that individually run one or more VNF applications, including, for example, a cloud service provider, a database network service, a website hosting service, a routing network service, an email service, a firewall service, a domain name service (DNS), a caching service, a network address translation (NAT) service, or a virus scanning network service. VMs 210A-210N in computing system 200 may be managed or controlled by a hypervisor or virtual machine manager (VMM), such as hypervisor / VMM 208. In other embodiments, computing system 200 may be configured as a more traditional server with the various computing resources described above housed in the same physical enclosure, chassis, or container.

[0053] In some embodiments, a virtual machine is a software computer that runs an operating system and applications, similar to a physical computer. Some virtual machines are configured by a set of configuration files and are backed by the physical resources of a host. A hypervisor or VMM is computer software, firmware, or hardware that creates and manages virtual machines. A computer on which a hypervisor runs one or more virtual machines is referred to as a host machine, and each virtual machine is referred to as a guest machine. The hypervisor or VMM presents guest operating systems through a virtual operating platform and manages their execution. Multiple instances of different operating systems may share virtualized hardware resources. For example, Linux, Windows, and macOS instances can all run on a single physical processor with multiple cores.

[0054] In some examples, as shown in FIG. 2, at least a portion of the computing resources for computing system 200 may include processing elements, such as CPUs / cores 206A, 206B, . . . 206N, having a shared last level cache (LLC) 204.

[0055] In some examples, LLC 204 is external to processor 202. According to some examples, shared LLC 204 may be a relatively fast-access memory type, serving as a shared LLC for CPUs / cores 206A through 206N to minimize access latency. The relatively fast-access memory type included in shared LLC 204 may include, but is not limited to, volatile or nonvolatile memory. Volatile memory types may include, but are not limited to, static random access memory (SRAM) or dynamic random access memory (DRAM), thyristor RAM (TRAM), or zero-capacitor RAM (ZRAM). Nonvolatile memory types may include, but are not limited to, byte- or block-addressable nonvolatile memory types having a three-dimensional (3D) cross-point memory structure including a chalcogenide phase-change material (e.g., chalcogenide glass) (hereinafter referred to as "3D cross-point memory"). Nonvolatile memory types may also include other types of byte- or block-addressable nonvolatile memory. Examples of this include, but are not limited to, multi-threshold NAND flash memory, NOR flash memory, single or multiple phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) incorporating memristor technology, spin transfer torque MRAM (STT-MRAM), or any combination of the above.

[0056] FIG. 3 illustrates an exemplary LLC cache partitioning scheme, according to some embodiments. As illustrated, scheme 300 is one example of a scheme that may be used for shared LLC 204 in computing system 200, such as that shown in FIG. 2. Here, LLC 304 is shown as an 8-way set associative cache, with each cache way 302 containing eight cache lines. Some cache lines of LLC 304 are allocated to low-priority application 306, some to high-priority application 310, and some are invalid 308. For simplicity, shared LLC 354 is shown as an 8-way set associative cache, with each way containing one cache line. Some cache lines of LLC 354 are allocated to low-priority application 356, some to high-priority application 360, and some are invalid 358. The illustration in FIG. 3 does not limit the disclosed embodiments to any particular configuration. Alternative schemes may include more or fewer sets, more or fewer ways within a set, more or fewer cache lines within each way, etc. For example, LLC 204 may be an N-way set associative cache, with each set containing M cache lines, where N and M are positive integers greater than or equal to 1.

[0057] In operation, as described further below, LLC 204 is dynamically repartitioned as needed by the applications sharing the LLC. An advantage of the disclosed embodiments is that they seek to minimize eviction of cache lines allocated to higher priority applications by lower priority applications.

[0058] FIG. 4 is a block diagram illustrating cache line eviction according to some embodiments of the Flex-CAT algorithm. According to disclosed embodiments, Flex-CAT is an eviction algorithm that performs priority-based cache partitioning at cache set granularity. As shown, scheme 400 illustrates application of priorities that fall within a range of priorities 402. Arcs 404, 406, and 408 illustrate cache line evictions to make room for requests to fill a cache line with a subsequent cache line from the requesting core. Some evictions, such as eviction 408, involve eviction of lower priority assignments to make room for higher priority assignments. Some evictions are self-evictions, as illustrated by arc 406 (e.g., a priority that has already allocated the maximum number of ways self-evicts to make room for a subsequent CL). When a requester's occupancy reaches its maximum allocation, Flex-CAT prioritizes self-eviction over other priority evictions to stay within partition boundaries. In the limited circumstances where no victim can be found in these previous two steps, Flex-CAT selects the HP CL for eviction to make room for subsequent cache fills. Flex-CAT attempts to maximize eviction of LP CLs, such as eviction 408, and minimize eviction of HP CLs, such as eviction 404.

[0059] FIG. 5 is a block flow diagram illustrating operations performed by a cache control circuit in response to a cache fill request, according to some embodiments. For example, flow 500 can be performed by cache control circuit (CCC) 201 of FIG. 2. As shown, flow 500 begins at 501, where the CCC receives a subsequent cache fill request from a requestor having a requestor priority. For example, the requestor may be one of cores 206A, 206B, . . . 206N of FIG. 2, and the subsequent cache line may be obtained from a memory, such as memory 115 of FIG. 1. The requestor priority may reflect a priority assigned to an application running in the requesting core. At operation 502, the CCC determines whether any invalid cache lines (CLs) exist in the LLC. If so, at operation 504, the CCC writes the subsequent CL to the storage location of the invalid cache line; if the storage location is found at 505, the flow ends. However, if operation 502 indicates that there are no invalid CLs, then in 506 the CCC shall determine, for each priority in the system, the priority (P), the index of the LRU CL with priority P(LRUp), the age of LRUp, and the number of ways occupied by the priority. In operation 508, the CCC shall determine the requestor priority (P R If it is the lowest priority, then in operation 510 the CCC shall determine whether the requestor priority (O[P R If so, the flow proceeds to operation 524. Here, the occupancy count of the successor CL(P R ) to make room for the higher priority CL(P H ) is evicted.

[0060] Operation 524 illustrates a situation in which a high-priority cache line is evicted to make room for a lower-priority cache line. This is a situation that, except as noted above, disclosed embodiments attempt to avoid to the greatest extent possible. In some embodiments, a cache monitoring circuit, such as cache monitoring circuit 203 of FIG. 2, maintains heuristic tracking responses to cache fill requests that include an instance of operation 524. In some embodiments, the CCC monitors the heuristics and dynamically adjusts the minimum and maximum number of ways assigned to each priority as needed, thereby regulating the aggressiveness of higher-priority applications relative to the eviction of lower-priority applications, which ultimately leads to operation 524. In some embodiments, cache monitoring circuit 203 repartitions the LLC. Or, in some embodiments, if the maintained heuristics exceed a predetermined threshold, such as the occurrence of operation 524, the cache monitoring circuit adjusts the way boundaries associated with various priorities. For example, the number of ways assigned to high-priority applications can be reduced to reduce repeated, aggressive, and complete evictions of lower-priority applications, which ultimately leads to repeated execution of operation 524. If the CCC determines in operation 510 that the requestor occupancy is not zero, then the CCC shall evict the least recently used CL of the requestor priority in operation 514 .

[0061] Returning to operation 508, if the CCC determines that the requestor priority is not the lowest priority, then the CCC shall determine whether the occupancy count for the requestor priority is the highest in operation 512. If so, the CCC shall evict the least recently used CL for the requestor priority in operation 514. If a storage location is found in operation 515, the flow ends.

[0062] Returning to operation 512, if the CCC determines that the occupancy count for the requestor priority is not the maximum, then the CCC determines in operation 516 whether the occupancy count for the requestor priority is less than the maximum and greater than or equal to the minimum for the requestor priority. If so, flow proceeds to operation 518; otherwise, flow proceeds to operation 520. In operation 518, the CCC determines whether the occupancy count for the requestor priority (P R ) or lower priority (P L ) and the flow ends when a storage location is found in 519. In operation 520, the CCC attempts to evict an LRU CL with a priority lower than the requester priority. If such a line exists, the storage location in 522 is determined to be non-NULL and the flow proceeds to 523, where the flow ends when a storage location is found. If no such CL exists, the storage location in 522 is equal to NULL and the flow proceeds to operation 524, where an LRU CL with a priority higher than the requester priority is evicted. If a storage location is found in 525, the flow ends.

[0063] FIG. 6 is a flow diagram illustrating a method performed by a cache control circuit (CCC) for processing a cache fill request, according to some embodiments. For example, flow 600 can be performed by cache control circuit (CCC) 201 of FIG. 2. As shown, in operation 605, the CCC receives a request to store a subsequent cache line (CL) having a requester priority among a plurality of priorities in a last level cache (LLC). In operation 610, if an invalid cache line (CL) exists in the LLC, the subsequent cache line (CL) is stored in the invalid CL. In operation 615, if the requester priority is the lowest among the plurality of priorities and has an occupancy count of one or more, or has the highest occupancy count for the requester priority, the subsequent CL is stored instead of a least recently used (LRU) CL for the requester priority. In operation 620, if the occupancy count is between the highest and lowest for the requester priority, the subsequent CL is stored instead of an LRU CL for the requester priority or a lower priority. In operation 625, if a CL with an occupancy count less than the minimum and a lower priority exists, the successor CL is stored in place of the LRU CL with the lower priority. In operation 630, if there is no invalid CL or a CL with the requestor priority or lower, the successor CL is stored in place of the LRU CL with the higher priority. [Instruction Set]

[0064] An instruction set may include one or more instruction formats. A given instruction format may determine, among other things, various fields (e.g., number of bits, bit positions) and / or other data field(s) (e.g., masks) for specifying the operation to be performed (e.g., opcode) and the operand(s) on which the operation is to be performed. Some instruction formats are further classified by the definition of instruction templates (or sub-formats). For example, instruction templates of a particular instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because fewer fields are included) and / or may be defined to have certain fields that are interpreted differently. Thus, each instruction of an ISA is expressed using a particular instruction format (and, if defined, in a particular one of the instruction templates of that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has an instruction format that includes a particular opcode and an opcode field for specifying the opcode and an operand field for selecting an operand (source 1 / destination / source 2). When this ADD instruction appears in an instruction stream, it will have particular content in the operand field that selects a particular operand. A set of SIMD extensions has been released and / or published called the Advanced Vector Extensions (AVX) (AVX1 and AVX2) and uses the Vector Extensions (VEX) coding scheme (see, e.g., the September 2014 Intel® 64 and IA-32 Architecture Software Developer's Manual and the October 2014 Intel® Advanced Vector Extensions Programming Reference). [Example instruction format]

[0065] Embodiments of the instructions described herein may be embodied in different formats. Further, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instructions may execute on such systems, architectures, and pipelines, but are not limited to these details. [General-purpose vector instruction format]

[0066] A vector friendly instruction format is an instruction format that is suitable for vector instructions (e.g., there are certain fields that are specific to vector operations). Although embodiments are described that support both vector and scalar operations via the vector friendly instruction format, alternatively, embodiments may use only vector operations via the vector friendly instruction format.

[0067] Figures 7A and 7B are block diagrams illustrating a generic vector instruction format and its instruction templates according to some embodiments of the present invention. Figure 7A is a block diagram illustrating a generic vector instruction format and its class A instruction templates according to some embodiments of the present invention, while Figure 7B is a block diagram illustrating a generic vector instruction format and its class B instruction templates according to some embodiments of the present invention. Specifically, the generic vector instruction format 700 defined for class A and class B instruction templates includes no-memory access 705 instruction templates and memory access 720 instruction templates for both classes. The term generic in the context of the vector instruction format refers to an instruction format that is not tied to any particular instruction set.

[0068] Embodiments of the invention are described in which the vector-friendly instruction format supports 64-byte vector operand lengths (or sizes) with 32-bit (4 byte) or 64-bit (8 byte) data element widths (or sizes) (so a 64-byte vector consists of 16 double-word sized elements, or alternatively 8 quad-word sized elements), 64-byte vector operand lengths (or sizes) with 16-bit (2 byte) or 8-bit (1 byte) data element widths (or sizes), 32-byte vector operand lengths (or sizes) with 32-bit (4 byte), 64-bit (8 byte), 16-bit (2 byte), or 8-bit (1 byte) data element widths (or sizes), and 16-byte vector operand lengths (or sizes) with 32-bit (4 byte), 64-bit (8 byte), 16-bit (2 byte), or 8-bit (1 byte) data element widths (or sizes). Alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., 256-byte vector operands) with larger, smaller, or different data element widths (e.g., 128-bit (16-byte) data element widths).

[0069] The class A instruction templates in Figure 7A include 1) a no-memory access full round control type operation 710 instruction template and a no-memory access data transform type operation 715 instruction template, shown within the no-memory access 705 instruction templates, and 2) a memory access transient 725 instruction template and a memory access non-temporal 730 instruction template, shown within the memory access 720 instruction templates. The class B instruction templates in Figure 7B include 1) a no-memory access write mask control partial round control type operation 712 instruction template and a no-memory access write mask control VSIZE type operation 717 instruction template, shown within the no-memory access 705 instruction templates, and 2) a memory access write mask control 727 instruction template, shown within the memory access 720 instruction templates.

[0070] The generic vector friendly instruction format 700 includes the following fields in the order shown in Figures 7A and 7B:

[0071] Format field 740 - a particular value (the instruction format identifier value) in this field uniquely identifies the vector friendly instruction format and therefore the occurrence of an instruction in the vector friendly instruction format in an instruction stream. This field is therefore optional in the sense that it is not required for instruction sets that have only a generic vector friendly instruction format.

[0072] Base operation field 742: Its contents identify different base operations.

[0073] Register index field 744: its contents specify the location of source and destination operands, whether in registers or memory, directly or through address generation. These contain enough bits to select N registers from a P×Q (e.g., 32×512, 16×128, 32×1024, 64×1024) register file. In one embodiment, N can be up to three source and one destination register, although alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources, where one of the sources also functions as the destination, or up to three sources, where one of the sources also functions as the destination, where up to two sources and one destination).

[0074] Qualifier field 746: its content distinguishes the occurrence of instructions in the generic vector instruction format that specify memory access from instructions that do not; that is, distinguishes between no-memory access 705 instruction templates and memory access 720 instruction templates. Memory access operations read and / or write to the memory hierarchy (possibly using values in registers to specify source and / or destination addresses), while non-memory access operations do not (e.g., the source and destination are registers). Also, in one embodiment, this field selects between three separate ways to perform memory address calculations, although alternative embodiments may support more, fewer, or different ways to perform memory address calculations.

[0075] Extended Operation Field 750: Its contents distinguish which of a variety of different operations is performed in addition to the base operation. This field is context specific. In some embodiments, this field is divided into a Class field 768, an Alpha field 752, and a Beta field 754. Extended Operation Field 750 allows common groups of operations to be performed with a single instruction rather than two, three, or four instructions.

[0076] Scale field 760: its contents determine the scale for memory address generation (e.g., 2 scale* Allows scaling of the contents of the index field (for address generation using index+base).

[0077] Displacement field 762A: its contents are used for memory address generation (e.g., 2 scale* Used as part of an address generation using index + base + displacement.

[0078] Displacement factor field 762B (note that the juxtaposition of displacement field 762A directly above displacement factor field 762B indicates that one or the other may be used): its contents are used as part of address generation; it specifies the displacement factor to be scaled by the size of the memory access (N), where N is the number of bytes in the memory access (e.g., 2 scale*(for address generation using index + base + scaled displacement). Redundant low-order bits are ignored, and therefore the contents of the displacement factor field are multiplied by the total size of the memory operands (N) to generate the final displacement used to calculate the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 774 (described later herein) and the data operation field 754C. The displacement field 762A and displacement factor field 762B are optional in the sense that they are not used for non-memory access 705 instruction templates and / or different embodiments may implement only one of these two, or none at all.

[0079] Data element width field 764: its content distinguishes which of multiple data element widths are used (in some embodiments for all instructions, in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or if data element widths are supported using some aspect of the opcode.

[0080] Write mask field 770: its content controls, on a data element position basis, whether that data element position in the destination vector operand reflects the results of the base and extend operations. Class A instruction templates support merge write masks, while class B instruction templates support both merge and zeroize write masks. In the case of merge, the vector mask allows any set of elements in the destination to be protected from being updated during the execution of any operation (specified by the base and extend operations). In another embodiment, if the corresponding mask bit has a 0, the old value of each element in the destination is preserved. In contrast, in the case of zeroize, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and extend operations). In one embodiment, if the corresponding mask bit has a 0 value, the element in the destination is set to 0. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span over which elements are modified, from first to last), although the modified elements do not need to be contiguous. Thus, write mask field 770 allows for partial vector operations including loads, stores, arithmetic, logical, etc. Although embodiments of the present invention are described such that the contents of write mask field 770 selects which of multiple write mask registers contains the write mask to be used (thus the contents of write mask field 770 indirectly identify the masking to be performed), alternative embodiments allow the contents of write mask field 770 to alternatively or additionally directly specify the masking to be performed.

[0081] Immediate field 772: its content allows specification of an immediate value. This field is optional in the sense that it is absent in implementations of the generic vector friendly format that do not support immediate values, and is absent in several instructions that do not use immediate values.

[0082] Class field 768: its content distinguishes between different classes of instructions. With reference to Figures 7A and 7B, the content of this field selects between class A and class B instructions. In Figures 7A and 7B, a rounded corner box is used to indicate that a particular value is present in the field (e.g., class A 768A and class B 768B for class field 768, respectively). [Class A instruction template]

[0083] For class A no-memory access 705 instruction templates, the alpha field 752 is interpreted as an RS field 752A whose content distinguishes which of the different extended operation types is performed (e.g., round 752A.1 and data transform 752A.2 are specified for the no-memory access round type operation 710 and the no-memory access data transform type operation 715 instruction templates, respectively), while the beta field 754 distinguishes which of the specified types of operation is performed. The scale field 760, displacement field 762A, and displacement factor field 762B are not present in the no-memory access 705 instruction templates. [Non-memory access instruction template - full round control type operation]

[0084] In the no-memory-access full-round-control type operation 710 instruction template, the beta field 754 is interpreted as a round control field 754A, the contents of which provide static rounding. In the described embodiment, the round control field 754A includes a Suppress All Floating-Point Exceptions (SAE) field 756 and a round operation control field 758, while alternative embodiments may encode both of these concepts in the same field, or alternative embodiments may have only one or the other of these concepts / fields (e.g., only the round operation control field 758).

[0085] SAE field 756: its content determines whether exception event reporting is disabled. If the content of SAE field 756 indicates that suppression is enabled, the particular instruction will not report any kind of floating-point exception flags and will not raise the floating-point exception handler.

[0086] Round operation control field 758: its contents distinguish which of a group of round operations (e.g., round up, round down, round towards zero, and round towards nearest) is performed. Thus, the round operation control field 758 allows the rounding mode to be changed on an instruction-by-instruction basis. In some embodiments where the processor includes a control register for specifying the rounding mode, the contents of the round operation control field 750 overwrite the value of that register. [Non-memory access instruction template - data conversion type operation]

[0087] In the non-memory access data transform type operation 715 instruction template, the beta field 754 is interpreted as a data transform field 754B, and the contents of the data transform field 754B distinguish which of several data transforms (e.g., no data transform, swizzle, broadcast) is performed.

[0088] In the case of class A memory access 720 instruction templates, the alpha field 752 is interpreted as an eviction hint field 752B, whose content distinguishes which of the eviction hints should be used (in FIG. 7A , temporal 752B.1 and non-temporal 752B.2 are specified for the memory access temporal 725 instruction template and the memory access non-temporal 730 instruction template, respectively), while the beta field 754 is interpreted as a data manipulation field 754C, whose content distinguishes which of several data manipulation operations (also known as primitives) is performed (e.g., no operation, broadcast, source upconversion, and destination downconversion). The memory access 720 instruction templates include a scale field 760 and, optionally, a displacement field 762A or a displacement factor field 762B.

[0089] Vector memory instructions perform vector loads from memory and vector stores to memory, with translation support. As with regular vector instructions, vector memory instructions transfer data from / to memory in whole data elements, with the actual elements transferred being described by the contents of the vector mask selected as the write mask. [Memory access instruction template:temporary]

[0090] Transient data is data that is likely to be reused quickly enough to benefit from caching. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely. [Memory access instruction template:non-temporal]

[0091] Non-temporal data is data that is unlikely to be reused quickly enough to benefit from caching in the first level cache, and should be given eviction priority. However, this is a hint, and different processors may implement it in different ways, including ignoring the hint entirely. [Class B instruction template]

[0092] For class B instruction templates, the alpha field 752 is interpreted as a write mask control (Z) field 752C, and the contents of the write mask control (Z) field 752C distinguish whether the write masking controlled by the write mask field 770 should be merging or zeroing.

[0093] For class B no-memory access 705 instruction templates, part of the beta field 754 is interpreted as an RL field 757A, whose content distinguishes which of the different extended operation types is performed (e.g., round 757A.1 and vector length (VSIZE) 757A.2 are specified for the no-memory access writemask control partial round control type operation 712 instruction template and the no-memory access writemask control VSIZE type operation 717 instruction template, respectively), while the remainder of the beta field 754 distinguishes which of the specified types of operation is performed. The scale field 760, displacement field 762A, and displacement factor field 762B are not present in the no-memory access 705 instruction templates.

[0094] In the non-memory access write mask control partial round control type operation 712 instruction template, the remainder of the beta field 754 is interpreted as the round operation field 759A and exception event reporting is disabled (the particular instruction does not report any kind of floating-point exception flags and does not raise any floating-point exception handlers).

[0095] Round operation control field 759A: Similar to round operation control field 758, its content distinguishes which of a group of round operations is performed (e.g., round up, round down, round towards zero, and round towards nearest). Thus, round operation control field 759A allows the rounding mode to be changed on an instruction-by-instruction basis. In some embodiments, if the processor includes a control register for specifying the rounding mode, the content of round operation control field 750 overwrites the value of that register.

[0096] In the non-memory access write mask control VSIZE type operation 717 instruction template, the remainder of the beta field 754 is interpreted as a vector length field 759B, and the contents of the vector length field 759B distinguish between execution with multiple data vector lengths (e.g., 128, 256, or 512 bytes).

[0097] In the case of a class B memory access 720 instruction template, a portion of the beta field 754 is interpreted as a broadcast field 757B, whose content distinguishes whether a broadcast-type data manipulation operation is to be performed, while the remainder of the beta field 754 is interpreted as a vector length field 759B. The memory access 720 instruction template includes a scale field 760 and optionally a displacement field 762A or a displacement factor field 762B.

[0098] For generic vector friendly instruction format 700, full opcode field 774 is shown to include format field 740, base operation field 742, and data element width field 764. While one embodiment is shown in which full opcode field 774 includes all of these fields, in embodiments that do not support all of the fields, full opcode field 774 includes less than all of the fields. Full opcode field 774 provides an operation code (opcode).

[0099] The extended operation field 750, data element width field 764, and write mask field 770 allow these features to be specified on a per-instruction basis in the generic vector friendly instruction format.

[0100] The combination of the write mask field and the data element width field form a typed instruction in that they allow masks to be applied based on different data element widths.

[0101] The various instruction templates found within class A and class B are useful in different situations. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high-performance, general-purpose, out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both may support both. (Of course, a core having some combination of templates and instructions from both classes, but not all templates and instructions from both classes, is within the scope of the present invention.) Also, a single processor may include multiple cores, all of which support the same class, or different cores of which support different classes. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more of the general-purpose cores may be a high-performance, general-purpose core with out-of-order execution and register renaming for general-purpose computing that supports only class B. Another processor that does not have a separate graphics core may include one or more general-purpose in-order or out-of-order cores that support both Class A and Class B. Of course, in different embodiments of the invention, functions belonging to one class may be implemented in the other class. Programs written in high-level languages may be put into a variety of different executable forms (e.g., just-in-time compiled or statically compiled), including 1) a form having only instructions of classes supported by the target processor for execution, or 2) a form having alternative routines written using different combinations of instructions of all classes, with control flow code that selects between the routines to execute based on the instructions supported by the processor currently executing the code. [Example vector-specific instruction formats]

[0102] Figure 8A is a block diagram illustrating an exemplary vector-specific instruction format according to some embodiments of the present invention. Figure 8A shows a specific vector-specific instruction format 800, which is specific in that it specifies the location, size, interpretation, and order of fields, as well as values for some of these fields. The specific vector-specific instruction format 800 may be used to extend the x86 instruction set, and thus some of the fields are similar or identical to fields used in the existing x86 instruction set and its extensions (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R / M field, SIB field, displacement field, and immediate field of the existing x86 instruction set with some extensions. The fields from Figure 7A or Figure 7B to which the fields from Figure 8A map are illustrated.

[0103] While embodiments of the present invention are described with respect to the specific vector instruction format 800 in the context of the generic vector instruction format 700 for illustrative purposes, it should be understood that the present invention is not limited to the specific vector instruction format 800 except as claimed. For example, while the specific vector instruction format 800 is shown as having fields of particular sizes, the generic vector instruction format 700 contemplates a variety of possible sizes for the various fields. As a particular example, while the data element width field 764 is shown as a one-bit field in the specific vector instruction format 800, this is not intended to be a limitation of the present invention (i.e., the generic vector instruction format 700 contemplates data element width fields 764 of other sizes).

[0104] The vector-specific instruction format 800 includes the following fields, listed below in the order shown in FIG. 8A:

[0105] EVEX prefix (bytes 0-3) 802. This is encoded in a 4-byte format.

[0106] Format field 740 (EVEX byte 0, bits [7:0]): The first byte (EVEX byte 0) is the format field 740, which contains 0x62 (a unique value used in some embodiments to distinguish vector friendly instruction formats).

[0107] The second through fourth bytes (EVEX bytes 1-3) contain multiple bit fields that provide specific functions.

[0108] REX field 805 (EVEX byte 1, bits [7-5]): Consists of the EVEX.R bit field (EVEX byte 1, bit [7] - R), the EVEX.X bit field (EVEX byte 1, bit [6] - X), and the EVEX.B bit field (EVEX byte 1, bit [5] - B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide identical functionality to the corresponding VEX bit fields, and they are encoded using one's complement format, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields in the instruction encode the lower three bits of the register index (rrr, xxx, and bbb), as known in the art, so that Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0109] REX' 810A: This is the first part of the REX' field 810, the EVEX.R' bit field (EVEX byte 1, bit [4] - R') used to encode either the upper 16 or lower 16 of the extended 32-register set. In some embodiments, this bit, along with others shown below, is stored in bit-reversed format to distinguish it from the BOUND instruction (in the well-known x86 32-bit mode). The real opcode byte of the BOUND instruction is 62, but within the MOD R / M field (described below), it does not accept a value of 11 for the MOD field. Alternative embodiments of the invention do not store this bit, and other bits described below, in inverted format. A value of 1 is used to encode the lower 16 registers. In other words, EVEX.R', EVEX.R, and other RRR fields combine to form R'Rrrr.

[0110] Opcode map field 815 (EVEX byte 1, bits [3:0]-mmmm): its contents encode the suggested leading opcode byte (0F, 0F38, or 0F3).

[0111] The data element width field 764 (EVEX byte 2, bit [7]-W) is represented by the notation EVEX.W, which is used to specify the granularity (size) of the data type (32-bit data elements or 64-bit data elements).

[0112] EVEX.vvvv field 820 (EVEX byte 2, bits [6:3]-vvvv). The role of EVEX.vvvv may include: 1) EVEX.vvvv encodes the first source register operand in a specified inverted (one's complement) format, and EVEX.vvvv is valid for instructions with two or more source operands; 2) EVEX.vvvv encodes the destination register operand in a specified one's complement format for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, and the field is reserved and should contain 1111b. Thus, EVEX.vvvv field 820 encodes the four low-order bits of the first source register specifier stored in inverted (one's complement) format. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0113] EVEX.U 768 Class field (EVEX byte 2, bit [2] - U): If EVEX.U=0, it indicates class A or EVEX.U0. If EVEX.U=1, it indicates class B or EVEX.U1.

[0114] Prefix Encoding Field 825 (EVEX Byte 2, bits [1:0]-pp): Provides additional bits to the Base Operation field. In addition to providing support for legacy SSE instructions in the EVEX prefix format, this also has the benefit of compacting the SIMD prefix (instead of requiring one byte to represent the SIMD prefix, the EVEX prefix only requires two bits). In one embodiment, to support legacy SSE instructions that use SIMD prefixes (66H, F2H, F3H) in both the legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded in the SIMD prefix encoding field. These legacy SIMD prefixes are expanded to legacy SIMD prefixes at runtime before being provided to the decoder's PLA (thus the PLA can execute both the legacy and EVEX formats of these legacy instructions without modification). Although newer instructions can use the contents of the EVEX prefix encoding field directly as an opcode extension, certain embodiments extend them in a similar manner for consistency but allow for different means specified by these legacy SIMD prefixes. Alternative embodiments can redesign the PLA to support 2-bit SIMD prefix encodings and therefore do not require the extension.

[0115] Alpha field 752 (EVEX byte 3, bit [7] - EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.WriteMaskControl, and EVEX.N; also denoted α): As previously described, this field is context specific.

[0116] Beta field 754 (EVEX byte 3, bits [6:4] - SSS.EVEX.S 2-0 ,EVEX.r 2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB. Also denoted as βββ): As noted above, this field is context specific.

[0117] REX' 810B. This is the remainder of the REX' field 810, the EVEX.V' bit field (EVEX byte 3, bit [3] V') which can be used to encode either the top 16 or bottom 16 of the extended 32 register set. This bit is stored in bit-reversed format. A value of 1 is used to encode the bottom 16 registers. In other words, combining EVEX.V', EVEX.vvvv forms V'VVVV.

[0118] Write mask field 770 (EVEX byte 3, bits [2:0]-kkk): its contents specify the index of a register in the write mask register, as described above. In some embodiments, a particular value EVEX.kkk=000 has special behavior that implies that no write mask is used for the particular instruction (this may be implemented in various ways, including using a write mask hardwired to all ones or using hardware that bypasses the masking hardware).

[0119] The real opcode field 830 (byte 4), also known as the opcode byte, specifies part of the opcode.

[0120] MOD R / M field 840 (byte 5) includes MOD field 842, Reg field 844, and R / M field 846. As noted above, the contents of MOD field 842 distinguish between memory access and non-memory access operations. The role of Reg field 844 can be summarized in two situations: encoding either a destination register operand or a source register operand, or being treated as an opcode extension and not used to encode an instruction operand. The role of R / M field 846 may include encoding an instruction operand that references a memory address, or encoding either a destination register operand or a source register operand.

[0121] The Scale, Index, Base (SIB) byte 850 (byte 6) contains SS 852 for scale. As previously described, the scale field 760 is used in memory address generation: SIB.xxx 854 and SIB.bbb 856. The contents of these fields have been described for register indexes Xxxx and Bbbb.

[0122] Displacement field 762A (bytes 7-10): If the MOD field 842 contains 10, then bytes 7-10 are the displacement field 762A, which functions the same as the legacy 32-bit displacement (disp32) and operates at byte granularity.

[0123] Displacement Factor Field 762B (Byte 7): When the MOD field 842 contains 01, byte 7 is the displacement factor field 762B. The location of this field is the same as that of the 8-bit displacement (disp8) in the legacy x86 instruction set, which operates at byte granularity. Because disp8 is sign-extended, disp8 can only address between -128 and 127 byte offsets. For a 64-byte cache line, disp8 uses 8 bits that can only be set to four practically useful values: -128, -64, 0, and 64. Typically, a wider range is needed, so disp32 is used, but disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 762B is a reinterpretation of disp8. When using the displacement factor field 762B, the actual displacement is determined by the contents of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte is used for the displacement, but with a very large range). Such a compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and therefore the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 762B replaces the 8-bit displacement of the legacy x86 instruction set. Therefore, the displacement factor field 762B is encoded in the same way as the 8-bit displacement of the x86 instruction set, with the only exception that disp8 is overloaded to disp8*N (hence, there are no changes to the ModRM / SIB encoding rules). That is, there are no changes to the encoding rules or encoding length, only to the interpretation of the displacement value by the hardware (which must scale the displacement by the size of the memory operand to obtain the per-byte address offset). The immediate field 772 operates as described above. [Full Opcode Field]

[0124] 8B is a block diagram illustrating the fields that make up the full opcode field 774 of the vector-specific instruction format 800, according to some embodiments. Specifically, the full opcode field 774 includes a format field 740, a base operation field 742, and a data element width (W) field 764. The base operation field 742 includes a prefix encoding field 825, an opcode map field 815, and a real opcode field 830. [Register index field]

[0125] 8C is a block diagram illustrating the fields that make up the register index field 744 of the vector-specific instruction format 800, according to some embodiments. Specifically, the register index field 744 includes a REX field 805, a REX' field 810, a MODR / M.reg field 844, a MODR / Mr / m field 846, a VVVV field 820, a xxx field 854, and a bbb field 856. Extended computed field

[0126] 8D is a block diagram illustrating the fields that make up the extended operation field 750 of the specific vector instruction format 800, according to one embodiment of the present invention. When the class (U) field 768 contains a 0, it represents EVEX.U0 (Class A 768A). When the class (U) field 768 contains a 1, it represents EVEX.U1 (Class B 768B). When U=0 and the MOD field 842 contains an 11 (indicating a non-memory access operation), the alpha field 752 (EVEX byte 3, bits [7]-EH) is interpreted as the rs field 752A. When the rs field 752A contains a 1 (round 752A.1), the beta field 754 (EVEX byte 3, bits [6:4] SSS) is interpreted as the round control field 754A. The round control field 754A includes a 1-bit SAE field 756 and a 2-bit round operation field 758. If the rs field 752A contains 0 (data translation 752A.2), the beta field 754 (EVEX byte 3, bits [6:4] SSS) is interpreted as a 3-bit data translation field 754B. If U=0 and the MOD field 842 contains 00, 01, or 10 (signifying a memory access operation), the alpha field 752 (EVEX byte 3, bits [7] - EH) is interpreted as an eviction hint (EH) field 752B, and the beta field 754 (EVEX byte 3, bits [6:4] SSS) is interpreted as a 3-bit data manipulation field 754C.

[0127] If U=1, the alpha field 752 (EVEX byte 3, bits [7]-EH) is interpreted as a write mask control (Z) field 752C. If U=1 and the MOD field 842 contains 11 (indicating a non-memory access operation), part of the beta field 754 (EVEX byte 3, bit [4] S0) is interpreted as the RL field 757A. If the RL field 757A contains 1 (round 757A.1), the remainder of the beta field 754 (EVEX byte 3, bits [6-5] S 2-1) is interpreted as the round operation field 759A, while if the RL field 757A contains 0 (VSIZE 757.A2), the remainder of the beta field 754 (EVEX byte 3, bits [6-5]S 2-1 ) is the vector length field 759B (EVEX byte 3, bits [6-5]L 1-0 If U=1 and the MOD field 842 contains 00, 01, or 10 (indicating a memory access operation), the beta field 754 (EVEX byte 3, bits [6:4] SSS) is interpreted as the vector length field 759B (EVEX byte 3, bits [6-5] L 1-0 ) and broadcast field 757B (EVEX byte 3, bit [4]B). [Example Register Architecture]

[0128] 9 is a block diagram of a register architecture 900, according to some embodiments. In the illustrated embodiment, there are 32 vector registers 910, each 512 bits wide. These registers are referenced as zmm0 through zmm31. The lower 256 bits of the lower 16 zmm registers overlap registers ymm0 through ymm15. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) overlap registers xmm0 through xmm15. The vector-specific instruction format 800 operates on these overlapping register files as shown in the following table: [Table 2]

[0129] In other words, the vector length field 759B selects between a maximum length and one or more other shorter lengths, each such shorter length being half the length of the preceding length, and instruction templates without the vector length field 759B operate on the maximum vector length. Furthermore, in one embodiment, the class B instruction templates of the specific vector-oriented instruction format 800 operate on packed single-precision / double-precision floating-point data or scalar single-precision / double-precision floating-point data and packed integer data or scalar integer data. Scalar operations are operations performed on the lowest data element position in a zmm / ymm / xmm register; the higher data element positions are either left the same as before the instruction or are zeroed, depending on the embodiment.

[0130] In the illustrated embodiment, there are eight write mask registers 915 (k0 through k7), each 64 bits in size. In an alternative embodiment, the write mask registers 915 are 16 bits in size. As noted above, in some embodiments, the vector mask register k0 is unavailable as a write mask. If the encoding normally indicating k0 is used for the write mask, it selects a hardwired write mask of 0xffff, effectively disabling write masking for that instruction.

[0131] General purpose registers 925 in the illustrated embodiment include sixteen 64-bit general purpose registers that are used in conjunction with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0132] In the illustrated embodiment, scalar floating-point stack register file (x87 stack) 945 is shown aliased as MMX packed integer flat register file 950; the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extensions. MMX registers are used to perform operations on 64-bit packed integer data, but are also used to hold operands for some operations performed between MMX registers and XMM registers.

[0133] Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may use more, fewer, or different register files and registers. [Exemplary Core Architectures, Processors, and Computer Architectures]

[0134] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, such core implementations may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; or 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU including one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing, and 2) a coprocessor including one or more specialized cores intended primarily for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor on a separate die in the same package as the CPU; or 3) a coprocessor on the same die as the CPU (in which case such coprocessors may also be referred to as specialized logic, such as integrated graphics and / or scientific (throughput) logic, or specialized cores). 4) A system-on-chip that may include the described CPUs (sometimes referred to as application core(s) or application processor(s)), the coprocessors described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture. [Example Core Architecture] [Block diagram of in-order and out-of-order cores]

[0135] FIG. 10A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, according to some embodiments of the present invention. FIG. 10B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core, included in a processor, according to some embodiments of the present invention. The solid lined boxes in FIGS. 10A and 10B illustrate the in-order pipeline and in-order core, while the optional addition of dashed lined boxes illustrates the register renaming, out-of-order issue / execution pipeline and core. The out-of-order aspects will be described, as the in-order aspects are a subset of the out-of-order aspects.

[0136] In FIG. 10A , a processor pipeline 1000 includes a fetch stage 1002, a length decode stage 1004, a decode stage 1006, an allocation stage 1008, a renaming stage 1010, a scheduling (also known as distribution or issue) stage 1012, a register read / memory read stage 1014, an execution stage 1016, a writeback / memory write stage 1018, an exception handling stage 1022, and a commit stage 1024.

[0137] 10B shows a processor core 1090 that includes a front-end unit 1030 coupled to an execution engine unit 1050, both of which are coupled to a memory unit 1070. Core 1090 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, core 1090 may be a specialized core, such as, for example, a network or communications core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0138] The front-end unit 1030 includes a branch prediction unit 1032 coupled to an instruction cache unit 1034, which is coupled to an instruction translation lookaside buffer (TLB) 1036, which is coupled to an instruction fetch unit 1038, which is coupled to a decode unit 1040. The decode unit 1040 (i.e., decoder) may decode instructions and may generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, reflect, or are derived from the original instruction. The decode unit 1040 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, a lookup table, a hardware implementation, a programmable logic array (PLA), a microcode read-only memory (ROM), etc. In one embodiment, core 1090 includes a microcode ROM or other medium that stores microcode for particular macro instructions (e.g., in decode unit 1040 or otherwise within front end unit 1030). Decode unit 1040 is coupled to rename / allocator unit 1052 within execution engine unit 1050.

[0139] The execution engine unit 1050 includes a rename / allocator unit 1052 coupled to a retirement unit 1054 and a set of one or more scheduler units 1056. The scheduler units 1056 represent any number of different schedulers, including multiple reservation stations, a central instruction window, etc. The scheduler unit(s) 1056 are coupled to physical register file unit(s) 1058. Each of the physical register file units 1058 represents one or more physical register files, each different one of which stores one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, state (e.g., an instruction pointer, which is the address of the next instruction to be executed), etc. In one embodiment, the physical register file units 1058 comprise multiple vector register units, a writemask register unit, and a scalar register unit. These register units may provide the vector registers, vector mask registers, and general-purpose registers of the architecture. The physical register file unit 1058 overlaps with the retirement unit 1054 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer and retirement register file; using a future file, a history buffer, and / or a retirement register file; using multiple register maps and register pools, etc.). The retirement unit 1054 and the physical register file unit(s) 1058 are coupled to the execution cluster(s) 1060. The execution cluster(s) 1060 include a set of one or more execution units 1062 and a set of one or more memory access units 1064. The execution units 1062 may perform various operations (e.g., shift, add, subtract, multiply) on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).Some embodiments may include multiple execution units dedicated to a particular function or set of functions, while other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scheduler unit 1056, Physical Register File Unit 1058, and Execution Cluster 1060 are illustrated as multiple because certain embodiments form separate pipelines for particular types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each of which has its own scheduler unit, Physical Register File Unit, and / or execution cluster. In the case of a separate memory access pipeline, certain embodiments are implemented with only the execution cluster of this pipeline having memory access unit(s) 1064. It should also be understood that if separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the rest in-order.

[0140] A set of multiple memory access units 1064 is coupled to a memory unit 1070, which includes a data TLB unit 1072 coupled to a data cache unit 1074 coupled to a level 2 (L2) cache unit 1076. In one exemplary embodiment, the memory access units 1064 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 1072 of the memory unit 1070. The instruction cache unit 1034 is further coupled to the level 2 (L2) cache unit 1076 of the memory unit 1070. The L2 cache unit 1076 is coupled to one or more other levels of cache and ultimately to main memory.

[0141] By way of example, an exemplary register renaming, out-of-order issue / execution core architecture may implement pipeline 1000 as follows: 1) the instruction fetch unit 1038 performs the fetch stage 1002 and the length decode stage 1004; 2) the decode unit 1040 performs the decode stage 1006; 3) the rename / allocator unit 1052 performs the allocation stage 1008 and the renaming stage 1010; 4) the scheduler unit 1056 performs the schedule stage 1012; 5) the physical register file unit 1058 and the memory unit 1070 perform the register read / memory read stage 1014; the execution cluster 1060 performs the execution stage 1016; 6) the memory unit 1070 and the physical register file unit 1058 perform the writeback / memory write stage 1018; 7) various units may be involved in the exception handling stage 1022; and 8) the retirement unit 1054 and the physical register file unit 1058 perform the commit stage 1024.

[0142] Core 1090 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies of Sunnyvale, California, or the ARM instruction set from ARM Holdings of Sunnyvale, California (with any additional extensions such as NEON)), including the instructions described herein. In one embodiment, core 1090 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), which allows several operations used by many multimedia applications to be performed using packed data.

[0143] Cores support multithreading (the execution of two or more parallel sets of operations or threads) and can do so in a variety of ways, including time-sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-sliced fetch and decode followed by simultaneous multithreading, such as in Intel® Hyper-Threading Technology).

[0144] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in in-order architectures. The illustrated embodiment of the processor may also include separate instruction cache unit 1034 and data cache unit 1074, as well as a shared L2 cache unit 1076, although alternative embodiments may have a single internal cache for both instructions and data, such as a level 1 (L1) internal cache or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and / or processor. Alternatively, all of the cache may be external to the core and / or processor. [Specific Exemplary In-Order Core Architecture]

[0145] 11A and 11B show block diagrams of a more specific example in-order core architecture, where a core may be one of several logic blocks (including other cores of the same and / or different types) within a chip. The logic block communicates with some fixed-function logic, memory I / O interfaces, and other necessary I / O logic, depending on the application, through a high-bandwidth interconnection network (e.g., a ring network).

[0146] FIG. 11A is a block diagram of a single processor core with a connection to an on-die interconnect network 1102 and a local subset of a level 2 (L2) cache 1104, according to some embodiments of the present invention. In one embodiment, an instruction decoder 1100 supports the x86 instruction set with the packed data instruction set extension. An L1 cache 1106 allows low-latency access to cache memory within the scalar and vector units. In one embodiment, (for design simplicity) the scalar unit 1108 and the vector unit 1110 use separate register sets (scalar registers 1112 and vector registers 1114, respectively), and data transferred between them is written to and re-read from the level 1 (L1) cache 1106 memory, although alternative embodiments of the present invention may use different approaches (e.g., using a single register set or including a communication path that allows data transfer between the two register files without writes and re-reads).

[0147] The local L2 cache subset 1104 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local L2 cache subset 1104. Data read by a processor core is stored in its L2 cache subset 1104, where it can be accessed quickly in parallel with other processor cores' accesses to their local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1104 and is flushed from other subsets if necessary. The ring network ensures coherency for shared data. The ring network is bidirectional, allowing agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide per direction.

[0148] FIG. 11B is an expanded view of a portion of the processor core of FIG. 11A according to some embodiments of the present invention. FIG. 11B includes an L1 data cache 1106A, which is part of the L1 cache 1106, as well as more details regarding the vector unit 1110 and vector registers 1114. Specifically, the vector unit 1110 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 1128) that executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling of register inputs using a swizzle unit 1120, numeric conversion using numeric conversion units 1122A and 1122B, and replication on memory inputs using a replication unit 1124. A write mask register 1126 allows prediction of resulting vector writes.

[0149] Figure 12 is a block diagram of a processor 1200, which may have two or more cores, an integrated memory controller, and integrated graphics, according to some embodiments of the invention. The solid-lined box in Figure 12 illustrates processor 1200, which includes a single core 1202A, a system agent unit 1210, and a set of one or more bus controller units 1216. The dashed-lined box illustrates an optional additional processor 1200, which includes multiple cores 1202A-1202N, a set of one or more integrated memory controller units 1214 in system agent unit 1210, and dedicated logic 1208.

[0150] Thus, different implementations of processor 1200 may include: 1) a CPU in which special purpose logic 1208 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores) and cores 1202A-1202N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor in which cores 1202A-1202N are multiple special-purpose cores primarily for graphics and / or scientific (throughput); and 3) a coprocessor in which cores 1202A-1202N are multiple general-purpose in-order cores. Thus, processor 1200 may be a general-purpose processor, coprocessor, or special-purpose processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput multiple integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 1200 may be a part of and / or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0151] The memory hierarchy includes one or more levels of cache within the core, a set of one or more shared cache units 1206, and external memory (not shown) coupled to a set of integrated memory controller units 1214. The set of shared cache units 1206 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other level caches, a last-level cache (LLC), and / or combinations thereof. In one embodiment, a ring-based interconnect unit 1212 interconnects integrated graphics logic 1208 (the integrated graphics logic 1208 is an example of dedicated logic and is also referred to herein as dedicated logic), the set of shared cache units 1206, and system agent unit 1210 / integrated memory controller unit 1214, while alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 1206 and cores 1202A-1202N.

[0152] In some embodiments, one or more of cores 1202A-1202N are capable of multithreading. System agent unit 1210 includes these components that coordinate and operate cores 1202A-1202N. System agent unit 1210 may include, for example, a power control unit (PCU) and a display unit. The PCU may be or may include the logic and components needed to coordinate the power state of cores 1202A-1202N and integrated graphics logic 1208. The display unit is for driving one or more externally connected displays.

[0153] The cores 1202A-1202N may be homogeneous or heterogeneous with respect to architectural instruction sets, i.e., two or more of the cores 1202A-1202N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set. [Example Computer Architecture]

[0154] 13-16 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable media players, handheld devices, and a variety of other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can incorporate the processors and / or other execution logic disclosed herein are generally suitable.

[0155] 13, a block diagram of a system 1300 according to one embodiment of the present invention is shown. The system 1300 may include one or more processors 1310, 1315 coupled to a controller hub 1320. In one embodiment, the controller hub 1320 includes a graphics memory controller hub (GMCH) 1390 and an input / output hub (IOH) 1350 (which may be on separate chips), where the GMCH 1390 includes a memory controller and a graphics controller to which memory 1340 and a coprocessor 1345 are coupled, and the IOH 1350 couples input / output (I / O) devices 1360 to the GMCH 1390. Alternatively, one or both of the memory controller and the graphics controller are integrated within the processor (as described herein), and the memory 1340 and the coprocessor 1345 are coupled directly to the controller hub 1320 in a single chip with the processor 1310 and the IOH 1350.

[0156] The optional nature of the additional processor 1315 is indicated by the dashed lines in Figure 13. Each processor 1310, 1315 may include one or more of the processing cores described herein and may be some version of processor 1200.

[0157] The memory 1340 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1320 communicates with the processors 1310, 1315 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface such as a QuickPath Interconnect (QPI), or similar connection 1395.

[0158] In one embodiment, coprocessor 1345 is a special-purpose processor, such as a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, controller hub 1320 may include an integrated graphics accelerator.

[0159] There may be a wide variety of differences between the physical resources 1310, 1315 with respect to various criteria of merit, including architectural, microarchitectural, thermal, and power consumption characteristics.

[0160] In one embodiment, the processor 1310 executes instructions that control general types of data processing operations. Coprocessor instructions may be embedded within these instructions. The processor 1310 recognizes these coprocessor instructions as being of a type that should be executed by an attached coprocessor 1345. Accordingly, the processor 1310 issues these coprocessor instructions (or control signals representing the coprocessor instructions) to the coprocessor 1345 over a coprocessor bus or other interconnect. The coprocessor(s) 1345 accept and execute the received coprocessor instructions.

[0161] Referring now to FIG. 14, a block diagram of a first, more specific, exemplary system 1400 is shown in accordance with an embodiment of the present invention. As shown in FIG. 14, multiprocessor system 1400 is a point-to-point interconnect system and includes a first processor 1470 and a second processor 1480 coupled via a point-to-point interconnect 1450. Each of processors 1470 and 1480 may be some version of processor 1200. In some embodiments of the present invention, processors 1470 and 1480 are processors 1310 and 1315, respectively, while coprocessor 1438 is coprocessor 1345. In other embodiments, processors 1470 and 1480 are processor 1310 and coprocessor 1345, respectively.

[0162] Processors 1470 and 1480 are shown as including integrated memory controller (IMC) units 1472 and 1482, respectively. Processor 1470 also includes point-to-point (PP) interfaces 1476 and 1478 as part of its bus controller unit; similarly, second processor 1480 includes PP interfaces 1486 and 1488. Processors 1470, 1480 may exchange information using PP interface circuits 1478, 1488 via point-to-point (PP) interface 1450. As shown in FIG. 14 , IMCs 1472 and 1482 couple the processors to respective memories, namely memory 1432 and memory 1434. Memory 1432 and memory 1434 may be part of main memory locally attached to the respective processors.

[0163] Processors 1470, 1480 may each exchange information with chipset 1490 using point-to-point interface circuits 1476, 1494, 1486, 1498 via respective PP interfaces 1452, 1454. Chipset 1490 may optionally exchange information with coprocessor 1438 via high performance interface 1492. In one embodiment, coprocessor 1438 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, or an embedded processor.

[0164] A shared cache (not shown) may be included either within the processor or external to both processors already connected to the processor via the PP interconnect, so that when the processors are placed into a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0165] Chipset 1490 may be coupled to a first bus 1416 via an interface 1496. In one embodiment, first bus 1416 may be a bus such as a Peripheral Component Interconnect (PCI) bus, or a PCI Express bus or another third generation I / O interconnect bus, although the scope of the invention is not so limited.

[0166] As shown in FIG. 14 , various I / O devices 1414 may be coupled to the first bus 1416, along with a bus bridge 1418 coupling the first bus 1416 to a second bus 1420. In one embodiment, one or more additional processors 1415, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (e.g., a graphics accelerator or digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 1416. In one embodiment, the second bus 1420 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 1420, including, for example, a keyboard and / or mouse 1422, a communication device 1427, and a storage unit 1428, such as a disk drive or other mass storage device, which may contain a plurality of instructions / code and data 1430. Additionally, audio I / O 1424 may be coupled to the second bus 1420. It should be noted that other architectures are possible, for example, instead of the point-to-point architecture of Figure 14, the system could implement a multi-drop bus or other such architecture.

[0167] Referring now to Figure 15, there is shown a block diagram of a second, more specific exemplary system 1500, in accordance with an embodiment of the present invention. Identical elements in Figures 14 and 15 have identical reference numerals, and certain aspects of Figure 14 have been omitted from Figure 15 to avoid obscuring other aspects of Figure 15.

[0168] Figure 15 shows that processors 1470, 1480 may include integrated memory and I / O control logic ("CL") 1572 and 1582, respectively. Thus, CL 1572, 1582 include integrated memory controller units and include I / O control logic. Figure 15 shows that not only memory 1432, 1434 are coupled to CL 1572, 1582, but also multiple I / O devices 1514 are coupled to CL 1572, 1582. Legacy I / O device 1515 is coupled to chipset 1490.

[0169] Referring now to FIG. 16, a block diagram of an SoC 1600 is shown in accordance with one embodiment of the present invention. Similar elements in FIG. 12 have the same reference numerals. Also, dashed boxes represent optional functionality on a more advanced SoC. In FIG. 16, an interconnect unit 1602 is coupled to an application processor 1610, a system agent unit 1210, a bus controller unit 1216, an integrated memory controller unit 1214, a set of one or more coprocessors 1620, a static random access memory (SRAM) unit 1630, a direct memory access (DMA) unit 1632, and a display unit 1640 for coupling to one or more external displays. The application processor 1610 includes a set of one or more cores 1202A-1202N, including cache units 1204A-1204N, and a shared cache unit 1206. The set of coprocessors 1620 may include integrated graphics logic, an image processor, an audio processor, and a video processor. In one embodiment, the coprocessor 1620 includes a special purpose processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, an embedded processor, or the like.

[0170] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation means. Embodiments of the present invention may be implemented as a computer program or program code running on a programmable system, the programmable system comprising at least one processor, a storage system (e.g., volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0171] 14 may be applied to input instructions to perform functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that includes a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0172] The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. Also, if desired, the program code may be implemented in assembly or machine language. Indeed, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

[0173] One or more aspects of at least one embodiment may be implemented by exemplary instructions stored on a machine-readable medium that represent various logic within a processor and, when read by a machine, cause the machine to create logic for performing the techniques described herein. Such descriptive representations, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities to be loaded into manufacturing machines that actually create the logic or processor.

[0174] Such machine-readable storage media may include non-transitory tangible configurations of articles manufactured or formed by a machine or apparatus, including, but not limited to, storage media such as hard disks, floppy disks, optical disks, any other type of disk such as compact disk read-only memory (CD-ROM), compact disk re-writeable (CD-RW) and magneto-optical disks, read-only memory (ROM), random access memory (RAM) such as dynamic random access memory (DRAM), static random access memory (SRAM), semiconductor devices such as erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic or optical cards, or any other type of medium suitable for storing electronic instructions.

[0175] Accordingly, embodiments of the present invention also include non-transitory tangible machine-readable media, such as hardware description languages (HDLs), that include instructions or include design data that define the structures, circuits, devices, processors, and / or system features described herein. Such embodiments may be referred to as program products. [Emulation (including binary translation, code morphing, etc.)]

[0176] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may interpret, morph, emulate, or otherwise convert (e.g., using static binary translation, dynamic binary translation including dynamic compilation) the instructions into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may reside within the processor, outside the processor, or partially within the processor or partially outside the processor.

[0177] Figure 17 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set, according to some embodiments of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 17 shows a program in a high-level language 1702 that may be compiled using an x86 compiler 1704 to generate x86 binary code 1706 that may be natively executed by a processor 1716 that uses at least one x86 instruction set core. The processor 1716 that uses at least one x86 instruction set core represents any processor that can perform substantially the same functions as an Intel® processor that uses at least one x86 instruction set core, and does so as follows: That is, by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of an Intel® x86 instruction set core, or (2) an object code version of an application or other software intended to run on an Intel® processor using at least one x86 instruction set core, to achieve substantially the same results as an Intel® processor using at least one x86 instruction set core. x86 compiler 1704 represents a compiler operable to generate x86 binary code 1706 (e.g., object code) executable on a processor using at least one x86 instruction set core 1716, with or without further linking.Similarly, Figure 17 shows a program in a high-level language 1702 that can be compiled using an alternative instruction set compiler 1708 to generate alternative instruction set binary code 1710 that can be natively executed by a processor 1714 that does not use at least one x86 instruction set core (e.g., a processor that executes the MIPS instruction set from MIPS Technology of Sunnyvale, California, and / or that uses multiple cores that execute the ARM instruction set from ARM Holdings of Sunnyvale, California). An instruction converter 1712 is used to convert the x86 binary code 1706 into code that the processor 1714 that does not use an x86 instruction set core can natively execute. This converted code may not be the same as the alternative instruction set binary code 1710 because an instruction converter that can do this would be difficult to create. However, the converted code implements common operations and is composed of instructions in the alternative instruction set. Thus, instruction converter 1712 represents software, firmware, hardware, or a combination thereof that enables a processor or other electronic device that does not have an x86 instruction set processor or core to execute x86 binary code 1706 through emulation, simulation, or any other process. [More examples]

[0178] Example 1 includes an exemplary system including a processor with one or more cores, a last level cache (LLC), and a cache control circuit (CCC), where the LLC has multiple ways each assigned to one of multiple priorities, with each priority associated with a class of service (CLOS) register that specifies a minimum and maximum number of ways to occupy. If an invalid cache line (CL) exists in the LLC, the CCC stores a subsequent cache line having the requestor priority among the multiple priorities in the invalid CL, or stores the subsequent CL in place of a least recently used (LRU) CL of the requestor priority if the requestor priority is the lowest among the multiple priorities and has an occupancy count that is one or more, or if the occupancy count is the largest for the requestor priority, or stores the subsequent CL in place of an LRU CL of the requestor priority or lower if the occupancy count is between the minimum and maximum for the requestor priority, or stores the subsequent CL in place of an LRU CL of the requestor priority or lower if an LRU CL exists whose occupancy count is lower than the minimum and has a lower priority, or stores the subsequent CL in place of the LRU CL of the requestor priority if there is no eviction candidate having the requestor priority or lower.

[0179] Example 2 includes the contents of the exemplary system of Example 1, where the LLC includes multiple sets of ways, the multiple ways are part of the multiple sets, and the CCC determines which of the multiple sets the subsequent CL is in based on a hashing algorithm performed on the logical address of the subsequent CL before determining where to store the subsequent CL.

[0180] Example 3 includes the contents of the exemplary system of Example 1, and further includes a cache monitoring circuit that maintains heuristics for LLC cache eviction, where if a higher than threshold percentage of cache lines with high priority are evicted to make room for subsequent CLs with lower priority, the CLOS registers for the high priority are updated to increase the minimum and maximum ways they occupy.

[0181] Example 4 includes the contents of the exemplary system of Example 1, where each of the multiple ways includes N CLs, where N is a positive integer greater than or equal to 1.

[0182] Example 5 includes the contents of the exemplary system of Example 1, and when an LRU CL with a lower priority exists and a successor CL is stored instead, the CCC flushes other CLs if they exist in the way containing the LRU CL.

[0183] Example 6 includes the contents of the exemplary system of Example 1, where one or more cores each implement a virtual machine and the CCC includes a hypervisor.

[0184] Example 7 includes the exemplary system of Example 1, where the processor is one of multiple processors in a data center of a cloud service provider.

[0185] Example 8 includes an exemplary method performed by a cache control circuit (CCC) in a system including a processor with one or more cores and a last level cache (LLC) having multiple ways each assigned to one of multiple priorities, each priority associated with a class of service (CLOS) register that specifies a minimum and maximum number of ways to occupy. The method includes receiving a request to store a successor cache line (CL) having a requester priority among a plurality of priorities in an LLC; if an invalid CL exists in the LLC, storing the successor CL in the invalid CL; or, if the requester priority is the lowest among the plurality of priorities and has an occupancy count that is one or more, or the occupancy count is the largest for the requester priority, storing the successor CL instead of a least recently used (LRU) CL of the requester priority; or, if the occupancy count is between the minimum and maximum for the requester priority, storing the successor CL instead of an LRU CL of the requester priority or a lower priority; or, if an LRU CL having an occupancy count lower than the minimum and a lower priority exists, storing the successor CL instead of the LRU CL; or, if there is no eviction candidate having the requester priority or a lower priority, storing the successor CL instead of an LRU CL of a higher priority than the requester priority.

[0186] Example 9 includes the content of the exemplary method of Example 8, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC determines which of the multiple sets the subsequent CL is included in based on a hashing algorithm performed on the logical address of the subsequent CL before determining where to store the subsequent CL.

[0187] Example 10 includes the exemplary method of Example 8, and uses LLC cache monitoring circuitry to maintain heuristics for LLC cache eviction, and updates CLOS registers for high priorities to increase the minimum and maximum ways they occupy when a higher than threshold percentage of cache lines with high priorities are evicted to make room for subsequent CLs with lower priorities to fill.

[0188] Example 11 includes the exemplary method of Example 8, wherein each of the multiple ways includes N CLs, where N is a positive integer greater than or equal to 1.

[0189] Example 12 includes the contents of the exemplary method of Example 8, and when an LRU CL with a lower priority exists and a successor CL is stored instead, the CCC flushes other CLs, if any, in the way containing the LRU CL.

[0190] Example 13 includes the exemplary method of Example 8, wherein the one or more cores each implement a virtual machine, and the CCC includes a hypervisor.

[0191] Example 14 includes the exemplary method of Example 8, wherein the processor is one of a plurality of processors in a data center of a cloud service provider.

[0192] Example 15 includes an exemplary non-transitory computer-readable medium including instructions to which a cache control circuit (CCC) in a system including a processor with one or more cores and a last level cache (LLC) having multiple ways each assigned to one of multiple priorities, each priority associated with a class of service (CLOS) register that specifies a minimum and maximum number of ways to occupy. The response is performed by storing a successor CL having a requester priority among multiple priorities in an invalid cache line (CL) in the invalid CL if the invalid CL exists; or by storing the successor CL in place of a least recently used (LRU) CL for the requester priority if the requester priority is the lowest among multiple priorities and has an occupancy count of one or more, or the occupancy count is the highest for the requester priority; or by storing the successor CL in place of an LRU CL of the requester priority or lower if the occupancy count is between the minimum and maximum for the requester priority; or by storing the successor CL in place of an LRU CL of the requester priority or lower if an LRU CL exists with an occupancy count lower than the minimum and a lower priority; or by storing the successor CL in place of the LRU CL of a higher priority than the requester priority if there is no eviction candidate having the requester priority or lower.

[0193] Example 16 includes exemplary non-transitory computer-readable medium content of the exemplary method of Example 15, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC, further responsive to the instruction, determines in which of the multiple sets the subsequent CL is included based on a hashing algorithm performed on the logical address of the subsequent CL before determining where to store the subsequent CL.

[0194] Example 17 includes an example non-transitory computer-readable medium content of the example method of Example 15, wherein the processor is one of a plurality of processors in a data center of a cloud service provider.

[0195] Example 18 includes an exemplary non-transitory computer-readable medium of the exemplary method of Example 15, wherein each of the plurality of ways includes N CLs, where N is a positive integer greater than or equal to 1.

[0196] Example 19 includes an exemplary non-transitory computer-readable medium content of the exemplary method of Example 15, wherein when an LRU CL with a lower priority exists and a successor CL is stored instead, the CCC flushes other CLs, if any, in the way containing the LRU CL.

[0197] Example 20 includes an exemplary non-transitory computer-readable medium content of the exemplary method of Example 15, wherein the one or more cores each implement a virtual machine and the CCC includes a hypervisor.

[0198] [Other possible items] (Item 1) A last level cache (LLC) having a plurality of ways each assigned to one of a plurality of priorities, each priority associated with a class of service (CLOS) register specifying a minimum and maximum number of ways to occupy; and a cache control circuit (CCC), wherein, when an invalid cache line (CL) exists in the LLC, a successor cache line (CL) having a requestor priority that is one of the plurality of priorities is stored in the invalid CL, and, if the requestor priority is the lowest of the plurality of priorities and has an occupancy count that is one or more, or if the occupancy count is the largest for the requestor priority, the successor CL is stored in place of a least recently used (LRU) CL of the requestor priority, and, if the occupancy count is between the minimum and the maximum for the requestor priority, the successor CL is stored in place of an LRU CL of the requestor priority or a lower priority, and, if the occupancy count is lower than the minimum and a CL having a lower priority exists, the LRU CL having the lower priority is stored. and a CCC that stores the successor CL in place of a CL, and if there is no invalid CL or a CL having the requestor priority or a lower priority, stores the successor CL in place of a higher priority LRU CL. (Item 2) The system described in Item 1, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC determines which of the multiple sets the subsequent CL is included in based on a hashing algorithm performed on the logical address of the subsequent CL before determining where to store the subsequent CL. (Item 3) The system described in Item 1 further comprises a cache monitoring circuit that maintains heuristics regarding LLC cache eviction, and when a percentage of cache lines with high priority greater than a threshold are evicted to make room for subsequent CLs with lower priority, the CLOS register for the high priority is updated to increase the minimum and maximum ways occupied. (Item 4) The system according to item 1, wherein each of the plurality of ways includes N CLs, where N is a positive integer greater than or equal to 1. (Item 5) The system described in Item 1, wherein when there is an LRU CL with a lower priority and the successor CL is stored instead, the CCC flushes other CLs if they exist in the way containing the LRU CL. (Item 6) The system described in Item 1, further comprising a processor incorporating the LLC and the CCC, each having one or more cores that implement a virtual machine, wherein the CCC includes a hypervisor. (Item 7) The system according to item 6, wherein the processor is one of multiple processors in a data center of a cloud service provider. (Item 8) A method executed by a cache control circuit (CCC) in a system including a last level cache (LLC) having a plurality of ways each assigned to one of a plurality of priorities, each priority associated with a class of service (CLOS) register specifying a minimum and maximum number of ways to occupy, the method comprising: receiving a request to store a successor cache line (CL) having a requester priority among the plurality of priorities in the LLC; if an invalid CL exists in the LLC, storing the successor CL in the invalid CL; if the requester priority is the lowest of the plurality of priorities and has an occupancy count of one or more, or if the occupancy count is the maximum for the requester priority, storing the successor CL in place of a least recently used (LRU) CL of the requester priority; if the occupancy count is between the minimum and the maximum for the requester priority, storing the successor CL in place of an LRU CL of the requester priority or a lower priority; if the occupancy count is lower than the minimum and a CL with a lower priority exists, storing the successor CL in place of an LRU CL of the requester priority or a lower priority. storing the successor CL in place of a CL; and if there is no invalid CL or a CL having the requestor priority or a lower priority, storing the successor CL in place of a higher priority LRU CL. (Item 9) The method described in Item 8, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC determines in which of the multiple sets the subsequent CL is included based on a hashing algorithm performed on the logical address of the subsequent CL before determining where to store the subsequent CL. (Item 10) The method described in Item 8, using an LLC cache monitoring circuit to maintain heuristics for LLC cache eviction, and if a percentage of cache lines with high priority higher than a threshold are evicted to make room to fill subsequent CLs with lower priority, updating the CLOS register for the high priority to increase the minimum and maximum ways occupied. (Item 11) The method according to Item 8, wherein each of the plurality of ways includes N CLs, where N is a positive integer greater than or equal to 1. (Item 12) The method described in Item 8, wherein when there is an LRU CL with a lower priority and the successor CL is stored instead, the CCC flushes other CLs if they exist in the way containing the LRU CL. (Item 13) The method described in Item 8, wherein the system further includes a processor incorporating the LLC and the CCC, each having one or more cores that implement a virtual machine, and the CCC includes a hypervisor. (Item 14) The method of item 13, wherein the processor is one of multiple processors in a data center of a cloud service provider. (Item 15) A non-transitory computer-readable medium containing instructions for a cache control circuit (CCC) in a system including a last level cache (LLC) having a plurality of ways each assigned to one of a plurality of priorities, each priority associated with a class of service (CLOS) register specifying a minimum and maximum number of ways to occupy, the response including receiving a request to store a subsequent cache line (CL) having a requester priority among the plurality of priorities in the LLC; if an invalid CL exists in the LLC, storing the subsequent CL in the invalid CL; if the requester priority is the lowest of the plurality of priorities and has an occupancy count that is one or more, or if the occupancy count is the maximum for the requester priority, storing the subsequent CL in place of a least recently used (LRU) CL of the requester priority; and if the occupancy count is between the minimum and the maximum for the requester priority, storing the subsequent CL in place of an LRU CL of the requester priority or a lower priority. storing the successor CL in place of a CL; if a CL exists whose occupancy number is lower than the minimum and has the lower priority, storing the successor CL in place of an LRU CL with the lower priority; and if there is no invalid CL or a CL with the requestor priority or a lower priority, storing the successor CL in place of an LRU CL with a higher priority. (Item 16) The non-transitory computer-readable medium described in Item 15, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC, further responsive to the instruction, determines in which of the multiple sets the subsequent CL is included based on a hashing algorithm performed on the logical address of the subsequent CL before determining where to store the subsequent CL. (Item 17) The non-transitory computer-readable medium described in Item 15, wherein the system further comprises a processor incorporating the LLC and the CCC, the processor being one of multiple processors within a cloud service provider's data center. (Item 18) The non-transitory computer-readable medium of item 15, wherein each of the plurality of ways includes N CLs, where N is a positive integer greater than or equal to 1. (Item 19) A non-transitory computer-readable medium as described in Item 15, wherein when an LRU CL with a lower priority exists and the successor CL is stored instead, the CCC flushes other CLs if they exist in the way containing the LRU CL. (Item 20) The non-transitory computer-readable medium described in Item 15, wherein the system further comprises a processor incorporating the LLC and the CCC, each having one or more cores that implement a virtual machine, and the CCC includes a hypervisor.

Claims

1. a last level cache (LLC) having a plurality of ways each assigned to one of a plurality of priorities, each priority associated with a class of service register (CLOS register) specifying a minimum and maximum number of ways to occupy; A cache control circuit (CCC) If an invalid cache line (invalid CL) exists in the LLC, storing a subsequent cache line (successor CL) having a requestor priority that is one of the plurality of priorities in the invalid CL; storing the successor CL in place of a least recently used (LRU) CL for the requester priority if the requester priority is the lowest of the plurality of priorities and has an occupancy count that is one or more, or if the occupancy count is the highest for the requester priority; if the occupancy number is between a minimum and the maximum for the requester priority, storing the successor CL in place of an LRU CL of the requester priority or lower; If the occupancy number is lower than the minimum and a CL with the lower priority exists, storing the successor CL instead of the LRU CL with the lower priority; a CCC that stores the successor CL in place of a higher priority LRU CL if there is no invalid CL or a CL with the requestor priority or a lower priority; A system comprising:

2. 2. The system of claim 1, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC determines in which of the multiple sets the successor CL is included based on a hashing algorithm performed on the logical address of the successor CL before determining where to store the successor CL.

3. further comprising a cache monitoring circuit that maintains heuristics regarding LLC cache eviction; 2. The system of claim 1, wherein if a higher than threshold percentage of cache lines with high priority are evicted to make room for subsequent CLs with lower priority, the CLOS register for the high priority is updated to increase the minimum and maximum ways occupied.

4. The system of claim 1 , wherein each of the plurality of ways includes N CLs, where N is a positive integer greater than or equal to 1.

5. 2. The system of claim 1, wherein when the LRU CL having the lower priority exists and the successor CL is stored instead, the CCC flushes other CLs if they exist in a way containing the LRU CL.

6. The system of claim 1 , further comprising a processor incorporating the LLC and the CCC, each having one or more cores that implement a virtual machine, wherein the CCC includes a hypervisor.

7. The system of claim 6 , wherein the processor is one of a plurality of processors in a data center of a cloud service provider.

8. 1. A method performed by a cache control circuit (CCC) in a system having a last level cache (LLC) having a plurality of ways each assigned to one of a plurality of priorities, each priority associated with a class of service register (CLOS register) that specifies a minimum and maximum number of ways to occupy, comprising: receiving a request to store a successor cache line (successor CL) having a requestor priority among the plurality of priorities in the LLC; If an invalid CL exists in the LLC, storing the subsequent CL in the invalid CL; storing the successor CL in place of a least recently used (LRU) CL of the requester priority if the requester priority is the lowest of the plurality of priorities and has an occupancy count that is one or more, or if the occupancy count is the highest for the requester priority; storing the successor CL in place of an LRU CL of the requestor priority or lower if the occupancy number is between a minimum and the maximum for the requestor priority; storing the successor CL instead of the LRU CL having the lower priority if the occupancy number is lower than the minimum and a CL having the lower priority exists; storing the successor CL in place of a LRU CL with a higher priority if there is no invalid CL or a CL with the requestor priority or a lower priority; A method comprising:

9. 9. The method of claim 8, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC determines in which of the multiple sets the successor CL is included based on a hashing algorithm performed on the logical address of the successor CL before determining where to store the successor CL.

10. maintaining heuristics for LLC cache eviction using LLC cache monitoring circuitry; 9. The method of claim 8, further comprising: updating the CLOS register for a high priority cache line to increase the minimum and maximum ways occupied if a higher than threshold percentage of the high priority cache lines are evicted to make room for subsequent CLs with lower priorities.

11. The method of claim 8 , wherein each of the plurality of ways includes N CLs, where N is a positive integer greater than or equal to 1.

12. 9. The method of claim 8, wherein when the LRU CL having the lower priority exists and the successor CL is stored instead, the CCC flushes other CLs if they exist in the way containing the LRU CL.

13. 13. The method of claim 8, wherein the system further comprises a processor incorporating the LLC and the CCC, each processor having one or more cores that implement a virtual machine, the CCC including a hypervisor.

14. The method of claim 13 , wherein the processor is one of a plurality of processors in a data center of a cloud service provider.

15. 1. A computer program product comprising instructions to be responded to by a cache control circuit (CCC) in a system having a last level cache (LLC) having a plurality of ways each assigned to one of a plurality of priorities, each priority associated with a class of service (CLOS) register specifying a minimum and maximum number of ways to occupy, the response comprising: receiving a request to store a successor cache line (successor CL) having a requestor priority among the plurality of priorities in the LLC; If an invalid CL exists in the LLC, storing the succeeding CL in the invalid CL; storing the successor CL in place of a least recently used (LRU) CL for the requester priority if the requester priority is the lowest of the plurality of priorities and has an occupancy count that is one or more, or if the occupancy count is the highest for the requester priority; storing the successor CL in place of an LRU CL of the requestor priority or lower if the occupancy number is between a minimum and the maximum for the requestor priority; If the occupancy number is lower than the minimum and a CL with the lower priority exists, storing the successor CL instead of the LRU CL with the lower priority; if there is no invalid CL or a CL having the requestor priority or a priority lower than the requestor priority, storing the successor CL in place of a higher priority LRU CL; A computer program implemented by

16. 16. The computer program product of claim 15, wherein the LLC includes multiple sets of ways, the multiple ways being part of the multiple sets, and the CCC, in response to the instruction, determines in which of the multiple sets the successor CL is included based on a hashing algorithm performed on the logical address of the successor CL before determining where to store the successor CL.

17. 16. The computer program product of claim 15, wherein the system further comprises a processor that houses the LLC and the CCC, the processor being one of a plurality of processors in a data center of a cloud service provider.

18. The computer program product of claim 15 , wherein each of the plurality of ways includes N CLs, where N is a positive integer greater than or equal to 1.

19. 16. The computer program product of claim 15, wherein when the LRU CL having the lower priority exists and the successor CL is stored instead, the CCC flushes other CLs if they exist in a way containing the LRU CL.

20. 20. The computer program product of claim 15, wherein the system further comprises a processor incorporating the LLC and the CCC, each processor having one or more cores that implement a virtual machine, and the CCC includes a hypervisor.

21. A non-transitory computer readable medium storing a computer program according to any one of claims 15 to 20.

Images