Semiconductor device

Abstract

To provide a semiconductor device capable of improving the EM life.SOLUTION: The semiconductor device that makes up an upper and lower arm circuit for one phase includes joints 80 and 81 connected via a solder 104. Each of the multiple solders electrically connected to the main electrode of the semiconductor element includes Cu and Sn. Each solder connection target has a Ni layer. The solder 104 includes Cu and Sn, and the joint parts 80 and 81 have Ni layers 801 and 811. The particle size of the solder 104 is smaller than the particle size of the solder to which the collector electrode is connected.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] TECHNICAL FIELD The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor element that configures the upper arm and a semiconductor element that configures the lower arm of an upper and lower arm circuit. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-92166 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device described above includes a joint conductor that connects, via solder, a conductor connected to a low-potential main electrode of a semiconductor element that constitutes an upper arm and a conductor connected to a high-potential main electrode of a semiconductor element that constitutes a lower arm. The joint area of the solder joint of the joint conductor is small. In Patent Document 1, a Ni layer is provided on the joint conductor to suppress the progression of EM in the solder joint of the joint conductor. EM is an abbreviation for Electromigration.

[0005] As carbon neutrality is advocated and the shift to electric vehicles is progressing, semiconductor devices are required to be further miniaturized and capable of handling larger currents. In other words, further improvements are required to improve EM life. Further improvements are required for semiconductor devices in the above-mentioned respects and in other respects not mentioned.

[0006] The present disclosure has been made in view of such problems, and aims to provide a semiconductor device that can improve the EM lifetime. [Means for solving the problem]

[0007] One disclosed semiconductor device is: a plurality of semiconductor elements (40) each having a signal pad and an upper electrode as a main electrode on its upper surface, and a lower electrode as a main electrode on its lower surface, which is the surface opposite to the upper surface in the thickness direction, and having a larger area than the upper electrode when viewed in a plan view from the thickness direction; a plurality of conductors (50, 60, 70, 80, 81, 82, 92) electrically connected to the main electrodes via solder; the plurality of semiconductor elements include a first semiconductor element (40H) constituting an upper arm (9H) of the upper and lower arm circuit (9), and a second semiconductor element (40L) constituting a lower arm (9L) of the upper and lower arm circuit, and arranged side by side with the first semiconductor element in one direction perpendicular to the plate thickness direction so that their upper surfaces are on the same side in the plate thickness direction; The plurality of conductors include first upper conductors (50H, 70H) connected to the upper electrodes of the first semiconductor elements via first upper solders (101H, 102H), first lower conductors (60H) connected to the lower electrodes of the first semiconductor elements via first lower solders (103H), second upper conductors (50L, 70L) connected to the upper electrodes of the second semiconductor elements via second upper solders (101L, 102L), second lower conductors (60L) connected to the lower electrodes of the second semiconductor elements via second lower solders (103L), and joint conductors (80, 81) connecting the first upper conductors and the second lower conductors via relay solders (104), Each solder contains Cu and Sn, Each of the solder connection targets has a Ni layer (801, 811), the particle size of at least one of the first upper solder, the second upper solder, and the relay solder is smaller than the particle size of the first lower solder and the second lower solder; The small solder particles, which are smaller in particle size than the first lower solder and the second lower solder, have solidification starting points for reducing the particle size inside the small solder particles or on the surface of the object to be connected to the small solder particles.

[0008] In a configuration in which the upper electrode is smaller than the lower electrode and includes a joint conductor, the current density in the first upper solder, the second upper solder, and the relay solder is higher than the current density in the first lower solder and the second lower solder. According to the disclosed semiconductor device, the grain size of at least one of the first upper solder, the second upper solder, and the relay solder, which has a high current density, is smaller than the grain size of the first lower solder and the second lower solder. This slows the loss of the Ni layer due to EM. As a result, a semiconductor device with improved EM life can be provided.

[0009] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing a schematic configuration of a vehicle drive system to which a semiconductor device according to a first embodiment is applied; [Figure 2] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] FIG. [Figure 6] FIG. 10 is a plan view in which the heat sink on the emitter electrode side is omitted. [Figure 7] FIG. 2 is a diagram showing an output current and a reflux current. [Figure 8] FIG. 8 is an enlarged cross-sectional view of region VIII in FIG. 3. [Figure 9] FIG. 2 is an enlarged cross-sectional view of the vicinity of the solder joint surface of the joint portion. [Figure 10] FIG. 10 is a cross-sectional view showing a reference example. [Figure 11] This is a reference diagram showing the mechanism of EM progression. [Figure 12] FIG. [Figure 13] 10 is an enlarged cross-sectional view of the vicinity of a solder joint surface of a joint portion in a semiconductor device according to a second embodiment. FIG. [Figure 14] FIG. 10 is a plan view showing a heat sink including a joint portion in a semiconductor device according to a third embodiment. [Figure 15] FIG. 15 is an enlarged view of region XV in FIG. 14. [Figure 16] FIG. 10 is a cross-sectional view showing a soldered joint structure of a joint portion in a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0012] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile object using a rotating electric machine as a drive source. The mobile object may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0013] (First embodiment) First, a schematic configuration of a vehicle drive system 1 will be described with reference to FIG.

[0014] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0015] The DC power supply 2 is a DC voltage source made up of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0016] <Power conversion device> Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. As shown in Fig. 1, the power conversion device 4 includes a smoothing capacitor 5 and an inverter 6, which is a power conversion circuit.

[0017] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power line on the high potential side, and an N line 8, which is a power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. Similarly, the negative electrode is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0019] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is made up of a conductive member such as a bus bar.

[0020] The elements constituting each arm include an IGBT 11 which is a switching element and a freewheeling diode 12. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In this embodiment, an n-channel IGBT 11 is used. The diode 12 is connected in anti-parallel to the corresponding IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. The emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the emitter of the corresponding IGBT 11, and the cathode is connected to the collector.

[0021] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage increase and decrease. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0022] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the IGBT 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding IGBT 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0023] The power conversion device 4 may include a control circuit for the switching elements. The control circuit generates a drive command for operating the IGBT 11 and outputs it to the drive circuit. The control circuit generates the drive command based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as the drive command. The control circuit is configured to include, for example, a processor and a memory. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.

[0024] <Semiconductor device> Next, a schematic configuration of the semiconductor device 20 will be described with reference to Figs. 2 to 6. Fig. 2 is a plan view showing the semiconductor device 20. Fig. 2 is a top plan view of the semiconductor device 20. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2. Fig. 5 is a view in which the sealing body 30 is omitted from Fig. 2. Fig. 6 is a view in which the heat sink 50 on the emitter electrode 42 side is omitted from Fig. 5.

[0025] Some of the elements constituting the semiconductor device are designated by the suffix "H" indicating the upper arm 9H side and "L" indicating the lower arm 9L side. For the rest of the elements, the same reference numerals are used for both the upper arm 9H and the lower arm 9L for convenience.

[0026] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the X direction. The direction perpendicular to both the Z direction and the X direction is referred to as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. Furthermore, the planar view from the Z direction may sometimes be simply referred to as the planar view.

[0027] 2 to 6, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, heat sinks 50 and 60, a conductive spacer 70, joints 80 to 82, and an external connection terminal 90. The semiconductor device 20 further includes a bonding wire 97 and solder 100. The semiconductor device 20 constitutes the upper and lower arm circuits 9 for one phase described above.

[0028] The encapsulant 30 encapsulates some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed outside the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of a resin is an epoxy-based resin. The encapsulant 30 is molded using, for example, a transfer molding method using a resin. Such a encapsulant 30 may be referred to as an encapsulating resin body, a molded resin, a resin molded body, or the like. The encapsulant 30 may be formed using, for example, a gel. The gel is filled (placed) in the opposing regions of the heat sinks 50 and 60, for example.

[0029] As shown in FIGS. 2 to 4, the sealing body 30 has a generally rectangular planar shape. The sealing body 30 has one surface 30a as its outer surface and a back surface 30b opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, generally flat surfaces. The sealing body 30 also has side surfaces 30c, 30d, 30e, and 30f connected to the one surface 30a and the back surface 30b. The side surface 30c is the surface from which main terminals 91 to 93 of the external connection terminals 90 protrude. The side surface 30d is the surface opposite to the side surface 30c in the Y direction. The side surface 30d is the surface from which the signal terminal 94 protrudes. The side surfaces 30e and 30f are surfaces from which the external connection terminals 90 do not protrude. The side surface 30e is the surface opposite to the side surface 30f in the X direction.

[0030] The semiconductor element 40 includes a semiconductor substrate 41, an emitter electrode 42, a collector electrode 43, and a pad 44. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is made of a material such as silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon, and a vertical element is formed on the semiconductor substrate 41. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0031] The vertical element is configured to pass a main current in the thickness direction of the semiconductor substrate 41 (semiconductor element 40), i.e., in the Z direction. The vertical element of this embodiment is an IGBT 11 and a diode 12 that form one arm. The vertical element is an IGBT with the diode 12 connected in antiparallel, i.e., an RC-IGBT. RC stands for Reverse Conducting. The vertical element is a heat-generating element that generates heat when current is applied. A gate electrode (not shown) is formed on the semiconductor substrate 41. The gate electrode has, for example, a trench structure.

[0032] The semiconductor substrate 41 has a generally rectangular shape in plan view. An emitter electrode 42, which is one of the main electrodes, is disposed on one surface of the semiconductor substrate 41. A collector electrode 43, which is the other of the main electrodes, is disposed on the back surface of the semiconductor substrate 41. The one surface of the semiconductor substrate 41 is the surface of the main surface of the semiconductor substrate 41 that faces the first surface 30a of the sealing body 30 in the thickness direction. The back surface of the semiconductor substrate 41 is the surface of the main surface of the semiconductor substrate 41 that faces the back surface 30b of the sealing body 30 in the thickness direction.

[0033] When the IGBT 11 is turned on, a current (main current) flows between the main electrodes, that is, between the emitter electrode 42 and the collector electrode 43. The emitter electrode 42 also serves as the anode electrode of the diode 12. The collector electrode 43 also serves as the cathode electrode of the diode 12. The collector electrode 43 is formed on almost the entire back surface of the semiconductor substrate 41. The emitter electrode 42 is formed on a portion of one surface of the semiconductor substrate 41. That is, in a plan view, the collector electrode 43 has a larger area than the emitter electrode 42. The emitter electrode 42 corresponds to an upper electrode, and the collector electrode 43 corresponds to a lower electrode.

[0034] The emitter electrode 42 has a Ni layer formed using a material containing Ni (nickel) as its main component. The emitter electrode 42 of this embodiment has an Al layer formed using a material containing Al (aluminum) as its main component, and a Ni layer laminated on the Al layer. Like the emitter electrode 42, the collector electrode 43 also has an Al layer and a Ni layer.

[0035] The pads 44 are electrodes for signals. The pads 44 are formed on one surface of the semiconductor substrate 41 in a region different from the region where the emitter electrodes 42 are formed. The pads 44 are formed at the end opposite the region where the emitter electrodes 42 are formed in the Y direction. The pads 44 are provided alongside the emitter electrodes 42 in the Y direction. The number of pads 44 is not particularly limited. The pads 44 include at least a pad for a gate electrode.

[0036] As an example, the semiconductor element 40 has five pads 44. Specifically, there are pads for a gate electrode, for detecting an emitter potential, for detecting a cathode potential of a temperature-sensitive diode (not shown) included in the semiconductor element 40, for detecting an anode potential of the same, and for sensing a current. The five pads 44 are aligned in the X direction.

[0037] The semiconductor device 20 includes two semiconductor elements 40. Specifically, the semiconductor element 40H forms the upper arm 9H, and the semiconductor element 40L forms the lower arm 9L. The semiconductor element 40H may be referred to as a first semiconductor element, an upper arm element, etc. The semiconductor element 40L may be referred to as a second semiconductor element, a lower arm element, etc. The semiconductor elements 40H and 40L have the same specifications, i.e., are common components. The semiconductor elements 40H and 40L are aligned in the X direction. The semiconductor elements 40H and 40L are arranged at approximately the same position as each other in the Z direction. The semiconductor elements 40H and 40L are arranged so that their respective surfaces, i.e., their emitter electrodes 42, are located on the same side in the Z direction.

[0038] The heat sink 50 is electrically connected to the emitter electrode 42 and provides a wiring function. Similarly, the heat sink 60 is electrically connected to the collector electrode 43 and provides a wiring function. The heat sinks 50, 60 provide a heat dissipation function that dissipates heat generated by the semiconductor element 40. For this reason, the heat sinks 50, 60 are sometimes referred to as wiring members, conductive members, heat dissipation members, etc. The heat sinks 50, 60 are arranged to sandwich the semiconductor element 40 in the Z direction. The heat sinks 50, 60 are arranged so that at least portions of them face each other in the Z direction. The heat sinks 50, 60 enclose the semiconductor element 40 in a plan view.

[0039] The heat sinks 50 and 60 are metal plates made of a metal with good conductivity, such as Cu or a Cu alloy. The metal plate is provided, for example, as part of a lead frame. The heat sinks 50 and 60 have a Ni layer formed on their surfaces by plating or other processes. The heat sinks 50 and 60 have the Ni layer at least on the solder joint surfaces.

[0040] Instead of the heat sinks 50 and 60, a substrate having metal bodies disposed on both sides of an insulating base material such as ceramic or resin may be used as the wiring member. In this case, the metal body on the semiconductor element 40 side corresponds to the conductor to be soldered, i.e., the upper conductor or the lower conductor. The metal body on the semiconductor element 40 side has a Ni layer on its surface.

[0041] The heat sink 50 has an opposing surface 50a, which is the surface facing the semiconductor element 40, and a back surface 50b, which is the surface opposite the opposing surface 50a. Similarly, the heat sink 60 also has an opposing surface 60a and a back surface 60b. The back surfaces 50b, 60b of the heat sinks 50, 60, respectively, are exposed from the sealing body 30. The back surfaces 50b, 60b are sometimes referred to as heat dissipation surfaces, exposed surfaces, etc. The back surface 50b of the heat sink 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the heat sink 60 is substantially flush with the back surface 30b of the sealing body 30.

[0042] The semiconductor device 20 includes two heat sinks 50. Specifically, the semiconductor device 20 includes a heat sink 50H that constitutes the upper arm 9H and a heat sink 50L that constitutes the lower arm 9L. The heat sink 50H corresponds to the first body portion of the first upper conductor, and the heat sink 50L corresponds to the second body portion of the second upper conductor.

[0043] As shown in FIG. 5, the heat sinks 50H, 50L have a generally rectangular shape in plan view. The heat sinks 50H, 50L are aligned in the X direction. As shown in FIGS. 3 and 4, the heat sinks 50H, 50L have approximately the same thickness and are disposed at approximately the same positions in the Z direction. The heat sinks 50H, 50L contain the corresponding semiconductor elements 40 and conductive spacers 70 in plan view. A groove 51 for accommodating overflowing solder is formed in the opposing surface 50a of each of the heat sinks 50H, 50L. The groove 51 surrounds the solder joint on the opposing surface 50a. The groove 51 is formed, for example, in a ring shape. The back surfaces 50b of the heat sinks 50H, 50L exposed from the sealing body 30 are aligned in the X direction.

[0044] The semiconductor device 20 includes two heat sinks 60. Specifically, the semiconductor device 20 includes a heat sink 60H that constitutes the upper arm 9H and a heat sink 60L that constitutes the lower arm 9L. The heat sink 60H corresponds to the first lower conductor, and the heat sink 60L corresponds to the second lower conductor.

[0045] As shown in Fig. 6, the heat sinks 60H, 60L have a generally rectangular shape in plan view. The heat sinks 60H, 60L are aligned in the X direction. As shown in Figs. 3 and 4, the heat sinks 60H, 60L have approximately the same thickness and are arranged at approximately the same position in the Z direction. The heat sinks 60H, 60L house the corresponding semiconductor elements 40 in plan view. The back surfaces 60b of the heat sinks 60H, 60L exposed from the sealing body 30 are aligned in the X direction.

[0046] The conductive spacer 70 is interposed between the semiconductor element 40 and the heat sink 50 in the Z direction. The conductive spacer 70 provides a spacer function that ensures a predetermined distance between the semiconductor element 40 and the heat sink 50. For example, the conductive spacer 70 ensures the height required to electrically connect the corresponding signal terminal 94 to the pad 44 of the semiconductor element 40. The conductive spacer 70 is located midway along the electrical and thermal conduction paths between the emitter electrode 42 of the semiconductor element 40 and the heat sink 50, and provides wiring and heat dissipation functions. The conductive spacer 70, together with the heat sink 50, constitutes an upper conductor.

[0047] The conductive spacer 70 is a metal member made of a metal such as Cu that has good electrical and thermal conductivity. The conductive spacer 70 may also be called a terminal, a terminal block, or a metal block. The conductive spacer 70 has a Ni layer formed on its surface by plating or the like. The conductive spacer 70 has a Ni layer at least on the solder joint surface. The conductive spacer 70 of this embodiment is a columnar body with a generally rectangular shape in plan view that is approximately the same size as the emitter electrode 42.

[0048] The semiconductor device 20 includes two conductive spacers 70. Specifically, the semiconductor device 20 includes a conductive spacer 70H that constitutes the upper arm 9H and a conductive spacer 70L that constitutes the lower arm 9L. The conductive spacer 70H corresponds to the first spacer portion of the first upper conductor, and the conductive spacer 70L corresponds to the second spacer portion of the second upper conductor.

[0049] The joints 80 to 82 connect the elements that make up the upper and lower arm circuits 9. The joints 80 to 82 connect the elements that make up the semiconductor device 20. The joints 80 to 82 are metal members made of a metal with good electrical and thermal conductivity, such as Cu. The joints 80 to 82 have a Ni layer formed on their surfaces by plating or the like. The joints 80 to 82 have a Ni layer at least on the solder joint surfaces.

[0050] As shown in FIGS. 3 and 6, the joint part 80 is connected to the heat sink 60L. The joint part 80 is thinner than the heat sink 60L. The joint part 80 is connected to the opposing surface (side surface) of the heat sink 60H, for example, in a state where it is substantially flush with the opposing surface 60a of the heat sink 60L. The joint part 80 has two bent parts, and thus is substantially crank-shaped in the ZX plane. The joint part 80 is covered by the sealing body 30.

[0051] The joint part 80 may be provided integrally and continuously with the heat sink 60L, or may be provided as a separate member and connected by bonding. The joint part 80 of this embodiment is provided integrally with the heat sink 60L as part of the lead frame. The Ni layer is provided integrally and continuously with the heat sink 60L and the joint part 80.

[0052] As shown in Figures 3, 4, and 5, the joints 81 and 82 are connected to the corresponding heat sinks 50. The joint 81 is connected to the heat sink 50H. The joint 82 is connected to the heat sink 50L. The joints 81 and 82 are thinner than the corresponding heat sinks 50. The joints 81 and 82 are covered with the sealing body 30.

[0053] The joints 81, 82 may be connected by being provided continuously and integrally with the heat sink 50, or may be provided as separate members and connected by joining. In this embodiment, the joints 81, 82 are provided integrally with the corresponding heat sinks 50H, 50L. The joints 81, 82 extend in the X direction from the opposing side surfaces of the heat sinks 50H, 50L. The Ni layer is provided continuously and integrally with the heat sink 50H and the joint 81. The Ni layer is provided continuously and integrally with the heat sink 50L and the joint 82. As an example, the heat sink 50H including the joint portion 81 and the heat sink 50L including the joint portion 82 are common components. The heat sink 50H including the joint portion 81 and the heat sink 50L including the joint portion 82 are arranged in dyad symmetry with the Z axis as the axis of rotation. Solder is interposed between the opposing surfaces of the joint portion 80 and the joint portion 81, forming a soldered joint. As shown in FIG. 5, the joint portions 81 and 82 are arranged between the heat sinks 50H and 50L in a plan view. The joint portions 81 and 82 are aligned in the Y direction between the heat sinks 50H and 50L.

[0054] A groove 83 for accommodating overflowing solder is formed on the joint surfaces of the joint parts 81 and 82. The groove 83 is formed in a ring shape so as to surround the solder joint part. The groove 83 is formed by, for example, press working. The joint parts 80 and 81 correspond to the joint conductor and the first joint conductor. The joint part 82 corresponds to the second joint conductor.

[0055] The external connection terminals 90 are terminals for electrically connecting the semiconductor device 20 to external devices. The external connection terminals 90 are formed using a metal material with good conductivity, such as copper. The external connection terminals 90 are, for example, a plate material. The external connection terminals 90 are sometimes called leads. The external connection terminals 90 include main terminals 91, 92, and 93 and a signal terminal 94. The main terminals 91, 92, and 93 are external connection terminals 90 electrically connected to main electrodes of the semiconductor element 40.

[0056] As shown in FIGS. 5 and 6 , the main terminal 91 is electrically connected to the collector electrode 43 of the semiconductor element 40H. The main terminal 91 is electrically connected to the positive terminal of the smoothing capacitor 5. The main terminal 91 may also be referred to as a P terminal, a high-potential power supply terminal, or the like. The main terminal 91 is connected to the collector electrode 43 of the semiconductor element 40H via the heat sink 60H. The main terminal 91 is connected to one end of the heat sink 60H in the Y direction. The thickness of the main terminal 91 is thinner than that of the heat sink 60H. The main terminal 91 is connected to the heat sink 60H so as to be, for example, substantially flush with the opposing surface 60a. The main terminal 91 may be connected by being provided integrally and continuously with the heat sink 60H, or may be provided as a separate member and connected by joining.

[0057] In this embodiment, the main terminal 91 is provided integrally with the heat sink 60H as part of the lead frame. The main terminal 91 extends in the Y direction from the heat sink 60H and protrudes to the outside from the side surface 30c of the sealing body 30. The main terminal 91 has a bent portion midway through the portion covered by the sealing body 30, and protrudes from near the center in the Z direction on the side surface 30c.

[0058] 5 and 6, the main terminal 92 is electrically connected to the emitter electrode 42 of the semiconductor element 40L. The main terminal 92 is electrically connected to the negative terminal of the smoothing capacitor 5. The main terminal 92 may also be referred to as an N terminal, a low-potential power supply terminal, or the like. The main terminal 92 is connected to the emitter electrode 42 of the semiconductor element 40L via the joint portion 82, the heat sink 50L, and the conductive spacer 70L. The main terminal 92 extends in the Y direction and protrudes outside the sealing body 30 from the same side surface 30c as the main terminal 91.

[0059] The main terminal 92 has a connection portion 920 with the joint portion 82 near one end in the Y direction. A portion of the main terminal 92, including the connection portion 920, is covered by the sealing body 30, and the remaining portion protrudes from the sealing body 30. The connection portion 920 is thicker than the portion protruding from the sealing body 30. The thickness of the connection portion 920 is, for example, approximately the same as that of the heat sink 50L. Like the main terminal 91, the main terminal 92 also has a bent portion, which protrudes from near the center in the Z direction on the side surface 30c. The main terminal 92 has a Ni layer formed on its surface by plating or the like. The main terminal 92 has a Ni layer at least on the solder joint surface of the connection portion 920.

[0060] The main terminal 93 is connected to the connection point between the upper arm 9H and the lower arm 9L. The main terminal 93 is electrically connected to the emitter electrode 42 of the semiconductor element 40H and the collector electrode 43 of the semiconductor element 40L. The main terminal 93 is electrically connected to the winding 3a of the corresponding phase of the motor-generator 3. The main terminal 93 may also be referred to as an output terminal, AC terminal, or O terminal. The main terminal 93 is electrically connected to the emitter electrode 42 of the semiconductor element 40H via the heat sink 60L, joints 80 and 81, the heat sink 50H, and the conductive spacer 70H. The main terminal 93 is connected to the collector electrode 43 of the semiconductor element 40L via the heat sink 60L.

[0061] The main terminal 93 is connected to one end of the heat sink 60L in the Y direction. The thickness of the main terminal 93 is thinner than that of the heat sink 60L. The main terminal 93 is connected to the heat sink 60L so as to be substantially flush with the opposing surface 60a, for example. The main terminal 93 may be connected by being provided integrally and continuously with the heat sink 60L, or may be provided as a separate member and connected by joining.

[0062] The main terminal 93 in this embodiment is provided integrally with the heat sink 60L as part of the lead frame. The main terminal 93 extends in the Y direction from the heat sink 60L and protrudes outside the sealing body 30 from the same side surface 30c as the main terminal 91. Like the main terminal 91, the main terminal 93 also has a bent portion and protrudes from near the center of the side surface 30c in the Z direction. The three main terminals 91 to 93 are lined up in the X direction in the order of main terminal 91, main terminal 92, and main terminal 93.

[0063] The signal terminals 94 are electrically connected to the corresponding pads 44 of the semiconductor element 40. In this embodiment, the signal terminals 94 are electrically connected to the pads 44 via bonding wires 97. The signal terminals 94 extend in the Y direction and protrude from the side surface 30d of the sealing body 30 to the outside. The semiconductor device 20 has five signal terminals 94 for one semiconductor element 40, that is, a total of ten signal terminals 94. The multiple signal terminals 94 are arranged side by side in the X direction. The signal terminals 94 are configured, for example, on a lead frame common to the heat sink 60 and the main terminals 91 to 93.

[0064] The semiconductor device 20 includes a suspension lead 95. The heat sink 60 (60H, 60L), the joint portion 81, the main terminals 91 to 93, and the signal terminal 94 are configured as a lead frame, which is a common component. The lead frame is a profile strip with thicknesses that vary in parts. Before cutting, the signal terminal 94 is supported by the suspension lead 95 via tie bars (not shown). Unnecessary portions of the lead frame, such as the tie bars and the peripheral frame, are cut (removed) after the sealing body 30 is formed.

[0065] The semiconductor device 20 includes a plurality of solders 100 for connecting elements. The solders 100 include solders 101H, 101L, 102H, 102L, 103H, 103L, 104, and 105. The solder 101H is interposed between the emitter electrode 42 of the semiconductor element 40H and the conductive spacer 70H, joining the emitter electrode 42 and the conductive spacer 70H. The solder 102H is interposed between the conductive spacer 70H and the heat sink 50H, joining the conductive spacer 70H and the heat sink 50H. The solders 101H and 102H correspond to a first upper solder. The solder 103H is interposed between the collector electrode 43 of the semiconductor element 40H and the heat sink 60H, joining the collector electrode 43 and the heat sink 60H. The solder 103H corresponds to a first lower solder.

[0066] The solder 101L is interposed between the emitter electrode 42 of the semiconductor element 40L and the conductive spacer 70L, joining the emitter electrode 42 and the conductive spacer 70L. The solder 102L is interposed between the conductive spacer 70L and the heat sink 50L, joining the conductive spacer 70L and the heat sink 50L. The solders 101L and 102L correspond to the second upper solder. The solder 103L is interposed between the collector electrode 43 of the semiconductor element 40L and the heat sink 60L, joining the collector electrode 43 and the heat sink 60L. The solder 103L corresponds to the second lower solder.

[0067] The solders 101H and 101L are sometimes referred to as on-chip solder, the solders 102H and 102L are sometimes referred to as on-spacer solder, and the solders 103H and 103L are sometimes referred to as under-chip solder.

[0068] The solder 104, together with the joints 80 and 81, electrically connects the heat sink 50H and the heat sink 60L. In this embodiment, the solder 104 is interposed between the joint 80 connected to the heat sink 60L and the joint 81 connected to the heat sink 50H, joining the joints 80 and 81. The solder 104 corresponds to relay solder or first relay solder. The solder 105, together with the joint 82, electrically connects the heat sink 50L and the main terminal 92. In this embodiment, the solder 105 is interposed between the joint 82 connected to the heat sink 50L and the connection portion 920 of the main terminal 92, joining the joint 82 and the main terminal 92. The solder 105 corresponds to second relay solder.

[0069] Each of the plurality of solders 100 contains Cu and Sn. For example, the solder 100 is a multi-element lead-free solder containing Cu, Bi, Sb, etc., with the remainder being Sn. Each solder 100 has a thickness of, for example, about 100 μm.

[0070] As described above, in the semiconductor device 20, the plurality of semiconductor elements 40 that constitute the upper and lower arm circuits 9 for one phase are sealed by the sealing body 30. The sealing body 30 integrally seals the plurality of semiconductor elements 40, a portion of each of the heat sinks 50, a portion of each of the heat sinks 60, the conductive spacer 70, the joint portions 80 to 82, the main terminals 91 to 93, and a portion of each of the signal terminals 94.

[0071] The semiconductor element 40 is disposed between the heat sinks 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the heat sinks 50 and 60, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the heat sink 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the heat sink 60 is substantially flush with the back surface 30b of the sealing body 30. Because the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

[0072] An Au layer may be formed on the Ni layer by plating or other methods. Au, for example, inhibits oxidation of Ni and improves wettability with solder. Au diffuses into the solder during soldering, so it exists before bonding and does not exist after bonding.

[0073] <Output current and return current> Next, the output current and the return current will be described with reference to Fig. 7. Fig. 7 shows the output current and the return current for the semiconductor element 40H on the upper arm 9H side as an example. In Fig. 7, the output current is indicated by a dashed arrow, and the return current is indicated by a dashed arrow.

[0074] An output current (main current) flows when the IGBT is operating. The output current on the upper arm 9H side flows from the main terminal 91 to the motor generator 3 via the IGBT 11 of the semiconductor element 40H and the main terminal 93. Specifically, as shown by the dashed arrows in Figure 7, the current flows through the main terminal 91 (P terminal) → heat sink 60H → semiconductor element 40H (IGBT 11) → conductive spacer 70H → heat sink 50H → joint 81 → joint 80 → heat sink 60L → main terminal 93 (O terminal).

[0075] A return current flows when the diode operates. The return current on the upper arm 9H side flows in the opposite direction to the output current, that is, from the main terminal 93 to the DC power supply 2 side via the diode 12 of the semiconductor element 40H and the main terminal 91. Specifically, as shown by the dashed-dotted arrow in Figure 7, the current flows through the main terminal 93 (O terminal) → heat sink 60L → joint 80 → joint 81 → heat sink 50H → conductive spacer 70H → semiconductor element 40H (diode 12) → heat sink 60H → main terminal 91 (P terminal).

[0076] The same applies to the lower arm 9L. An output current flows from the main terminal 93 to the IGBT 11 of the semiconductor element 40L to the main terminal 92. A return current flows from the main terminal 92 to the diode 12 of the semiconductor element 40L to the main terminal 93.

[0077] <Joint structure and solder particle size> Next, the joint structure and solder particle size will be described with reference to FIGS. 8 to 10. FIG. 8 is a cross-sectional view showing the joint structure of joints 80 and 81 in the semiconductor device 20 according to this embodiment. FIG. 8 is an enlarged cross-sectional view of region VIII indicated by the dashed dotted line in FIG. 3. For convenience, the wire piece 120 is omitted from FIG. 8. FIG. 9 is a cross-sectional view showing the wire piece 120 provided on the surface of the joint 80. For convenience, the alloy layer 110 is omitted from FIG. 9. FIG. 10 is a cross-sectional view showing a reference example. FIG. 10 corresponds to FIG. 8. In the reference example, the reference symbols of each element are those of the related elements of the semiconductor device 20 with r added to the end.

[0078] 8, the joint 80 has a Cu-based base material 800 and a Ni layer 801 provided on the base material 800. Similarly, the joint 81 has a Cu-based base material 810 and a Ni layer 811 provided on the base material 810. As an example, the Ni layers 801 and 811 are NiP films formed by electroless plating. The Ni layers 801 and 811 are Ni plating films containing P.

[0079] The semiconductor device 20 includes an alloy layer 110 interposed between the Ni layer 801 and the solder 104, and an alloy layer 111 interposed between the Ni layer 801 and the solder 104. The alloy layers 110 and 111 are sometimes referred to as IMC. IMC is an abbreviation for Intermetallic Compound. The alloy layers 110 and 111 are formed during solder bonding. The alloy layers 110 and 111 contain Ni, Cu, and Sn. The composition of the alloy layers 110 and 111 is, for example, (Ni-Cu)3Sn4.

[0080] The semiconductor device 20 further includes P-rich layers 802 and 812. The P-rich layer 802 is formed on the surface of the Ni layer 801. The P-rich layer 812 is formed on the surface of the Ni layer 811. The P-rich layers 802 and 812 are formed when part of the Ni in the Ni layers 801 and 811 diffuses toward the solder 104 during bonding. The P-rich layers 802 and 812 are layers that are richer in P than the Ni layers 801 and 811 (NiP). The composition of the P-rich layers 802 and 812 is, for example, Ni3P.

[0081] As shown in FIG. 9 , at least one of the joints 80, 81 has multiple wire pieces 120 on the solder joint surface. The wire pieces 120 are small pieces of a bonding wire. The wire pieces 120 are sometimes referred to as protrusions or stud bonding. The wire pieces 120 are disposed within the solder 104. Multiple wire pieces 120 are dispersed within the solder 104. By appropriately setting the height of the wire pieces 120, it is possible to ensure a minimum thickness of the solder 104. The multiple wire pieces 120 are fixed (bonded) to a first opposing surface, which is one of the opposing surfaces constituting the solder joint, and protrude toward a second opposing surface, which is the other opposing surface. As an example, in this embodiment, the wire pieces 120 are provided on the solder joint surface of the joint 80. The wire pieces 120 are arranged, for example, at a predetermined pitch.

[0082] The presence of the wire piece 120 gives the surface of the joint portion 80 an uneven shape. The solder 104 begins to grow as grains from the wire piece 120 as the solder 104 solidifies. Grain boundaries 106 are formed when adjacent grains collide. The crystal grains grow from corners of the wire piece 120, for example, the upper corners. Therefore, the grain size of the solder 104 is smaller than the grain size of the solders 103H and 103L, for example. As described above, the thickness of the solder 104 is approximately 100 μm. The grain size of the solder 104 is smaller than the thickness of the solder 104, i.e., 100 μm.

[0083] In the comparative example shown in FIG. 10, no wire pieces are provided on the solder joint surfaces of the joint portions 80r and 81r. In other words, the grain size of the solder 104 is not controlled. The other configurations are the same as those of the semiconductor device 20 of this embodiment. In this case, the grain size of the solder 104r is about 100 μm. There are about one or two crystal grains of the solder 104r in the thickness direction (Z direction) of the solder 104.

[0084] In this embodiment, of the multiple solders 100, solders 103H and 103L do not have wire pieces 120 arranged thereon. The particle sizes of the solders 103H and 103L are the same as those of the comparative example shown in Fig. 10. The particle sizes of the solders 103H and 103L are larger than that of the solder 104 on which the wire pieces 120 are arranged.

[0085] <em> Next, EM (electromigration) will be described with reference to FIG. 11. FIG. 11 is a reference diagram showing the mechanism of EM progression. In FIG. 11, the reference symbols for each element are the same as those of the related elements of the semiconductor device 20 with r added to the end. In the example shown in the reference diagram, similar to the configuration shown in FIG. 10, no particle size control of the solder 104r is performed. The other configurations are the same as those of the semiconductor device 20 of this embodiment.

[0086] 11 shows the initial stage before current is applied. An alloy layer 110r is interposed between a Ni layer 801r and solder 104r. A P-rich layer 802r is formed on the surface of the Ni layer 801r.

[0087] The second, third, and fourth lines in FIG. 11 show the state when an output current is applied. The dashed arrows indicate the direction of electron (e-) flow. As shown in the second line in FIG. 11, as the electrons move, Cu and other elements in the alloy layer 110r move (diffuse) toward the joint 81r. Specifically, metals such as Cu ionize and move toward the joint 81r. As a result, the alloy layer 110r gradually becomes thinner and disappears, as shown in the third line in FIG. 11.

[0088] When the alloy layer 110r disappears, Ni in the Ni layer 801r moves (diffuses) toward the joint portion 81r as electrons move, reducing the Ni layer 801r and increasing the P-rich layer 802r, as shown in FIG. 11(c), and then, as shown in FIG. 11(d), the Ni layer 801r disappears and the P-rich layer 802r reaches the base material 800r. In other words, the P-rich layer 802r is replaced by the Ni layer 801r.

[0089] After the P-rich layer 802r reaches the base material 800r, the adhesion decreases over time, causing, for example, voids. Furthermore, cracks may occur along the interface starting from the voids. Cracks may also occur in the P-rich layer 802r.

[0090] As described above, in the configuration where the solder particle size is not controlled (see FIG. 10), the grain size of the solder 104r is large. There are few grain boundaries along the migration path of the Cu. Therefore, the Cu in the alloy layer 110r easily migrates with the migration of electrons.

[0091] While an example of output current is shown, the same applies to return current. When return current is applied, the alloy layer 111r on the joint portion 81r side first disappears, and then the P-rich layer 812r is replaced by the Ni layer 811r. After the P-rich layer 812r reaches the base material 810r, adhesion deteriorates over time, resulting in, for example, voids and cracks. Because the grain size of the solder 104r is large, Cu in the alloy layer 111r easily migrates with the movement of electrons.

[0092] On the other hand, in the configuration of this embodiment (see FIG. 8), the grain size of the solder 104 at the joints 80 and 81 where the current density is high is smaller than the grain size of the solder 103H and 103L where the solder grain size is not controlled. Therefore, Cu in the alloy layers 110 and 111 is less likely to migrate with the movement of electrons. In other words, the alloy layers 110 and 111 are less likely to disappear. The time it takes for the alloy layers 110 and 111 to disappear is longer. As a result, the time it takes for the Ni layers 801 and 811 to become the P-rich layers 802 and 812 and begin to decrease is delayed. The time it takes for the Ni layers 801 and 811 to disappear is longer.

[0093] <Summary of the First Embodiment> In a plan view, the area of the collector electrode 43, which is the main electrode on the high potential side, is larger than the area of the emitter electrode 42, which is the main electrode on the low potential side. Furthermore, due to miniaturization of the semiconductor device 20, it is difficult to increase the area of the solder joints of the joints 80 and 81 and the joint 82. As a result, in the semiconductor device 20 constituting one phase of the upper and lower arm circuits 9, the current density of the solders 101H, 101L, 102H, 102L, 104, and 105 is higher than the current density of the solders 103H and 103L. In other words, among the multiple solders 100, EM is likely to progress at the joints of the solders 101H, 101L, 102H, 102L, 104, and 105. Among the multiple solders 100, EM is less likely to progress at the joints of the solders 103H and 103L.

[0094] As an example, in this embodiment, the grain size of the solder 104 (relay solder, first relay solder) is smaller than the grain size of the solders 103H and 103L (first lower solder and second lower solder). The solder 104 has more grain boundaries 106 between the connection objects. The grain boundaries 106 hinder the movement of Cu. Therefore, Cu in the alloy layers 110 and 111 does not easily move with the movement of electrons. This makes it possible to lengthen the time it takes for the alloy layers 110 and 111 to disappear. Furthermore, it is possible to lengthen the time it takes for the Ni layers 801 and 811 to disappear. As a result, the EM life can be improved.

[0095] The current density of the semiconductor device 20, i.e., the current density of the current path connected to the main electrodes, is maximum, for example, at the solder joints of the joints 80 and 81. In this embodiment, the particle size of the solder 104 is reduced, thereby improving the EM life.

[0096] The effect of the particle size of the solder 104 has already been confirmed through prototypes. It was confirmed that reducing the particle size of the solder 104 slows down the disappearance of the alloy layers 110 and 111, that is, it slows down the progression of EM. In this case, the Ni layers 801 and 811 were formed by electroless NiP plating. The composition of the alloy layers 110 and 111 was (Ni-Cu)3Sn4.

[0097] In this embodiment, the joint portion 80 has a plurality of wire pieces 120 on the solder joint surface. The solder 104 solidifies starting from the wire pieces 120. The wire pieces 120 are the starting points for solidification. By providing the wire pieces 120, the particle size of the solder 104 can be reduced, thereby improving the EM life.

[0098] <Modification> Although an example in which the wire piece 120 is provided on the joint portion 80 has been shown, this is not limiting. The wire piece 120 may also be provided on the solder joint surface of the joint portion 81. This also causes the solder 104 to solidify and break down into small particles, starting from the wire piece 120. The wire piece 120 may also be provided on each of the joint portions 80 and 81. In other words, it is sufficient to provide the wire piece 120 on at least one of the objects to be connected.

[0099] Although the solder 104 is shown as an example of small solder particles having small particle diameters, the present invention is not limited to this. At least one of the solder particles 100 other than the solder particles 103H and 103L may be used as the small solder particles.

[0100] For example, the solder 105 may be small-particle solder. By providing a plurality of wire pieces 120 on the solder joint surface of the joint portion 82 and / or the connection portion 920 of the main terminal 92, the particle size of the solder 105 can be made smaller than the particle size of the solders 103H and 103L. This makes it possible to suppress the progression of EM at the joint portion of the solder 105.

[0101] For example, the solders 101H and 101L may be small-grain solder. By providing multiple wire pieces 120 on the solder joint surfaces of the emitter electrode 42 and / or the conductive spacer 70, the grain size of the solders 101H and 101L can be made smaller than the grain size of the solders 103H and 103L. This makes it possible to suppress the progression of EM at the joints of the solders 101H and 101L. This is effective in miniaturizing the semiconductor element 40.

[0102] For example, the solders 102H and 102L may be small-grain solder. By providing multiple wire pieces 120 on the solder joint surfaces of the conductive spacer 70 and / or the heat sink 50, the grain size of the solders 102H and 102L can be made smaller than the grain size of the solders 103H and 103L. This makes it possible to suppress the progression of EM at the joints of the solders 102H and 102L. Similar to reducing the grain size of the solders 101H and 101L, this is effective in miniaturizing the semiconductor element 40.

[0103] The arrangement of the multiple wire pieces 120 is not particularly limited. For example, as shown in FIG. 12, multiple wire pieces 120 may be provided on the solder joint surface of the conductive spacer 70 in a portion that overlaps with the vicinity of the center of the semiconductor element 40. EM progresses more as the temperature and current density increase. By providing the wire pieces 120 in a portion that overlaps with the vicinity of the element center in a planar view, it is possible to reliably reduce the grain size in the portion where the temperature is high. This makes it possible to suppress the progression of EM. Furthermore, multiple wire pieces 120 may be provided on the solder joint surface of the conductive spacer 70 in a portion that overlaps with the four corners of the emitter electrode 42. The four corners have a lower temperature, making it easier for solder to solidify. This promotes reduction in grain size.

[0104] 12 is not limited to the conductive spacer 70. The wire pieces 120 may be provided near the center of the element or at the four corners of the emitter electrode 42. The wire pieces 120 may be provided in the heat sink 50 in a portion overlapping the center of the element or at the four corners.

[0105] Although the semiconductor device 20 includes the conductive spacer 70 in the example shown, the present invention is not limited to this. Instead of the conductive spacer 70, a protrusion that functions as a spacer may be provided on the heat sink 50. In this case, the heat sink 50 corresponds to the upper conductor. The upper solder is interposed between the emitter electrode 42 and the heat sink 50, joining the emitter electrode 42 and the heat sink 50. In order to refine the upper solder grains, multiple wire pieces 120 may be provided on the solder joint surfaces of the emitter electrode 42 and / or the heat sink 50.

[0106] Although an example in which the semiconductor device 20 includes the joint portion 82 has been described, the present invention is not limited to this. The heat sink 50L, the joint portion 82, and the main terminal 92 may be provided continuously and integrally. In other words, the semiconductor device 20 may not include the solder 105.

[0107] Although the example has been shown in which the semiconductor device 20 includes two joints 80, 81 for connecting the upper arm 9H and the lower arm 9L, the present invention is not limited to this. Only one of the joints 80, 81 may be included. For example, a configuration may be adopted in which only the joint 80 is included and the joint 80 is connected to the heat sink 50H via solder 104. A configuration may be adopted in which only the joint 81 is included and the joint 81 is connected to the heat sink 60L via solder 104.

[0108] (Second embodiment) This embodiment is a modification of the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, multiple wire pieces are provided as starting points for solidification. Instead of this, a rough oxide film formed by laser irradiation may be provided.

[0109] <Uneven oxide film> Fig. 13 is a cross-sectional view showing an uneven oxide film 803 provided on the surface of the joint portion 80 in the semiconductor device 20 according to this embodiment. Fig. 13 corresponds to Fig. 9. For convenience, the P-rich layer 802 and the alloy layer 110 are omitted in Fig. 13.

[0110] As described above, the joint 80 has the base material 800 and the Ni layer 801 provided on the surface of the base material 800. As shown in Fig. 13, the joint 80 further has an uneven oxide film 803 provided on the Ni layer 801. The uneven oxide film 803 is formed in a dispersed manner at multiple locations on the solder joint surface of the joint 80 by irradiating the Ni layer 801 with laser light.

[0111] The uneven oxide film 803 is an oxide film containing Ni as a main component. For example, the uneven oxide film 803 is made up of 80% NI2O3, 10% NiO, and 10% Ni.

[0112] The recesses 801a on the surface of the Ni layer 801 are formed by irradiation with pulsed laser light. One recess 801a is formed for each pulse. The uneven oxide film 803 is formed when the surface portion of the Ni layer 801 is melted, vaporized, and deposited by irradiation with laser light. The uneven oxide film 803 is an oxide film derived from the Ni layer 801. The uneven oxide film 803 is a film of oxide of the metal (Ni), which is the main component of the Ni layer 801. The uneven oxide film 803 is formed following the unevenness of the surface of the Ni layer 801 having the recesses 801a. The unevenness is formed on the surface of the uneven oxide film 803 at a pitch finer than the width of the recesses 801a. In other words, very fine unevenness (roughened portions) is formed.

[0113] The pulsed laser light is adjusted so that the energy density is greater than 0 J / cm2 and less than 100 J / cm2, and the pulse width is less than 1 μsec. To meet these conditions, a YAG laser, YVO4 laser, fiber laser, or the like can be used. For example, in the case of a YAG laser, an energy density of 1 J / cm2 or more is sufficient. In the case of electroless Ni plating, the Ni layer 801 can be processed even with an energy density of, for example, about 5 J / cm2.

[0114] <Void> The oxide film (rough oxide film 803) has lower wettability with solder than a metal film. Because the rough oxide film 803 has minute irregularities on its surface, the contact area with the solder is small, and some of the solder becomes spherical due to surface tension. In other words, the contact angle is large, and the wettability with solder is low.

[0115] As described above, the uneven oxide film 803 has low wettability with respect to the solder 104. Therefore, as shown in FIG. 13, voids 121 are formed so as to cover the uneven oxide film 803. The voids 121 are formed around the uneven oxide film 803. In the semiconductor device 20, a plurality of voids 121 are present near the solder joint surface of the joint portion 80. The other configurations are the same as those described in the preceding embodiment.

[0116] <Summary of the second embodiment> The configuration described in this embodiment can achieve the same effects as the configuration described in the preceding embodiment. Specifically, multiple voids 121 originating from the uneven oxide film 803 exist in the solder 104. When the solder 104 solidifies, grain growth occurs starting from the voids 121. The voids 121 are the starting points of solidification. By providing the uneven oxide film 803 and, therefore, the voids 121, the grain size of the solder 104 can be made smaller than the grain size of the solders 103H and 103L, thereby improving the EM life.

[0117] <Modification> Although an example in which the uneven oxide film 803 is provided on the joint portion 80 has been shown, this is not limiting. The uneven oxide film may be provided on other conductors to be connected, excluding the heat sink 60. For example, the uneven oxide film may be provided on the solder joint surface of the joint portion 81. The uneven oxide film may be provided on each of the joint portions 80 and 81. The uneven oxide film may be provided on the solder joint surface of the heat sink 50. The uneven oxide film may be provided on the solder joint surface of the conductive spacer 70.

[0118] The arrangement of the uneven oxide film is not particularly limited. It may be arranged in a dispersed manner at a predetermined pitch. As shown in Fig. 12, the uneven oxide film may be provided in the heat sink 50 or the conductive spacer 70 in a portion overlapping the center of the element or in a portion overlapping the four corners.

[0119] (Third embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the solder particle size was reduced by providing wire pieces or an uneven oxide film. Instead, unevenness may be provided on the inner peripheral edge of the groove that accommodates overflowing solder.

[0120] Fig. 14 is a plan view showing a heat sink 50H including a joint portion 81 in the semiconductor device 20 according to this embodiment. Fig. 14 is a plan view seen from the opposing surface 50a side. Fig. 15 is an enlarged view of an area XV indicated by a dashed line in Fig. 14. Fig. 15 shows solder 104 arranged on the joint portion 81. Fig. 15 shows only a portion of a grain boundary 106.

[0121] As in the preceding embodiment, the joint portion 81 is provided integrally and continuously with the heat sink 50H. As shown in FIG. 14 , the heat sink 50H has a groove 51. The joint portion 81 also has a groove 83. As shown in FIG. 15 , in a plan view, an inner circumferential end 830 of the groove 83 has a continuous uneven shape. The joint portion 81 has an uneven portion 831 at the inner circumferential end 830 of the groove 83. As an example, the uneven portion 831 is provided over the entire length of the groove 83.

[0122] During solidification, the solder 104 undergoes grain growth starting from the recesses and / or protrusions of the uneven portion 831 provided on the inner peripheral end 830 of the groove 83. Because growth starts from the unevenness in this way, the crystal grains become smaller in the solder 104. The other configurations are the same as those described in the preceding embodiment.

[0123] <Summary of the third embodiment> The configuration described in this embodiment can achieve the same effects as the configuration described in the preceding embodiment. Specifically, the inner circumferential edge 830 of the groove 83 that accommodates the overflowing solder 104 has a continuous uneven shape. When the solder 104 solidifies, grain growth occurs starting from the unevenness of the inner circumferential edge 830. The uneven portion 831 is the starting point of solidification. By making the inner circumferential edge 830 of the groove 83 uneven, the grain size of the solder 104 can be made smaller than the grain size of the solders 103H and 103L, thereby improving the EM life.

[0124] Although an example has been shown in which uneven portion 831 is provided over the entire length of groove 83, this is not limiting. It is sufficient that uneven portion 831 is provided over at least a portion of the entire length of groove 83. By making at least a portion of inner circumferential end 830 of groove 83 uneven, the grain size of solder 104 can be made smaller than the grain size of solders 103H and 103L.

[0125] In addition, when the heat sink 50H including the joint portion 81 and the heat sink 50L including the joint portion 82 are made of a common member, the joint portion 82 also has an uneven portion 831 on the inner peripheral end 830 of the groove 83. In this case, the solder 105 can also be made small in size.

[0126] <Modification> Although an example in which the uneven portion 831 is provided in the groove 83 has been shown, the present invention is not limited to this. The uneven portion may be provided on the inner peripheral edge of the groove 51 of the heat sink 50. The uneven portion may be provided on the inner peripheral edge of the groove 51 of the heat sink 50H, or on the inner peripheral edge of the groove 51 of the heat sink 50L. The uneven portion may be provided on both the groove 51 and the groove 83.

[0127] (Fourth embodiment) This embodiment is a modification of the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the particle size of the solder was reduced by improving the solder connection target. Alternatively, the particle size of the solder may be reduced by improving the solder itself.

[0128] 16 is a cross-sectional view showing the joining structure of joints 80 and 81 in the semiconductor device 20 according to this embodiment. FIG. 16 corresponds to FIG.

[0129] 16, conductive balls 122 are added to the solder 104. The balls 122 are mainly composed of Ni or Cu. Such balls 122 are sometimes called Ni balls or Cu balls. By appropriately setting the diameter of the balls 122, it is possible to ensure, for example, a minimum thickness of the solder 104.

[0130] The presence of the balls 122 causes grain growth of the solder 104 starting from the balls 122 during solidification. Because the grains start from the balls 122, the crystal grains of the solder 104 become smaller compared to a configuration in which the balls 122 are not added. The other configurations are the same as those described in the preceding embodiment.

[0131] <Summary of the Fourth Embodiment> The configuration described in this embodiment can achieve the same effects as the configuration described in the preceding embodiment. Specifically, balls 122 are added to the solder 104. When the solder 104 solidifies, grain growth occurs starting from the balls 122. The balls 122 are the starting points for solidification. By providing the balls 122, the grain size of the solder 104 can be made smaller than the grain size of the solders 103H and 103L, thereby improving the EM life.

[0132] The effect of the balls 122 has also been confirmed by a prototype. It was confirmed that adding the balls 122 reduces the particle size of the solder 104. It was also confirmed that the disappearance of the alloy layers 110 and 111 is slowed down, that is, the progression of EM can be slowed down. At this time, the Ni layers 801 and 811 were formed by electroless NiP plating. The composition of the alloy layers 110 and 111 was (Ni-Cu)3Sn4.

[0133] <Modification> The solder 104 may have a multi-layer structure, and the occupancy rate of the balls 122 per unit volume may vary depending on the layer. In the example shown in Fig. 17, the solder 104 has a first layer 104a and a second layer 104b. The first layer 104a is the layer on the joint part 80 side, and the second layer 104b is the layer on the joint part 81 side. Fig. 17 corresponds to Fig. 16. For convenience, the grain boundary 106 is omitted in Fig. 17.

[0134] 17, the occupancy rate of the balls 122 in the first layer 104a is higher than the occupancy rate of the balls 122 in the second layer 104b. The number of balls 122 in the first layer 104a is greater than that in the second layer 104b. With this configuration, the grain size in the first layer 104a can be further reduced while the grain size in the second layer 104b is reduced. Therefore, in a configuration in which EM easily progresses due to output current, the EM life can be improved.

[0135] The occupancy rate of the balls 122 in the first layer 104a may be higher than the occupancy rate of the balls 122 in the second layer 104b by making the diameter of the balls 122 different between the first layer 104a and the second layer 104b. Both the number and diameter of the balls may be made different.

[0136] The occupancy rate of the balls 122 in the second layer 104b may be higher than the occupancy rate of the balls 122 in the first layer 104a. With this configuration, the grain size in the first layer 104a can be reduced while the grain size in the second layer 104b can be further reduced. Therefore, in a configuration in which EM easily progresses due to a reflux current, the EM life can be improved.

[0137] The two-layer structure of the solder 104 can be realized, for example, by arranging two layers of solder foil with different ball content. Alternatively, three layers of solder foil without balls may be laminated, with the number and / or diameter of the balls 122 arranged between each solder foil being different. The number of layers of the solder 104 is not limited to two; three or more layers may be used.

[0138] Although an example in which the ball 122 is disposed on the solder 104 has been shown, the present invention is not limited to this. The ball 122 may be disposed on at least one of the solders 100 other than the solders 103H and 103L.

[0139] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0140] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0141] When an element or layer is referred to as being "on," "coupled," "connected," or "coupled," it may be directly on, coupled, connected, or coupled to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers present. Other language used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0142] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0143] The vehicle drive system 1 is not limited to the above-described configuration. For example, although an example has been shown in which one motor generator 3 is provided, this is not limiting. Multiple motor generators may be provided. Although an example has been shown in which the power conversion device 4 is provided with an inverter 6 as a power conversion unit, this is not limiting. For example, a configuration with multiple inverters may be provided. A configuration with at least one inverter and a converter may be provided. Or only a converter may be provided.

[0144] The switching element is not limited to the IGBT 11. For example, a MOSFET may be used. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. In the case of an n-channel MOSFET, the source electrode corresponds to the upper electrode and the drain electrode corresponds to the lower electrode. In the case of a MOSFET, a parasitic diode (body diode) may be used as the freewheeling diode, or an external diode may be used.

[0145] Although an example has been shown in which the semiconductor device 20 includes only one semiconductor element 40 that configures each arm, this is not limiting. The semiconductor device 20 may include a plurality of semiconductor elements 40 that configure each arm. That is, a plurality of semiconductor elements 40H may be connected in parallel to configure one arm 9H, and a plurality of semiconductor elements 40L may be connected in parallel to configure one arm 9L.

[0146] Although an example has been shown in which the back surfaces 50b, 60b of the heat sinks 50, 60 are exposed from the sealing body 30, this is not limiting. At least one of the back surfaces 50b, 60b may be covered by the sealing body 30. At least one of the back surfaces 50b, 60b may be covered by an insulating member (not shown) that is separate from the sealing body 30. The semiconductor device 20 may not include the sealing body 30.

[0147] Although an example in which the semiconductor device 20 includes the encapsulant 30 has been described, the present invention is not limited to this and may have a configuration in which the encapsulant 30 is eliminated.

[0148] (Disclosure of technical ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be written in a multiple dependent form, with the subsequent clause referring to the preceding clause as an alternative. Furthermore, some clauses may be written in a multiple dependent form, referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0149] <Technical philosophy 1> a plurality of semiconductor elements (40) each having a signal pad and an upper electrode as a main electrode on its upper surface, and a lower electrode as a main electrode on its lower surface, which is the surface opposite to the upper surface in the thickness direction of the plate, and having an area larger than that of the upper electrode when viewed in a plan view from the thickness direction; a plurality of conductors (50, 60, 70, 80, 81, 82, 92) electrically connected to the main electrodes via solder; the plurality of semiconductor elements include a first semiconductor element (40H) constituting an upper arm (9H) of an upper / lower arm circuit (9), and a second semiconductor element (40L) constituting a lower arm (9L) of the upper / lower arm circuit, the second semiconductor element (40L) being arranged alongside the first semiconductor element in one direction perpendicular to the plate thickness direction so that the upper surfaces are on the same side in the plate thickness direction, The plurality of conductors include first upper conductors (50H, 70H) connected to the upper electrodes of the first semiconductor elements via first upper solders (101H, 102H), first lower conductors (60H) connected to the lower electrodes of the first semiconductor elements via first lower solders (103H), second upper conductors (50L, 70L) connected to the upper electrodes of the second semiconductor elements via second upper solders (101L, 102L), second lower conductors (60L) connected to the lower electrodes of the second semiconductor elements via second lower solders (103L), and joint conductors (80, 81) connecting the first upper conductors and the second lower conductors via relay solders (104), Each solder contains Cu and Sn, Each of the solder connection targets has a Ni layer (801, 811), A semiconductor device, wherein the grain size of at least one of the first upper solder, the second upper solder, and the relay solder is smaller than the grain size of the first lower solder and the second lower solder.

[0150] <Technical philosophy 2> the first upper conductor has a first body portion (50H) and a first spacer portion (70H) interposed between the upper electrode of the first semiconductor element and the first body portion, the second upper conductor has a second body portion (50L) and a second spacer portion (70L) interposed between the upper electrode of the second semiconductor element and the second body portion, the first upper solder is interposed between the upper electrode of the first semiconductor element and the first spacer portion, and between the first spacer portion and the first body portion, A semiconductor device described in technical idea 1, wherein the second upper solder is interposed between the upper electrode of the second semiconductor element and the second spacer portion, and between the second spacer portion and the second main body portion.

[0151] <Technical philosophy 3> the joint conductor is a first joint conductor that connects the first upper conductor and the second lower conductor via a first relay solder that is the relay solder, The plurality of conductors include a main terminal (92) and a second joint conductor (82) that connects the second upper conductor and the main terminal via a second relay solder (105), The semiconductor device according to Technical Idea 1 or 2, wherein the grain size of the second relay solder is smaller than the grain size of the first lower solder and the second lower solder.

[0152] <Technical philosophy 4> A semiconductor device described in any one of technical ideas 1 to 3, in which the small-particle solder, which is the solder having a particle size smaller than that of the first lower solder and the second lower solder, has a solidification starting point for reducing the particle size inside the small-particle solder, or on the surface of the object to be connected to the small-particle solder.

[0153] <Technical philosophy 5> The semiconductor device according to Technical Idea 4, wherein the starting point portion is a plurality of wire pieces (120) arranged within the small solder particles and fixed to the surface of the object to be connected to the small solder particles.

[0154] <Technical philosophy 6> The conductor to be connected with the small solder particles has, on the Ni layer, an uneven oxide film (803) whose main component is Ni and whose surface is continuously uneven, The semiconductor device according to Technical Concept 4, wherein the starting point portion is a void (121) that covers the uneven oxide film.

[0155] <Technical philosophy 7> The conductor to which the small solder particles are connected has a groove (83) for accommodating overflowing solder, The inner circumferential edge of the groove has a continuous uneven shape, The semiconductor device according to Technical Concept 4, wherein the starting point portion is a recess and / or a protrusion at the inner circumferential end of the groove.

[0156] <Technical philosophy 8> The small solder particles are doped with conductive balls (122), The semiconductor device according to Technical Concept 4, wherein the starting point portion is the ball.

[0157] <Technical philosophy 9> The semiconductor device according to Technical Concept 8, wherein the balls contain Ni or Cu. [Explanation of symbols]

[0158] 1... drive system, 2... DC power supply, 3... motor generator, 3a... winding, 4... power conversion device, 5... smoothing capacitor, 6... inverter, 7... P line, 8... N line, 9... upper and lower arm circuits, 9H... upper arm, 9L... lower arm, 10... output line, 11... IGBT, 12... diode, 20... semiconductor device, 30... encapsulant, 30a... one surface, 30b... back surface, 30c, 30d, 30e, 30f... side, 40, 40H, 40L... semiconductor element, 41... semiconductor substrate, 42... emitter electrode, 43... collector electrode, 44... pad, 50, 50H, 50L... heat sink, 50a... opposing surface, 50b... back surface, 51... groove, 60, 60H, 60L... heat sink, 60 a...opposing surface, 60b...rear surface, 70, 70H, 70L...conductive spacer, 80, 81, 82...joint portion, 800, 810...base material, 801, 811...Ni layer, 801a...recess, 802, 812...P-rich layer, 803...uneven oxide film, 83...groove, 830...inner peripheral edge, 831...uneven portion, 90...external connection terminal, 91, 92, 93...main terminal, 9 20...Connection portion, 94...Signal terminal, 95...Suspension lead, 97...Bonding wire, 100, 101H, 101L, 102H, 102L, 103H, 103L, 104, 105...Solder, 104a...First layer, 104b...Second layer, 106...Grain boundary, 110, 111...Alloy layer, 120...Wire piece, 121...Void, 122...Ball< / em>

Claims

1. a plurality of semiconductor elements (40) each having a signal pad and an upper electrode as a main electrode on its upper surface, and a lower electrode as a main electrode on its lower surface, which is the surface opposite to the upper surface in the thickness direction of the plate, and having an area larger than that of the upper electrode when viewed in a plan view from the thickness direction; a plurality of conductors (50, 60, 70, 80, 81, 82, 92) electrically connected to the main electrodes via solder; The plurality of semiconductor elements include a first semiconductor element (40H) constituting an upper arm (9H) of an upper / lower arm circuit (9), and a second semiconductor element (40L) constituting a lower arm (9L) of the upper / lower arm circuit, and arranged alongside the first semiconductor element in one direction perpendicular to the plate thickness direction so that the upper surfaces are on the same side in the plate thickness direction, The plurality of conductors include first upper conductors (50H, 70H) connected to the upper electrode of the first semiconductor element via first upper solders (101H, 102H), a first lower conductor (60H) connected to the lower electrode of the first semiconductor element via first lower solders (103H), second upper conductors (50L, 70L) connected to the upper electrode of the second semiconductor element via second upper solders (101L, 102L), a second lower conductor (60L) connected to the lower electrode of the second semiconductor element via second lower solders (103L), and joint conductors (80, 81) connecting the first upper conductor and the second lower conductor via relay solders (104), Each solder contains Cu and Sn; Each of the solder connection targets has a Ni layer (801, 811), a particle size of at least one of the first upper solder, the second upper solder, and the relay solder is smaller than a particle size of the first lower solder and the second lower solder; A semiconductor device having a solidification starting point for reducing the particle size inside small-particle solder, which is the solder having a particle size smaller than that of the first lower solder and the second lower solder, or on the surface of the object to be connected to the small-particle solder.

2. the first upper conductor has a first body portion (50H) and a first spacer portion (70H) interposed between the upper electrode of the first semiconductor element and the first body portion; the second upper conductor has a second body portion (50L) and a second spacer portion (70L) interposed between the upper electrode of the second semiconductor element and the second body portion; the first upper solder is interposed between the upper electrode of the first semiconductor element and the first spacer portion, and between the first spacer portion and the first body portion, 2. The semiconductor device according to claim 1, wherein the second upper solder is interposed between the upper electrode of the second semiconductor element and the second spacer portion, and between the second spacer portion and the second body portion.

3. the joint conductor is a first joint conductor that connects the first upper conductor and the second lower conductor via a first relay solder that is the relay solder, The plurality of conductors include a main terminal (92) and a second joint conductor (82) that connects the second upper conductor and the main terminal via a second relay solder (105); The semiconductor device according to claim 1 , wherein the grain size of said second relay solder is smaller than the grain sizes of said first lower solder and said second lower solder.

4. The semiconductor device according to any one of claims 1 to 3, wherein the starting point portion is a plurality of wire pieces (120) arranged within the small solder particles and fixed to the surface of the object to be connected to the small solder particles.

5. The conductor to be connected with the small solder particles has, on the Ni layer, an uneven oxide film (803) whose main component is Ni and whose surface is continuously uneven, 4. The semiconductor device according to claim 1, wherein the starting point portion is a void (121) covering the uneven oxide film.

6. The conductor to which the small solder droplets are connected has a groove (83) for accommodating overflowing solder, The inner circumferential edge of the groove has a continuous uneven shape, 4. The semiconductor device according to claim 1, wherein the starting point portion is a recess and / or a protrusion at an inner peripheral end of the groove.

7. The small solder particles are doped with conductive balls (122), 4. The semiconductor device according to claim 1, wherein the starting point portion is the ball.

8. The semiconductor device according to claim 7 , wherein the balls contain Ni or Cu.

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