Da conversion circuit, electro-optical device, and electronic apparatus

Abstract

To simplify the configuration of a DA conversion circuit.SOLUTION: A DA conversion circuit 500 includes: a capacitive element C0 having a first end and a second end and charged with the first voltage in an initial state; and junction capacitance Cser having a third end and a fourth end. A potential of the first end is maintained or changed corresponding to an upper bit D1 in a first period, and the capacitive element C0 is charged with the first voltage in a state in which a potential of the fourth end is held in a second period. In a third period, the second end is connected to the fourth end through the junction capacitance Cser, the voltage of the first end is maintained or changed corresponding to a lower bit D0 paired with the bit D1, and the voltage of the fourth end is output.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a DA conversion circuit, an electro-optical device, and an electronic device. [Background technology]

[0002] Electro-optical devices using, for example, OLEDs as display elements are known. OLED stands for Organic Light Emitting Diode. In electro-optical devices, pixel circuits are provided corresponding to the pixels of a display image. The pixel circuits include display elements and transistors that supply current to the display elements. The display elements emit light at a brightness that corresponds to the current supplied by the transistors.

[0003] In the pixel circuit, a voltage corresponding to brightness is applied to the gate node of the transistor via a data line. More specifically, data specifying brightness is converted into an analog voltage by a DA conversion circuit, and the converted voltage is applied to the data line. As such a DA conversion circuit, for example, a technique has been proposed in which a pair of a switch and a capacitance element is provided corresponding to each bit, and charging and discharging of the capacitance element is controlled by the switch according to each bit (see, for example, Patent Document 1).

[0004] In the technology described in Patent Document 1, when the number of bits increases, not only do more capacitive elements are required, but the capacitance size of the capacitive elements also needs to be increased according to the weight of the bits. Therefore, a technology has been proposed in which the number of capacitive elements is half or less of the number of bits, and the capacitance size of the capacitive elements is also small compared to the weight of the bits (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-341125 [Patent Document 2] Japanese Patent Publication No. 2022-169108 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the technology described in Patent Document 2, during the lower bit write period, the voltage applied to one end of the capacitive element corresponding to the lower bit needs to be switched depending on the upper bit paired with the lower bit. This poses the problem that not only does the configuration for switching voltages require a memory or the like, but the number of voltages to be selected increases, making the circuit configuration more complex. [Means for solving the problem]

[0007] A DA conversion circuit according to one embodiment of the present disclosure includes a first capacitive element having a first terminal and a second terminal, and being initially charged to a first voltage between the first terminal and the second terminal, and a first junction capacitance having a third terminal and a fourth terminal, wherein during a first period, the potential of the first terminal is maintained or changed in accordance with a first higher-order bit of input data, during a second period, the potential of the fourth terminal is maintained and the potential between the first terminal and the second terminal is charged to the first voltage, and during a third period, the second terminal is connected to the fourth terminal via the first junction capacitance, and the potential of the first terminal is maintained or changed in accordance with a second lower-order bit that forms a pair with the first bit, and the potential of the fourth terminal is output. [Brief explanation of the drawings]

[0008] [Figure 1] 2 is a diagram illustrating an equivalent circuit of the DA conversion circuit according to the first embodiment. FIG. [Figure 2] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 3] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 4] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 5] FIG. 1 is a perspective view showing an electro-optical device to which a DA conversion circuit is applied. [Figure 6]FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device. [Figure 7] FIG. 2 is a circuit diagram of a pixel circuit in the electro-optical device. [Figure 8] FIG. 2 is a diagram illustrating an equivalent circuit of a DA conversion circuit in the electro-optical device. [Figure 9] FIG. 1 is a circuit diagram of a DA conversion circuit. [Figure 10] FIG. 2 is a circuit diagram of a voltage selection circuit in the DA conversion circuit. [Figure 11] 4 is a timing chart showing the operation of the electro-optical device. [Figure 12] 4 is a timing chart showing the operation of the electro-optical device. [Figure 13] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 14] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 15] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 16] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 17] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 18] FIG. 4 is a diagram showing voltage changes on data lines in an electro-optical device. [Figure 19] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 20] FIG. 10 is a diagram illustrating an equivalent circuit of a DA conversion circuit according to a second embodiment. [Figure 21] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 22] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 23] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 24] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 25] FIG. 2 is a diagram illustrating the operation of a DA conversion circuit. [Figure 26] FIG. 2 is a diagram illustrating an equivalent circuit of a DA conversion circuit in the electro-optical device. [Figure 27] FIG. 1 is a circuit diagram of a DA conversion circuit. [Figure 28] FIG. 2 is a circuit diagram of a voltage selection circuit in the DA conversion circuit. [Figure 29] FIG. 1 is a perspective view showing a head-mounted display using an electro-optical device. [Figure 30] FIG. 2 is a diagram illustrating an optical configuration of a head-mounted display. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. Furthermore, the embodiments described below are preferred examples, and therefore various technically preferable limitations are applied, but the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited.

[0010] First Embodiment FIG. 1 is a circuit diagram showing an example of a DA converter circuit 500 according to a first embodiment. In this example, the DA converter circuit 500 converts data consisting of four bits, D0 to D3, into an analog voltage. Of the four bits, the least significant bit is D0, and the weights of D1 and D2 increase in order from bit D0, with the most significant bit being D3. In this example, of the bits D0 to D3, bits D0 and D1 are classified as lower bits, and bits D2 and D3 are classified as higher bits. Also, in this example, bits D0 and D2 form a pair, and bits D1 and D3 form a pair.

[0011] The operation period of the DA conversion circuit 500 is divided into the following three periods: a higher-order bit write period, a reset period, and a lower-order bit write period.

[0012] The DA conversion circuit 500 includes capacitance elements C0 and C1, a junction capacitance Cser, switches Sw1, Sw2, and Sw3, and voltage selection circuits 510 and 511. The capacitance sizes of the capacitance elements C0, C1, and Cser will be described later.

[0013] The voltage selection circuit 510 selects the voltage VH_H when the bit D2 is "1" during the upper bit write period, selects the voltage VH_L when the bit D0 is "1" during the lower bit write period, and selects the voltage VL in other cases. The voltage selection circuit 510 applies the selected voltage to one end of the capacitance element C0. The voltage selection circuit 511 selects the voltage VH_H when the bit D3 is "1" during the upper bit write period, selects the voltage VH_L when the bit D1 is "1" during the lower bit write period, and selects the voltage VL in other cases. The voltage selection circuit 511 applies the selected voltage to one end of the capacitive element C1.

[0014] The other ends of the capacitance elements C0 and C1 are connected in common and are connected to one end of the switch Sw1 and one end of the switch Sw2, respectively. For convenience, the other ends of the capacitance elements C0 and C1 are referred to as a node Nd.

[0015] One end of the switch Sw3 is connected to the power supply line of the voltage Vrst_C. The other end of the switch Sw1, the other end of the switch Sw3, and one end of the junction capacitance Cser are commonly connected. The other end of the switch Sw2 and the other end of the junction capacitance Cser are commonly connected and form the output end Da_out of the DA conversion circuit 500. The on or off state of the switches Sw1, Sw2, and Sw3 is controlled by a switch control circuit (not shown).

[0016] In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, a connection between two or more elements in a semiconductor substrate via different wiring layers and contact holes, even if the connection is not direct. The "on state" of a switch or transistor means that both ends of the switch, or the source and drain nodes of a transistor, are electrically closed, resulting in a low impedance state. The "off state" of a switch or transistor means that both ends of the switch, or the source and drain nodes of a transistor, are electrically open, resulting in a high impedance state. Also, voltage means the potential difference between two points, but unless otherwise specified, it refers to the potential at the point in question relative to the ground point Gnd, which is the reference for zero voltage.

[0017] As shown in FIG. 1, the initial state of the DA conversion circuit 500 is such that the switch Sw1 is in an off state and the switches Sw2 and Sw3 are in an on state. In this initial state, the output terminal Da_out and the node Nd are at the same voltage. For convenience, the voltages at the output terminal Da_out and the node Nd in the initial state are designated as Va. In the initial state, one end of the junction capacitance Cser is at a voltage Vrst_C. Therefore, the junction capacitance Cser is charged to a voltage (Va-Vrst_C). Note that the voltage Vrst_C is set to approximately the same voltage as the voltage Va, as will be described later. In addition, in the initial state, both voltage selection circuits 510 and 511 select the voltage VL, so that the capacitance elements C0 and C1 are charged to the voltage (Va-VL).

[0018] 2 is a diagram showing the operation during the upper bit write period in the DA conversion circuit 500. As shown in the diagram, during the upper bit write period, the switch Sw1 is maintained in the off state, and the switches Sw2 and Sw3 are maintained in the on state. During the upper bit write period, the voltage selection circuit 510 selects the voltage VH_H if the bit D2 is "1", and selects the voltage VL if the bit D2 is "0". Regarding the voltages VL and VH_H, VL <VH_H This is the relationship. Furthermore, during the upper bit write period, the voltage selection circuit 511 selects the voltage VH_H if the bit D3 is "1", and selects the voltage VL if the bit D3 is "0".

[0019] During the upper bit write period, the switch Sw2 is in an on state, so that the other end of the capacitance element C0 and the other end of the capacitance element C1b, that is, the node Nd, are directly connected to the output terminal Da_out.

[0020] When bit D2 is "0", one end of capacitance element C0 does not change from the initial voltage VL, and therefore no discharge occurs in capacitance element C0. Therefore, when bit D2 is "0", capacitance element C0 does not contribute to the voltage increase at output terminal Da_out. Similarly, when bit D3 is "0", one end of capacitive element C1 does not change from voltage VL, and therefore no discharge occurs in capacitive element C1. Therefore, when bit D3 is "0", capacitive element C1 does not contribute to the voltage increase at output terminal Da_out. For convenience, the voltage at the output terminal Da_out during the upper bit write period is set to Vb. When bits D2 and D3 are both "0", the voltage Vb at the output terminal Da_out does not change from the voltage Va in the initial state.

[0021] When bit D2 is "1" and bit D3 is "0", one end of capacitance element C0 rises from the initial voltage VL to voltage VH_H, causing discharge in capacitance element C0, and charge flows out, increasing the voltage at output terminal Da_out. In this case, one end of junction capacitance Cser is at voltage Vrst_C during the upper bit write period and has not changed from the initial state, and one end of capacitance element C1 remains at voltage VL, so part of the charge flowing out from capacitance element C0 flows into junction capacitance Cser and capacitance element C1, and the remainder of the flowed-out charge increases the voltage at output terminal Da_out.

[0022] During the upper bit write period, node Nd is directly connected to output terminal Da_out, so the voltage increase at output terminal Da_out in response to bits D4 and D5 is determined by the capacitance ratio of capacitive elements C0, C1 and junction capacitance Cser.

[0023] Specifically, the capacitance ratios of the capacitance elements C0, C1 and the junction capacitance Cser are set to, for example, "1," "2," and "1," respectively. In this setting, when bit D2 is "1" and bit D3 is "0", the increase from voltage Va to voltage Vb at output terminal Da_out is assumed to be a ratio of "4". When bit D3 is "1" and bit D2 is "0", the voltage increase at output terminal Da_out is doubled to "8". Also, if bit D2 is "1" and bit D3 is "1", the voltage increase at output terminal Da_out corresponds to the ratio of "12", which is the sum of "4" and "8". If both bits D2 and D3 are "0", the voltage Vb at the output terminal Da_out does not change from the voltage Va, that is, the voltage increase is "0".

[0024] Therefore, the voltage Vb at the output terminal Da_out during the upper bit writing period becomes a voltage that is increased from the initial voltage Va by a voltage corresponding to one of the ratios of "0", "4", "8" or "12" depending on the upper bits D2 and D3.

[0025] 3 is a diagram showing the operation of the DA conversion circuit 500 during the reset period. As shown in the diagram, during the reset period, the switch Sw1 changes to the ON state, the switch Sw2 changes to the OFF state, and the switch Sw3 remains ON. As a result, the output terminal Da_out is electrically disconnected from the node Nd, but the node Nd is maintained at the voltage Vrst_C. Therefore, during the reset period, the output terminal Da_out is maintained at the voltage Vb that was present during the previous upper-bit write period by the junction capacitance Cser. Furthermore, during the reset period, both voltage selection circuits 510 and 511 select the voltage VL, so that the capacitance elements C0 and C1 are charged again to the voltage (Vrst_C-VL).

[0026] 4 is a diagram showing the operation during the lower-order bit write period in the DA conversion circuit 500. As shown in the diagram, during the lower-order bit write period, the switch Sw1 is maintained in the on state and the switch Sw2 is maintained in the off state, and the switch Sw3 changes to the off state. During the lower bit write period, the voltage selection circuit 510 selects the voltage VH_L if the bit D0 is "1", and selects the voltage VL if the bit D0 is "0". Regarding the voltages VL and VH_L, VL <VH_L This is the relationship. Furthermore, during the lower bit write period, the voltage selection circuit 511 selects the voltage VH_L if the bit D1 is "1", and selects the voltage VL if the bit D1 is "0".

[0027] During the lower-order bit write period, unlike the upper-order bit write period, the switch Sw1 is on and the switch Sw2 is off, so the node Nd is connected to the output terminal Da_out via the junction capacitance Cser. Therefore, the voltage change at the node Nd is compressed at a ratio determined by the capacitance sizes of the capacitive elements C0 and C1 and the junction capacitance Cser, causing the voltage at the output terminal Da_out to increase. This ratio is called the compression ratio. In this example, the compression ratio is: Cser / (Cser+C0+C1) Specifically, it is 1 / 4 (=1 / (1+1+2)).

[0028] For ease of explanation, VH_L=VH_H Let's say. Also, the voltage at the output terminal Da_out during the lower bit writing period is set to Vd. As described above, the voltage Vrst_C and the voltage Va are substantially the same voltage. Therefore, it can be considered that the voltage Vd at the output terminal Da_out during the lower bit write period rises from the voltage Vb during the upper bit write period by the voltage increase at the node Nd multiplied by the compression ratio.

[0029] Therefore, if bit D0 is "1" and bit D1 is "0", the voltage increase at output terminal Da_out is "1", which is the voltage increase "4" due to capacitance element C0 multiplied by 1 / 4 of the compression ratio. If bit D0 is "0" and bit D1 is "1", the voltage increase at output terminal Da_out is "2", which is the voltage increase "8" due to capacitance element C1 multiplied by 1 / 4 of the compression ratio. If bits D0 and D1 are both "1", the voltage increase at the output terminal Da_out is "3", which is the sum of "1" and "2". If both bits D0 and D1 are "0", the voltage Vd at the output terminal Da_out does not change from the voltage Vb, that is, the voltage increase at the output terminal Da_out becomes "0". In this way, the voltage Vd at the output terminal Da_out during the lower bit write period is a voltage that is increased from the voltage Vb during the upper bit write period by a voltage corresponding to the ratio of "0", "1", "2" or "3" depending on the lower bits D0 and D1.

[0030] According to the DA conversion circuit 500, the output terminal Da_out first rises from voltage Va during the upper bit write period by a voltage corresponding to the ratio of "0," "4," "8," or "12" depending on the two upper bits D2 and D3, to voltage Vb, and is then held at that voltage during the reset period. Then, during the lower bit write period, the output terminal Da_out rises from voltage Vb during the upper bit write period by a voltage corresponding to the ratio of "0," "1," "2," or "3" depending on the two lower bits D0 and D1, to voltage Vd. Therefore, in the DA conversion circuit 500, the voltage Vd at the output terminal Da_out changes from the initial voltage Va to one of 16 levels from "0" to "15" according to the four bits D0 to D3.

[0031] The voltage Vd output from the output terminal Da_out, i.e., the voltage Vd in 16 steps corresponding to "0" to "15", can be set by the voltages VH_H, VH_L, VL, the capacitances of the capacitive elements C0 and C1, and the capacitance of the junction capacitance Cser. Furthermore, a certain degree of error is allowed for the capacitance ratio of the capacitive elements C0 and C1 and the junction capacitance Cser, as long as the voltage characteristics output from the output terminal Da_out, specifically, the linearity of the voltage in the 16 steps from "0" to "15", is maintained.

[0032] Here, the DA conversion circuit 500 is configured to convert 4-bit data into an analog voltage, but it may be configured to convert, for example, 2-bit data into an analog voltage more simply. When converting 2-bit data into an analog voltage, the most significant bit D1 and the least significant bit D0 form a pair, and one capacitive element C0 is provided for this pair.

[0033] Also, here, the operation period of the DA conversion circuit 500 progresses in chronological order as a higher-order bit write period, a reset period, and a lower-order bit write period, but it may also progress in the opposite order as a lower-order bit write period, a reset period, and an upper-order bit write period. In a configuration in which the periods proceed in this order, first, during the lower-order bit write period, the output terminal Da_out rises from voltage Va by a voltage corresponding to the ratio of "0," "1," "2," or "3" depending on the two lower-order bits D0 and D1. Then, during the upper-order bit write period, the output terminal Da_out rises from the voltage during the lower-order bit write period by a voltage corresponding to the ratio of "0," "4," "8," or "12" depending on the two upper-order bits D1 and D2.

[0034] In the DA conversion circuit 500, the capacitance elements required for conversion of 4-bit data consisting of bits D0 to D3 are half the number of bits, ie, two capacitance elements (C0, C1) and one junction capacitance (Cser). In a configuration in which a capacitive element is provided for each bit, the capacitance of the capacitive element corresponding to the most significant bit is larger than the capacitance of the capacitive element corresponding to the least significant bit. Specifically, in a configuration in which a capacitive element is provided for each of four bits, if the capacitance of the capacitive element corresponding to the least significant bit is "1," the capacitance of the capacitive element corresponding to the most significant bit will be "8," requiring a large area for the capacitive elements. In contrast, in the DA conversion circuit according to this embodiment, even in the case of four bits, not only is the maximum capacitance size required to be approximately "2," but the number of capacitive elements required is also reduced by almost half. Therefore, according to this embodiment, when integrating the DA conversion circuit 500 on a semiconductor substrate, for example, it is possible to simplify the configuration and save space.

[0035] Furthermore, in the technology described in Patent Document 2, during a lower-order bit write period (second write period), the voltage selection circuit needs to switch the voltage applied to one end of the capacitive element corresponding to the lower-order bit depending on the upper-order bit paired with the lower-order bit. For this reason, in the technology described in Patent Document 2, the voltage selection circuit requires a memory or the like, which complicates the configuration. Furthermore, in the technology described in Patent Document 2, the number of voltages selected by the voltage selection circuit is "4," which complicates the configuration of not only the voltage selection circuit but also the power supply circuit.

[0036] In contrast, in this embodiment, during the lower-order bit write period, the voltage selection circuits 511 and 512 only need to select the voltage to be applied to one end of the capacitive element corresponding to the lower-order bit in accordance with the lower-order bit, and there is no need to switch the voltage in consideration of the upper-order bit paired with the lower-order bit. Also, while the number of voltages selected by the voltage selection circuit is "4" in the technology described in Patent Document 2, in this embodiment, only "3" is required, which simplifies the configurations of the voltage selection circuits 511 and 512 and the power supply circuit 15.

[0037] Note that the capacitance element C0 is an example of a "first capacitance element," and the capacitance element C1 is an example of a "second capacitance element." Therefore, one end of the capacitance element C0 is an example of a "first end," the other end of the capacitance element C0 is an example of a "second end," one end of the capacitance element C1 is an example of a "third end," and the other end of the capacitance element C0 is an example of a "fourth end." The junction capacitance Cser is an example of a "first junction capacitance." Furthermore, bit D2 is an example of a "first most significant bit," bit D0 is an example of a "second least significant bit," bit D3 is an example of a "bit having a weight greater than that of the most significant bit," and bit D0 is an example of a "bit paired with a bit having a weight greater than that of the most significant bit." The voltage (Va-VL) and the voltage (Vrst_C-VL) that is approximately equal to the voltage (Va-VL) are examples of a "first voltage." Furthermore, the upper bit write period is an example of a "first period," the reset period is an example of a "second period," and the lower bit write period is an example of a "third period."

[0038] Next, an electro-optical device using the DA conversion circuit 500 according to the embodiment will be described. Note that, although the DA conversion circuit 500 shown in Fig. 1 is an example of 4-bit conversion for the sake of explanation, the DA conversion circuit 500 applied to the electro-optical device is an example of 10-bit conversion for practical use.

[0039] 5 is a perspective view showing an electro-optical device 10 to which a 10-bit DA conversion circuit 500 is applied. The electro-optical device 10 is a microdisplay panel that displays images in, for example, a head-mounted display. In the electro-optical device 10, a plurality of pixel circuits and a drive circuit that drives the pixel circuits are formed on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0040] The electro-optical device 10 is housed in a frame-shaped case 192 that opens to the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 for connecting to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194.

[0041] In the figure, the X direction indicates the direction in which the scanning lines extend in the electro-optical device 10, and the Y direction indicates the direction in which the data lines extend. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and is the emission direction of light emitted from the OLED.

[0042] 6 is a block diagram showing the electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 is roughly divided into a power supply circuit 15, a control circuit 30, a data signal output circuit 50, a peripheral circuit 60, a display area 100, and a scanning line driving circuit 120. In the display area 100, m rows of scanning lines 12 are arranged along the X direction in the figure, and n columns of data lines 14 are arranged along the Y direction in the figure so as to be electrically insulated from each other. Note that m and n are integers of 2 or more.

[0043] In the display area 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. That is, the pixel circuits 110 are arranged in a matrix of m rows and n columns in the figure. To distinguish the rows of the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from top to bottom in the figure. Similarly, to distinguish the columns of the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from left to right in the figure. Note that an integer i of 1 or more and m or less is used to generalize the scanning lines 12. Similarly, an integer j of 1 or more and n or less is used to generalize the data lines 14.

[0044] The control circuit 30 controls each unit based on video data Vid and a synchronization signal Sync supplied from the host device. The video data Vid specifies the gradation level of pixels in an image to be displayed, for example, by 8 bits for each of the three primary colors. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of video data.

[0045] In the electro-optical device 10, there is a one-to-one correspondence between the pixels of an image to be displayed and the pixel circuits 110 in the display area 100. However, the brightness characteristics specified by the grayscale level do not match the luminance of the pixel circuit 110 corresponding to that pixel, more specifically, the luminance characteristics of the OLED included in the pixel circuit 110. Therefore, in order to make the OLED emit light at a brightness corresponding to the gradation level specified by the video data Vid, the control circuit 30 upconverts the 8 bits of the video data Vid to, for example, 10 bits and outputs it as video data Vdata that specifies the brightness of the OLED.

[0046] For such up-conversion, a look-up table is used that stores in advance the correspondence between the 8 bits of input video data Vid and the 10 bits of output video data Vdata. The 8-bit video data Vid has a decimal value of zero when the gradation level is the lowest black level, increasing as the gradation level increases, reaching a decimal value of 255 when the gradation level is the highest white level. In the electro-optical device 10, the highest voltage output from the DA conversion circuit 500 corresponds to the black level at which no current flows through the OLED, and the lowest voltage corresponds to the white level at which the OLED has maximum brightness. Therefore, when converting the 8-bit video data Vid into 10-bit video data Vdata, the control circuit 30 inverts 8 bits of the video data Vid, converts the 8-bit data into 10 bits, and outputs the video data Vdata. In other words, the highest value of the 10-bit video data Vdata, which is a decimal value of 1023, specifies the lowest brightness of the OLED, and the lowest value, which is a decimal value of zero, specifies the highest brightness of the OLED. The control circuit 30 generates various control signals for controlling each part, and the control signals will be described in detail later.

[0047] The scanning line driving circuit 120 is a circuit for driving the pixel circuits 110 arranged in m rows and n columns, row by row, in accordance with control by the control circuit 30, and outputs various signals. For example, the scanning line driving circuit 120 supplies scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), and / Gwr(m) to the scanning lines 12 in the first, second, third, ..., (m-1), and m-th rows, respectively. Generally, the scanning signal supplied to the scanning line 12 in the i-th row is represented as / Gwr(i). The scanning line driving circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(m), but details will be described later.

[0048] The data signal output circuit 50 is a circuit that outputs a data signal of a voltage corresponding to brightness to the pixel circuits 110 located in a row selected by the scanning line drive circuit 120. In detail, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500. The selection circuit group 52 includes selection circuits 520 corresponding to each of the n columns, the first latch circuit group 54 includes first latch circuits L1 corresponding to each of the n columns, and the second latch circuit group 56 includes second latch circuits L2 corresponding to each of the n columns. In other words, a set of the selection circuit 520, the first latch circuit L1, the second latch circuit L2, and the DA conversion circuit 500 is provided corresponding to each example.

[0049] Here, the jth column selection circuit 520 instructs the jth column first latch circuit L1 to select the jth column video data Vdata from the video data Vdata output from the control circuit 30, and the jth column first latch circuit L1 latches the video data Vdata in accordance with the instruction. The second latch circuit L2 in the jth column outputs the 10 bits of the video data Vdata latched by the first latch circuit L1 in the jth column in two separate periods under the control of the control circuit 30. In detail, the second latch circuit L2 in the jth column outputs the upper 5 bits of the 10 bits of the video data Vdata latched by the first latch circuit L1 in the jth column in the upper bit write period and outputs the lower 5 bits in the lower bit write period.

[0050] The peripheral circuit 60 is a collection of transistors 66 that correspond one-to-one to the data lines 14. One end of the transistor 66 corresponding to the jth column is connected to a power supply line for a voltage Vini, and the other end of the transistor 66 is connected to the jth column data line 14. A control signal / Gini from the control circuit 30 is commonly supplied to the gate nodes of the transistors 62 in each column.

[0051] The voltages of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are respectively represented as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n). In general, the voltage of the data line 14 in the jth column is represented as Vd(j).

[0052] The power supply circuit 15 generates various voltages used in the electro-optical device 10. The various voltages include power supply voltages for the scanning line driving circuit 120 and the data signal output circuit 50, and voltages Vel, Vini, Vct, Vrst_C, VH_H, VH_L, and VL.

[0053] 7 is a circuit diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the ith row and jth column as a representative.

[0054] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 124, and a capacitance element 140. The transistors 121 to 124 are, for example, MOS type transistors. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor. Furthermore, the pixel circuits 110 in the i-th row are supplied with control signals / Gel(i) and / Gcmp(i) from the scanning line driving circuit 120 in addition to the scanning signal / Gwr(i).

[0055] Control signal / Gel(i) is a generalized notation for control signals / Gel(1), / Gel(2), ..., / Gel(m-1), / Gel(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows. Similarly, control signal / Gcmp(i) is a generalized notation for control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(m-1), / Gcmp(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows.

[0056] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. In the OLED 130, the pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is optically transparent. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby emitting white light.

[0057] In the case of color display, the generated white light resonates in an optical resonator composed of, for example, a reflective film and a half mirror (not shown), and is emitted at a resonance wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light exit side of the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter before being viewed by the viewer. The optical resonator is not shown in the figure. When the electro-optical device 10 displays a monochrome image consisting of only light and dark, the color filter is omitted.

[0058] In the transistor 121 of the pixel circuit 110 in the i-th row and j-th column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116 for the voltage Vel, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. In the capacitance element 140, one end is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and the source node s of the transistor 121. In the transistor 123 of the pixel circuit 110 in the ith row and jth column, a control signal / Gcmp(i) is supplied to the gate node, and the drain node is connected to the jth column data line 14. In the transistor 124 of the pixel circuit 110 in the ith row and jth column, a control signal / Gel(i) is supplied to the gate node, and the drain node is connected to the pixel electrode 131, which is the anode of the OLED 130. A voltage Vct is applied to the common electrode 133, which functions as the cathode of the OLED 130.

[0059] In the transistors 122, 123, and 124, when the direction of current flow is reversed, the source node and the drain node are switched, but in this description, the source node and the drain node are as described above.

[0060] The other end of the capacitive element 140 may be connected to a power supply line other than the power supply line 116, or to another power supply line whose voltage is kept substantially constant. For example, a so-called MOS capacitor formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer and a gate electrode layer of a transistor is used as the capacitive element 140. Note that the parasitic capacitance of the gate node g of the transistor 121 may be used as the capacitive element 140, or a so-called metal capacitor formed by sandwiching an insulating layer between different conductive layers on a semiconductor substrate may be used.

[0061] 8 is a diagram showing an equivalent circuit of a DA conversion circuit 500 applied to the electro-optical device 10, and shows the DA conversion circuit 500 outputting a data signal to the j-th column data line 14. As described above, the DA conversion circuit 500 converts 10-bit video data Vdata into a data signal of voltage Vd(j). The video data Vdata consists of 10 bits D0 to D9, with D0 being the least significant bit, followed by D1, D2, and so on up to the most significant bit D9. In this example, of the bits D0 to D9, bits D0 to D4 are classified as lower-order bits, and bits D5 to D9 are classified as higher-order bits. In this example, bits D0 and D5 form a pair, bits D1 and D6 form a pair, and so on until bits D4 and D9 form a pair. 8, the notation D0 / D5 means bit D0 or D5, since bit D5 is supplied during the upper bit write period and bit D0 is supplied during the lower bit write period. The notations D1 / D6, D2 / D7, D3 / D8, and D4 / D9 are similar to the notation D0 / D5.

[0062] 8 has a configuration in which capacitance elements C2, C3, C4 and voltage selection circuits 512, 513, and 514 are added to the configuration of the DA conversion circuit shown in Fig. 1. In detail, voltage selection circuit 510 and capacitance element C0 are paired in correspondence with bits D0 / D5, voltage selection circuit 511 and capacitance element C1 are paired in correspondence with bits D1 / D6, and similarly, voltage selection circuit 514 and capacitance element C4 are paired in correspondence with bits D4 / D9. The capacitance size ratios of the capacitance elements C0 to C4 are "1," "2," "4," "8," and "16," respectively, assuming that the capacitance size of the capacitance element C0 is "1." The capacitance size of the junction capacitance Cser is "1," the same as in the previous example.

[0063] FIG. 9 is a diagram showing an actual circuit configuration of a DA conversion circuit 500 applied to the electro-optical device 10. As shown in FIG.

[0064] The switch Sw1 is an analog switch composed of a transmission gate and an inverter. Specifically, the transmission gate is configured by combining an N-channel transistor and a P-channel transistor. A control signal Csel_H supplied from the control circuit 30 is supplied to the gate node of the N-channel transistor, and an inverted signal of the control signal Csel_H by the inverter is supplied to the gate node of the P-channel transistor. Therefore, the switch Sw1 is turned on when the control signal Csel_H is at H level, and turned off when the control signal Csel_H is at L level.

[0065] Switches Sw2 and Sw3 are analog switches similar to switch Sw1, except that they differ in the control signal that specifies the on or off state. Switch Sw2 is in the on state when a control signal Csel_L supplied from the control circuit 30 is at H level, and is in the off state when it is at L level. Switch Sw3 is in the on state when a control signal / Rst supplied from the control circuit 30 is at L level, and is in the off state when it is at H level.

[0066] Control signals Enb0 to Enb4 are output from the control circuit 30 and are signals that specify the timing of capturing bits D0 / D5, D1 / D6, D2 / D7, D3 / D8, and D4 / D9 in that order.

[0067] FIG. 10 is a diagram showing the actual circuit configuration of the voltage selection circuit 510. As shown in FIG. The voltage selection circuit 510 includes an AND circuit Ds, a level shifter Ls, a resistance element Pd, a selector 530, and various switches, which are the switches Sw_DL, Sw_DH, Sw_VL, and Sw_VH.

[0068] The switch Sw_DL is an analog switch that is turned on when the control signal Sel_L is at H level and turned off when the control signal Sel_L is at L level between the bit line to which the bit D0 is supplied during the lower bit write period and one input terminal k of the AND circuit Ds. The switch Sw_DH is an analog switch that is connected between the bit line to which the bit D5 is supplied during the upper bit write period and the input terminal k, and is turned on when the control signal Sel_H is at H level, and turned off when the control signal Sel_H is at L level. The control signals Sel_L and Sel_H are output from the control circuit 30.

[0069] The resistor element Pd pulls down one input terminal k of the AND circuit Ds to the ground point Gnd, which is at the L level. The level of the input terminal k may become unstable if only the switches Sw_DL and Sw_DH are used. In this case, the resistor element Pd is provided to fix the input terminal k at the L level. Therefore, input terminal k becomes H level when bit D0 is "1" in the lower bit write period and when bit D5 is "1" in the upper bit write period, and is fixed at L level in other cases.

[0070] The AND circuit Ds outputs a logical product signal of the control signal Enb0 and the level appearing at the input terminal k. The AND circuit Ds is actually composed of a NAND circuit Lg1 that outputs a non-logical product signal of the control signal Enb0 and the level appearing at the input terminal k, and a NOT circuit Lg2 that outputs the negation of the non-logical product signal.

[0071] The level shifter Ls takes in the logical product signal output by the AND circuit Ds at the input terminal In, converts it to a high logic amplitude, outputs the converted high logic amplitude normal signal from the output terminal Out, and outputs the high logic amplitude inverted signal from the output terminal / Out.

[0072] The switch Sw_VL is an analog switch that is connected between the power supply line of the voltage VH_L and one input terminal q of the selector 530 and is turned on when the control signal Sel_L is at H level, and turned off when the control signal Sel_L is at L level. The switch Sw_VH is an analog switch that is connected between the power supply line of the voltage VH_H and the input terminal q and is turned on when the control signal Sel_H is at H level, and turned off when the control signal Sel_H is at L level. The input terminal q is at the voltage VH_L if the control signal Sel_L is at the H level during the lower bit write period, and at the voltage VH_H if the control signal Sel_H is at the H level during the upper bit write period.

[0073] The selector 530 selects the voltage VL or the voltage at the input terminal q in accordance with the output signal of the level shifter Ls, and applies the selected voltage to one terminal of the capacitive element C0. For convenience, the output terminal of the selector 530, i.e., one terminal of the capacitive element C0, is referred to as a node Sel_out.

[0074] The selector 530 includes transmission gates Tg1 and Tg2. When the output signal from the output terminal Out of the level shifter Ls is at the L level (when the output signal from the output terminal / Out is at the H level), the transmission gate Tg1 is in the ON state and the transmission gate Tg2 is in the OFF state, so that the node Sel_out becomes the voltage VL. On the other hand, if the output signal from the output terminal Out of the level shifter Ls is at H level (if the output signal from the output terminal / Out is at L level), the transmission gate Tg1 is in the OFF state and the transmission gate Tg2 is in the ON state, so that the node Sel_out becomes the voltage of the input terminal q. Therefore, during the upper bit write period, if the control signal Enb0 is at H level and bit D5 is "1", the node Sel_out becomes voltage VH_H, and if bit D5 is "0", the node Sel_out becomes voltage VH_L when the control signal Enb0 is at H level and bit D0 is "1", and if bit D0 is "0", the node Sel_out becomes voltage VL.

[0075] Here, the voltage selection circuit 510 corresponding to bits D0 / D5 has been described, but the voltage selection circuits 511, 512, 513 and 514 corresponding to bits D1 / D6, D2 / D7, D3 / D8 and D4 / D9, respectively, have the same configuration.

[0076] 11 and 12 are timing charts for explaining the operation of the electro-optical device 10. FIG. In the electro-optical device 10, m scanning lines 12 are scanned one by one in one frame period (V) in the order of the 1st, 2nd, 3rd, ..., mth rows. In detail, as shown in the figure, the scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) are sequentially and exclusively set to L level by the scanning line driving circuit 120 for each horizontal scanning period (H). In this embodiment, the periods during which adjacent scan signals / Gwr(1) to / Gwr(m) are at L level are not separated in time, but they may be separated. Specifically, after scan signal / Gwr(i-1) changes from L level to H level, the next scan signal / Gwr(i) may be at L level after a certain interval.

[0077] In this description, one frame period (V) refers to the time required to display one frame of an image specified by the video data Vid. If the length of one frame period (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Furthermore, the horizontal scanning period (H) is the time interval during which the scanning signals / Gwr(1) to / Gwr(m) sequentially go low; more specifically, it is the length of time from when the scanning signal / Gwr(i-1) changes from high to low until the next scanning signal / Gwr(i) changes to low.

[0078] In this embodiment, one horizontal scanning period (H) is divided into three periods: an initialization period (A), a compensation period (B), and a writing period (C). Of these, the writing period (C) is divided into a higher-order bit writing period (C-1), a reset period (C-2), and a lower-order bit period (C-3). In addition to the above periods, a light-emitting period (D) is also added as an operation of the pixel circuit 110.

[0079] The initialization period (A) is a period during which a voltage Vini for turning on the transistor 121 is supplied to the gate node g via the data line 14. The voltage Vini is a voltage that turns on the transistor 121 when applied to the gate node g of the transistor 121. The compensation period (B) is a period for causing the gate node g of the transistor 121 to converge to a threshold voltage corresponding to the threshold voltage of the transistor 121. The end of the compensation period (B) corresponds to the initial state of the DA conversion circuit 500. The write period (C) is a period during which a voltage corresponding to the gradation level is held (written) at the gate node g of the transistor 121, and more specifically, is a period during which the gate node g of the transistor 121 is changed from a voltage equivalent to the threshold voltage by an amount corresponding to the current flowing through the OLED 130. The light emitting period (D) is a period for causing a current corresponding to the voltage of the gate node g maintained during the writing period (C) to flow through the OLED 130 to emit light.

[0080] During the initialization period (A) of each horizontal scanning period (H), the control signal / Gini is at L level, the control signal Csel_L is at L level, the control signal Csel_H is at L level, the control signal / Rst is at H level, and the control signal Enb is at L level. The control signal Enb is a general term for the control signals Enb0 to Enb4. As will be described later, the phases of the control signals Enb0 to Enb4 are sequentially shifted during the upper bit write period (C-1) and the lower bit write period (C-3), but the waveforms are the same outside of these periods, and so the control signals are collectively referred to as the control signal Enb.

[0081] In the compensation period (B), the control signal / Gini changes to H level, the control signal Csel_L maintains L level, the control signal Csel_H changes to H level, the control signal / Rst changes to L level, and the control signal Enb maintains L level. In the write period (C), the control signal / Gini maintains the H level. In the upper bit write period (C-1) of the write period (C), the control signal Csel_L maintains the L level, the control signal Csel_H maintains the H level, and the control signal / Rst maintains the L level. In the reset period (C-2), the control signal Csel_L changes to the H level, the control signal Csel_H changes to the L level, and the control signal / Rst maintains the L level. In the lower bit write period (C-3), the control signal Csel_L maintains the H level, the control signal Csel_H maintains the L level, and the control signal / Rst changes to the H level.

[0082] In the upper bit write period (C-1), after the control signal Enb0 changes to H level, the control signals Enb1 to Enb4 change to H level sequentially with a delay of ΔT each. When the control signal Enb0 changes from H level to L level, the control signals Enb1 to Enb4 change to L level sequentially with a delay of ΔT each. During the reset period (C-2), the control signals Enb0 to Enb4 are at the L level. In the lower bit write period (C-3), similarly to the upper bit write period (C-1), the H level pulses of the control signals Enb1 to Enb4 are sequentially delayed by time ΔT with respect to the H level pulse of the control signal Enb0.

[0083] The operation during the horizontal scanning period (H) will be described by taking the i-th row as an example, and the pixel circuit 110 will be described by taking the pixel circuit 110 in the i-th row and j-th column as an example.

[0084] FIG. 13 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the j-th column data line 14 during the initialization period (A) of the i-th row. The initialization period (A) is a meaningless period for the DA conversion circuit 500.

[0085] In the initialization period (A), the control signal / Gini goes to the L level, causing the transistor 66 to go into the ON state. Furthermore, during the initialization period (A) of the horizontal scanning period (H) in the i-th row, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, and the control signal / Gel(i) is at H level. Therefore, during the initialization period (A), in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 is in the ON state, the transistor 123 is in the OFF state, and the transistor 124 is in the OFF state.

[0086] Therefore, during the initialization period (A), in the pixel circuit 110 in the i-th row and j-th column as shown in the figure, the voltage Vini is applied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 66, the j-th column data line 14, and the transistor 122 in that order. After the initialization period (A) ends, the compensation period (B) begins.

[0087] FIG. 14 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the j-th column data line 14 during the compensation period (B) of the i-th row. In the compensation period (B), the control signals Enb0 to Enb4 are at L level, and therefore the voltage VL is selected by the voltage selection circuits 510 to 514. Therefore, one ends of the capacitance elements C0 to C4 are at the voltage VL.

[0088] During the compensation period (B), the control signal / Gini goes to H level, causing the transistor 66 to go into an off state. Furthermore, during the compensation period (B) of the horizontal scanning period (H) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the L level, and the control signal / Gel(i) maintains the H level. As a result, in the pixel circuit 110 of the i-th row and j-th column, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0089] At the start of the compensation period (B), in the i-th row pixel circuit 110, the gate node g of the transistor 121 is at voltage Vini. When the transistor 123 is turned on while the gate node g is at voltage Vini, the transistor 121 is in a diode-connected state, i.e., the gate node g and the drain node d are connected together.

[0090] Therefore, during the compensation period (B), the voltage between the gate node g and the source node s of the transistor 121 approaches the threshold voltage Vth of the transistor 121. Then, at the end of the compensation period (B), the gate node g of the transistor 121, the data line 14, and the other end of the junction capacitance Cser become approximately equal to the threshold voltage (Vel-Vth).

[0091] During the compensation period (B), the switch Sw1 is in the off state due to the L level of the control signal Csel_L, the switch Sw2 is in the on state due to the H level of the control signal Csel_H, and the switch Sw3 is in the on state due to the L level of the control signal / Rst. Therefore, during the compensation period (B), one end of the junction capacitance Cser becomes the voltage Vrst_C. The voltage Vrst_C is approximately the same as the voltage Va in the DA conversion circuit in FIG. 1, that is, approximately the same as the threshold voltage (Vel-Vth) in the electro-optical device 10. Therefore, at the end of the compensation period (B), the charge stored in the junction capacitance Cser is reset to approximately zero, while the gate node g, drain node d, data line 14, the other end of the junction capacitance Cser, and the other ends of the capacitance elements C0 to C4 in the transistor 121 become approximately the threshold voltage (Vel-Vth).

[0092] During the compensation period (B), the voltage selection circuits 510-514 select the voltage VL, and therefore the capacitance elements C0-C4 accumulate charges corresponding to the product of the differential voltage between both ends and the capacitance size. The ratio of the charges accumulated in the capacitance elements C0-C4 is the same as the capacitance size ratio, and is "1", "2", "4", "8", and "16" in that order.

[0093] In this way, during the compensation period (B) of the DA conversion circuit 500 shown in FIG. 14, the voltage Va in the initial state of the DA conversion circuit shown in FIG. 1 is replaced by the threshold voltage (Vel-Vth).

[0094] After the compensation period (B) ends, the writing period (C) begins. The first upper bit write period (C-1) of the write period (C) is a period for changing the voltage at the gate node g of the transistor 121 from the threshold voltage according to the upper bits D5 to D9 of the video data Vdata. The second reset period (C-2) of the write period (C) is a period for making the charge accumulation state in the capacitance elements C0 to C4 almost the same as the accumulation state at the end of the compensation period (B). Of the write periods (C), the third lower bit write period (C-3) is a period for changing the voltage at the gate node g of transistor 121 from the voltage of the upper bit write period by an amount corresponding to the lower bits D0 to D4 of the video data Vdata. First, the operation during the upper bit writing period (C-1) will be described.

[0095] FIG. 15 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the j-th column data line 14 during the i-th row upper bit writing period (C-1). During the upper bit write period (C-1), the control signal Csel_L maintains the L level, the control signal Csel_H maintains the H level, and the control signal / Rst maintains the L level, so that switch Sw1 maintains the off state, switch Sw2 maintains the on state, and switch Sw3 maintains the on state.

[0096] In the upper bit write period (C-1), the second latch circuit L2 in the j-th column outputs the upper bits D5 to D9 of the video data Vdata, while the control circuit 30 sequentially outputs the control signals Enb0 to Enb4 at H level. In addition, during the upper bit write period (C-1), the control signal Sel_H is at H level, and the control signal Sel_L is at L level. Therefore, the voltage selection circuit 510 selects the voltage VH_H if the bit D5 is "1", and maintains the selection of the voltage VL if the bit is "0". Similarly, the voltage selection circuits 511 to 514 select the voltage VH_H if the corresponding higher-order bit is "1", and maintains the selection of the voltage VL if the corresponding higher-order bit is "0".

[0097] Strictly speaking, in the voltage selection circuit 510, the period during which the level of the input terminal k is input to the level shifter Ls is limited by the AND circuit Ds to the period during which the control signal Enb0 is at H level. Therefore, in the upper bit write period (C-1), the voltage selection circuit 510 takes in a level corresponding to the bit D5 appearing at the input terminal k during the period during which the control signal Enb0 is at H level, and selects the voltage VH_H or VL according to the taken-in level. Similarly, the period during which bits D6 to D9 are sequentially input to the level shifters Ls in the voltage selection circuits 511 to 514 is limited by the AND circuit Ds to the period during which the control signals Enb1 to Enb4 are at H level. Therefore, during the upper bit write period (C-1), the voltage selection circuits 511 to 514 sequentially take in levels corresponding to bits D6 to D9 during the period during which the control signals Enb0 to Enb4 are at H level, and select the voltage VH_H or VL according to the taken-in levels.

[0098] During the upper bit write period (C-1), one end of the capacitive element corresponding to the bit “0” among the capacitive elements C0 to C4 does not change from the voltage VL of the compensation period (B), and therefore the capacitive element does not contribute to the voltage increase of the data line 14. In contrast, one end of the capacitive element corresponding to the bit "1" among the capacitive elements C0 to C4 rises and changes from voltage VL to voltage VH_H during the upper bit write period (C-1). As a result, discharge occurs in the capacitive element corresponding to the bit "1" among the capacitive elements C0 to C4, and the data line 14 is raised from the threshold voltage (Vel-Vth) during the compensation period (B) by an amount corresponding to the ratio of the capacitance sizes, i.e., the weights of the bits D5 to D9.

[0099] During the upper bit writing period (C-1), in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 remains on and the transistor 123 is turned off, so that the voltage Vd(j) output from the DA conversion circuit 500 in the j-th column is applied to the gate node g of the transistor 121 via the j-th column data line 14. In the figure, the difference voltage between the voltage of the gate node g and the voltage Vel of the source node of the transistor 121 is represented as Vgs and is held in the capacitance element 140.

[0100] Note that Figure 15 shows an example in which, when bits D5 to D9 are "1", "0", "1", "0", "1" in order, one end of capacitive elements C1 and C3 is maintained at voltage VL, and one end of capacitive elements C0, C2, and C4 changes to voltage VH_H. Next, the operation during the reset period (C-2) will be described.

[0101] FIG. 16 is a diagram for explaining the operation of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the j-th column data line 14 during the i-th row reset period (C-2). During the reset write period (C-2), the control signal Csel_L changes to H level, the control signal Csel_H changes to L level, and the control signal / Rst remains at L level, so that the switch Sw1 changes to the ON state, the switch Sw2 changes to the OFF state, and the switch Sw3 remains on. In the reset write period (C-2), the control signals Enb0 to Enb4 are at L level, so that the voltage selection circuits 510 to 514 each select the voltage VL.

[0102] Therefore, in the reset write period (C-2), one end of each of the capacitance elements C0 to C4 becomes the voltage VL, and the other end of each of the capacitance elements C0 to C4 becomes the voltage Vrst_C. Since one end of the junction capacitance Cser continues to be fixed to the voltage Vrst_C from the upper bit write period (C-1), the data line 14 and the other end of the junction capacitance Cser maintain the voltage of the upper bit write period (C-1). As described above, the voltage Vrst_C is set to approximately the threshold voltage (Vel-Vth), so during the reset period (C-2), the voltage state of the capacitance elements C0 to C4 becomes approximately equal to the end of the compensation period (B), in other words, the initial state. Next, the operation during the lower bit writing period (C-3) will be described.

[0103] FIG. 17 is a diagram for explaining the operations of the pixel circuit 110 in the i-th row and j-th column and the DA conversion circuit 500 corresponding to the j-th column data line 14 during the i-th row lower bit writing period (C-3). During the lower bit write period (C-3), the control signal Csel_L remains at the H level, the control signal Csel-H remains at the L level, and the control signal / Rst changes to the H level, so that switch Sw1 remains on, switch Sw2 remains off, and switch Sw3 changes to the off state.

[0104] In the lower bit write period (C-3), the second latch circuit L2 in the j-th column outputs the lower bits D0 to D4 of the video data Vdata, while the control circuit 30 sequentially outputs the control signals Enb0 to Enb4 at H level. Furthermore, in the lower bit write period (C-3), the control signal Sel_H is at L level, and the control signal Sel_L is at H level. Therefore, the voltage selection circuit 510 selects the voltage VH_L if the bit D0 is "1", and maintains the selection of the voltage VL if the bit is "0". Similarly, the voltage selection circuits 511 to 514 select the voltage VH_L if the corresponding lower bit is "1", and maintains the selection of the voltage VL if the corresponding lower bit is "0".

[0105] Strictly speaking, in the lower bit write period (C-3), the period during which bits D0 to D4 are sequentially input to the level shifters Ls in the voltage selection circuits 510 to 514 is limited by the AND circuit Ds to the period during which the control signals Enb0 to Enb4 are sequentially at H level, as in the upper bit write period (C-1). Therefore, in the lower bit write period (C-3), the voltage selection circuits 510 to 514 sequentially take in levels corresponding to bits D0 to D4 during the period during which the control signals Enb0 to Enb4 are at H level, and select the voltage VH_L or VL according to the taken levels.

[0106] During the lower bit write period (C-3), one end of the capacitive element corresponding to the bit "0" among the capacitive elements C0 to C4 does not change from the voltage VL of the reset period (C-2), and therefore the capacitive element does not contribute to the voltage increase of the data line 14. On the other hand, one end of the capacitance element corresponding to the bit "1" among the capacitance elements C0 to C4 rises and changes from voltage VL to voltage VH_L during the lower bit write period (C-3), causing discharge in the capacitance element corresponding to the bit "1" among the capacitance elements C0 to C4.

[0107] It should be noted that during the upper bit write period (C-1), switch Sw1 is in the off state and switch Sw2 is in the on state, whereas during the lower bit write period (C-3), switch Sw1 is in the on state and switch Sw2 is in the off state. That is, during the upper bit write period (C-1), the other ends of the capacitance elements C0 to C4 are directly connected to the data line 14, and a voltage change at one end of the capacitance elements C0 to C4 directly changes the voltage of the data line 14. In contrast, during the lower bit write period (C-3), the other ends of the capacitance elements C0 to C4 are coupled to the data line 14 via the junction capacitance Cser, and therefore the voltage change at one end of the capacitance elements C0 to C4 is compressed at a compression ratio determined by the junction capacitance Cser and the capacitance elements C0 to C4, and increases the voltage of the data line 14. The compression ratio in this configuration is 1 / 32 (=1 / (1+1++2+4+8+16)).

[0108] In this way, during the lower bit write period (C-3), the jth column DA conversion circuit 500 increases the voltage of the jth column data line 14 from the voltage corresponding to the upper bits D5 to D9 during the upper bit write period (C-1) by the voltage corresponding to the lower bits D0 to D4.

[0109] During the lower bit writing period (C-3) of the i-th row, in the pixel circuit 110 of the i-th row, the transistor 122 continues to be in the on state, the transistor 123 continues to be in the off state, and the transistor 124 continues to be in the off state. Therefore, at the end of the lower bit write period (C-3), i.e., at the end of the write period (C), the gate node g of the transistor 121 in the pixel circuit 110 at row i and column j changes from the threshold voltage to a voltage that is changed by an amount corresponding to bits D0 to D9 of the video data Vdata, i.e., a voltage that specifies the brightness of the OLED at row i and column j.

[0110] 17 shows an example in which the bits D0 to D4 are, in order, "0", "1", "0", "1", and "0". In detail, an example is shown in which one ends of the capacitance elements C1 and C3 change from voltage VL to voltage VH_L, and one ends of the capacitance elements C0, C2, and C4 are maintained at voltage VL.

[0111] (a), (b), (c), and (d) in Figure 18 are diagrams showing changes in voltage Vd(j) on the jth column data line 14 during the compensation period (B), the upper bit writing period (C-1), the reset period (C-2), and the lower bit writing period (C-3). Among these, (a) shows the voltage change when the bits D0 to D9 are all "1." When the bits D0 to D9 are all "1," the OLED 130 is designated to have the minimum brightness. (b) shows the voltage change when the upper bits D5 to D9 are "1" and the lower bits D0 to D4 are "0". (c) shows the voltage change when the upper bits D5 to D9 are "0" and the lower bits D0 to D4 are "1". (d) shows the voltage change when bits D0 to D9 are all "0." When bits D0 to D9 are all "0," the OLED 130 is designated to have the maximum brightness.

[0112] In the compensation period (B), (a), (b), (c) and (d) are all common in that the voltage Vini converges to the threshold voltage (Vel-Vth). In the upper bit write period (C-1), as shown in (a) and (b), the voltage rises stepwise from the threshold voltage (Vel-Vth) to a voltage according to the upper bits D5 to D9. In the reset period (C-2), (a), (b), (c) and (d) are all common in that the voltage in the upper bit write period (C-1) is maintained. In the lower bit write period (C-3), as shown in (a) and (c), the voltage rises stepwise from the voltage in the upper bit write period (C-1) to a voltage according to the lower bits D0 to D4.

[0113] The reason why the voltage rises stepwise in the upper bit write period (C-1) and the lower bit write period (C-3) is that the control signals Enb0 to Enb4 go high in this order and rise according to the bits D0 / D5, D1 / D6, D2 / D7, D3 / D8, and D4 / D9. The reason why the rise is larger the later in the stepwise rise is because the weights of the bits D0 / D5, D1 / D6, D2 / D7, D3 / D8, and D4 / D9 increase in order.

[0114] FIG. 19 is a diagram for explaining the operation of the pixel circuit 110 in the ith row and jth column during the light emission period (D) of the ith row. Before the light-emitting period (D) of the i-th row, the control signal / Gcmp(i) becomes H level. When the light-emitting period (D) of the i-th row is reached, the control signal / Gel(i) is inverted to L level, and the transistor 124 is turned on. Therefore, a current Ids corresponding to the voltage Vgs held by the capacitance element 140 flows through the OLED 130 via the transistor 121. Therefore, the OLED 130 emits light at a brightness corresponding to the current Ids.

[0115] 19 shows an example in which the light-emitting period (D) continues after the control signal / Gel(i) goes to L level after the selection of the i-th scanning line 12 is completed, but the period in which the control signal / Gel(i) goes to L level may be intermittent or adjusted according to the specified brightness. Furthermore, the level of the control signal / Gel(i) in the light-emitting period (D) may be increased from the L level in the compensation period (B). In other words, the level of the control signal / Gel(i) in the light-emitting period (D) may be an intermediate level between H level and L level.

[0116] Furthermore, during the light emission period (D) of the i-th row, the DA conversion circuit 500 corresponding to the j-th column may be operating during the horizontal scanning period (H) for rows other than the i-th row, so the DA conversion circuit 500 is omitted in Figure 19.

[0117] 13 to 17, the operation is shown focusing on the DA conversion circuit 500 corresponding to the jth column and the pixel circuit 110 in the i-th row and j-th column during the i-th row horizontal scanning period (H), but similar operations are performed for the DA conversion circuits 500 and pixel circuits 110 corresponding to columns other than the j-th column. Also, in Figures 13 to 17, we have focused on the horizontal scanning period (H) of the i-th row and explained the operation of that horizontal scanning period (H), but similar operations are sequentially performed for the horizontal scanning periods (H) of the 1st, 2nd, 3rd, ..., mth rows.

[0118] In the pixel circuit 110, the voltage Vgs in the writing period (C) and the light-emitting period (D) is a voltage obtained by changing the threshold voltage in the compensation period (B) in accordance with the gradation level of the pixel circuit 110. Similar operations are performed in the other pixel circuits 110, so in this embodiment, a current corresponding to the gradation level flows through the OLED 130 in a state in which the threshold voltages of the transistors 121 are compensated across all pixel circuits 110 in m rows and n columns. Therefore, in this embodiment, the luminance variation is reduced, enabling a high-quality display.

[0119] A DA conversion circuit 500 that converts 10-bit data to analog requires only five capacitance elements (C0 to C4), half the number of bits, and one junction capacitance (Cser), which roughly halves the number of capacitance elements required compared to a configuration in which a capacitance element is provided for each bit. Therefore, when integrating the DA conversion circuit 500 on a semiconductor substrate, for example, it is possible to simplify the configuration and save space.

[0120] Furthermore, in the electro-optical device 10, the voltage selection circuits 510-514 are only required to switch the voltage applied to one end of the capacitive element corresponding to the lower bit during the lower bit writing period in accordance with the lower bit, and do not need to switch the voltage in consideration of the upper bit paired with the lower bit. Furthermore, according to this embodiment, the number of voltages selected by the voltage selection circuits 510-514 is only three, which simplifies the configuration of the power supply circuit 15.

[0121] In the electro-optical device 10, the periods during which the control signals Enb0 to Enb4 are at H level are sequentially delayed by a time ΔT during the upper bit write period (C-1) and the lower bit write period (C-3). The reason for this is that if the control signals Enb0 to Enb4 are all set to H level at the same time, voltage switching occurs simultaneously at one end of the capacitance elements C0 to C4, and the spike fluctuations caused by the voltage switching become larger and propagate to various parts, particularly the data line 14, thereby reducing the DA conversion accuracy. Therefore, in this embodiment, the phases of the control signals Enb0 to Enb4 are shifted sequentially so that the voltages do not switch simultaneously. According to this embodiment, the influence of voltage fluctuations due to spikes caused by voltage switching is reduced, and therefore, the deterioration of DA conversion accuracy is suppressed. The order in which the control signals Enb0 to Enb4 become H level does not have to be the same as this example.

[0122] Second Embodiment Next, a DA conversion circuit according to a second embodiment will be described.

[0123] 20 is a circuit diagram showing an example of a DA converter circuit 500 according to the second embodiment. In this example, the DA converter circuit 500 converts data consisting of six bits, D0 to D5, into an analog voltage. Of the six bits, the least significant bit is D0, and the weights of D1, D2, and so on increase from bit D0, until the most significant bit is D5. In this example, bits D0 to D5 are classified into lower, middle, and upper bits. Specifically, bits D0 and D1 are classified as lower bits, bits D2 and D3 are classified as middle bits, and bits D4 and D5 are classified as upper bits. Also, in this example, bits D0, D2, and D4 form a pair, and bits D1, D3, and D5 form a pair.

[0124] In the DA conversion circuit 500 according to the second embodiment, the operation period is divided into the following five periods. Specifically, the operation period is divided into an upper-bit writing period, a first reset period, a middle-bit writing period, a second reset period, and a lower-bit writing period.

[0125] The DA conversion circuit 500 shown in FIG. 20 has a configuration in which a junction capacitor Cser_M and switches Sw3M and Sw4 are added to the first embodiment shown in FIG. 1. Note that the junction capacitor Cser_L and the switch Sw3L in FIG. 20 are merely for convenience of changing the reference numerals of the junction capacitor Cser and the switch Sw3 shown in FIG. 1 and are substantially the same. Note that the capacitance sizes of the junction capacitors Cser_L and Cser_M are in the relationship of Cser_L < Cser_M.

[0126] The voltage selection circuit 510 selects the voltage VH_H when bit D4 is "1" in the upper-bit writing period, selects the voltage VH_M when bit D2 is "1" in the middle-bit writing period, selects the voltage VH_L when bit D0 is "1" in the lower-bit writing period, and selects the voltage VL in other cases. The point where the voltage selection circuit 510 applies the selected voltage to one end of the capacitive element C0 is the same as that in the first embodiment. The voltage selection circuit 511 selects the voltage VH_H when bit D5 is "1" during the upper bit write period, selects the voltage VH_M when bit D3 is "1" during the middle bit write period, selects the voltage VH_L when bit D1 is "1" during the lower bit write period, and selects the voltage VL in other cases. The voltage selection circuit 511 applies the selected voltage to one end of the capacitive element C1, similar to the first embodiment.

[0127] One end of the switch Sw3M is connected to one end of the switch Sw3L. That is, one end of the switch Sw3M is applied with the voltage Vrst_C together with one end of the switch Sw3L. Furthermore, one end of the switch Sw4 is connected to the node Nd, and the other ends of the switches Sw3M and Sw4 are connected to one end of the junction capacitance Cser_M. The other end of the junction capacitance Cser_M is connected to the output terminal Da_out.

[0128] 20, the initial state of the DA conversion circuit 500 is such that switch Sw1 is off, switches Sw2, Sw3L, and Sw3M are on, and switch Sw4 is off. In this state, the output terminal Da_out and node Nd are at a common voltage Va, and both voltage selection circuits 510 and 511 select voltage VL, so that capacitance elements C0 and C1 are charged to a voltage (Va-VL). Furthermore, junction capacitances Cser_L and Cser_M are charged to a voltage (Va-Vrst_C).

[0129] 21 is a diagram showing the operation during the upper bit write period in the DA conversion circuit 500. As shown in the diagram, during the upper bit write period, the switch Sw1 is maintained in the off state, the switches Sw2, Sw3L, and Sw3M are maintained in the on state, and the switch Sw4 is maintained in the off state. In this state, the voltage selection circuit 510 selects the voltage VH_H if the bit D4 is "1", and selects the voltage VL if the bit D4 is "0". Furthermore, the voltage selection circuit 511 selects the voltage VH_H if the bit D5 is "1", and selects the voltage VL if the bit D5 is "0". In the second embodiment, during the upper bit write period, as in the first embodiment (see Figure 2), the node Nd is directly connected to the output terminal Da_out, so the voltage increase at the output terminal Da_out according to bits D4 and D5 is determined by the capacitance ratio of the capacitance elements C0, C1 and the junction capacitance (Cser_L + Cser_M).

[0130] Specifically, the capacitance ratios of the capacitance elements C0, C1 and the junction capacitance (Cser_L+Cser_M) are set to "1", "2" and "1" in that order. In this setting, when bit D4 is "1" and bit D5 is "0", the voltage increase at the output terminal Da_out is assumed to be a ratio of "16". In this setting, when bit D4 is "0" and bit D5 is "1", the voltage increase at output terminal Da_out is doubled to "32". Also, if bit D4 is "1" and bit D5 is "1", the voltage increase at output terminal Da_out is "48", which is the sum of "16" and "32". If both bits D4 and D5 are "0", the voltage Vb at the output terminal Da_out does not change from the voltage Va, that is, the voltage increase is "0".

[0131] 22 is a diagram showing the operation of the first reset period in the DA conversion circuit 500. As shown in the diagram, in the first reset period, with the lower-order bit write period as the reference, the switch Sw2 changes to the OFF state and the switch Sw4 changes to the ON state. In this state, both voltage selection circuits 510 and 511 select voltage VL, so that at the output terminal Da_out, the voltage Vb from the immediately preceding upper bit write period is maintained, and the capacitance elements C0 and C1 are charged to a voltage (Vrst_C-VL), similar to the reset period in the first embodiment. Although the switch Sw4 is in the on state here, it is sufficient if one or both of the switches Sw1 and Sw4 are in the on state.

[0132] 23 is a diagram showing the operation during the middle-order bit write period in the DA conversion circuit 500. As shown in the diagram, during the middle-order bit write period, the switch Sw3M changes to the OFF state with respect to the first reset period. In this state, the voltage selection circuit 510 selects the voltage VH_M if the bit D2 is "1", and selects the voltage VL if the bit D2 is "0". Furthermore, the voltage selection circuit 511 selects the voltage VH_M if the bit D3 is "1", and selects the voltage VL if the bit D3 is "0". During the middle bit writing period, the node Nd is connected to the output terminal Da_out via the junction capacitance Cser_M, so the voltage change at the node Nd is compressed at a compression ratio determined by the capacitance sizes of the capacitance elements C0, C1, and the junction capacitances Cser_M and Cser_L, thereby increasing the voltage at the output terminal Da_out. Here, the compression ratio during the middle bit writing period is set to, for example, 1 / 4.

[0133] For ease of explanation, VH_M=VH_H Let's say. Also, the voltage at the output terminal Da_out during the middle bit writing period is set to Vc. It can be considered that the voltage Vc at the output terminal Da_out during the middle bit write period rises from the voltage Vb during the upper bit write period by a voltage obtained by multiplying the voltage rise at the node Nd by the compression ratio.

[0134] If bit D2 is "1" and bit D3 is "0", the voltage increase at output terminal Da_out is "4", which is the voltage increase "16" due to capacitance element C0 multiplied by 1 / 4 of the compression ratio. If bit D2 is "0" and bit D3 is "1", the voltage increase at output terminal Da_out is "8", which is the voltage increase "32" due to capacitance element C1 multiplied by 1 / 4 of the compression ratio. If bits D2 and D3 are both "1", the sum of "4" and "8" is "12". If both bits D2 and D3 are "0", the voltage Vc at the output terminal Da_out does not change from the voltage Vb, that is, the voltage increase at the output terminal Da_out becomes "0".

[0135] 24 is a diagram showing the operation of the DA conversion circuit 500 in the second reset period. As shown in the figure, in the second reset period, with the middle-order bit write period as the reference, the switch Sw1 changes to the ON state and the switch Sw4 changes to the OFF state. In this state, the voltage selection circuits 510 and 511 both select the voltage VL, and therefore, similar to the first reset period, the capacitance elements C0 and C1 are charged to the voltage (Vrst_C-VL) while the output terminal Da_out is held at the voltage Vc from the immediately preceding middle-order bit write period.

[0136] 25 is a diagram showing the operation during the lower bit write period in the DA conversion circuit 500. As shown in the diagram, during the lower bit write period, the switch Sw3L changes to the OFF state when viewed from the second reset period as a reference. In this state, the voltage selection circuit 510 selects the voltage VH_L if the bit D0 is "1", and selects the voltage VL if the bit D1 is "0". Furthermore, the voltage selection circuit 511 selects the voltage VH_L if the bit D1 is "1", and selects the voltage VL if the bit D1 is "0". During the lower bit write period, the node Nd is connected to the output terminal Da_out via the junction capacitance Cser_L, so the voltage change at the node Nd is compressed at a compression ratio determined by the capacitance sizes of the capacitance elements C0, C1 and the junction capacitance Cser_L, causing the voltage at the output terminal Da_out to increase. Here, the compression ratio during the lower-order bit writing period is set to, for example, 1 / 16. Furthermore, during the lower bit write period, the other end of the junction capacitance Cser_M is not electrically connected to any part, so the capacitance size of the junction capacitance Cser_M does not affect the compression ratio during the lower bit write period.

[0137] For ease of explanation, VH_L=VH_M Let's say. It can be considered that the voltage Vd at the output terminal Da_out during the lower bit write period rises from the voltage Vc during the middle bit write period by a voltage obtained by multiplying the voltage rise at the node Nd by the compression ratio.

[0138] Therefore, if bit D0 is "1" and bit D1 is "0", the voltage increase at output terminal Da_out is "1", which is the voltage increase due to capacitance element C0, "16", multiplied by the compression ratio 1 / 16. If bit D0 is "0" and bit D1 is "1", the voltage increase at output terminal Da_out is "2", which is the voltage increase "32" due to capacitance element C1 multiplied by the compression ratio 1 / 16. If bits D0 and D1 are both "1", the voltage Vd at the output terminal Da_out is "3", which is the sum of "1" and "2". If both bits D0 and D1 are "0", the voltage Vd at the output terminal Da_out does not change from the voltage Vc, that is, the voltage increase at the output terminal Da_out becomes "0".

[0139] In the DA converter circuit 500 according to the second embodiment, the output terminal Da_out first rises from voltage Va during the most significant bit write period by a voltage corresponding to one of the ratios of "0," "16," "32," or "48" depending on the two most significant bits D4 and D5, to voltage Vb, and is then held at this voltage for the first reset period. Next, during the middle-significant bit write period, the output terminal Da_out rises from voltage Vb during the most significant bit write period by a voltage corresponding to one of the ratios of "0," "4," "8," or "12" depending on the two middle-significant bits D2 and D3, to voltage Vc, and is then held at this voltage for the second reset period. Then, during the least significant bit write period, the output terminal Da_out rises from voltage Vc during the middle-significant bit write period by a voltage corresponding to one of the ratios of "0," "1," "2," or "3" depending on the two least significant bits D0 and D1, to voltage Vd. Therefore, in the DA conversion circuit 500 according to the second embodiment, the voltage Vd at the output terminal Da_out changes from the initial voltage Va to one of 64 levels from "0" to "63" according to the six bits D0 to D6.

[0140] In the second embodiment, the DA conversion circuit 500 is configured to convert 6-bit data into an analog voltage, but a simpler configuration, for example, to convert 3-bit data into an analog voltage, is also possible. When converting 3-bit data into an analog voltage, the most significant bit D2, the middle bit D1, and the least significant bit D0 form a pair, and one of the capacitance elements C0 is provided for this pair.

[0141] Here, the operation period of the DA conversion circuit 500 has been described in chronological order as the upper bit write period, the first reset period, the middle bit write period, the second reset period, and the lower bit write period, but is not limited to this order. For example, it is sufficient to provide the first or second reset period between the write periods of each bit. Specifically, contrary to the above example, the write operation may proceed in the order of a lower bit write period, a second reset period, a middle bit write period, a first reset period, and an upper bit write period.

[0142] In this configuration, the output terminal Da_out first rises from the voltage Va during the lower-order bit write period by a voltage corresponding to a ratio of "0," "1," "2," or "3" depending on the two lower-order bits D0 and D1. Then, during the middle-order bit write period, the output terminal Da_out rises from the voltage during the lower-order bit write period by a voltage corresponding to a ratio of "0," "4," "8," or "12" depending on the two middle-order bits D2 and D3. Then, during the upper-order bit write period, the output terminal Da_out rises from the voltage during the middle-order bit write period by a voltage corresponding to a ratio of "0," "8," "16," or "32" depending on the two upper-order bits D4 and D5.

[0143] The junction capacitance Cser_M is an example of a "second junction capacitance," and the bit D2 is an example of a "middle bit paired with a lower bit."

[0144] FIG. 26 is a diagram showing an equivalent circuit of the DA conversion circuit 500 applied to the electro-optical device 10 according to the second embodiment, and shows the DA conversion circuit 500 that outputs a data signal to the j-th data line 14. Here, the DA conversion circuit 500 converts 12-bit video data Vdata into an analog data signal. The 12 bits are bits D0 to D11, with D0 being the least significant bit and D11 being the most significant bit. Bits D0 to D3 are classified as low-order, bits D4 to D7 are classified as middle-order, and bits D8 to D11 are classified as high-order.

[0145] The DA converter circuit 500 shown in FIG. 26 has a configuration in which capacitance elements C2 and C3 and voltage selection circuits 512 and 513 are added to the DA converter circuit shown in FIG. In detail, voltage selection circuit 510 and capacitance element C0 are paired in correspondence with bits D0 / D4 / D8, voltage selection circuit 511 and capacitance element C1 are paired in correspondence with bits D1 / D5 / D9, and similarly, voltage selection circuit 513 and capacitance element C3 are paired in correspondence with bits D3 / D7 / D11. The ratios of the capacitance sizes of the capacitive elements C0 to C3 are "1," "2," "4," and "8," respectively, where the capacitance size of the capacitive element C0 is "1."

[0146] FIG. 27 is a diagram showing an actual circuit configuration of the DA conversion circuit 500. Compared to FIG. 9, the DA conversion circuit 500 shown in this figure has a configuration in which the switch Sw3 is replaced with a switch Sw3L, switches Sw3M and Sw4 are added, and the capacitive element C4 and the voltage selection circuit 514 are eliminated. The switch Sw3L is an analog switch made up of a transmission gate and an inverter, and is turned on when the control signal / Rst_CL supplied from the control circuit 30 is at L level, and is turned off when the control signal / Rst_CL is at H level. The switch Sw3M is a similar analog switch, and is turned on when the control signal / Rst_CM supplied from the control circuit 30 is at L level, and is turned off when the control signal / Rst_CM is at H level. The switch Sw4 is a similar analog switch, and is turned on when the control signal Csel_M supplied from the control circuit 30 is at H level, and is turned off when the control signal Csel_M is at L level.

[0147] FIG. 28 is a diagram showing the circuit configuration of the voltage selection circuit 510 in FIG. The voltage selection circuit 510 shown in this figure has a configuration in which switches Sw_VM and Sw_DM are added compared to FIG.

[0148] The switch Sw_DM is an analog switch that is connected between the bit line to which the bit D4 is supplied and the input terminal k of the AND circuit Ds during the middle-order bit write period, and is turned on when the control signal Sel_M is at H level and turned off when it is at L level. The control signal Sel_M is supplied from the control circuit 30, and is turned H level during the middle-order bit write period and is turned L level otherwise. The switch Sw_VM is an analog switch that is connected between the power supply line of the voltage VH_M and the input terminal q of the selector 530 and is turned on when the control signal Sel_M is at H level, and is turned off when the control signal Sel_M is at L level.

[0149] The operation of the DA conversion circuit 500 shown in FIG. 25 can be easily inferred from the explanations of FIGS. 13 to 17 and FIGS. 20 to 25, and therefore the explanation will be omitted.

[0150] <Modifications and application examples> The above-described first and second embodiments (hereinafter referred to as "embodiments, etc.") can be modified or applied in various ways as follows.

[0151] In the electro-optical device 10 according to the embodiments, the first period of the horizontal scanning period (H) is the initialization period (A), during which a voltage Vini is applied to the data line 14 and the gate node g of the transistor 121. Before the initialization period (A), a period may be provided during which a voltage Vel, for example, is applied to the data line 14 and the gate node g of the transistor 121, thereby resetting the display state from the previous horizontal scanning period.

[0152] Although the electro-optical device 10 according to the embodiment and the like has been described using the OLED 130 as an example of a display element, other display elements may be used, for example, LEDs may be used as the display elements. Furthermore, as the DA conversion circuit 500, the example in FIG. 1 shows a 4-bit conversion example, the example in FIG. 8 shows a 10-bit conversion example, the example in FIG. 20 shows a 6-bit conversion example, and the example in FIG. 26 shows a 12-bit conversion example, but the number of bits before conversion is not limited to these examples.

[0153] <Electronic equipment> Next, an electronic device that actually uses the electro-optical device 10 to which the DA conversion circuit 500 according to the embodiment and the like is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized, high-definition displays. Therefore, a head-mounted display will be used as an example of the electronic device.

[0154] FIG. 29 is a diagram showing the appearance of a head-mounted display, and FIG. 30 is a diagram showing its optical configuration. First, as shown in Fig. 29, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to ordinary eyeglasses. Furthermore, as shown in Fig. 30, the head mounted display 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320 and behind the lenses 301L and 301R (below in the figure). The image display surface of the electro-optical device 10L is disposed on the left side in FIG. 30. As a result, the image displayed by the electro-optical device 10L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed on the right side, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction.

[0155] In this configuration, a person wearing the head-mounted display 300 can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state, with the images superimposed on the outside. Furthermore, in this head-mounted display 300, when the electro-optical device 10L displays the image for the left eye and the electro-optical device 10R displays the image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0156] In addition to the head-mounted display 300, electronic devices including the electro-optical device 10 can also be applied to electronic viewfinders in video cameras and interchangeable lens digital cameras, smart watches, display units of wearable devices, light bulbs in projection projectors, and the like.

[0157] <Additional Notes> From the above-described exemplary embodiments, the following aspects can be understood, for example.

[0158] A DA conversion circuit according to one aspect 1 includes a first capacitive element having a first terminal and a second terminal, and being initially charged to a first voltage between the first terminal and the second terminal, and a first junction capacitance having a third terminal and a fourth terminal, wherein during a first period, the potential of the first terminal is maintained or changed in accordance with a first higher-order bit of input data, during a second period, the potential of the fourth terminal is maintained and the first voltage is charged between the first terminal and the second terminal, and during a third period, the second terminal is connected to the fourth terminal via the first junction capacitance, and the potential of the first terminal is maintained or changed in accordance with a second lower-order bit paired with the first bit, and the potential of the fourth terminal is output. According to the DA conversion circuit of aspect 1, when applying a voltage to the first capacitive element, a configuration such as a memory is not required, and the number of voltages is reduced, so that the configuration can be simplified.

[0159] A DA conversion circuit according to a specific aspect 2 of aspect 1 includes a switch control circuit, a first switch that controls the electrical connection between the second terminal and the third terminal, a second switch that controls the electrical connection between the second terminal and the fourth terminal, and a third switch that controls the electrical connection between a power supply line to which an initial potential is applied and the third terminal, wherein the switch control circuit sets the first switch in an off state, the second switch in an on state, and the third switch in an on state during the first period, sets the first switch in an on state, the second switch in an off state, and the third switch in an off state during the second period, and sets the third switch in an off state during the third period.

[0160] A specific aspect 3 of aspect 1 is a DA conversion circuit having a fifth terminal and a sixth terminal, further including a second capacitive element that is charged to the first voltage in the initial state and has a capacitance size larger than that of the first capacitive element, the sixth terminal being electrically connected to the second terminal, and during the first period, maintaining or changing the potential of the fifth terminal in accordance with a third bit that is higher than the first bit, and during the second period, the second capacitive element being charged to the first voltage, and during the third period, maintaining or changing the potential of the fifth terminal in accordance with a fourth bit that is a lower bit and pairs with the third bit.

[0161] A DA conversion circuit according to a specific aspect 4 of aspect 1 further includes a second junction capacitor having a seventh terminal and an eighth terminal and having a capacitance size larger than the capacitance size of the first junction capacitor, wherein the eighth terminal is electrically connected to the fourth terminal, and during a period different from the first period, the second period, and the third period, the second terminal is in a state where it is connected to the fourth terminal via the second junction capacitor, and the seventh terminal is in a state where it is electrically connected to the second terminal, and the potential of the first terminal is maintained or changed in accordance with the first bit and a middle fifth bit that forms a pair with the second bit.

[0162] An electro-optical device according to aspect 5 includes a DA conversion circuit according to any one of claims 1 to 4, in which the input data is data corresponding to a gradation level, a data line electrically connected to the fourth terminal, a scanning line, and a pixel circuit provided corresponding to the scanning line and the data line, wherein the pixel circuit has a first transistor and a light-emitting element, and the first transistor supplies a current to the light-emitting element according to the voltage between the gate node of the first transistor and the source node of the first transistor during a light-emitting period.

[0163] In an electro-optical device according to a specific aspect 6 of aspect 5, the pixel circuit has a second transistor that electrically connects the data line and the gate node of the first transistor, and a third transistor that electrically connects the data line and the source node of the first transistor, and the on state of the second transistor and the third transistor is the initial state.

[0164] An electronic device according to a seventh aspect includes the electro-optical device according to the fifth aspect. [Explanation of symbols]

[0165] 10...electro-optical device, 12...scanning line, 14...data line, 30...control circuit, 50...data signal output circuit, 60...auxiliary circuit, 110...pixel circuit, 120...scanning line driving circuit, 121-124...transistor, 130...OLED, 300...head mounted display, 500...DA conversion circuit, C0-C4...capacitive elements, Cser, Csel_L, Csel_M...junction capacitance, Sw1, Sw2, Sw3, Sw3L, Sw3M...switch, Da_out...output terminal, 510-514...voltage selection circuit.

Claims

1. a first capacitance element having a first end and a second end, the first end and the second end being initially charged to a first voltage; a first junction capacitor having a third end and a fourth end; Including, In the first period, maintaining or changing the potential of the first end in response to a first most significant bit of the input data; In the second period, The potential between the first terminal and the second terminal is charged to the first voltage while the potential of the fourth terminal is maintained, In the third period, the second end is connected to the fourth end via the first junction capacitance, The potential of the first terminal is maintained or changed in accordance with a second bit that is a lower bit paired with the first bit, and the potential of the fourth terminal is output. DA conversion circuit.

2. A switch control circuit; a first switch that controls an electrical connection between the second end and the third end; a second switch that controls an electrical connection between the second end and the fourth end; a third switch that controls an electrical connection between the power supply line to which the initial potential is applied and the third end; Including, The switch control circuit In the first period, The first switch is turned off, the second switch is turned on, and the third switch is turned on; In the second period, The first switch is turned on and the second switch is turned off, In the third period, The third switch is turned off.

2. The DA conversion circuit according to claim 1.

3. a second capacitance element having a fifth terminal and a sixth terminal, being charged to the first voltage in the initial state, and having a capacitance size larger than that of the first capacitance element; Further including, the sixth end is electrically connected to the second end; In the first period, maintaining or changing the potential of the fifth end in response to a third bit that is higher than the first bit; In the second period, the second capacitive element is charged to the first voltage; In the third period, The potential of the fifth terminal is maintained or changed in accordance with a fourth bit which is a lower bit and which forms a pair with the third bit. The electro-optical device according to claim 1 .

4. a second junction capacitor having a seventh end and an eighth end and a capacitance size larger than a capacitance size of the first junction capacitor; the eighth end is electrically connected to the fourth end; In a period different from the first period, the second period, and the third period, the second end is connected to the fourth end via the second junction capacitance, the seventh end is electrically connected to the second end, The potential of the first end is maintained or changed in accordance with the first bit and a middle fifth bit paired with the second bit. The electro-optical device according to claim 1 .

5. 5. A DA conversion circuit according to claim 1, wherein the input data is data corresponding to a gradation level; a data line electrically connected to the fourth end; Scan lines and pixel circuits provided corresponding to the scanning lines and the data lines; Including, the pixel circuit includes a first transistor and a light emitting element; The first transistor is During a light emission period, a current corresponding to a voltage between the gate node of the first transistor and the source node of the first transistor is supplied to the light emitting element. Electro-optical device.

6. The pixel circuit a second transistor electrically connecting the data line and a gate node of the first transistor; a third transistor electrically connecting the data line and a source node of the first transistor; and The on-state of the second transistor and the third transistor is the initial state. The electro-optical device according to claim 5 .

7. An electronic device comprising the electro-optical device according to claim 5 .

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