Display device and method for manufacturing display device

Abstract

To solve various problems with sub-pixels.SOLUTION: A display device is such that, in each sub-pixel, a cathode electrode layer and a power connection line at each undercut are electrically connected to each other via a structure providing the undercut, so that power can be stably supplied to each of sub-pixels via the power connection line electrically connected to a power line.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present specification relates to a display device and a method for manufacturing the same, and more particularly to a display device having a structure for applying power to a cathode electrode layer, and a method for manufacturing the same. [Background technology]

[0002] Display devices are configured in various forms, such as televisions, monitors, smartphones, tablet PCs, laptops, and wearable devices.

[0003] As an example of a display device, an organic light emitting display (OLED), which is a self-emissive display device, is advantageous in terms of power consumption due to low voltage driving, as well as excellent color realization, response speed, viewing angle, and light-dark contrast ratio.

[0004] The organic light emitting display device may include a plurality of pixels defined by gate lines and data lines that intersect with each other.

[0005] In this case, power can be applied to each pixel to drive a plurality of pixels. Summary of the Invention [Problem to be solved by the invention]

[0006] The display device may include a power supply unit that applies power to a plurality of pixels, and power wiring that supplies power from the power supply unit.

[0007] The power supply wiring may be a high potential voltage (VDD) wiring or a low potential voltage (VSS) wiring.

[0008] For example, when the display device is an organic light-emitting display device, the low-potential voltage wiring can apply a low-potential voltage to a cathode electrode constituting an organic light-emitting diode.

[0009] When a low potential voltage is applied to the cathode electrode, each pixel including an organic light emitting diode connected to the cathode electrode can emit light.

[0010] In this way, in order to emit light from a plurality of pixels arranged in a display area, a low potential voltage must be applied to the cathode electrodes connected to the plurality of pixels, and the cathode electrodes can be formed over the entire display area.

[0011] For example, the cathode electrode may be formed in the form of a surface electrode that covers the entire surface of the display area and may be formed as a common electrode for a plurality of pixels.

[0012] However, when the cathode electrode is formed in the form of a surface electrode that covers the entire display area, a parasitic capacitor may be formed between the cathode electrode and the data line that are arranged to overlap each other.

[0013] When a parasitic capacitor is formed between the cathode electrode and the data line, a delay in electrical transmission speed (RC delay) occurs, which may make it difficult to drive the display device at high speed.

[0014] For this reason, the inventors of the present application have conducted various experiments to reduce the occurrence of the delay phenomenon in the electrical transmission speed of the display device.

[0015] Through various experiments, the inventors of the present specification have discovered a display device and a method for manufacturing the display device, which has a structure that reduces the occurrence of parasitic capacitance between the cathode electrode layer and the data wiring and can supply stable power to the cathode electrode layer.

[0016] The problem to be solved by the embodiments of the present specification is to provide a display device having a structure capable of stably supplying power to each of a plurality of sub-pixels, and a method for manufacturing the display device.

[0017] In addition, an object of the present invention is to provide a display device and a method for manufacturing the display device, which can improve the light extraction efficiency of an organic light-emitting layer included in a plurality of sub-pixels.

[0018] In addition, the problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device that can reduce the occurrence of lateral leakage current in an organic light-emitting layer included in a plurality of sub-pixels.

[0019] In addition, the problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device that can reduce the occurrence of parasitic capacitance between a cathode electrode layer and a data line.

[0020] In addition, the problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device that can reduce damage to organic light-emitting layers that may occur during the process of forming organic light-emitting layers included in multiple sub-pixels.

[0021] The problems to be solved by the embodiments of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0022] A display device according to an embodiment of the present specification includes a plurality of sub-pixels, a power supply wiring for applying a voltage to the plurality of sub-pixels, and a plurality of power supply connecting wirings for electrically connecting the plurality of sub-pixels to the power supply wiring.

[0023] In this case, each subpixel includes an organic light-emitting layer, a cathode electrode layer, and a passivation layer that are sequentially stacked, but the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent subpixels are isolated from each other, and each subpixel includes a structure that provides an undercut portion, but the power supply connection wiring is arranged to overlap the structure and is electrically connected to the cathode electrode layer in the undercut portion.

[0024] In addition, a display device according to an embodiment of the present specification includes a substrate on which a plurality of subpixels are defined, a plurality of power supply connecting lines arranged on the substrate, a plurality of structures arranged on the power supply connecting lines to be included in each subpixel and providing undercut portions that expose portions of the power supply connecting lines, a bank layer arranged on the power supply connecting lines and including first openings that are opened to expose the undercut portions, and an organic light-emitting layer, a cathode electrode layer, and a passivation layer sequentially stacked to cover the bank layer and the structures.

[0025] In this case, the power supply connection wiring is electrically connected to the cathode electrode layer in the undercut portion, and the organic light emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are disconnected from each other.

[0026] In addition, a method for manufacturing a display device according to an embodiment of the present specification includes the steps of forming an overcoat layer by forming a plurality of source / drain electrodes, a plurality of power supply connecting lines, and a plurality of data lines on a substrate; forming a plurality of anode electrode layers electrically connected to the plurality of source / drain electrodes, respectively, and a plurality of second structure layers electrically connected to the plurality of power supply connecting lines, respectively, on the overcoat layer; patterning the overcoat layer to form a plurality of first structure layers each providing undercut portions below the plurality of second structure layers; forming a bank layer including a plurality of first openings exposing outer peripheries of the plurality of undercut portions and a plurality of second openings exposing portions of the plurality of anode electrode layers; and forming a bank layer including a plurality of first openings exposing outer peripheries of the plurality of undercut portions and a plurality of second openings exposing portions of the plurality of anode electrode layers, respectively, so as to expose the first openings and the second openings corresponding to first sub-pixels. forming a first protective layer and a first photoresist film, sequentially forming a first organic light-emitting layer that realizes a first color, a first cathode electrode layer, and a first passivation layer, and then removing the first protective layer and the first photoresist film; forming a second protective layer and a second photoresist film to expose a first opening and a second opening corresponding to a second sub-pixel, sequentially forming a second organic light-emitting layer that realizes a second color, a second cathode electrode layer, and a second passivation layer, and then removing the second protective layer and the second photoresist film; forming a third protective layer and a third photoresist film to expose the first opening and the second opening corresponding to a third sub-pixel, sequentially forming a third organic light-emitting layer that realizes a third color, a third cathode electrode layer, and a third passivation layer, and then removing the third protective layer and the third photoresist film. [Effects of the Invention]

[0027] According to the embodiments of the present specification, each sub-pixel is electrically connected to a power supply connecting line through a cathode electrode layer in each undercut portion provided by a structure, and therefore, power can be stably supplied to each of the plurality of sub-pixels through the power supply connecting line electrically connected to the power supply line.

[0028] In addition, according to the embodiments of the present specification, since the organic light emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are separated from each other, an out-coupling phenomenon occurs in which light from the organic light emitting layer escapes to the outside at the separated ends, thereby improving light extraction efficiency through the organic light emitting layer and realizing a low-power display device.

[0029] In addition, according to the embodiments of the present specification, since the organic light emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are isolated from each other, it is possible to reduce the occurrence of lateral leakage current in the organic light emitting layers, which may occur when the organic light emitting layers are continuously connected to each other.

[0030] In addition, according to the embodiment of the present specification, by arranging the cathode electrode layer and the data wiring so that they do not overlap each other in the vertical direction, it is possible to reduce the occurrence of parasitic capacitance between the cathode electrode layer and the data wiring, thereby reducing the occurrence of a delay in the electrical transmission speed (RC delay).

[0031] Furthermore, according to the embodiments of the present specification, after forming an organic light-emitting layer, a cathode electrode layer, and a passivation layer that realizes a first color, an organic light-emitting layer that realizes a second color and an organic light-emitting layer that realizes a third color are formed in the same process. Therefore, the passivation layer can act as a protective film that reduces deterioration of the organic light-emitting layer that may occur in the successive processes, thereby reducing damage to the organic light-emitting layer.

[0032] The above-mentioned effects and specific effects of the present invention will be described in conjunction with the following description of the preferred embodiment of the invention. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a schematic plan view of a display device according to an embodiment of the present disclosure; [Figure 2]FIG. 2 is a circuit diagram for one subpixel of a display device according to an embodiment of the present disclosure. [Figure 3a] 2 is an enlarged plan view of a plurality of subpixels of the display device according to the embodiment of the present disclosure shown in FIG. 1. [Figure 3b] 2 is an enlarged plan view of a plurality of sub-pixels of a display device according to another embodiment of the present disclosure shown in FIG. 1. FIG. [Figure 4] 3b is a cross-sectional view of a plurality of sub-pixels of a display device according to an embodiment herein shown in FIG. 3a. [Figure 5a] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5b] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5c] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5d] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5e] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5f] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5g] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5h] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5i] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5j] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5k] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5l] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5m] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 5n] 1A to 1C are process plan views of a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6a] 5b are cross-sectional views of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure shown in FIG. 5a. [Figure 6b] 5b is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6c] 5c is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6d] 5d shows cross-sectional views of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6e] 5e is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6f] 5f is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6g] 5g is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6h] 5h is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6i] 5i-5i are cross-sectional views of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6j] 5j is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. [Figure 6k] 5k is a cross-sectional view of a process for a plurality of subpixels of a display device according to an embodiment of the present disclosure. [Figure 6l] 5l is a cross-sectional view of a process for a plurality of subpixels of a display device according to an embodiment of the present disclosure. [Figure 6m]5A-5M are cross-sectional views of a process for a plurality of subpixels of a display device according to an embodiment of the present disclosure. [Figure 6n] 5n is a cross-sectional view of a process for a plurality of sub-pixels of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0034] The advantages and features of the present specification, as well as methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various different forms. However, the present embodiments are provided to complete the disclosure of the specification and to fully convey the scope of the invention to those skilled in the art to which the specification pertains, and the specification is defined only by the scope of the claims.

[0035] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative only, and the specification is not limited to the illustrated matters. The same reference symbols throughout the specification refer to the same components. Furthermore, in explaining this specification, if a specific description of related publicly known technology is deemed to obscure the gist of this specification, the detailed description thereof will be omitted. When using words such as "include," "have," and "be," other parts can be added unless "only" is used. When a component is indicated in the singular, it also includes the plural unless otherwise explicitly stated.

[0036] When interpreting elements, they are interpreted as including a margin of error unless otherwise expressly stated.

[0037] When describing the positional relationship between two parts, for example, when using "above," "at the top," "below," "to the side," etc., one or more other parts may be located between the two parts, unless "immediately" or "directly" is used.

[0038] When describing a temporal relationship, for example, when describing a temporal sequence using "after," "following," "next to," or "before," non-sequential sequences can also be included, as long as "immediately" or "directly" is not used.

[0039] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0040] The features of the multiple embodiments of this specification can be partially or wholly combined or combined with each other, and various technical interlocking and driving mechanisms are possible, and each embodiment can be implemented independently of each other or can be implemented together in a linked relationship.

[0041] Display devices according to embodiments of the present specification will be described in detail below with reference to FIGS.

[0042] FIG. 1 is a schematic plan view of a display device according to an embodiment of the present specification.

[0043] The display device 1 described below will be described as an organic light emitting diode display device as an example, but is not limited to this.

[0044] The display device 1 can include a display area (AA) and a non-display area (NA) surrounding the periphery of the display area (AA).

[0045] In the display area (AA), a plurality of data lines (DL) extending in a first direction and a plurality of gate lines (GL) extending in a second direction intersecting the first direction may be arranged.

[0046] The data lines (DL) and gate lines (GL) cross each other, and the divided areas can be defined as sub-pixels SP1, SP2, and SP3, respectively.

[0047] Each of the sub-pixels SP1, SP2, and SP3 may be implemented to emit light of the same color, such as white (W) light, or may be implemented to emit light of different colors, such as red (R), green (G), or blue (B).

[0048] For example, the sub-pixels SP1, SP2, and SP3 may be implemented as a combination of red (R), green (G), and blue (B) lights, or a combination of red (R), green (G), blue (B), and white (W) lights.

[0049] A single pixel (P) can be configured by combining a plurality of sub-pixels SP1, SP2, and SP3 as described above.

[0050] Hereinafter, an example will be described in which one pixel (P) includes a first sub-pixel (SP1) that realizes a first color, a second sub-pixel (SP2) that realizes the first color, and a third sub-pixel (SP3) that realizes a third color.

[0051] In this case, the first hue may be red (R), the second hue may be green (G), and the third hue may be blue (B), but is not limited to this.

[0052] The plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix of rows and columns.

[0053] In this specification, the first direction is the column direction and can be defined as the Y-axis direction, and the second direction is the row direction and can be defined as the X-axis direction.

[0054] In the non-display area (NA), a plurality of wirings and pads may be arranged to supply various signals and power sources to the inside of the pixels.

[0055] A data driving circuit (D-IC; 10) may be disposed on one side of the non-display area (NA).

[0056] The data drive circuit 10 can apply a data signal to the data line (DL) and a drive voltage such as a high potential voltage (VDD) or a low potential voltage (VSS) to the pixel (P).

[0057] The power supply wiring 20 may be arranged along the edge of the display area (AA) except for one side of the non-display area (NA) where the data driving circuit 10 is arranged.

[0058] For example, in the non-display areas (NA) located on both sides of the display area (AA), a gate driver 30 that applies a gate signal to the gate line (GL) may be arranged, and a power supply line 20 that can apply a voltage to the anode electrode or cathode electrode in the pixel (P) may be arranged along the outer periphery of the gate driver 30.

[0059] The power supply wiring 20 may be a low potential voltage wiring capable of applying a low potential voltage (VSS) to the cathode electrode of the pixel (P), but is not limited to this, and a high potential voltage wiring capable of applying a high potential voltage (VDD) to the thin film transistor of the pixel (P) may also be arranged.

[0060] In the display area (AA), a plurality of power supply connecting lines 112 may be arranged to electrically connect the power supply line 20 to the plurality of sub-pixels SP1, SP2, and SP3 so as to apply a low potential voltage to the plurality of sub-pixels SP1, SP2, and SP3.

[0061] For example, the plurality of power supply connecting lines 112 may extend in the same first direction as the plurality of data lines (DL).

[0062] The plurality of power supply connection lines 112 and the plurality of data lines (DL) may be alternately arranged one by one in the second direction.

[0063] One power supply connection line 112 may extend to pass through a plurality of sub-pixels arranged in the column direction and be electrically connected to the power supply line 20 arranged in the lower part of the display area (AA).

[0064] Therefore, a plurality of sub-pixels arranged in the same column direction may be electrically connected to the same power supply connecting line 112 and may receive a low potential voltage from the power supply line 20 via the power supply connecting line 112.

[0065] FIG. 2 is a circuit diagram of one subpixel of a display device according to an embodiment of the present disclosure.

[0066] As described above, each of the sub-pixels SP1, SP2, and SP3 defined by the gate lines (GL) and data lines (DL) intersecting each other may include a switching thin film transistor (Ts), a driving thin film transistor (Td), a storage capacitor (Cst), and a light emitting diode (De).

[0067] The gate electrode of the switching thin film transistor (Ts) may be connected to the gate line (GL), and the source electrode may be connected to the data line (DL).

[0068] The gate electrode of the driving thin film transistor (Td) may be connected to the drain electrode of the switching thin film transistor (Ts), and the source electrode may be connected to a high potential voltage (VDD).

[0069] The anode electrode of the light emitting diode (De) may be connected to the drain electrode of the driving thin film transistor (Td), and the cathode electrode may be connected to a low potential voltage (VSS).

[0070] One side and the other side of the storage capacitor Cst may be connected to the gate electrode and the drain electrode of the driving thin film transistor Td, respectively.

[0071] The display device 1 including the sub-pixels SP1, SP2, and SP3 having such a circuit diagram can display an image as follows.

[0072] The switching thin film transistor (Ts) is turned on according to the gate signal applied through the gate line (GL), and the data signal applied through the data line (DL) can be applied to the gate electrode of the driving thin film transistor (Td) and one electrode of the storage capacitor (Cst) through the switching thin film transistor (Ts).

[0073] The driving thin film transistor (Td) is turned on in response to a data signal to control a current flowing through the light emitting diode (De), thereby displaying an image.

[0074] The light emitting diode (De) can emit light by a current of a high potential voltage (VDD) transmitted through the driving thin film transistor (Td).

[0075] Figures 3a and 3b are enlarged plan views of multiple subpixels of a display device according to an embodiment of the present specification shown in Figure 1, respectively, and Figure 4 is a cross-sectional view of multiple subpixels of a display device according to an embodiment of the present specification shown in Figure 3a.

[0076] Specifically, FIG. 3a shows an enlarged view of a plurality of sub-pixels corresponding to the region indicated by reference numeral 3 in FIG.

[0077] Although the following description will be given based on one sub-pixel, the same can be applied to other sub-pixels unless otherwise specified.

[0078] 3a and 4, a thin film transistor including an active layer 101 may be disposed on a substrate 100. In this case, the thin film transistor may be a driving thin film transistor (Td) or a switching thin film transistor (Ts).

[0079] A buffer layer may further be disposed between the substrate 100 and the thin film transistor.

[0080] The thin film transistor may include an active layer 101 , a gate electrode, and a pair of source-drain electrodes 111 .

[0081] A first insulating layer 102, which is an interlayer insulating layer, is disposed on the active layer 101 and the gate electrode, and the source / drain electrode 111 can be electrically connected to the active layer 101 through a contact hole formed in the first insulating layer 102.

[0082] A second insulating layer 103 may be further disposed on the first insulating layer 102 and the source / drain electrode 111, and the source / drain electrode 111 may be disposed on the second insulating layer 103 via a contact hole formed in the second insulating layer 103.

[0083] On the second insulating layer 103, a power supply connection line 112 and a data line (DL) may be arranged in the same layer as the source / drain electrodes 111.

[0084] The power supply connection lines 112 and the data lines (DL) may extend in parallel to each other in the first direction and be arranged alternately (see FIG. 1).

[0085] As a result, the plurality of data lines (DL) and the plurality of power supply connecting lines 112 may be arranged so as not to overlap each other in the vertical direction, and the occurrence of parasitic capacitors formed between the data lines (DL) and the power supply connecting lines 112 can be reduced.

[0086] An overcoat layer 120 may be formed on the source / drain electrodes 111 , and an anode electrode layer 130 may be formed on the overcoat layer 120 .

[0087] The overcoat layer 120 can be formed from an organic material.

[0088] The anode electrode layer 130 may be electrically connected to the source / drain electrode 111 through the contact hole 120 h of the overcoat layer 120 .

[0089] A first structure layer 121 made of the same material as the overcoat layer 120 may be disposed on the power supply connection wiring 112 .

[0090] The first structure layer 121 can be formed by patterning the overcoat layer 120 into an island shape.

[0091] The first structure layer 121 may be disposed so as to overlap the power supply connection wiring 112 in the vertical direction.

[0092] The first structure layer 121 may be formed in a positive tapered shape, the width of which decreases from the bottom to the top.

[0093] The left-right width (x-axis direction in FIG. 4) of the lower surface of the first structure layer 121 may be formed to be smaller than the left-right width (x-axis direction in FIG. 4) of the power supply connecting wire 112.

[0094] Therefore, a portion of the upper surface and side surfaces of the power supply connecting wire 112 that do not overlap with the first structure layer 121 may be exposed to the outside without being covered by the first structure layer 121 .

[0095] In this way, a partial region of the upper surface of the power supply connecting wire 112 exposed to the outside may be an undercut portion (UC).

[0096] For example, the undercut portion (UC) may be formed along the periphery of the lower surface of the first structure layer 121, and the power connection wiring 112 corresponding to the undercut portion (UC) may be exposed to the outside without being covered by the first structure layer 121.

[0097] A second structure layer 131 made of the same material as the anode electrode layer 130 may be disposed on the first structure layer 121 .

[0098] The second structure layer 131 can be formed by patterning the anode electrode layer 130 into an island shape.

[0099] The second structure layer 131 may be disposed so as to overlap the first structure layer 121 and the power supply connecting wiring 112 in the vertical direction.

[0100] The second structure layer 131 may be electrically connected to the power supply connection wiring 112 through the contact hole 121 h of the first structure layer 121 .

[0101] The second structure layer 131 may be formed such that its left-right width (x-axis direction in FIG. 4) is greater than the left-right width (x-axis direction in FIG. 4) of the upper and lower surfaces of the first structure layer 121 disposed below.

[0102] Accordingly, the second structure layer 131 may include protrusions 1311 that protrude outward from the upper and lower surfaces of the first structure layer 121 .

[0103] Due to the protrusion 1311 of the second structure layer 131 formed in this manner, an undercut portion (UC) may be formed on the power supply connection wire 112 along the outer periphery of the lower surface of the first structure layer 121.

[0104] At least a part of the undercut portion (UC) may be located inside the second structure layer 131 in a plan view.

[0105] Therefore, the outermost boundary of the undercut portion (UC) may be located outside the second structure layer 131, but is not limited to this, and the outermost boundary of the undercut portion (UC) may be located inside the second structure layer 131 or may be coincident with each other.

[0106] A bank layer 140 may be formed on the anode electrode layer 130, the second structure layer 131, and the data line (DL).

[0107] The bank layer 140 can function as a pixel defining layer (PDL) that separates the sub-pixels SP1, SP2, and SP3.

[0108] Therefore, a bank layer 140, which is a pixel defining layer, is disposed between each of the sub-pixels SP1, SP2, and SP3 to define the boundaries between the sub-pixels SP1, SP2, and SP3 having different hues and prevent color mixing.

[0109] The bank layer 140 disposed on the power supply connecting wiring 112 may include a first opening 1401 opened to expose the undercut portion (UC).

[0110] In this specification, the first openings 1401 of the bank layer 140 exposing the undercut portions (UC) means that the bank layer 140 has an open pattern without covering the undercut portions (UC).

[0111] Specifically, the outermost boundary of the first opening 1401 may be formed outside the outermost boundary of the undercut portion (UC), and the first opening 1401 may be formed to include the undercut portion (UC).

[0112] Therefore, through the first opening 1401, not only the undercut portion (UC), which is a partial region above the power supply connecting wire 112, but also a partial region of the second insulating layer 103 can be exposed to the outside.

[0113] A third structure layer 141 made of the same material as the bank layer 140 may be disposed on the second structure layer 131 .

[0114] The third structure layer 141 can be formed by patterning the bank layer 140 into an island shape.

[0115] The third structure layer 141 may be disposed so as to overlap the second structure layer 131, the first structure layer 121, and the power supply connecting wiring 112 in the vertical direction.

[0116] The third structure layer 141 may be formed in a positive tapered shape, the width of which decreases from the bottom to the top.

[0117] The left-right width (x-axis direction in FIG. 4) of the third structure layer 141 may be formed smaller than the left-right width (x-axis direction in FIG. 4) of the upper surface of the second structure layer 131 disposed below.

[0118] Therefore, the upper surface of the protruding portion 1311 of the second structure layer 131 protruding outward from the first structure layer 121 can be exposed to the outside without being covered by the third structure layer 141.

[0119] In this manner, the first structure layer 121, the second structure layer 131, and the third structure layer 141, which are stacked in order, can form a structure (ST).

[0120] Accordingly, the structure (ST) may be disposed overlapping the power supply connection wiring 112 to provide an undercut portion (UC) that exposes a partial region of the upper portion of the power supply connection wiring 112 .

[0121] The bank layer 140 may also include a second opening 1402 that is opened to expose a partial region of the anode electrode layer 130 .

[0122] The second opening 1402 formed in the first sub-pixel (SP1) can define the first light-emitting portion (OLE1), the second opening 1402 formed in the second sub-pixel (SP2) can define the second light-emitting portion (OLE2), and the second opening 1402 formed in the third sub-pixel (SP3) can define the third light-emitting portion (OLE3).

[0123] An organic light-emitting layer, a cathode electrode layer, and a passivation layer may be sequentially stacked on the bank layer 140 .

[0124] Specifically, the first sub-pixel (SP1) may be arranged with a first organic light-emitting layer 151, a first cathode electrode layer 161, and a first passivation layer 171 that realize a first color, the second sub-pixel (SP2) may be arranged with a second organic light-emitting layer 152, a second cathode electrode layer 162, and a second passivation layer 172 that realize a second color, and the third sub-pixel (SP3) may be arranged with a third organic light-emitting layer 153, a third cathode electrode layer 163, and a third passivation layer 173 that realize a third color.

[0125] In this case, the organic light emitting layer, the cathode electrode layer, and the passivation layer of the adjacent sub-pixels may be arranged to be disconnected from each other.

[0126] As used herein, "disconnected" means that they are physically separated from each other and are not electrically connected to each other.

[0127] However, even if they are isolated from each other, they can be electrically connected in an indirect manner through other intermediaries.

[0128] For example, the first organic light-emitting layer 151 and the second organic light-emitting layer 152, which are adjacent to each other, may be disconnected from each other, the second organic light-emitting layer 152 and the third organic light-emitting layer 153, which are adjacent to each other, may be disconnected from each other, and the third organic light-emitting layer 153 and the first organic light-emitting layer 151, which are adjacent to each other, may be disconnected from each other.

[0129] In addition, the first cathode electrode layer 161 and the second cathode electrode layer 162 that are adjacent to each other may be disconnected from each other, the second cathode electrode layer 162 and the third cathode electrode layer 163 that are adjacent to each other may be disconnected from each other, and the third cathode electrode layer 163 and the first cathode electrode layer 161 that are adjacent to each other may be disconnected from each other.

[0130] In addition, the first passivation layer 171 and the second passivation layer 172 that are adjacent to each other may be disconnected from each other, the second passivation layer 172 and the third passivation layer 173 that are adjacent to each other may be disconnected from each other, and the third passivation layer 173 and the first passivation layer 171 that are adjacent to each other may be disconnected from each other.

[0131] The outermost boundary portion 1511 of the first organic light emitting layer 151, the outermost boundary portion 1611 of the first cathode electrode layer 161, and the outermost boundary portion 1711 of the first passivation layer 171 may be disposed within a first sub-pixel (SP1) formed between adjacent data lines (DL).

[0132] Therefore, the first organic light emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 do not need to overlap the data line (DL) in the vertical direction.

[0133] In addition, the outermost boundary portion 1521 of the second organic light-emitting layer 152, the outermost boundary portion 1621 of the second cathode electrode layer 162, and the outermost boundary portion 1721 of the second passivation layer 172 may be disposed within a second sub-pixel (SP2) formed between adjacent data lines (DL).

[0134] Therefore, the second organic light emitting layer 152, the second cathode electrode layer 162, and the second passivation layer 172 do not need to overlap the data line (DL) in the vertical direction.

[0135] In addition, the outermost boundary 1531 of the third organic light-emitting layer 153, the outermost boundary 1631 of the third cathode electrode layer 163, and the outermost boundary 1731 of the third passivation layer 173 may be disposed within a third sub-pixel (SP3) formed between adjacent data lines (DL).

[0136] Therefore, the third organic light emitting layer 153, the third cathode electrode layer 163, and the third passivation layer 173 do not need to overlap the data line (DL) in the vertical direction.

[0137] If adjacent cathode electrode layers are not separated from each other but are formed from tubular electrodes and arranged continuously to cover the entire display area, the cathode electrode layers may be arranged to overlap with the data wiring, which may result in an unintended parasitic capacitor between the cathode electrode layer and the data wiring.

[0138] In this way, when a parasitic capacitor occurs, the RC delay may increase.

[0139] RC delay is the product of resistance (R) and capacitance (C), and indicates the delay in electrical transmission speed.

[0140] Therefore, when the RC delay increases, the delay in electrical transmission speed increases, which makes it difficult to drive the display device at high speed.

[0141] However, according to the embodiments of the present specification, by arranging the cathode electrode layer and the data wiring so that they do not overlap each other in the vertical direction, it is possible to reduce the occurrence of parasitic capacitors that may be formed between the cathode electrode layer and the data wiring.

[0142] As a result, according to the embodiment of the present specification, the occurrence of RC delay can be reduced, thereby greatly reducing the difficulty of driving a display device at high speed.

[0143] A first organic light-emitting layer 151, a first cathode electrode layer 161, and a first passivation layer 171 are sequentially stacked in a region of the bank layer 140 corresponding to the second opening 1402 of the first sub-pixel (SP1), and the region where the anode electrode layer 130, the first organic light-emitting layer 151, and the first cathode electrode layer 161 overlap may be a first light-emitting section (OLE1) that emits light.

[0144] In addition, a second organic light-emitting layer 152, a second cathode electrode layer 162, and a second passivation layer 172 are sequentially stacked in a region of the bank layer 140 corresponding to the second opening 1402 of the second sub-pixel (SP2), and the region where the anode electrode layer 130, the second organic light-emitting layer 152, and the second cathode electrode layer 162 overlap may be a second light-emitting section (OLE2) that emits light.

[0145] In addition, a third organic light-emitting layer 153, a third cathode electrode layer 163, and a third passivation layer 173 are sequentially stacked in a region of the bank layer 140 corresponding to the second opening 1402 of the third sub-pixel (SP3), and the region where the anode electrode layer 130, the third organic light-emitting layer 153, and the third cathode electrode layer 163 overlap may be a third light-emitting section (OLE3) that emits light.

[0146] The first organic light-emitting layer 151, the second organic light-emitting layer 152, and the third organic light-emitting layer 153 may include emission layers (EMLs) that emit red, green, and blue light, respectively, and the emission layers may be made of a phosphorescent material or a fluorescent material, and the specific material is not particularly limited.

[0147] For example, a hole injection layer (HIL) and / or a hole transporting layer (HTL) may be further disposed between the anode electrode layer 130 and the organic light emitting layer, and an electron transporting layer (ETL) and / or an electron injection layer (HIL) may be disposed between the light emitting layer (EML) and the cathode electrode layer.

[0148] If adjacent organic light-emitting layers are not separated from each other and are arranged continuously to cover the entire display area, a problem may occur in which light generated in the light-emitting portion but not escaping to the outside continues to be reflected at the interface, propagates to the side, and then disappears.

[0149] However, according to the embodiments of the present specification, the organic light-emitting layer, the cathode electrode layer, and the passivation layer of adjacent sub-pixels are separated from each other, so that the light from the organic light-emitting layer can change its path at the separated end and escape to the outside.

[0150] Therefore, according to the embodiments of the present specification, the light extraction efficiency in the organic light emitting layer can be further improved by the occurrence of the out-coupling phenomenon.

[0151] In addition, according to the embodiments of the present specification, since the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are isolated from each other, it is possible to reduce the occurrence of lateral leakage current in the organic light-emitting layers, which may occur when the organic light-emitting layers are continuously connected to each other.

[0152] To drive each of the sub-pixels SP1, SP2, and SP3, a low potential voltage (VSS) must be applied to the cathode electrode layer.

[0153] However, according to the embodiment of the present specification, since the cathode electrode layers included in the adjacent sub-pixels SP1, SP2, and SP3 are disconnected from each other, a low potential voltage (VSS) can be applied to the cathode electrode layers included in each of the sub-pixels SP1, SP2, and SP3 via the power supply connecting wiring 112.

[0154] In the case of the first sub-pixel (SP1), the first cathode electrode layer 161 in the undercut portion (UC) of the power supply connecting line 112 arranged under the structure (ST) comes into contact with the power supply connecting line 112, thereby allowing electrical connection.

[0155] Specifically, the first organic light emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 may be in contact with the undercut portion (UC).

[0156] For example, the first organic light emitting layer 151 may be formed in the first opening 1401 so as to contact the side of the power supply connecting line 112 .

[0157] In this case, the first organic light emitting layer 151 may also be in contact with a partial area of the undercut portion (UC).

[0158] The first cathode electrode layer 161 formed on the first organic light emitting layer 151 may be formed in the first opening 1401 so as to be in contact with a partial region of the undercut portion (UC).

[0159] The first cathode electrode layer 161 may be made of a material having relatively better step coverage than the first organic light emitting layer 151, and thus the end of the first cathode electrode layer 161 adjacent to the undercut portion (UC) may be located closer to the structure (ST), i.e., inside the undercut portion (UC), than the end of the first organic light emitting layer 151.

[0160] Therefore, the first cathode electrode layer 161 is formed to cover the first organic light-emitting layer 151 as a whole, so that the outermost boundary portion 1611 of the first cathode electrode layer 161 can be formed outside the outermost boundary portion 1511 of the first organic light-emitting layer 151.

[0161] The first cathode electrode layer 161 thus formed can be electrically connected to the power supply connecting wire 112 by contacting a portion of the undercut portion (UC).

[0162] As a result, each of the first cathode electrode layers 161, which are disconnected from each other, can be electrically connected to the power supply line 20 by one power supply connecting line 112 passing through a plurality of first sub-pixels (SP1), thereby applying a low potential voltage.

[0163] The first passivation layer 171 formed on the first cathode electrode layer 161 can be formed in the first opening 1401 so as to be in contact with a partial region of the undercut portion (UC).

[0164] However, without being limited to this, the first passivation layer 171 may also contact the side of the first structure layer 121, or may contact the side of the first structure layer 121 of the structure (ST) without directly contacting the undercut portion (UC).

[0165] The first passivation layer 171 may use a material having relatively better step coverage than the first cathode electrode layer 161, so that the end of the first passivation layer 171 adjacent to the undercut portion UC may be located closer to the structure ST than the end of the first cathode electrode layer 161. In this case, having good step coverage means having a relatively uniform thickness across the entire step.

[0166] Therefore, the first passivation layer 171 is formed to cover the first cathode electrode layer 161 as a whole, so that the outermost boundary portion 1711 of the first passivation layer 171 can be formed outside the outermost boundary portion 1611 of the first cathode electrode layer 161.

[0167] As described above, according to the embodiments of the present specification, the cathode electrode layer in each undercut portion of each subpixel is electrically connected to the power supply connecting line through a structure that provides an undercut portion, and therefore, power can be stably supplied to each of the plurality of subpixels through the power supply connecting line that is electrically connected to the power supply line.

[0168] Furthermore, according to the embodiments of the present specification, undercut portions are formed along at least both sides or the periphery of the structure, and the cathode electrode layer and the power supply connection wiring are in contact with each other in the undercut portions. Therefore, even if the structure of one side undercut portion is not fully realized due to external factors such as the occurrence of process errors, the structure of the other side undercut portion can be used.

[0169] Therefore, according to the embodiment of the present specification, power can be stably supplied to each of the plurality of sub-pixels through the power supply connecting wires electrically connected to the power supply wires.

[0170] A first organic light emitting layer 151, a first cathode electrode layer 161, and a first passivation layer 171 may be sequentially stacked on the structure (ST) of the first sub-pixel (SP1) (see FIG. 4).

[0171] Specifically, the first organic light emitting layer 151 , the first cathode electrode layer 161 , and the first passivation layer 171 may be formed to cover the third structure layer 141 .

[0172] The first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 may be formed to cover the protrusion 1311 of the second structure layer 131 and may extend to cover the side surfaces of the second structure layer 131.

[0173] In this case, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 can be formed in an island shape by being interrupted by the first structure layer 121 disposed below the second structure layer 131.

[0174] The first cathode electrode layer 161 disposed on the third structure layer 141 may be electrically connected to the second structure layer 131 formed of the same material as the anode electrode layer 130 .

[0175] Since the second structure layer 131 is electrically connected to the lower power supply connecting wiring 112 through the contact hole 121h of the first structure layer 121, the first cathode electrode layer 161, the second structure layer 131, and the power supply connecting wiring 112 arranged on the third structure layer 141 can be electrically connected.

[0176] Since the first cathode electrode layer 161 and the second structure layer 131 are formed of a conductive material such as metal, the first cathode electrode layer 161, the second structure layer 131, and the power supply connecting wire 112 are electrically connected, which has the advantageous effect of reducing the overall resistance of the power supply connecting wire 112.

[0177] The connection structure in the undercut portion (UC) of the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 of the first sub-pixel (SP1) described above can be similarly applied to the second sub-pixel (SP2) and the third sub-pixel (SP3), and therefore, the overlapping content will be omitted.

[0178] FIG. 3b is an enlarged plan view of a plurality of sub-pixels of the display device according to another embodiment of the present disclosure shown in FIG.

[0179] Referring to FIG. 3b, the structure (ST) of the first sub-pixel (SP1) may be formed continuously along the periphery of the first light-emitting portion (OLE1), the structure (ST) of the second sub-pixel (SP2) may be formed continuously along the periphery of the second light-emitting portion (OLE2), and the structure (ST) of the third sub-pixel (SP3) may be formed continuously along the periphery of the third light-emitting portion (OLE3).

[0180] In this way, by forming the structure (ST) continuously along the periphery of each light-emitting portion, the undercut portion (UC) provided by the structure (ST) may also be formed continuously along the periphery of the light-emitting portion.

[0181] In this way, the structure (ST) and the undercut portion (UC) provided by the structure (ST) are continuously formed along the periphery of the light emitting portion, so that even if the structure of one side structure or the structure of the undercut portion is not fully realized due to external factors such as the occurrence of process errors, the structure of the other side structure and the structure of the undercut portion can be used to stably connect the cathode electrode layer and the power supply connection wiring.

[0182] Although not shown in the drawings, the structures (ST) can be formed discontinuously along the periphery of each light-emitting portion, and the arrangement of the structures (ST) is not particularly limited.

[0183] 5a to 5n are process plan views relating to multiple subpixels of a display device according to an embodiment of the present specification, and FIGS. 6a to 6n are process cross-sectional views relating to multiple subpixels of a display device according to an embodiment of the present specification shown in FIGS. 5a to 5n.

[0184] For the sake of convenience, the process plan views of FIGS. 5a to 5n show only a part of the configuration shown in the process cross-sectional views of FIGS. 6a to 6n.

[0185] The pattern formation method for each layer described below may use a photolithography process including deposition, photoresist coating, exposure, development, etching, and photoresist stripping, which are techniques commonly used by those skilled in the art, and a detailed description thereof will be omitted.

[0186] For example, when depositing a metal material, a method such as sputtering can be used, and when depositing a semiconductor or insulating film, a method such as plasma enhanced vapor deposition (PECVD) can be used. In the case of etching, dry etching or wet etching can be selected depending on the material, and techniques commonly used by those skilled in the art can be applied.

[0187] Referring to FIGS. 5a and 6a, a thin film transistor including an active layer 101 may be formed on a substrate 100, and a first insulating layer 102 and a second insulating layer 103 may be sequentially formed thereon.

[0188] A plurality of source / drain electrodes 111 connected to the active layer 101 may be formed on the second insulating layer 103 .

[0189] In addition, a plurality of power supply connection lines 112 and a plurality of data lines (DL) may be formed on the second insulating layer 103.

[0190] The source / drain electrodes 111, the power supply connection lines 112, and the data lines (DL) may be formed in the same layer using the same patterning process and made of the same material.

[0191] The plurality of power supply connection lines 112 and the plurality of data lines (DL) are formed to extend in a first direction, but may be arranged alternately in a second direction.

[0192] An overcoat film 120a may be formed on the source / drain electrodes 111, the power supply connection lines 112, and the data lines (DL).

[0193] Referring to Figures 5b and 6b, contact holes 120h connected to each source / drain electrode 111 may be formed in the overcoat film 120a, and a plurality of anode electrode layers 130 electrically connected to the source / drain electrodes 111 through the contact holes 120h may be formed on the overcoat film 120a.

[0194] In addition, contact holes 121h connected to each power supply connecting wiring 112 may be formed in the overcoat film 120a, and a plurality of second structure layers 131 may be formed on the overcoat film 120a, electrically connected to the power supply connecting wiring 112 through the contact holes 121h.

[0195] The anode electrode layer 130 and the second structure layer 131 may be formed in the same layer and made of the same material using the same patterning process.

[0196] The second structure layer 131 may be formed with a pair of protruding portions 1311 that extend outward.

[0197] For example, one end of the protruding portion 1311 of the second structure layer 131 may be located inside one end of the power supply connecting wire 112, but is not limited to this.

[0198] The protrusion 1311 of the second structure layer 131 can be formed continuously along the periphery of the second structure layer 131 when viewed from above.

[0199] Referring to FIGS. 5c and 6c, a photoresist layer 132 having a predetermined pattern may be formed on the anode electrode layer 130 and the second structure layer 131.

[0200] For example, the photoresist layer 132 can be formed to have a predetermined pattern by depositing and developing a photoresist material.

[0201] The photoresist layer 132 formed on the anode electrode layer 130 can be formed to have an area larger than that of the anode electrode layer 130 so as to cover the anode electrode layer 130 .

[0202] The photoresist layer 132 formed on the second structure layer 131 can be formed with an area smaller than that of the second structure layer 131 so that a frame region corresponding to a portion of the protrusion 1311 of the second structure layer 131 is exposed.

[0203] Referring to FIGS. 5d and 6d, the overcoat film 120a may be etched using the photoresist layer 132 as a photomask to form the overcoat layer 120 and the first structure layer 121. As shown in FIG.

[0204] Therefore, the overcoat layer 120 and the first structure layer 121 can be formed in the same layer and made of the same material through the same patterning process.

[0205] For example, the overcoat film 120a can be patterned by dry etching.

[0206] An overcoat layer 120 may be formed under the anode electrode layer 130 .

[0207] Below each second structure layer 131, a first structure layer 121 having a patterned overcoat film 120a may be formed.

[0208] Specifically, the second structure layer 131 and the photoresist layer 132 formed on the second structure layer 131 can serve as a photomask used to pattern the overcoat film 120a and form the first structure layer 121.

[0209] In this case, the first structure layer 121 may be formed in a positive tapered shape, the width of which decreases from the bottom to the top.

[0210] The outermost boundary of the lower surface of the first structure layer 121 may be formed to be located more inward than the outermost boundary of the protrusion 1311 of the second structure layer 131 .

[0211] Therefore, the first structure layer 121 is formed to have a left-right width (x-axis direction in Figure 4) narrower than that of the power supply connecting wiring 112, and the frame region of the power supply connecting wiring 112 can be formed as an undercut portion (UC) that is not covered by the first structure layer 121 and is exposed to the outside.

[0212] Based on a plan view, the undercut portion (UC) may be formed so as not to be exposed by the protrusion 1311 of the second structure layer 131, but is not limited to this, and a portion of the upper area located at the frame of the undercut portion (UC) based on a plan view may be exposed to the outside.

[0213] Therefore, a plurality of first structure layers 121 may be formed below a plurality of second structure layers 131, each providing an undercut portion (UC).

[0214] In this manner, the overcoat layer 120 and the first structure layer 121 formed by patterning the overcoat film 120a may expose the side of the power supply connecting wire 112 and a portion of the upper part of the power supply connecting wire 112 corresponding to the undercut portion (UC) to the outside.

[0215] Moreover, the overcoat film 120a in the region between the power supply connection wiring 112 and the overcoat layer 120 may be removed, thereby exposing the second insulating layer 103 to the outside.

[0216] In addition, the overcoat film 120a on the data line (DL) may be removed to expose the data line (DL) to the outside, and the overcoat film 120a between the data line (DL) and the power supply connecting line 112 may also be removed to expose the second insulating layer 103 to the outside.

[0217] Referring to FIGS. 5e and 6e, the photoresist layer 132 disposed on the anode electrode layer 130 and the second structure layer 131 may be removed.

[0218] For example, the photoresist layer 132 can be removed by stripping it off using a stripping process.

[0219] Referring to Figures 5f and 6f, a bank layer 140 can be formed that includes a plurality of first openings 1401 that expose outer peripheral portions of a plurality of undercut portions (UCs) and a plurality of second openings 1402 that expose portions of a plurality of anode electrode layers 130.

[0220] Except for the areas corresponding to the first opening 1401 and the second opening 1402, the bank layer 140 can be formed so as to cover the entire surface of the display area (AA).

[0221] On the second structure layer 131, a third structure layer 141 may be formed, on which the bank layer 140 is formed by patterning.

[0222] The third structure layer 141 can be formed in the same patterning step as the first opening 1401 and the second opening 1402 .

[0223] The third structure layer 141 may be formed in a positive tapered shape, the width of which decreases from the bottom to the top.

[0224] The lower surface of the third structure layer 141 is formed to have a width narrower than the upper surface of the second structure layer 131, so that at least a portion of the protrusion 1311 of the second structure layer 131 can be exposed to the outside without being covered by the third structure layer 141.

[0225] In this way, the first structure layer 121, the second structure layer 131, and the third structure layer 141 are sequentially stacked to form the structure (ST).

[0226] In this case, the second structure layer 131 of the structure (ST) can provide a canopy structure, and the canopy structure of the second structure layer 131 can electrically connect the cathode electrode layer in the undercut portion (UC) located below to the power supply connecting wiring 112.

[0227] As described above, both the first structure layer 121 and the third structure layer 141 of the structure (ST) can be formed in a positive tapered shape.

[0228] If the third structure layer 141 has an inverse tapered shape, in which the width increases from the bottom to the top, the organic light-emitting layer can penetrate deep into the undercut portion (UC) of the structure (ST) when the organic light-emitting layer is deposited as described below.

[0229] This may make it difficult for a cathode electrode layer formed in a subsequent process to contact the undercut portion (UC), which may hinder stable connection between the cathode electrode layer and the power supply connection wiring.

[0230] Therefore, when the third structure layer 141 has an inverted tapered shape, the width of the top surface of the third structure layer 141 must be increased to increase the length of the eaves in order to ensure stable connection between the cathode electrode layer and the power supply connection wiring.

[0231] However, if the length of the canopy is increased in this way, the total area occupied by the structure (ST) increases, which may be disadvantageous in terms of the aperture ratio of the display device.

[0232] Therefore, as in the embodiment of the present specification, the first structure layer 121 and the third structure layer 141 are both formed in a positive tapered shape, and the second structure layer 131 located in between provides an eave structure, thereby providing a stable connection between the cathode electrode layer and the power supply connecting wiring without increasing the size of the structure (ST) by increasing the eave length.

[0233] The structure (ST) thus formed may be located inside the first opening 1401 of the bank layer 140.

[0234] That is, the region of the bank layer 140 exposed by the first opening 1401 can be formed so as to surround the periphery of the structure (ST).

[0235] Also, the first opening 1401 may be opened so that a portion of the power supply connecting line 112 and the second insulating layer 103 including the undercut portion (UC) are exposed.

[0236] In this way, the plurality of structures (ST) and the plurality of first openings 1401 formed in each sub-pixel may be positioned on the power supply connecting wiring 112 extending in one direction and may be arranged so as to overlap with the power supply connecting wiring 112 based on the plan view.

[0237] The second openings 1402 in the bank layer 140 define pixel defining layers (PDLs) to be formed in each sub-pixel.

[0238] Referring to FIGS. 5g and 6g, a first protective film 142a may be formed to cover the entire surface of the substrate 100. As shown in FIG.

[0239] The first protective film 142a may contain a fluorine-based material.

[0240] For example, the first protective film 142a may be made of a fluoropolymer material having a carbon-carbon backbone and containing a large amount of fluorine (F) in its functional groups.

[0241] The following Chemical Formula 1 shows the chemical structure of a fluoropolymer material containing a large amount of fluorine (F) in the functional group according to one example of the present specification. [ka]

[0242] As shown in Chemical Formula 1, the fluoropolymer used as the material for the protective film contains a large amount of fluorine (F) in the functional group.

[0243] Fluoropolymers containing a large amount of fluorine (F) in functional groups can have orthogonality to organic materials.

[0244] Orthogonality can be understood as the property that two things exist independently, without regard to each other.

[0245] As a result, the first protective film 142a can have both hydrophobic properties, which means that it has little affinity to water, and oleophobic properties, which means that it has little affinity to oil.

[0246] Due to this orthogonality, the first protective film 142a can block the path through which moisture permeates due to its property of separating or repelling moisture.

[0247] In addition, it is less affected by the developer containing organic solvents used in the process steps, which reduces damage to organic materials caused by organic solvents.

[0248] Referring to FIGS. 5h and 6h, a first photoresist film 143 may be formed on the first passivation film 142a.

[0249] For example, the first photoresist film 143 can be formed to have a predetermined pattern by depositing and developing a photoresist material.

[0250] The first photoresist film 143 can be formed in a pattern that covers the second sub-pixel (SP2) and the third sub-pixel (SP3), while opening the region corresponding to the first sub-pixel (SP1) and not opening the regions corresponding to the second sub-pixel (SP2) and the third sub-pixel (SP3).

[0251] Specifically, the first photoresist film 143 may be formed in a pattern that exposes the first passivation film 142a corresponding to the first opening 1401 and the second opening 1402 of the first sub-pixel (SP1).

[0252] Referring to Figures 5i and 6i, the first photoresist film 143 is used as a photomask to develop the first protective film 142a disposed underneath, thereby forming a first protective layer 142 having a predetermined pattern.

[0253] The first protective layer 142 formed in this manner can expose the first opening 1401 and the second opening 1402 of the bank layer 140 to the outside.

[0254] In this case, the first protective layer 142 is positioned further inside than the first photoresist film 143 disposed on top thereof, so that the first photoresist film 143 can provide an overhanging structure on the first protective layer 142.

[0255] 5j and 6j, a first organic light emitting layer 151 that realizes a first color, a first cathode electrode layer 161, and a first passivation layer 171 may be sequentially stacked.

[0256] For example, the first organic light emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171, which realize a first color, may be sequentially deposited on the entire surface of the substrate 100, respectively.

[0257] As a result, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 are sequentially stacked on the first opening 1401 and the second opening 1402 of the bank layer 140, and the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 in the structure (ST) having an eave structure can be discontinuously connected.

[0258] Furthermore, the first organic light emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 in the first protective layer 142 can be discontinuously connected via the first photoresist film 143 having another overhanging structure.

[0259] Based on the structure (ST), the first passivation layer 171, the first cathode electrode layer 161, and the first organic light emitting layer 151 may be formed in this order to extend close to the structure (ST).

[0260] Specifically, the first cathode electrode layer 161 may be made of a material having relatively better step coverage than the first organic light emitting layer 151, and thus the end of the first cathode electrode layer 161 adjacent to the undercut portion (UC) may be located closer to the structure (ST), i.e., inside the undercut portion (UC), than the end of the first organic light emitting layer 151.

[0261] Therefore, the first cathode electrode layer 161 is formed to cover the first organic light-emitting layer 151 as a whole, so that the outermost boundary portion 1611 of the first cathode electrode layer 161 can be formed outside the outermost boundary portion 1511 of the first organic light-emitting layer 151.

[0262] The first cathode electrode layer 161 thus formed can be electrically connected to the power supply connecting wire 112 by contacting a portion of the undercut portion (UC).

[0263] As a result, each of the first cathode electrode layers 161, which are disconnected from each other, can be electrically connected to the power supply line 20 by one power supply connecting line 112 passing through a plurality of first sub-pixels (SP1), thereby applying a low potential voltage.

[0264] The first passivation layer 171 formed on the first cathode electrode layer 161 may be formed in the first opening 1401 so as to contact a portion of the undercut portion (UC).

[0265] However, this is not limited to this, and the first passivation layer 171 may also be in contact with the side of the first structure layer 121, or may be in contact with the side of the first structure layer 121 of the structure (ST) without directly contacting the undercut portion (UC).

[0266] The first passivation layer 171 may be made of a material having relatively better step coverage than the first cathode electrode layer 161, and thus the end of the first passivation layer 171 adjacent to the undercut portion (UC) may be located further inside the undercut portion (UC), i.e., closer to the structure (ST), than the end of the first cathode electrode layer 161.

[0267] Therefore, by forming the first passivation layer 171 so as to cover the first cathode electrode layer 161 as a whole, the outermost boundary portion 1711 of the first passivation layer 171 can be formed outside the outermost boundary portion 1611 of the first cathode electrode layer 161.

[0268] Meanwhile, by sequentially stacking the first organic light emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 in the second opening 1402, the area where the first organic light emitting layer 151, the first cathode electrode layer 161, and the anode electrode layer 130 overlap can be embodied as the first light emitting unit (OLE1).

[0269] Referring to FIG. 5k and FIG. 6k, the first protective layer 142 and the first photoresist film 143 may be removed.

[0270] Specifically, by stripping the first protective layer 142, the first photoresist film 143, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 stacked on the first protective layer 142 can also be removed.

[0271] Referring to Figures 5l, 5m and 6l, 6m, the steps for the first sub-pixel (SP1) previously described in Figures 5g to 5k and Figures 6g to 6k can be similarly repeated for the second sub-pixel (SP2) and the third sub-pixel (SP3).

[0272] Specifically, a second protective layer and a second photoresist film are formed to expose a first opening 1401 and a second opening 1402 corresponding to the second sub-pixel (SP2), and a second organic light-emitting layer 152, a second cathode electrode layer 162, and a second passivation layer 172 that embody a second color are sequentially formed, and then the second protective layer and the second photoresist film are removed.

[0273] This forms the second light-emitting portion (OLE2) of the second sub-pixel (SP2), and electrically connects the power supply connection wiring 112 passing through the second sub-pixel (SP2) in the undercut portion (UC) of the structure (ST) of each second sub-pixel (SP2) to the second cathode electrode layer 162.

[0274] After the process for the second sub-pixel (SP2) is completed, a third protective layer and a third photoresist film are formed to expose the first opening 1401 and the second opening 1402 corresponding to the third sub-pixel (SP3), and a third organic light-emitting layer 153, a third cathode electrode layer 163, and a third passivation layer 173 that embody a third color are sequentially formed, and then the third protective layer and the third photoresist film are removed.

[0275] This forms the third light emitting portion (OLE3) of the third sub-pixel (SP3), and electrically connects the power supply connecting wiring 112 passing through the third sub-pixel (SP3) in the undercut portion (UC) of the structure (ST) of each third sub-pixel (SP3) to the third cathode electrode layer 163.

[0276] As described above, according to the embodiments of the present specification, after forming an organic light-emitting layer, a cathode electrode layer, and a passivation layer that realize a first color, an organic light-emitting layer that realizes a second color and an organic light-emitting layer that realizes a third color can be formed in the same process.

[0277] Therefore, the passivation layer disposed on the organic light-emitting layer can act as a protective film to reduce deterioration of the organic light-emitting layer that may occur during the subsequent process of forming the organic light-emitting layer corresponding to each sub-pixel, thereby reducing damage to the organic light-emitting layer.

[0278] Furthermore, according to the embodiments of the present specification, the cathode electrode layer and the power supply connection wiring 112 in the undercut portion (UC) of the structure (ST) are not in contact on the bank layer 140, but are in contact at the opening where the bank layer 140 is removed, thereby reducing the overall number of mask processes.

[0279] Referring to Figures 5n and 6n, a capping layer 180 and a fourth passivation layer 190 may be further formed to cover the first sub-pixel (SP1), the second sub-pixel (SP2) and the third sub-pixel (SP3).

[0280] The display device and the method for manufacturing the display device according to the embodiments of the present specification described above can be explained as follows.

[0281] A display device according to an embodiment of the present specification includes a plurality of sub-pixels, a power supply wiring that applies a voltage to the plurality of sub-pixels, and a plurality of power supply connecting wirings that electrically connect the plurality of sub-pixels to the power supply wiring.

[0282] In this case, each of the sub-pixels includes an organic light-emitting layer, a cathode electrode layer, and a passivation layer that are sequentially stacked, but the organic light-emitting layer, the cathode electrode layer, and the passivation layer of adjacent sub-pixels are isolated from each other. Each of the sub-pixels includes a structure that provides an undercut portion, but the power supply connecting wiring is arranged to overlap the structure and is electrically connected to the cathode electrode layer in the undercut portion.

[0283] The display device may further include a plurality of data lines disposed between adjacent ones of the sub-pixels, the data lines being disposed so as not to overlap with the cathode electrode layer.

[0284] The plurality of data lines and the plurality of power supply connecting lines may extend alternately in a first direction, and the plurality of data lines and the plurality of power supply connecting lines may be arranged so as not to overlap each other.

[0285] The plurality of sub-pixels may be arranged in a matrix along a first direction and a second direction intersecting the first direction, and each of the power supply connection lines may extend in the first direction so as to electrically connect the plurality of sub-pixels arranged in the first direction to the power supply line.

[0286] Each of the sub-pixels may include an outermost boundary of an organic light-emitting layer, an outermost boundary of a cathode electrode layer, and an outermost boundary of a passivation layer, wherein the outermost boundary of the organic light-emitting layer is located more inward than the outermost boundary of the passivation layer, and the outermost boundary of the cathode electrode layer is located between the outermost boundary of the organic light-emitting layer and the outermost boundary of the passivation layer.

[0287] The structures included in each of the sub-pixels may be located within an outermost boundary of the organic light emitting layer, an outermost boundary of the cathode electrode layer, and an outermost boundary of the passivation layer.

[0288] The power supply wiring is a low potential voltage (VSS) wiring, and the power supply connecting wiring can apply a low potential voltage to each of the cathode electrode layers included in each of the sub-pixels.

[0289] In addition, a display device according to an embodiment of the present specification includes: a substrate on which a plurality of subpixels are defined; a plurality of power supply connecting lines disposed on the substrate; a plurality of structures disposed on the power supply connecting lines to be included in each of the subpixels and providing undercut portions exposing portions of the power supply connecting lines; a bank layer disposed on the power supply connecting lines and including first openings that are opened to expose the undercut portions; and an organic light-emitting layer, a cathode electrode layer, and a passivation layer sequentially stacked to cover the bank layer and the structures.

[0290] In this case, the power supply connection wiring is electrically connected to the cathode electrode layer in the undercut portion, and the organic light emitting layer, the cathode electrode layer, and the passivation layer of the adjacent sub-pixels are disconnected from each other.

[0291] The display device may further include a plurality of thin film transistors, each including a source / drain electrode, disposed on the substrate so as to be included in each of the sub-pixels, and a plurality of data lines disposed on the substrate, wherein the power supply connecting lines, the source / drain electrodes, and the data lines may be disposed on the same layer and made of the same material.

[0292] The bank layer may be disposed on the data wiring so as to overlap with the data wiring, and the data wiring may be disposed so as not to overlap with the cathode electrode layer.

[0293] The display device may further include an overcoat layer disposed on the source / drain electrodes, and an anode electrode layer disposed between the overcoat layer and the bank layer and electrically connected to the source / drain electrodes, wherein the structure is formed by sequentially stacking a first structure layer, a second structure layer, and a third structure layer, the first structure layer being disposed in the same layer as the overcoat layer and made of the same material as the anode electrode layer, the second structure layer being disposed in the same layer as the anode electrode layer and made of the same material as the bank layer, and the third structure layer being disposed in the same layer as the bank layer and made of the same material as the bank layer.

[0294] The first structure layer and the third structure layer may have a positive tapered shape.

[0295] The second structure layer may be electrically connected to the power supply connecting line through a contact hole of the first structure layer.

[0296] The second structure layer may include a protruding portion that protrudes outward beyond the first structure layer and the third structure layer.

[0297] The cathode electrode layer disposed on the structure may be electrically connected to the protrusion.

[0298] The display device further includes a power supply wiring, which is a low potential voltage (VSS) wiring, and the power supply connecting wiring electrically connected to the power supply wiring can apply a low potential voltage to each of the cathode electrode layers included in each of the sub-pixels.

[0299] Further, a display device according to an embodiment of the present specification may include the steps of: forming a plurality of source / drain electrodes, a plurality of power supply connecting lines, and a plurality of data lines on a substrate to form an overcoat layer; forming a plurality of anode electrode layers electrically connected to the plurality of source / drain electrodes, respectively, and a plurality of second structure layers electrically connected to the plurality of power supply connecting lines, respectively, on the overcoat layer; patterning the overcoat layer to form a plurality of first structure layers each providing undercut portions under the plurality of second structure layers; forming a bank layer including a plurality of first openings exposing outer peripheries of the plurality of undercut portions and a plurality of second openings exposing portions of the plurality of anode electrode layers; forming a first protective layer and a first photoresist film to cover the substrate; and patterning the first protective layer and the first photoresist film to expose the first openings and the second openings corresponding to first sub-pixels; the first and second openings corresponding to the second sub-pixels are exposed; the second organic light-emitting layer, the second cathode electrode layer, and the second passivation layer are sequentially formed; and the second organic light-emitting layer, the second cathode electrode layer, and the second passivation layer are sequentially formed; and the second organic light-emitting layer, the second cathode electrode layer, and the second passivation layer are sequentially formed; the second organic light-emitting layer, the second cathode electrode layer, and the second passivation layer are sequentially formed; and the third organic light-emitting layer, the third organic light-emitting layer, and the third passivation layer are sequentially formed; and the third organic light-emitting layer, the third cathode electrode layer, and the third passivation layer are sequentially formed; and the third organic light-emitting layer, the third organic light-emitting layer, and the third passivation layer are sequentially formed;

[0300] The step of forming the bank layer may include a step of forming a third structure layer on the second structure layer, and the third structure layer may be formed by the same patterning process as the first opening and the second opening.

[0301] The first organic light emitting layer, the second organic light emitting layer, and the third organic light emitting layer may be formed to be disconnected from one another, the first cathode electrode layer, the second cathode electrode layer, and the third cathode electrode layer may be formed to be disconnected from one another, and the first passivation layer, the second passivation layer, and the third passivation layer may be formed to be disconnected from one another.

[0302] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications are possible within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are for illustrative purposes only, and do not limit the technical concept of the present specification. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting.

Claims

[Claim 1] a plurality of sub-pixels; a power supply wiring that applies a voltage to the plurality of sub-pixels; a plurality of power supply connecting lines electrically connecting the plurality of sub-pixels to the power supply lines, each of the sub-pixels includes an organic light-emitting layer, a cathode electrode layer, and a passivation layer, which are sequentially stacked, and the organic light-emitting layer, the cathode electrode layer, and the passivation layer of the plurality of sub-pixels adjacent to each other are separated from each other; Each of the sub-pixels includes a structure providing an undercut portion, and each of the power supply connecting lines is disposed to overlap the structure and is electrically connected to the cathode electrode layer in the undercut portion. Display device.

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