Semiconductor device

Abstract

To provide a semiconductor device capable of miniaturization or high integration.SOLUTION: A semiconductor device includes a first conductor, a first insulator on the first conductor, a second conductor on the first insulator, an oxide including a region in contact with side surfaces of the first conductor, the first insulator, and the second conductor, a second insulator on the oxide, and a third conductor on the second insulator. The second insulator includes a region facing the side surfaces of the first conductor, the first insulator, and the second conductor through the oxide. The third conductor includes a region facing the side surfaces of the first conductor, the first insulator, and the second conductor through the oxide and the second insulator.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, and electronic There are cases where the equipment and the like can be said to have a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter It is related to. [Background technology]

[0004] The technology of constructing a transistor using a semiconductor thin film is attracting attention. refers to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely used as semiconductor thin films that can be applied to transistors. Although semiconductors are widely known, oxide semiconductors are also attracting attention as other materials.

[0005] For example, zinc oxide or In-Ga-Zn oxide is used as an oxide semiconductor to form a channel. A technique for manufacturing a display device using a transistor having a region is disclosed (Patent Document See Patent Document 1 and Patent Document 2.

[0006] In recent years, integrated circuits for memory devices have been fabricated using transistors containing oxide semiconductors. A technology for this has been disclosed (see Patent Document 3). and the like have also been manufactured using transistors including oxide semiconductors. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 Summary of the Invention [Problem to be solved by the invention]

[0008] Meanwhile, as electronic devices become more powerful, smaller, and lighter, integrated circuits are becoming more highly integrated. The size of transistors is becoming smaller. The size of the oxide semiconductors has also been decreasing year by year, from 45nm to 32nm and 22nm. Transistors with a fine structure also have good electrical characteristics as designed. is required.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Another object of one embodiment of the present invention is to reduce variation in electrical characteristics within a substrate surface. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of the present invention is to provide a semiconductor device that consumes low power. Another object of the present invention is to provide a semiconductor device having reduced noise. Another object of the present invention is to provide a semiconductor device with high flexibility. Another object of the present invention is to provide a semiconductor device with high productivity. An object of the present invention is to provide a new semiconductor device.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device including a first conductor, a first insulator on the first conductor, and a first insulator. the second conductor on the first insulating layer, the first conductor, the first insulator, and the area in contact with the side of the second conductor; an oxide having a region, a second insulator on the oxide, and a third conductor on the second insulator; The second insulator has an oxide interposed between the first conductor, the first insulator, and the second conductor. the third conductor has a region facing a side surface of the body, and the third conductor is connected to the oxide and the second insulator via a semiconductor substrate having a first conductor, a first insulator, and a region facing a side of a second conductor; It is a body device.

[0012] In the above-mentioned embodiment, the first conductor, the first insulator, and the second conductor are a third The third insulator has an opening, and the oxide, the second insulator, and the third conductor are may be formed to fill the opening.

[0013] In the above embodiment, the oxide has a region in contact with the upper surface of the second conductor, and the second The insulator has a region overlapping the top surface of the second conductor through an oxide, and the third conductor is The second conductive material may have a region overlapping the top surface of the second conductive material through the oxide and the second insulator. .

[0014] In the above aspect, the film thickness of the first insulator is 1 nm or more and 100 nm or less. Good too.

[0015] In the above embodiment, the oxide may include a metal oxide. [Effects of the Invention]

[0016] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with small variations in electrical characteristics within a substrate surface can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high design freedom can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0017] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above will be self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0018] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 15] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C are a block diagram and a circuit diagram illustrating a configuration example of a semiconductor device of one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device. [Figure 18] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A and 1B are a circuit diagram illustrating a configuration example of a semiconductor device of one embodiment of the present invention and a timing chart illustrating an operation example of the semiconductor device. [Figure 20] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 21] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 22] FIG. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. [Figure 23] 1A and 1B are a flowchart and a schematic perspective view illustrating an example of a manufacturing process for an electronic component. [Figure 24] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various changes in mode and details may be made. The present invention should not be construed as being limited to the following description of the embodiments.

[0020] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely schematic representations of the shapes and values shown in the drawings, and are not limited to the shapes or values shown in the drawings. In the manufacturing process, layers and resist masks are unintentionally damaged by etching and other processes. Although the drawings may be omitted to make it easier to understand, In the drawings, the same parts or parts having similar functions are designated by the same reference numerals. In addition, when referring to the same function, The hatch patterns are the same and may not be given specific reference numbers.

[0021] In addition, the invention can be easily understood, especially in top views (also called "plan views") and perspective views. In order to simplify the description, some components may be omitted. The information may be omitted.

[0022] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. Therefore, for example, "first" may be changed to "second" " or "third" etc. as appropriate. The ordinal numbers used to identify an aspect of the present invention may not match. There is a match.

[0023] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in describing the same with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those described above, and can be rephrased appropriately depending on the situation.

[0024] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Almost parallel" means that the two lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0025] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain A transistor is placed between the drain electrode and the source terminal. A channel forming region is provided, and a current is applied between the source and the drain through the channel forming region. In this specification and the like, the channel forming region is defined as This refers to the area where current mainly flows.

[0026] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0027] The channel length of a transistor is, for example, the length of a semiconductor (or transistor) The area where the gate electrode overlaps with the semiconductor (the area where current flows in the semiconductor when it is in the on state), or is the area between the source (source region or source electrode) and the drain in the region where the channel is formed. This refers to the distance between the drain electrode and the transistor. In this case, the channel length does not necessarily have the same value in all regions. The channel length of a star may not be determined to a single value. The channel length is any one value, maximum value, minimum value or average value in the region where the channel is formed. The average value is used.

[0028] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content of

[0029] In this specification, the term "metal oxide" is used in a broad sense. Metal oxides are oxide insulators, oxide conductors (transparent oxide conductors, ), oxide semiconductors (also known as oxide semiconductors or simply OS). For example, metal oxide is used in the channel formation region of a transistor. In this case, the metal oxide is sometimes called an oxide semiconductor. When the metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, The oxides are called metal oxide semiconductors, It can be abbreviated as OS. It can also be written as OS FET or OS transistor. In this case, the transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor. can.

[0030] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0031] In this specification, CAAC (C-Axis Aligned Crystal l), and when written as CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration. Represents.

[0032] In addition, in this specification and the like, CAC-OS or CAC-metal oxide means A part of the material has a conductive function, a part of the material has an insulating function, and the whole material has a has a semiconductor function. When e is used in the channel formation region of a transistor, the conductive function becomes a carrier. The insulating function is to allow electrons (or holes) to flow, and the insulating function is to prevent the electrons (or holes) from The conductive function and insulating function work in a complementary manner. By doing so, the switching function (On / Off function) can be set to CAC-OS or CA It can be added to C-metal oxide. By separating the functions of each compound, we maximize the functionality of both compounds. It can be increased.

[0033] In this specification and the like, CAC-OS or CAC-metal oxide is a The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. The region has the insulating function described above. In addition, the material has a conductive region and an insulating region. The regions may be separated at the nanoparticle level. The conductive regions may be unevenly distributed in the material. They may be observed connected in a similar manner.

[0034] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and an insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be dispersed in the material:

[0035] In addition, CAC-OS and CAC-metal oxide have different band gaps. For example, CAC-OS or CAC-metal oxide e is a component with a wide gap due to the insulating region and a narrow gap due to the conductive region. In this configuration, when a carrier is flowed, In the component with a narrow gap, carriers mainly flow. The component having a narrow gap acts complementary to the component having a wide gap. Carriers also flow to the wide gap component in conjunction with the CA component. C-OS or CAC-metal oxide is used for the channel formation region of the transistor. When the transistor is turned on, the transistor has a high current driving capability, i.e., a large on-state current. High field effect mobility can be obtained.

[0036] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called atrix composite.

[0037] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to

[0038] In addition, in this specification and the like, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." .

[0039] Furthermore, unless otherwise specified, the transistors described in this specification and the like are field-effect transistors. In addition, unless otherwise specified, the transistors shown in this specification and the like are n Therefore, the threshold voltage (also called "Vth") is Unless otherwise specified, it shall be greater than 0V.

[0040] (Embodiment 1) <Configuration Example 1 of Semiconductor Device> An example of the configuration of a semiconductor device including a transistor 10 according to one embodiment of the present invention will be described below. This will be explained with reference to FIG.

[0041] FIG. 1A is a top view of a semiconductor device including a transistor 10. ) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1(A). is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. The region indicated by the dashed line in A1 and the region indicated by the dashed line in A3-A4 are perpendicular to each other. In the top view of FIG. 1(A), some elements are omitted for clarity.

[0042] The semiconductor device according to one embodiment of the present invention includes a transistor 10 and a layer Insulator 100, insulator 102, insulator 105, insulator 110, insulator 175, an insulator 176, an insulator 178, and an insulator 180. Conductors 185 and 200 electrically connected to the conductor 10 and functioning as wiring, and The electrode 190 functions as a plug, and the electrode 195 functions as a plug.

[0043] The conductor 185 is formed in an opening provided in the insulator 105. It is preferable that the height of the upper surface of the insulating body 105 is approximately the same as the height of the upper surface of the insulating body 105. Although the conductor 185 has a single-layer structure in FIG. 1B, one embodiment of the present invention uses a For example, the conductor 185 may have a laminated structure of two or more layers.

[0044] The conductor 190 is formed in an opening provided in the insulator 110. The conductor 190 is provided so as to have an area in contact with the upper surface of the conductor 185. It is preferable that the height of the upper surface of the insulating body 110 is approximately the same as the height of the upper surface of the insulating body 110. Although the conductor 190 has a single-layer structure in FIG. 1(B), one embodiment of the present invention is not limited to this. For example, the conductor 190 is in contact with the inner wall of the opening provided in the insulator 110 and is immersed in water. A conductor is formed from a material that suppresses the permeation of impurities such as silicon and water, and oxygen, and the conductor A laminated structure of two or more layers in which a conductor made of a material with higher conductivity than the conductor is formed on the conductor. It may be of the same structure.

[0045] Conductor 195 is provided in insulators 175, 176, 178, and 180. The upper surface of the conductor 140 is formed in an opening that is formed in the conductor 195. It is preferable that the height of the surface of the insulating body 180 is approximately the same as the height of the upper surface of the insulating body 180. In B), the conductor 195 is shown as a single-layer structure, but one embodiment of the present invention is not limited to this. For example, conductor 195 is not connected to insulator 175, insulator 176, insulator 178, and insulator The insulating layer 180 is in contact with the inner wall of the opening, and prevents impurities such as hydrogen and water, and oxygen from passing through. A conductor made of a material that controls the conductivity is formed, and a material with a higher conductivity than the conductor is placed on the conductor. The conductive material may have a laminated structure of two or more layers.

[0046] The conductor 200 is disposed on the insulator 180 so as to have an area in contact with the upper surface of the conductor 195. Although the conductor 200 is shown as a single layer structure in FIG. However, one embodiment of the present invention is not limited to this. For example, the conductor 200 may have a laminated structure of two or more layers. Good too.

[0047] [Transistor 10] As shown in FIG. 1B, the transistor 10 is a conductor disposed on an insulator 110. 120 and oxide 150, an insulator 130 disposed on the conductor 120, and an insulator 13 1, a conductor 140 disposed on the oxide 150, an insulator 160 disposed on the oxide 150, and an insulating and a conductor 170 disposed on the insulator 160. Here, the oxide 150 is a conductive material. The insulating body 120, the insulating body 130, and the conductive body 140 are provided so as to have an area in contact with the side surfaces of the insulating body 120, the insulating body 130, and the conductive body 140. The insulator 160 is connected to the conductor 120, the insulator 130, and the oxide 150. The conductor 170 is provided so as to have an area facing the side surface of the conductor 140. , the conductor 120, the insulator 130, and the conductor 110 are connected via the oxide 150 and the insulator 160. 40 and has an area facing the side.

[0048] As shown in FIG. 1B and FIG. 1C, the conductor 120, the insulator 130, and the conductor 1 An insulator 175 is provided on the upper surface of the insulating film 40 so as to cover the insulating film 40. The insulating film 175 has a conductive layer. The openings are formed so that the side surfaces of the body 120, the insulator 130, and the conductor 140 overlap with a part of the inner wall. An oxide 150 is provided along the inner wall of the opening, and an insulator 160 is provided on the oxide 150. A conductor 170 is provided on the insulator 160 so as to fill the opening. As shown in FIG. 1B, the oxide 150, the insulator 160, and the conductor 170 are The height of the surface is preferably about the same as the height of the upper surface of the insulator 175. ) shows the oxide 150 as a single-layer structure, but one embodiment of the present invention is not limited to this. For example, the oxide 150 may have a stacked structure of two or more layers.

[0049] In the transistor 10, the conductor 120 serves as either a source electrode or a drain electrode. The conductor 140 functions as the other of the source electrode and the drain electrode. However, the region of the oxide 150 that overlaps with the insulator 130 functions as a channel formation region. The insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate electrode. It has all the functions.

[0050] As described above, the transistor 10 according to one embodiment of the present invention has a source electrode or a drain electrode. A conductive layer (conductor 120) that functions as one of the electrodes, an oxide layer that functions as a channel forming region, An insulating layer (insulator 130) having an area in contact with the object, and a source electrode or a drain electrode The conductive layer (conductor 140) that functions as the other is stacked in order from the bottom. That is, in the transistor 10, the direction in which carriers (electrons or holes) flow (channel length) The direction of the gate electrode 12 is substantially perpendicular to the substrate surface. The channel length of the transistor 10 is determined by the insulator sandwiched between the source and drain electrodes. Therefore, the channel length of the transistor 10 is determined by the thickness of the insulator 13 For example, the channel length of the transistor 10 can be controlled by the film thickness during film formation. It is possible to arbitrarily control the thickness within the range of 1 nm to 100 nm. This method allows for the creation of multiple fine patterns with higher precision within the substrate surface than when forming the channel length using methods such as lithography. Therefore, a transistor can be fabricated.

[0051] In the transistor 10, the oxide 15 having a function as a channel formation region The oxide semiconductor layer 0 is made of a metal oxide (hereinafter also referred to as an oxide semiconductor) A transistor using a metal oxide for a channel formation region is preferably in a non-conducting state. Since the leakage current (off-state current) is extremely small, it is possible to provide a semiconductor device with low power consumption. In addition, metal oxides can be deposited using methods such as sputtering, making it possible to form highly integrated The present invention can be used for a transistor that constitutes a semiconductor device.

[0052] On the other hand, transistors that use metal oxides in the channel formation region have a tendency to produce impurities in the metal oxides. Electrical characteristics may be easily changed due to defects or oxygen deficiency, resulting in poor reliability. The hydrogen contained in the metal oxide reacts with the oxygen that bonds with the metal atom to form water, so oxygen deficiency occurs. When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. Therefore, metal oxide containing oxygen vacancies is used in the channel formation region. The transistors used in this case tend to be normally-on. It is preferable that oxygen deficiency is reduced as much as possible.

[0053] In particular, the oxide 150 has a channel forming region and an insulator that functions as a gate insulator. If oxygen vacancies exist at the interface with 160, the electrical characteristics of the transistor 10 are likely to fluctuate. This may result in poor reliability.

[0054] Therefore, the insulator 160 in contact with the oxide 150 has more oxygen than the oxygen required for the stoichiometric composition. It is preferable that the insulator 160 contains a large amount of oxygen (also referred to as excess oxygen). The excess oxygen diffuses into the channel forming region of the oxide 150, forming the channel. Oxygen vacancies in the formation region can be reduced.

[0055] Furthermore, the transistor 10 has a barrier property that prevents the intrusion of impurities such as water or hydrogen. It is preferable that the insulating material is covered with an insulator. molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms Insulating material that has the function of suppressing the diffusion of impurities such as (the impurities are difficult to penetrate) It is an insulator using at least one of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (i.e., the oxygen is less likely to permeate). preferable.

[0056] For example, the transistor 10 is provided on an insulator 102 having a barrier property. An insulator 178 having a barrier property is provided on the transistor 10. 78 are arranged above and below the transistor 10, This structure prevents impurities such as hydrogen and water from entering the semiconductor device. enters the transistor 10 from the lower layer of the insulator 102 and from the upper layer of the insulator 178. Alternatively, the oxygen contained in the insulators 130 and 160 can be prevented from , diffusion into the lower layer of the insulator 102 and the upper layer of the insulator 178 can be suppressed. As a result, the oxygen contained in the insulators 130 and 160 is converted into the oxide 150. It can be efficiently supplied to the channel forming region.

[0057] The following describes a detailed configuration of a semiconductor device including a transistor 10 according to one embodiment of the present invention. We will explain about this.

[0058] The insulators 102 and 178 are formed so that impurities such as water or hydrogen are prevented from entering the outer side of the insulators. It is preferable that the film functions as a barrier film to prevent the foreign matter from entering the transistor 10. Therefore, the insulators 102 and 178 are made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, and nitrogen. Suppresses the diffusion of impurities such as elementary molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms It is preferable to use an insulating material that has the function of preventing the impurities from penetrating (the impurities are less likely to penetrate). Or, the function of suppressing at least one diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) It is preferable to use an insulating material that has the above-mentioned properties (which is difficult for the oxygen to permeate).

[0059] For example, the insulators 102 and 178 may be aluminum oxide or silicon nitride. It is preferable to use the insulator. This allows impurities such as hydrogen and water to be trapped inside the insulator. (transistor 10 side) can be suppressed. The oxygen contained in the insulating material is prevented from diffusing outside the insulating material 102 and the insulating material 178. This can be done.

[0060] For example, the insulators 102 and 178 may be made of aluminum oxide or hafnium oxide. An insulator such as silicon nitride or silicon dioxide can be used as a single layer or a laminate.

[0061] In addition, the insulators 100, 105, 110, and 17 functioning as interlayer films 5, the insulators 176 and 180 have a higher dielectric constant than the insulators 102 and 178. By using a material with a relatively low dielectric constant for the insulator, for example, The parasitic capacitance occurring between the wirings can be reduced.

[0062] For example, insulator 100, insulator 105, insulator 110, insulator 175, insulator 176, The insulator 180 may be silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide. Aluminum, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3(B Insulators such as PTFE (Teflon) can be used in a single layer or multilayer. For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide Titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added. Alternatively, these insulators may be nitrided. The above-mentioned various insulators may be used in a film by laminating silicon oxide or silicon nitride. It is preferable that the concentration of impurities such as hydrogen and water in the catalyst be reduced as much as possible.

[0063] In addition, in the transistor 10, the insulator 130 is formed on one of the source electrode and the drain electrode. A conductor 120 functions as one of the source and drain electrodes, and a conductor 130 functions as the other of the source and drain electrodes. The insulator 130 has a function of physically and electrically isolating the insulator 130 from the insulator 140. As described above, the side surface of the insulator 130 is preferably 100 nm or more and 100 nm or less. The oxide 150 is in contact with the channel formation region of the transistor 10. The insulator 130 is an oxide insulator containing more oxygen than the oxygen required for the stoichiometric composition. In other words, it is preferable that an excess oxygen region is formed in the insulator 130. By providing an insulator containing such excess oxygen in contact with the oxide 150, The oxide 150 reduces oxygen vacancies in the channel formation region, improving the reliability of the transistor 10. can be improved.

[0064] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 14 atoms / cm 2 Above, preferably 3.0 x10 15 atoms / cm 2 The oxide film is as described above. The surface temperature of the film in this case is preferably in the range of 100°C or higher and 700°C or lower.

[0065] It is preferable that the insulator 130 contains as much oxygen as possible, but it is also preferable that the insulator 130 contains as little hydrogen or water as possible. It is preferable that the transistor 10 does not contain as much as possible. This is because hydrogen and water can cause fluctuations in the electrical characteristics. The oxide 150 functions as a hole formation region, and the insulator 13 in contact with the oxide 150 Regarding 0, the concentration of hydrogen, water, etc., which may be impurities for the transistor 10, may vary. It is preferable that it is reduced as much as possible.

[0066] The oxide 150 serving as the channel formation region of the transistor 10 contains an oxide It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor). For example, the metal oxide used in the channel formation region has a band gap of 2 eV. It is preferable to use a band gap of 2.5 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large gap, the off-state current of a transistor can be reduced. Cut.

[0067] Oxide 150 is a laminated structure of two or more layers using oxides with different atomic ratios of each metal atom. For example, the oxide 150 may have an oxide 150a (first layer) and an oxide 150b (second layer). 50b (second layer), the metal oxide used for the oxide 150b In the oxide 150a, the atomic ratio of element M in the constituent elements is It is preferable that the atomic ratio of the element M in the constituent elements is larger than that of the oxide 150b. In the metal oxide used in the present invention, the atomic ratio of element M to In is In the metal oxide, the atomic ratio of element M to In is preferably larger than that of element M. In the metal oxide used for the oxide 150a, the atomic ratio of In to the element M is In the metal oxide used in the product 150b, the atomic ratio of In to element M is greater than that of In. is preferred.

[0068] When the oxide 150 has the above structure, the oxide 150a mainly functions as the transistor 1. 0 channel formation region. Here, the insulator 160 and the oxide At the interface of the oxide 150a and the oxide 150b, the oxide 150a and the oxide 150b are made of materials having similar compositions. The defect levels are more likely to be formed than in the case of the transistor 10. , which may become a trap level that causes deterioration of reliability. By using the structure having the oxide 150a, the defect level can be separated from the oxide 150a. This allows the transistor 10 to provide good electrical characteristics and reliability.

[0069] In addition, by having the oxide 150b on the oxide 150a, the oxide 150b is formed on the surface of the oxide 150a. Therefore, it is possible to suppress the diffusion of impurities into the channel forming region of the oxide 150a. can.

[0070] As described above, a transistor using a metal oxide for a channel formation region is in a non-conducting state. Since the leakage current is extremely small in this case, a semiconductor device with low power consumption can be provided. Metal oxides can be deposited using methods such as sputtering, making them ideal for the production of highly integrated semiconductor devices. It can be used for the transistors that make up the device.

[0071] For example, the oxide 150 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, One or more types of metals selected from the group consisting of tantalum, tungsten, and magnesium) It is preferable to use metal oxides. In addition, as the oxide 150, In-Ga oxide, In-Zn oxide, etc. Compounds may also be used.

[0072] The conductor 120 and the conductor 140 are the source electrode and the drain electrode of the transistor 10. As shown in FIG. 1B and FIG. 1C, the conductor 120 and the conductor The conductors 120 and 140 are provided above and below the insulator 130. For example, a conductor such as tantalum nitride, tungsten, or titanium nitride can be used. In FIG. 1, the conductor 120 and the conductor 140 are shown as a single layer structure. It may have a laminated structure of more than one layer.

[0073] For example, when the conductor 120 and the conductor 140 have a two-layer structure, the conductor 120 (conductor The first layer (second layer) of the conductor 140 is made of a metal such as tungsten, and the second layer of the conductor 120 is made of a metal such as tungsten. The second layer (first layer) of the body 140) is made of titanium nitride or tantalum nitride, which has the function of suppressing oxygen permeation. By using such a configuration, as described above, the conductor 12 When the insulator 130 sandwiched between the oxygen and the conductor 140 contains excess oxygen, the conductor The amount of oxygen mixed into the first layer (second layer) of the conductor 120 (conductor 140) is reduced, and the conductor 120 It is possible to suppress an increase in the electrical resistance value of the first layer (second layer) of the conductor 140. .

[0074] Although not shown in FIG. 1, aluminum oxide is formed on the conductor 120 (below the conductor 140). Alternatively, an insulating film having a function of suppressing oxygen permeation, such as ammonium, may be formed. The conductors 120 and 140 may be made of tantalum nitride, tungsten, titanium nitride, or the like. The conductor 120 is used, and an insulator such as aluminum oxide is stacked on the conductor 120 (under the conductor 140). By adopting such a structure, the insulating material 130 can be separated from the conductor 120 and the conductive material 130. The amount of oxygen mixed into the conductor 140 is reduced, and the electrical resistance values of the conductors 120 and 140 are increased. In addition, the incorporation of oxygen into the conductors 120 and 140 can be suppressed. The reduction in the amount of oxygen allows more oxygen to be supplied to the oxide 150. When the sputtering method is used to form the aluminum oxide film (below the conductor 140), excess oxygen The excess oxygen can be used to form an aluminum oxide film having the insulator 130. Furthermore, the oxygen supplied to the insulator 130 may be converted into oxide 15. It may be possible to supply 0.

[0075] Furthermore, the conductor 120 or the conductor 140 may react with the oxide 150. As a result, although not shown in FIG. 1, the oxide 150 and the conductor 120 or the conductor 140 are separated from each other by a thin film. In this case, a region where the n-type conductivity is increased and carriers are increased may be formed. This may contribute to increasing the drain current of the capacitor 10.

[0076] Insulator 160 serves as the gate insulator for transistor 10. The insulator 160 is preferably disposed in contact with the upper surface of the oxide 150. It is preferable that the insulating material be formed by using an insulating material that releases oxygen more easily. For example, the insulating material 160 is the amount of oxygen desorbed in terms of oxygen atoms, as determined by thermal desorption spectroscopy (TDS). 1.0×10 14 atoms / cm 2 or more, preferably 3.0 × 10 15 atoms / c m 2 It is preferable that the oxide film is an oxide film having a surface roughness of 100% or more during the TDS analysis. The surface temperature is preferably in the range of 100°C or more and 700°C or less.

[0077] An insulator that releases oxygen when heated is used as the insulator 160 and is attached to the top surface of the oxide 150. By providing the oxide 150 as the second insulating layer, oxygen can be efficiently supplied to the channel formation region of the oxide 150. In addition, like the insulator 130, impurities such as water or hydrogen in the insulator 160 can be removed. It is preferable that the concentration of the substance is reduced. Although the insulator 160 is shown as a single layer structure in FIG. It may have a laminated structure of two or more layers.

[0078] The conductor 170 functions as the gate electrode of the transistor 10. For example, a metal such as tungsten can be used for the conductive material. Although 170 is shown as a single layer structure, it may be a laminated structure of two or more layers.

[0079] For example, when the conductor 170 has a three-layer structure, the first layer of the conductor 170 is made of a conductive oxide. The second layer of the conductor 170 is made of titanium nitride, and the third layer of the conductor 170 is made of tungsten. It is preferable to use a metal such as stainless steel. If present, the first layer of conductor 170 is disposed along the top surface of insulator 160, and the first layer of conductor 170 is disposed along the top surface of insulator 160. The second layer of conductor 70 is disposed along the top surface of the first layer of conductor 170, and the third layer of conductor 170 is preferably formed to fill the remaining space in which the conductor 170 is provided. In addition, the topmost layers of the first layer of the conductor 170, the second layer of the conductor 170, and the third layer of the conductor 170 The height of the surface is preferably about the same as the height of the upper surface of the insulator 175 .

[0080] Examples of conductive oxides that can be used for the first layer of the conductor 170 include oxide 1. Metal oxides that can be used as the material for the electrode 50 include In-Ga-Zn oxide, in particular, Among them, the metal atomic ratio is [In]:[Ga]:[Zn]=4:2:3 and has high conductivity. It is preferable to use metal oxides having a molecular weight of 4.1 or a value close to that range. By using this for the first layer of the conductor 170, the conductor 170 The second and third layers of the conductor 170 are prevented from being contaminated with oxygen by oxidation. An increase in the electrical resistance of the first layer can be suppressed.

[0081] The conductive oxide that can be used for the first layer of the conductor 170 is deposited by sputtering. By forming the film using a quenching method, oxygen is added to the insulator 160 and oxygen is supplied to the oxide 150. As a result, oxygen vacancies in the channel formation region of the oxide 150 can be eliminated. can be reduced.

[0082] As described above, the second layer of the conductor 170 is made of a metal nitride such as titanium nitride. By using a metal nitride for the second layer of the conductor 170, the conductor 170 Even if impurities such as nitrogen are added to the first layer of the conductor 170 to improve the conductivity of the first layer of the conductor 170, In addition, the third layer of the conductor 170 may be made of a metal such as tungsten. By using a low resistivity material such as tungsten, the electrical resistance of the conductor 170 can be can be lowered.

[0083] Also, for example, when the conductor 170 has a two-layer structure, the first layer is made of a metal such as titanium nitride. Alternatively, a metal nitride may be laminated on the first layer, and a metal such as tungsten may be laminated on the second layer.

[0084] Although not shown in FIG. 1, a barrier layer for preventing oxygen permeation is provided between the insulators 175 and 176. For example, the insulator may be formed as follows: A film of an insulator such as aluminum oxide may be formed. The intrusion of oxygen from the insulator such as aluminum into the conductor 170 is reduced, and the conductor 170 is free from oxygen. This can prevent the deterioration of the system.

[0085] The conductor 170 having the function of a gate electrode is made of the conductor 120 and the insulator 130. and a portion of the insulator 175 that overlaps the side surface of the conductor 140. The opening is formed so as to be filled through the oxide 150 and the insulator 160 (FIG. 1(A) (See Fig. 1(B)). When a mask is used to form the gate electrode, the size of the gate electrode The smaller the value, the higher the alignment accuracy of the mask is required. The transistor 10 does not require a mask for forming the gate electrode or alignment of the mask. Therefore, compared to when a mask is used to form the gate electrode, it is possible to form a fine gate electrode with high precision. This allows for the formation of a gate electrode, resulting in excellent productivity.

[0086] As discussed above, in transistor 10, conductor 120 is the source electrode or drain electrode. The conductor 140 functions as one of the source and drain electrodes. The region of the oxide 150 that overlaps with the insulator 130 is the channel forming region. The insulator 160 functions as a gate insulator, and the conductor 17 0 functions as a gate electrode. Therefore, in the transistor 10, the conductor 1 The length of the oxide 150 in the region in contact with the insulator 130 sandwiched between the conductor 140 and the insulating material 130 is The thickness (i.e., the film thickness of the insulator 130) corresponds to the channel length of the transistor 10. With this configuration, in the transistor 10, the thickness of the insulator 130 during film formation determines the channel It is possible to control the length to a few nanometers or less, which is difficult to fabricate using lithography. Furthermore, the channel length can be reduced to a value smaller than the thickness of the insulator 130 when it is formed. Since the channel length can be controlled by There is no need for precision in resist dimensional variations, and it is easy to In other words, the transistor 10 according to one embodiment of the present invention can be is a transistor with a high degree of design freedom, and transistors with multiple fine channel lengths can be It can be manufactured with high precision within the substrate surface. Since multiple transistors can be fabricated at the same time, the channel length can be formed by lithography. In comparison with the case where the semiconductor device is used as a semiconductor substrate, the variation in electrical characteristics between elements can be reduced.

[0087] In addition to the channel length, the transistor 10 according to one embodiment of the present invention has a source The conductor 120 and the conductor 140 functioning as a drain electrode or a drain electrode are disposed on the insulator 1. The source voltage is applied to the insulator 130. The conductor having the function of the electrode and the conductor having the function of the drain electrode are By stacking the layers perpendicular to the substrate surface, the source electrode or the drain electrode can be The area occupied by the conductor functioning as the conductive electrode within the substrate surface can be reduced. This allows miniaturization of the individual transistors 10. Since the transistor 10 can be miniaturized, a semiconductor device having the transistor 10 This allows for high integration of the device.

[0088] Thus, in the transistor 10 according to one embodiment of the present invention, the source electrode or the drain electrode The conductor and insulator that will be one of the electrodes, and the conductor that will be the other of the source electrode or drain electrode By using a "vertical transistor structure" in which layers are deposited in order, an extremely small channel length can be achieved. A plurality of transistors having the same structure can be manufactured easily and accurately. In this way, transistors with small variations in electrical characteristics between elements can be manufactured. Furthermore, miniaturization of the transistor can be achieved. This allows for a high degree of integration of the device.

[0089] As transistors become smaller and the channel length becomes shorter, the Vg( Vth in the gate voltage (V)-Id (drain current) characteristics decreases (negative shift) ), the subthreshold swing value (S value) increases, the off-current increases, etc. However, as mentioned above, As described above, in the transistor 10 according to one embodiment of the present invention, the oxide 1 having the channel formation region Therefore, for example, when Si is used in the channel forming region, Compared to transistors using silicon dioxide, the short channel effect is less likely to occur and the off-current is significantly reduced. That is, the transistor 10 according to one embodiment of the present invention can be miniaturized and still have good characteristics. For details on metal oxides, see the Semiconductors section below. This is explained in Components of the Body Device.

[0090] The conductor 190 (conductor 195) is the source electrode or the drain electrode of the transistor 10. The conductor 120 (conductor 140) having the function as one (the other) and the function as wiring The conductor 185 (conductor 200) has a function as a plug for connecting the conductor 185 (conductor 200). The conductor 190 (conductor 195) is a conductor whose main component is tungsten, copper, or aluminum. It is preferable to use a conductive material. Although not shown in FIG. 1, a conductor 190 (conductive The insulator 110 (insulator 175, insulator 175) may have a laminated structure. 6, insulator 178, and insulator 180) and the inner wall of the opening formed in conductor 185 (conductor A film of titanium, titanium nitride, or the like is formed on the top surface (bottom surface) of the body 200, and the above-mentioned film is formed on the inside of the film. A conductive material may be provided.

[0091] When the conductor 190 (conductor 195) has a laminated structure, the insulator 110 (insulator 175, The inner walls of the openings formed in the insulators 176, 178, and 180, and the conductive The conductor in contact with the top surface (bottom surface) of the body 185 (conductor 200) is impurities such as hydrogen and water. It is preferable to use a conductive material that has the function of suppressing the permeation of materials. For example, tantalum tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having the function of suppressing the permeation of impurities such as water or hydrogen is preferably The conductive material may be used as a single layer or a laminate. Impurities such as hydrogen and water from the lower (upper) layer of the conductor 190 (conductor 195) This can prevent the oxide 150 from being mixed with the oxide 150.

[0092] The conductor 185 (conductor 200) having a function as a wiring may be made of tungsten, copper, or the like. It is preferable to use a conductive material containing aluminum as the main component. The body may have a laminated structure, for example, a laminate of titanium, titanium nitride and the above conductive material. You may do so.

[0093] The above describes a structural example of a semiconductor device including the transistor 10 according to one embodiment of the present invention. As described above, in one aspect of the present invention, a lithographic method is used to fabricate a semiconductor device. Multiple transistors with channel lengths of a few nanometers or less, which are difficult to fabricate, can be fabricated within the substrate. In addition, in one aspect of the present invention, the substrate It is possible to fabricate transistors with small variations in electrical characteristics between elements within the plane. In addition, in one embodiment of the present invention, the channel length is very small, but the short channel effect is not apparent. In addition, the present invention can fabricate a transistor having excellent electrical characteristics. In one aspect, not only the channel length but also the element size including wiring and plugs is finely controlled. In one embodiment of the present invention, the above-described miniaturized transistor can be manufactured. By being able to manufacture the transistor, it is possible to achieve high integration of a semiconductor device having the transistor. Furthermore, in one embodiment of the present invention, the semiconductor device can be manufactured with high yield.

[0094] <Configuration Example 2 of Semiconductor Device> Hereinafter, the semiconductor device having the transistor 10 shown in <Configuration Example 1 of Semiconductor Device> will be referred to as Regarding a structural example of a semiconductor device including the transistor 11 according to one embodiment of the present invention, This will be explained using Figure 2.

[0095] FIG. 2A is a top view of a semiconductor device including a transistor 11. ) is a cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 2(A). is a cross-sectional view of the portion indicated by the dashed line B3-B4 in FIG. The portion indicated by the dashed dotted line in B1 and the portion indicated by the dashed dotted line in B3-B4 are perpendicular to each other. In the top view of FIG. 2(A), some elements are omitted for clarity.

[0096] In the semiconductor device shown in FIG. 2, the semiconductor device shown in <Configuration Example 1 of the Semiconductor Device> The same reference numerals are used to designate structures that have the same functions as the structures that constitute the main components. Next, differences from the semiconductor device described in <Configuration Example 1 of Semiconductor Device> will be described. For other parts, the contents explained in <Configuration example 1 of semiconductor device> can be taken into consideration. Let's say.

[0097] The semiconductor device shown in FIG. 2 has a source electrode or a drain electrode as shown in FIGS. 2(A) and 2(B). Conductors that function as rain electrodes, and plugs that connect the conductors to the upper and lower wiring The oxide 150, the insulator 160, and the conductor 170 are sandwiched between the conductors. The fact that the semiconductor device has the transistor 11 provided as a This is different from the semiconductor device (see Figure 1).

[0098] The semiconductor device of one embodiment of the present invention includes a transistor 11 and a layer 12 over a substrate (not shown). Insulator 100, insulator 102, insulator 105, insulator 110, insulator 175, an insulator 176, an insulator 178, and an insulator 180. Conductors 185_1 and 185_2 are electrically connected to the sintered body 11 and function as wiring. The conductor 200_1, the conductor 200_2, and the conductor 190_ functioning as a plug 1, a conductor 190_2, a conductor 195_1, and a conductor 195_2. Conductor 185_1 and conductor 185_2, conductor 190_1 and conductor 190_2, conductor 19 The conductors 5_1 and 195_2, and the conductors 200_1 and 200_2 are all oxidized. The object 150, the insulator 160, and the conductor 170 are disposed opposite each other with the object 150, the insulator 160, and the conductor 170 sandwiched therebetween (see FIG. 2(B)). Light. ).

[0099] The conductor 185_1 (conductor 185_2) is formed in an opening provided in the insulator 105. Here, the height of the upper surface of the conductor 185_1 (conductor 185_2) and the height of the upper surface of the insulator 105 It is preferable that the heights of the upper surfaces are approximately the same. Although the conductor 185_2 is shown as having a single-layer structure, one embodiment of the present invention is not limited to this. For example, the conductor 185_1 (conductor 185_2) may have a laminated structure of two or more layers. good.

[0100] The conductor 190_1 (conductor 190_2) is formed in an opening provided in the insulator 110. The bottom surface of the conductor 190_1 (conductor 190_2) is 5_2). The height of the upper surface of the conductive body 190_2) and the height of the upper surface of the insulator 110 are preferably approximately the same. In FIG. 2(B), the conductor 190_1 (conductor 190_2) has a single-layer structure. However, one embodiment of the present invention is not limited to this. The body 190_2) is in contact with the inner wall of the opening provided in the insulator 110 and absorbs impurities such as hydrogen and water. A conductor made of a material that suppresses the permeation of oxygen is formed on the conductor. The conductive body may have a laminated structure of two or more layers, each of which is made of a material having a higher conductivity than the conductive body. .

[0101] The conductor 195_1 (conductor 195_2) is made of the insulators 175, 176, and 177. 8, and the upper surface of the conductor 140_1 (conductor 140_2) provided on the insulator 180. Here, the height of the upper surface of the conductor 195_1 (conductor 195_2) and 2B, the height of the upper surface of the insulator 180 is preferably approximately the same. Although the conductor 195_1 (conductor 195_2) is shown as a single-layer structure, one embodiment of the present invention However, the conductor 195_1 (conductor 195_2) is not limited to this. For example, the conductor 195_1 (conductor 195_2) is , in contact with the inner walls of the openings formed in the insulators 176, 178, and 180. A conductor is formed from a material that suppresses the permeation of impurities such as silicon and water, and oxygen, and the conductor A laminated structure of two or more layers in which a conductor made of a material with higher conductivity than the conductor is formed on the conductor. It may be of the same structure.

[0102] The conductor 200_1 (conductor 200_2) is the conductor 195_1 (conductor 195_2). The insulating layer 180 is formed on the insulating layer 180 so as to have a region in contact with the upper surface. Although the conductor 200_1 (conductor 200_2) is shown as a single layer structure, in one embodiment of the present invention, For example, the conductor 200_1 (conductor 200_2) may be formed of two or more layers. It may also have a laminated structure.

[0103] [Transistor 11] As shown in FIG. 2B, the transistor 11 is a conductor disposed on an insulator 110. 120_1, a conductor 120_2, and an oxide 150, disposed on the conductor 120_1. an insulator 130_1 disposed on the conductor 120_2; an insulator 130_2 disposed on the conductor 120_2; A conductor 140_1 is disposed on the insulator 130_1, and a conductor 140_2 is disposed on the insulator 130_2. The insulator 160 is disposed on the oxide 150. and a conductor 170 disposed thereon. Here, the conductor 120_1, the insulator 130_1, and the conductor 140_1, the conductor 120_2, the insulator 130_2, and the conductor 140_2 The oxide 150, the insulator 160, and the conductor 170 are disposed opposite each other. The oxide 150 is formed on the conductor 120_1, the insulator 130_1, and the conductor 140_2. _1, the conductor 120_2, the insulator 130_2, and the conductor 140_2 facing each other. The insulator 160 is formed so as to have a region in contact with the side surface of the oxide 150. The conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_ 2), and an area facing the side of the conductor 140_1 (conductor 140_2). The conductor 170 is provided on the oxide 150 and the insulator 160. 120_1 (conductor 120_2), insulator 130_1 (insulator 130_2), and conductor The conductive member 140_1 is provided so as to have an area facing the side surface of the conductive member 140_2.

[0104] As shown in FIG. 2B and FIG. 2C, the conductor 120_1, the conductor 120_2, the insulating On the body 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2, An insulator 175 is provided to cover these. The insulator 175 includes the conductor 120_1( conductor 120_2), insulator 130_1 (insulator 130_2), and conductor 140_1 ( An opening is provided in which the side surface of the conductor 140_2 overlaps with a part of the inner wall, and a An oxide 150 is provided on the insulating layer 160, and an insulator 160 is provided on the insulating layer 150. A conductor 170 is provided on the opening so as to fill the opening. Thus, the height of the top surfaces of the oxide 150, the insulator 160, and the conductor 170 is 2(B), the oxide 150 is preferably about the same height as the upper surface of the oxide 150. Although a single layer structure is shown, one embodiment of the present invention is not limited to this. The layer 0 may have a laminated structure of two or more layers.

[0105] In the transistor 11, the conductor 120_1 is one of the source electrode and the drain electrode. The conductor 140_1 functions as the other of the source electrode and the drain electrode. The region of the oxide 150 that overlaps with the insulator 130_1 serves as a channel formation region. the insulator 160 functions as a gate insulator, and the conductor 170 functions as a gate Similarly, in the transistor 11, the conductor 120_2 The conductor 140_1 functions as either a source electrode or a drain electrode, and the conductor 140_2 functions as a source electrode or a drain electrode. The insulator 130_2 of the oxide 150 has a function as the other of the source electrode and the drain electrode. The overlapping region functions as a channel forming region, and the insulator 160 functions as a gate insulator. The conductor 170 functions as a gate electrode.

[0106] That is, the transistor 11 has one gate electrode (conductor 170) and one gate An insulator (insulator 160) and two pairs of source or drain electrodes (conductors 120_1 and Conductor 140_1, conductor 120_2, and conductor 140_2) and two channel forming regions The region (the region where the oxide 150 overlaps with the insulator 130_1, the region where the oxide 150 overlaps with the insulator 130_2) It can be said that the transistor is composed of a transistor 1 and a transistor 2. 1 includes a conductor 170 that functions as a gate electrode and a gate insulator and a conductor 120 having a function as a source electrode or a drain electrode. 1 and the conductor 140_1, and the oxide 150 (insulating a transistor having a function as a gate electrode, a conductor 170 serving as a gate insulator; an insulator 160 serving as a source electrode or The conductor 120_2 and the conductor 140_2 function as drain electrodes, and the channel The oxide 150 (the region overlapping with the insulator 130_2) functions as a forming region. It can be said that it is composed of a transistor that

[0107] The transistor 11 having the above structure can be used as a semiconductor device. The drain is larger than that of the transistor 10 (see FIG. 1) of the semiconductor device shown in Example 1. For example, the source electrode or drain electrode of the transistor 11 can be connected to the The conductor 120_1 and the conductor 120_2, which function as one of the electrodes, are connected to the conductor 120_1. 90_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2. and a conductor 140_1 that functions as the other of the source electrode and the drain electrode. The conductor 140_2 is connected to the conductor 195_1, the conductor 200_1, the conductor 195_2, and Consider the case where the gate electrode is electrically connected via the conductor 200_2. A potential that turns on the transistor 11 is applied to the conductor 170 having the function of The transistor 11 is the transistor when the same magnitude of potential is applied to the conductor 170. The drain current of the transistor 11 is twice that of the transistor 10. By having the electrical connection configuration as described above, the transistor 11 is simply a transistor. The area occupied by two transistors 10 is smaller than that occupied by two transistors 10. Therefore, the same current output capacity as in the case of

[0108] In addition, the conductors 185_1 and 185_2, and the conductors 200_1 and 200_ 2 are not electrically connected, and the two transistors constituting the transistor 11 are each independently That is, the transistor 11 may be configured to be controlled independently. The conductor 170 has a function as a gate insulator, and the insulator 160 has a function as a source insulator. Conductors 120_1 and 140_1 each functioning as a source electrode or a drain electrode, The oxide 150 (the region overlapping with the insulator 130_1) functions as a channel forming region. ) a transistor consisting of a conductor 170 having a function as a gate electrode, and a gate The insulator 160 functions as an insulator, and the insulator 160 functions as a source electrode or a drain electrode. and a conductor 120_2 and a conductor 140_2 having a function as a channel forming region. a transistor consisting of an oxide 150 (a region overlapping with the insulator 130_2) and They may be configured to be controlled independently of each other.

[0109] In the transistor 11, the conductor 185_1 (the conductor 185_2) The same material as the conductor 185 of the resistor 10 can be used. The conductor 190_2) can be made of the same material as the conductor 190 of the transistor 10. In addition, the conductor 120_1 (conductor 120_2) is the conductor 120 of the transistor 10. The insulator 130_1 (insulator 130_2) can be made of the same material as that of the insulator 130_2. The same material as the insulator 130 of the transistor 10 can be used. 1 (conductor 140_2) can be made of the same material as the conductor 140 of the transistor 10. In addition, the conductor 195_1 (conductor 195_2) is the conductor 1 of the transistor 10. The same material as that of the conductor 95 can be used. , the same material as the conductor 200 of the transistor 10 can be used.

[0110] In the semiconductor device having the transistor 11, the configuration and effects other than those described above are In this regard, the semiconductor device having the transistor 10 described in <Configuration Example 1 of the Semiconductor Device> The composition and effects can be taken into consideration.

[0111] The above description concerns the semiconductor device having the transistor 10 shown in <Configuration Example 1 of Semiconductor Device>. Regarding a structural example of a semiconductor device including the transistor 11 according to one embodiment of the present invention, As described above, in one aspect of the present invention, a method for manufacturing a semiconductor device that cannot be manufactured by a lithography method is described. It is difficult to fabricate multiple transistors with channel lengths of a few nanometers or less on the substrate surface. In addition, in one embodiment of the present invention, the substrate surface In this way, transistors with small variations in electrical characteristics between elements can be manufactured. In one embodiment of the present invention, the channel length is very small, but the short channel effect is not apparent. It is possible to manufacture a transistor having good electrical characteristics. In one aspect, a transistor with a minute element size including not only the channel length but also the wiring and plugs is In addition, in one embodiment of the present invention, a semiconductor device having a small size and a low on-state current can be manufactured. In addition, in one embodiment of the present invention, a transistor having a large capacitance can be manufactured. By being able to fabricate transistors, it is possible to achieve high integration of semiconductor devices having the transistors. In addition, in one embodiment of the present invention, the semiconductor device can be manufactured with high yield. It is possible.

[0112] <Configuration Example 3 of Semiconductor Device> Hereinafter, a semiconductor device having the transistor 10 shown in <Configuration Example 1 of Semiconductor Device> will be described. and a semiconductor device having a transistor 11 shown in <Configuration Example 2 of Semiconductor Device>. 3 shows a structural example of a semiconductor device including a transistor 12 according to one embodiment of the present invention. This will be used to explain.

[0113] FIG. 3A is a top view of a semiconductor device including a transistor 12. ) is a cross-sectional view of the portion indicated by the dashed line C1-C2 in FIG. 3(A). is a cross-sectional view of the portion indicated by the dashed line C3-C4 in FIG. The region indicated by the dashed dotted line at C1 and the region indicated by the dashed dotted line at C3-C4 are perpendicular to each other. In the top view of FIG. 3(A), some elements are omitted for clarity.

[0114] In the semiconductor device shown in FIG. 3, <Configuration Example 1 of the Semiconductor Device> or <Semiconductor Device> The same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in Configuration Example 2. In the following, the description will be mainly focused on <Configuration Example 1 of Semiconductor Device> or <Configuration Example 2 of Semiconductor Device>. 2> The parts that are different from the semiconductor device explained in the previous section will be explained. The contents described in <Configuration Example 1 of Semiconductor Device> or <Configuration Example 2 of Semiconductor Device> can be taken into consideration. It shall be.

[0115] The semiconductor device shown in FIG. 3 has a source electrode or a drain electrode as shown in FIGS. 3(A) and 3(B). Conductors that function as rain electrodes, and plugs that connect the conductors to the upper and lower wiring The conductors having the above structure are provided facing each other with the insulator 160 and the conductor 170 sandwiched between them. The fact that the transistor 12 is included is the same as that of the semiconductor device shown in <Configuration Example 1 of the Semiconductor Device> (see FIG. 1.) In addition, the oxide 150 is connected to the side of the conductor 170 via the insulator 160. The oxide 150_1 and oxide 150_2 are only provided on the area facing the conductive layer. The point that the insulating layer 170 is not provided in the area overlapping with the bottom surface of the conductive body 170 is the same as that in the second configuration example of the semiconductor device. This is different from the semiconductor device shown in FIG.

[0116] The semiconductor device of one embodiment of the present invention includes a transistor 12 and a layer 13 over a substrate (not shown). Insulator 100, insulator 102, insulator 105, insulator 110, insulator 175, an insulator 176, an insulator 178, and an insulator 180. Conductors 185_1 and 185_2 are electrically connected to the conductor 12 and function as wiring. The conductor 200_1, the conductor 200_2, and the conductor 190_ functioning as a plug 1, a conductor 190_2, a conductor 195_1, and a conductor 195_2. Conductor 185_1, conductor 190_1, conductor 195_1, and conductor 200_1, and The conductor 185_2, the conductor 190_2, the conductor 195_2, and the conductor 200_2 are all These are also provided opposite to each other with the insulator 160 and the conductor 170 interposed therebetween (see FIG. 3(B)).

[0117] In the semiconductor device shown in FIG. 3, the conductor 185_1 (conductor 185_2), The conductor 190_1 (conductor 190_2), the conductor 195_1 (conductor 195_2), and the conductor Regarding the configuration applicable to the body 200_1 (the conductor 200_2), see <Configuration Examples of Semiconductor Device>. Please refer to the information explained in 2.

[0118] [Transistor 12] As shown in FIG. 3B, the transistor 12 is a conductor disposed on an insulator 110. 120_1, conductor 120_2, oxide 150_1, oxide 150_2, and insulator 16 0, an insulator 130_1 disposed on the conductor 120_1, and an insulator 130_2 disposed on the conductor 120_2. an insulator 130_2 disposed on the insulator 130_1; and a conductor 140_1 disposed on the insulator 130_1. , a conductor 140_2 disposed on the insulator 130_2, and a conductor 140_3 disposed on the insulator 160. Here, the conductor 120_1 and the conductor 120_2, the insulator 1 30_1 and insulator 130_2, conductor 140_1 and conductor 140_2, and oxide 150 The oxide 150_1 and the oxide 150_2 are set opposite to each other with the insulator 160 and the conductor 170 interposed therebetween. In addition, the oxide 150_1 (oxide 150_2) is formed on the conductor 120_1 (conductor 120_2), an insulator 130_1 (insulator 130_2), and a conductor 140_1 (conductor 140_2), the conductor 120_2 (conductor 120_1), the insulator 130_2 (insulator 1 30_1), and the area in contact with the side surface facing the conductor 140_2 (conductor 140_1). The insulator 160 is provided so as to have the oxide 150_1 (oxide 150_2 ) through the conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130 _2), and an area facing the side of the conductor 140_1 (conductor 140_2). The conductor 170 is formed by the oxide 150_1 (oxide 150_2) and the insulating film 150_2. The conductor 120_1 (conductor 120_2), the insulator 130_1 (insulator 130_2), and the insulating material 130_3 are connected via the insulating material 160. The area facing the side of the conductor 130_1 (conductor 140_2) and the conductor 140_1 (conductor 140_2) is The device is provided to have:

[0119] As shown in FIG. 3B and FIG. 3C, the conductor 120_1, the conductor 120_2, the insulating On the body 130_1, the insulator 130_2, the conductor 140_1, and the conductor 140_2, An insulator 175 is provided to cover these. The insulator 175 includes the conductor 120_1( conductor 120_2), insulator 130_1 (insulator 130_2), and conductor 140_1 ( An opening is provided in which a side surface of the conductor 140_2 and a part of the inner wall overlap, and the inner wall (side surface ) along the oxide 150_1 and the oxide 150_2, and the oxide 150_1 and the oxide The opposing sides of 150_2 and the gap between oxide 150_1 and oxide 150_2 An insulator 160 is provided to cover the upper surface of the insulator 110, and the insulator 160 is provided to cover the upper surface of the insulator 110. A conductor 170 is provided to fill the opening. Height of the top surfaces of the oxide 150_1, the oxide 150_2, the insulator 160, and the conductor 170 It is preferable that the height of the upper surface of the insulator 175 is approximately the same as the height of the upper surface of the insulator 175. Although the oxide 150_1 (oxide 150_2) is shown as a single layer structure, it is one embodiment of the present invention. For example, the oxide 150_1 (oxide 150_2) may be a stack of two or more layers. It may also have a layer structure.

[0120] In the transistor 12, the conductor 120_1 is one of the source electrode and the drain electrode. The conductor 140_1 functions as the other of the source electrode and the drain electrode. The region of the oxide 150_1 that overlaps with the insulator 130_1 is a channel formation region. The insulator 160 serves as a gate insulator, and the conductor 170 serves as a , which functions as a gate electrode. The conductor 140_2 functions as either a source electrode or a drain electrode. The insulator 13 of the oxide 150_2 has a function as the other of the source electrode or the drain electrode. The region overlapping with 0_2 functions as a channel forming region, and the insulator 160 functions as a gate The conductor 170 functions as a gate electrode.

[0121] That is, transistor 12 has one gate electrode (conductor 170) and one gate An insulator (insulator 160) and two pairs of source or drain electrodes (conductors 120_1 and Conductor 140_1, conductor 120_2, and conductor 140_2) and two channel forming regions The area (the area where the oxide 150_1 overlaps with the insulator 130_1, the area where the oxide 150_2 overlaps with the insulator 130_2) 0_2) and the transistor. The transistor 12 has a conductor 170 that functions as a gate electrode and a gate insulator 172 that functions as a gate insulator. an insulator 160 having a function as a source electrode or a drain electrode; 120_1 and the conductor 140_1, and the oxide 15 having a function as a channel forming region. 0_1 (a region overlapping with the insulator 130_1), and a transistor consisting of a gate electrode a conductor 170 having the function of a gate insulator, an insulator 160 having the function of a gate insulator, and Conductor 120_2 and conductor 140_2 functioning as a source electrode or a drain electrode and an oxide 150_2 (which overlaps with the insulator 130_2) having a function as a channel formation region. It can be said that the transistor is composed of a gate electrode and a gate electrode.

[0122] The transistor 12 having the above structure can be used as a semiconductor device. The drain is larger than that of the transistor 10 (see FIG. 1) of the semiconductor device shown in Example 1. For example, the source electrode or drain electrode of the transistor 12 can be connected to the The conductor 120_1 and the conductor 120_2, which function as one of the electrodes, are connected to the conductor 120_1. 90_1, the conductor 185_1, the conductor 190_2, and the conductor 185_2. and a conductor 140_1 that functions as the other of the source electrode and the drain electrode. The conductor 140_2 is connected to the conductor 195_1, the conductor 200_1, the conductor 195_2, and Consider the case where the gate electrode is electrically connected via the conductor 200_2. A potential that turns on the transistor 12 is applied to the conductor 170 having the function of The transistor 12 is then turned on when the same magnitude of potential is applied to the conductor 170. The drain current of the transistor 12 is twice that of the transistor 10. By having the electrical connection configuration as described above, the transistor 12 is simply a transistor. The area occupied by two transistors 10 is smaller than that occupied by two transistors 10. Therefore, the same current output capacity as in the case of

[0123] In addition, the conductors 185_1 and 185_2, and the conductors 200_1 and 200_ 2 are not electrically connected, and the two transistors that make up the transistor 12 are each independently That is, the transistor 12 may be configured to be controlled independently. The conductor 170 has a function as a gate insulator, and the insulator 160 has a function as a source insulator. Conductors 120_1 and 140_1 each functioning as a source electrode or a drain electrode, The oxide 150_1 (which overlaps with the insulator 130_1) functions as a channel forming region. A transistor consisting of a gate electrode (region), a conductor 170 having a function as a gate electrode, and a gate electrode The insulator 160 functions as a gate insulator, and the insulator 160 functions as a source electrode or a drain electrode. The conductors 120_2 and 140_2 have the function of forming a channel. a transistor consisting of an oxide 150_2 (a region overlapping with the insulator 130_2) having may be configured to be controlled independently of each other.

[0124] Here, the transistor 12 included in the semiconductor device shown in FIG. 3 is the same as that included in the semiconductor device shown in FIG. The shape of the oxide having the channel formation region is different from that of the transistor 11 having the channel formation region. Specifically, the transistor 11 is made up of a conductor 120_1, an insulator 130_1, and a conductor 140_2. 0_1, the conductor 120_2, the insulator 130_2, and the conductor 140_2, The oxide 150 contacts the opposing side surfaces and a portion of the top surface of the insulator 110, The transistor 12 is made up of a conductor 120_1, an insulator 130_1, and a conductor 140_1. The conductor 120_2, the insulator 130_2, and the acid contacting the side surface facing the conductor 140_2 The conductor 120_2, the insulator 130_2, and the conductor 140_2 are The oxide film contacting the side surface facing the insulator 120_1, the insulator 130_1, and the conductor 140_1 That is, the transistor 12 has a channel formation region. The oxides are arranged in two layers (oxide 150_1, oxide 150_2) with the insulator 160 and the conductor 170 sandwiched between them. 50_2) is different from the oxide 150 of the transistor 11. The oxide having the formation region is electrically conductive. When the two transistors constituting 12 are controlled independently, This makes it possible to suppress the occurrence of leakage current between transistors via oxides. The influence of the operation (on operation, off operation) of one of the transistors constituting the transistor 12 The other transistor is less susceptible to the influence of the other transistor, and the operation of each can be reliably controlled. Cut.

[0125] In the transistor 12, the oxide 150_1 (oxide 150_2) is The same material as the oxide 150 of the transistor 10 can be used. The conductor 185_2) can be made of the same material as the conductor 185 of the transistor 10. In addition, the conductor 190_1 (conductor 190_2) is the conductor 190 of the transistor 10. The same material as that of the conductor 120_1 (conductor 120_2) can be used. The same material as the conductor 120 of the transistor 10 can be used. 1 (insulator 130_2) can be made of the same material as the insulator 130 of the transistor 10. In addition, the conductor 140_1 (conductor 140_2) is the conductor 1 of the transistor 10. The same material as that of 40 can be used. In addition, the conductor 195_1 (conductor 195_2) The same material as the conductor 195 of the transistor 10 can be used. 0_1 (conductor 200_2) is made of the same material as the conductor 200 of the transistor 10. This can be done.

[0126] In the semiconductor device having the transistor 12, the configuration and effects other than those described above are In this regard, the semiconductor device having the transistor 10 described in <Configuration Example 1 of the Semiconductor Device>, Or the configuration of a semiconductor device including the transistor 11 described in <Configuration Example 2 of Semiconductor Device>, The effects can be taken into consideration.

[0127] The above description has been made regarding the semiconductor device having the transistor 10 shown in <Configuration Example 1 of Semiconductor Device>, or a semiconductor device having a transistor 11 different from that shown in <Configuration Example 2 of Semiconductor Device>. The structural example of the semiconductor device including the transistor 12 according to one embodiment of the present invention has been described. As described above, in one embodiment of the present invention, a method for manufacturing a semiconductor device that is difficult to manufacture by lithography is used. Multiple transistors with channel lengths of a few nm or less can be fabricated within the substrate surface. In addition, in one embodiment of the present invention, the substrate can be easily fabricated with high accuracy. This makes it possible to manufacture transistors with small variations in electrical characteristics between elements. In one aspect of the present invention, the channel length is very small, but the short channel effect is not easily manifested. A transistor having favorable electrical characteristics can be manufactured. The goal is to create transistors with minute element sizes, including not only the channel length but also the wiring and plugs. In addition, in one embodiment of the present invention, a semiconductor device having a large on-state current while being miniaturized can be manufactured. In one embodiment of the present invention, the above-described fine transistor can be manufactured. By being able to fabricate such transistors, it is possible to achieve high integration of semiconductor devices having such transistors. In addition, in one aspect of the present invention, it is possible to realize high integration while minimizing the risk of leakage between adjacent transistors. In addition, in one embodiment of the present invention, a semiconductor device having a small capacitance can be manufactured. The body devices can be fabricated with high yield.

[0128] <Modification of Semiconductor Device> Hereinafter, the semiconductor device having the transistor 10 shown in <Configuration Example 1 of the Semiconductor Device> will be described. As a modification, a semiconductor device including a transistor 13 according to one embodiment of the present invention is shown in FIG. 4 will be used to explain.

[0129] FIG. 4A is a top view of a semiconductor device including a transistor 13. ) is a cross-sectional view of the portion indicated by the dashed line D1-D2 in FIG. 4(A). is a cross-sectional view of the area indicated by the dashed line D3-D4 in FIG. The region indicated by the dashed line in and the region indicated by the dashed line in D3-D4 are perpendicular to each other. In the top view of FIG. 4(A), some elements are omitted for clarity.

[0130] In the semiconductor device shown in FIG. 4, <Configuration Example 1 of Semiconductor Device> to <Configuration Example 2 of Semiconductor Device> The same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in Configuration Example 3. In the following, the following mainly describes <Configuration Example 1 of Semiconductor Device> to <Configuration Example 2 of Semiconductor Device>. 3> The differences from the semiconductor device explained in the previous section will be explained. The contents described in <Configuration Example 1 of Semiconductor Device> to <Configuration Example 3 of Semiconductor Device> can be taken into consideration. It shall be.

[0131] The semiconductor device shown in FIG. 4 has a gate electrode as shown in FIGS. 4(B) and 4(C). The functional conductor 171 is formed by the oxide 151 which functions as a channel forming region and the gate electrode 152. The conductor 120, the insulator 130, and the conductor 140 are connected via the insulator 161, which functions as a ground insulator. A transistor having an area overlapping not only the side surface of the conductor 140 but also a part of the top surface of the conductor 140. The semiconductor device shown in <Configuration Example 1 of Semiconductor Device> (see FIG. 1) has the stator 13. ) is different from

[0132] The semiconductor device of one embodiment of the present invention includes a transistor 13 and a layer Insulator 100, insulator 102, insulator 105, insulator 110, insulator 175, an insulator 176, an insulator 178, and an insulator 180. Conductors 185 and 200 electrically connected to the conductor 13 and functioning as wiring, and The electrode 190 functions as a plug, and the electrode 195 functions as a plug.

[0133] In the semiconductor device shown in FIG. 4, the conductor 185, the conductor 190, the conductor 195, The configuration applicable to the conductor 200 is the same as that described in <Configuration Example 1 of Semiconductor Device>. The contents can be taken into consideration.

[0134] [Transistor 13] As shown in FIG. 4B, the transistor 13 is a conductor disposed on an insulator 110. 120 and oxide 151, an insulator 130 disposed on the conductor 120, and an insulator 13 1, a conductor 140 disposed on the oxide 151, an insulator 161 disposed on the oxide 151, and an insulating and a conductor 171 disposed on the insulator 161. Here, the oxide 151 is a conductive material. the side surfaces of the body 120, the insulator 130, and the conductor 140, and a part of the top surface of the conductor 140. The insulator 161 is provided so as to have a contact area with the oxide 151. The side surfaces of the conductor 120, the insulator 130, and the conductor 140, and a part of the top surface of the conductor 140; The conductor 171 is provided to have a region overlapping the oxide 151 and the insulating film 152. The side surfaces of the conductor 120, the insulator 130, and the conductor 140 are connected to the conductor 140 through the body 161. 40 so as to have an area overlapping with a part of the upper surface of the

[0135] As shown in FIG. 4B, on the conductor 120, the insulator 130, and the conductor 140, The insulator 175 is provided to cover these. A part of the inner wall overlaps the side surface of the body 130 and the conductor 140, and a part of the upper surface of the conductor 140. An opening is provided, and an oxide 151 is provided along the inner wall of the opening. An insulator 161 is provided on the opening, and a conductor 17 is provided on the insulator 161 so as to fill the opening. 4B, an oxide 151, an insulator 161, and The height of the top surface of the conductor 171 is preferably approximately the same as the height of the top surface of the insulator 175. Note that although the oxide 151 has a single-layer structure in FIG. For example, the oxide 151 may have a stacked structure of two or more layers.

[0136] In the transistor 13, the conductor 120 serves as either a source electrode or a drain electrode. The conductor 140 functions as the other of the source electrode and the drain electrode. However, the region of the oxide 151 that overlaps with the insulator 130 functions as a channel formation region. The insulator 161 functions as a gate insulator, and the conductor 171 functions as a gate electrode. It has all the functions.

[0137] Here, the transistor 10 is configured such that the contact surface between the oxide 150 and the insulator 130 is as shown in FIG. The transistor 13 has only one junction between the oxide 151 and the insulator 130. There are three contact surfaces in total, one shown in Figure 4(B) and two shown in Figure 4(C). That is, the transistor 10 and the transistor 13 are different in their functions. In the oxide (oxide 150 or oxide 151) that is to be formed, There is a difference in the area of the area that can be used (transistor 13 is larger than transistor 10, The area of the oxide that can function as the channel formation region is large. 13 has the same element size as transistor 10, but A large drain current can be output.

[0138] In addition, in the transistor 13, the conductor 171 functioning as a gate electrode is connected to the conductor 140 The transistor 1 differs from the transistor 10 in that it has an area overlapping a part of the top surface of the transistor 1. 3 has this structure, the channel forming region (oxide 15 The area overlapping with the insulator 130 of the first embodiment can be surrounded by the conductor 171. The transistor 13 has a gate electrode in the channel forming region more reliably than the transistor 10. Therefore, the transistor 13 can be controlled to operate ( This allows for reliable control of carriers during on / off operations, and is more efficient than transistor 10. Therefore, it is possible to realize both a larger on-current and a smaller off-current.

[0139] Note that in the transistor 13, the oxide 151 is the same as the oxide 150 in the transistor 10. The insulator 161 can be made of the same material as the insulator 1 of the transistor 10. The conductor 171 can be made of the same material as the conductor 60 of the transistor 10. The same material as body 170 can be used.

[0140] In the semiconductor device having the transistor 13, the configuration and effects other than those described above are In this regard, the semiconductor device having the transistor 10 described in <Configuration Example 1 of the Semiconductor Device>, The semiconductor device having the transistor 11 described in <Configuration Example 2 of the semiconductor device> or Please refer to the configuration and effects of the semiconductor device having the transistor 12 described in the "Configuration Example 3 of the Semiconductor Device" section. It is possible.

[0141] The above is a description of the semiconductor device having the transistor 10 shown in <Configuration Example 1 of the Semiconductor Device>. As a modification, a configuration example of a semiconductor device including the transistor 13 according to one embodiment of the present invention will be described. As described above, in one aspect of the present invention, a method for manufacturing a semiconductor device using a lithography method is described. Multiple transistors with channel lengths of a few nanometers or less, which are difficult to fabricate on the substrate surface, In addition, in one embodiment of the present invention, the substrate can be easily manufactured with high accuracy. It is possible to fabricate transistors with small variations in electrical characteristics between elements within the substrate. Furthermore, in one embodiment of the present invention, a transistor with large on-state current can be manufactured. Furthermore, in one embodiment of the present invention, a transistor with low off-state current can be manufactured. In one embodiment of the present invention, the channel length is very small, but the short channel effect is not apparent. It is possible to manufacture a transistor having good electrical characteristics. In one aspect, a transistor with a minute element size including not only the channel length but also the wiring and plugs is In addition, in one embodiment of the present invention, the fine transistor can be manufactured. By being able to fabricate such a transistor, it is possible to achieve high integration of a semiconductor device having the transistor. In addition, in one embodiment of the present invention, the semiconductor device can be manufactured with high yield. do.

[0142] An example of a semiconductor device according to one embodiment of the present invention is the transistor 10 described above. A semiconductor device having a transistor 11, a transistor 12, or a transistor 13 (see FIGS. 1 to 3) 4. The semiconductor device according to one embodiment of the present invention is not limited to the above-described semiconductor devices. The configurations of the conductor devices can be combined as appropriate.

[0143] <Components of semiconductor device> Hereinafter, a transistor 10, a transistor 11, and a transistor according to one embodiment of the present invention will be described. 12, or each applicable to a semiconductor device having a transistor 13 (see FIGS. 1 to 4). The components will be described in detail.

[0144] 〔substrate〕 The substrate may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. Substrates (such as yttria-stabilized zirconia substrates), resin substrates, etc. Also, semiconductor substrates Examples of the substrate include a semiconductor substrate such as silicon or germanium, or silicon carbide or silicon dioxide. Consists of germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates that have an insulating region inside the semiconductor substrate. Conductor substrates, such as SOI (Silicon On Insulator) substrates, Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. A substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have an element provided thereon. The element provided on the substrate may be a capacitor element. , resistor elements, switch elements, light-emitting elements, memory elements, etc.

[0145] A flexible substrate may be used as the substrate. As a method for providing the transistor, a transistor is formed on a non-flexible substrate, and then the transistor is peeled off. There is also a method of separating the substrate and transferring it to a flexible substrate. It is advisable to provide a release layer between the substrate and the transistor. A film or foil may be used. The substrate may be stretchable. The material may have the property of returning to its original shape when the bending or pulling is stopped. The substrate may have a thickness of, for example, 5 μm or more and 700 μm or less, preferably Preferably, the thickness is 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of the semiconductor device having the transistor can be reduced. Furthermore, by making the substrate thin, it is possible to obtain a flexible substrate even when glass or the like is used. They may have the property of returning to their original shape when the bending or pulling is stopped. Therefore, it is possible to reduce the impact that is applied to the semiconductor device on the board when it is dropped, etc. That is, a robust semiconductor device can be provided.

[0146] The flexible substrate may be, for example, a metal, an alloy, a resin, or a glass, or The substrate, which is a flexible substrate, has a low linear expansion coefficient. The substrate is preferably a flexible substrate, for example, a substrate having a linear expansion coefficient of 1.0 or less. The rate is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less Examples of resins include polyester, polyolefin, and polyamide. (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. In particular, aramid has a low coefficient of linear expansion and is therefore suitable for use as a flexible substrate.

[0147] [Insulator] Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0148] Insulator 100, insulator 105, insulator 110, insulator 130 (or insulator 130_1 , insulator 130_2) and the insulator 160 may be, for example, boron, carbon, nitrogen, oxygen, or the like. , fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, Germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum An insulator containing tantalum may be used in a single layer or a laminated layer. The body 105, the insulator 110, and the insulator 130 (or the insulator 130_1 and the insulator 130_2) The insulator 160 may include silicon oxide, silicon oxynitride, or silicon nitride. It is preferable to do so.

[0149] The insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1, the insulator 130_2) It is preferable that the concentration of impurities such as water, hydrogen, or nitrogen oxides in the fuel cell is reduced. For example, the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130) The amount of hydrogen desorption from the insulator 130 was measured by thermal desorption spectroscopy (TDS). In the case of the film surface temperature In the range of 50°C to 500°C, the amount of desorption converted to hydrogen molecules is per area of the insulator 110 or the insulator 130 (or the insulator 130_1, the insulator 130_2) Converted to 2 x 10 15 molecules / cm 2 Less than 1 × 10 15 molecules / cm 2 Less than or equal to 5 × 10 14 molecules / c m 2 In addition, the insulators 105, 110, and 130 (or The insulators 130_1 and 130_2 are made of an insulator that releases oxygen when heated. It is preferable to form the insulators 105, 110, and 130. (or the insulator 130_1, the insulator 130_2) 110 and the insulator 130 (or the insulator 130_1, the insulator 130_2), 150 (or oxide 150_1, oxide 150_2) to effectively supply oxygen can be done.

[0150] In addition, the insulator 160 preferably has a high relative dielectric constant. The body 160 may be made of gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, or aluminum oxide. Oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium oxides containing silicon and hafnium, and oxynitrides containing silicon and hafnium It is preferable to have a nitride containing silicon and hafnium, or a nitride containing silicon and hafnium, or the like. The insulator 160 is made of silicon oxide or silicon oxynitride and an insulator with a high dielectric constant. It is preferable that the layer has a laminated structure. Silicon oxide and silicon oxynitride are thermally stable. Therefore, by combining it with an insulator with a high dielectric constant, it is possible to obtain a film with few defects that is thermally stable. Furthermore, a laminated structure with a high relative dielectric constant can be obtained.

[0151] The insulator 160 is formed on the top surface of the oxide 150 (or the oxide 150_1 or the oxide 150_2). The insulator 160 is preferably an insulating material that releases oxygen when heated. It is preferable to form such an insulator 160 using an oxide 150 (or an oxide). By providing the oxide 150 ( Alternatively, oxygen can be effectively supplied to the oxides 150_1 and 150_2. In addition, the insulator 105, the insulator 110, and the insulator 130 (or the insulator 130_1, the insulator As with the insulator 130_2), the concentration of impurities such as water or hydrogen in the insulator 160 is reduced. The thickness of the insulator 160 is preferably 1 nm or more and 20 nm or less. For example, the film thickness may be set to about 1 nm.

[0152] The insulator 160 preferably contains oxygen. For example, thermal desorption spectroscopy (TDES) S analysis), the surface temperature range is 100℃ to 700℃ or 100℃ to 500℃ In this range, the amount of oxygen molecules desorbed is converted to an area of 160 m of insulator, which is 1 x 10 14 mole cules / cm 2 or more, preferably 2 x 10 14 molecules / cm 2 That's all. More preferably 4 x 10 14 molecules / cm 2 Anything above that is fine.

[0153] The insulators 175, 176, and 180 each have a low dielectric constant. For example, the insulators 175, 176, and 180 are preferably made of silicon oxide. Silicon oxide nitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine silicon dioxide doped with carbon, silicon dioxide doped with carbon and nitrogen, silicon dioxide with vacancies It is preferable that the insulating material 175 and the insulating material 17 6, and the insulator 180 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. silicon dioxide doped with fluorine, silicon dioxide doped with carbon, carbon and nitrogen It has a laminated structure of added silicon oxide or silicon oxide with pores and resin. Silicon oxide and silicon oxynitride are thermally stable and therefore can be used in combination with resin. By combining these resins, it is possible to create a laminated structure that is thermally stable and has a low dielectric constant. Examples of such materials include polyester, polyolefin, polyamide (nylon, aramid, etc.) Insulator 175, insulating material, etc. The edge 176 and the insulator 180 are connected to the insulators 105, 110, and 130 (or Similarly to the insulators 130_1, 130_2, and 160, water or It is preferable that the concentration of impurities such as hydrogen is reduced.

[0154] In addition, the insulators 102 and 178 have properties that allow them to resist impurities such as hydrogen and water, and oxygen. It is preferable to use an insulator with high barrier properties. By using the insulator 102 (insulator 178) as the insulator 78, the transistor 10, transistor 11, transistor 12, or transistor 13 contains hydrogen, water, or the like. In addition, the transistor 10 and the transistor The oxygen in the transistor 11, the transistor 12, or the transistor 13 is absorbed by the insulator 102 (insulator 17). 8) can be prevented from diffusing to the lower (upper) side. , boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, Chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, It is preferable to use an insulator containing oxydimium, hafnium, or tantalum, in a single layer or a laminate. stomach.

[0155] Furthermore, examples of the insulator include aluminum oxide, magnesium oxide, and gallium oxide. ammonium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, nickel oxide metal oxides such as oxydimium, hafnium oxide, or tantalum oxide; silicon oxide nitride or nitride; The insulator may be aluminum oxide or hafnium oxide. It is preferable that the compound has a fluorine atom or the like.

[0156] 〔conductor〕 Conductor 120 (or conductor 120_1, conductor 120_2), conductor 140 (or Conductor 140_1, Conductor 140_2), Conductor 185 (or Conductor 185_1, Conductor 185_2), conductor 190 (or conductor 190_1, conductor 190_2), conductor 195 (or conductor 195_1, conductor 195_2), conductor 200 (or conductor 2 00_1, conductor 200_2), and conductor 170 may be aluminum, chromium, copper , silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium , vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium Materials containing one or more metal elements selected from aluminum, ruthenium, etc. can be used. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, Conductors, silicides such as nickel silicide may also be used.

[0157] In addition, the conductor, particularly the conductor 170, may be an oxide 150 (or an oxide 150_ 1. Conductive materials containing metal elements and oxygen contained in metal oxides applicable to oxide 150_2) Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium oxide, including indium tin oxide and tungsten oxide, Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, and silicon-doped indium tin oxide are used. Alternatively, nitrogen-containing indium gallium zinc oxide may be used. By using such a material, the oxide 150 (or the oxide 150_1, the oxide 150_2) It may be possible to capture hydrogen contained in the material, or hydrogen that is mixed in from the outer insulator, etc. Hydrogen may be captured.

[0158] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0159] When an oxide is used for a channel formation region of a transistor, A laminated structure is used that combines the material containing the metal element and the conductive material containing oxygen. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, The oxygen released from the SiO 2 layer is more easily supplied to the channel formation region.

[0160] In addition, the conductor 185 (or the conductor 185_1 or the conductor 185_2), the conductor 190 ( Or, the conductor 190_1, the conductor 190_2), the conductor 195 (or the conductor 195_1 , conductor 195_2), and conductor 200 (or conductor 200_1, conductor 200_2 For example, a highly conductive material with high embedding properties, such as tungsten or polysilicon, is used as the material. In addition, conductive materials with high embeddability and titanium, titanium nitride, and tantalum nitride are also used. A conductive barrier film such as the above may be used in combination.

[0161] [Oxide] The oxide 150 (or oxide 150_1, oxide 150_2) is a metal oxide. However, instead of the oxide 150, silicon is used as the semiconductor material. (including strained silicon), germanium, silicon germanium, silicon carbide, gallium Arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors In the following, the oxide 150 (or The metal oxides preferably used for the oxides 150_1 and 150_2 are described below. Reveal.

[0162] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, iridium, It is preferable that the alloy contains tritium or tin. Also, boron, titanium, iron, niobium, etc. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, One or more selected from aluminum, tantalum, tungsten, magnesium, etc. Seeds may also be included.

[0163] Here, when the metal oxide is InMZnO having indium, element M, and zinc, The element M may be aluminum, gallium, yttrium, or tin. Other elements that can be used for M include boron, titanium, iron, nickel, and Al, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, However, the element M can be any of the elements mentioned above. There may be cases where a combination of multiple options is acceptable.

[0164] By using the above metal oxide in the channel formation region of a transistor, high field-effect mobility can be achieved. Furthermore, it is possible to realize a transistor with high reliability. It can be realized.

[0165] A transistor using a metal oxide channel region has extremely low current density in the non-conducting state. Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Since the film can be formed by sputtering or the like, it is suitable for use in transistors that constitute highly integrated semiconductor devices. It can be used for transistors.

[0166] In addition, a metal oxide with a low carrier density is used for the channel formation region of the transistor. In order to reduce the carrier density of the metal oxide film, it is preferable to It is sufficient to lower the impurity concentration and reduce the defect level density. A material with a low density of defect states is called a high-purity intrinsic material or a substantially high-purity intrinsic material. Metal oxides have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 End This can be done as follows.

[0167] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0168] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor in which a channel formation region is formed in a metal oxide may have unstable electrical characteristics. There is a match.

[0169] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be kept low. In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0170] Here, the influence of each impurity in the metal oxide will be described.

[0171] When metal oxides contain silicon or carbon, which are elements of Group 14, they become metal oxides. Defect levels are formed in the oxides. This leads to the formation of silicon and carbon concentrations in the metal oxides. The concentration of silicon and carbon near the interface with the metal oxide was measured by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectrometry) concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0172] Furthermore, when an alkali metal or alkaline earth metal is contained in a metal oxide, the metal Defect levels may be formed in the oxide, generating carriers. Transistors using metal oxides containing metal or alkaline earth metals in the channel formation region Therefore, alkali metals in metal oxides or It is preferable to reduce the concentration of alkaline earth metals. The concentration of alkali metals or alkaline earth metals in the metal oxide is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0173] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carriers As a result, the density increases and it becomes easier to make the metal oxide containing nitrogen into a channel type. The transistors used in the semiconductor region tend to be normally-on. In the metal oxide, it is preferable that the nitrogen content is reduced as much as possible. The nitrogen concentration in the material was 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0174] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, metal oxides containing hydrogen can generate electrons, which are carriers. The transistor used in the channel formation region tends to have normally-on characteristics. It is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. The hydrogen concentration obtained by SIMS in the oxide is 1×10 20 atoms / cm 3 Not yet less than 1×10 19 atoms / cm 3 less than 5 × 10 18 at oms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0175] Use of metal oxide with sufficiently reduced impurities in the channel formation region of a transistor This allows stable electrical properties to be imparted.

[0176] The CAC-OS is described in detail below. This is an example of a function or material structure that the metal oxide of such a transistor can have.

[0177] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are 0.5 nm to 10 nm in size. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, we will refer to metal oxides in which one or more metal elements are unevenly distributed. The area having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more. The mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. cormorant.

[0178] For example, CAC-OS in In-Ga-Zn oxide (In- Ga-Zn oxide may be specifically referred to as CAC-IGZO. (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0). ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are ) is a real number greater than 0. ) and the material is separated into mosaics. Zyclic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is uniformly distributed in the film (hereafter (Also called cloud-like.)

[0179] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite metal oxide having a mixed structure with a region in which In this specification, for example, when the atomic ratio of In to the element M in the first region is , the atomic ratio of In to the element M in the second region is greater than the atomic ratio of In in the first region. The concentration of In is higher than in the region

[0180] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In (1 +x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0181] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0182] On the other hand, CAC-OS is a material structure of metal oxides. In a material composition containing a, Zn, and O, nanoparticles with Ga as the main component were observed in some areas. The region where In is observed as a nanoparticle and the region where In is observed as a nanoparticle are the main component are shown in the model. Therefore, in CAC-OS, The crystal structure is a secondary factor.

[0183] Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, Not at all.

[0184] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but It may be difficult to observe a clear boundary between the main component region.

[0185] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. Aluminum, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum Cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. When one or more selected from the above are contained, CAC-OS is The nanoparticles are mainly composed of In and the nanoparticles are mainly composed of In. This refers to a configuration in which the areas observed in the image are randomly distributed in a mosaic pattern.

[0186] CAC-OS is, for example, a material that is deposited by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. In addition, the ratio of the oxygen concentration to the total flow rate of the deposition gas during deposition may be The lower the flow rate ratio of the oxygen gas, the more preferable. For example, the flow rate ratio of the oxygen gas is set to 0% or more and less than 30%. Preferably, it is set to 0% or more and 10% or less.

[0187] CAC-OS is an X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction, the measurement region It can be seen that no orientation in the ab plane direction or the c axis direction is observed.

[0188] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample with light, a ring-shaped region with high brightness and Several bright spots are observed in the ring region. Therefore, from the electron diffraction pattern, CA The crystal structure of C-OS is nc(na It can be seen that the crystalline structure is no-crystal.

[0189] For example, in the case of CAC-OS made of In-Ga-Zn oxide, the energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectrometry) EDX mapping obtained using oscopy revealed that GaO X3 The area where is the main component Area and In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0190] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from GZO compounds. X3 The main components are and the region where In X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0191] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 ZnY 2O Z2 , or InO X1 The carriers flow through the area where the main component is the metal oxide. Therefore, the conductivity of In is expressed as a X2 Zn Y2 O Z2 , or InO X1 The region where the main component is distributed in a cloud-like shape in the metal oxide allows the metal oxide to The used transistor can achieve high field-effect mobility.

[0192] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The main component is distributed in the metal oxide, and the transistor using the metal oxide is The transistor can suppress leakage current and achieve good switching operation.

[0193] Therefore, when CAC-OS is used in semiconductor devices such as transistors, X2 Z n Y2 O Z2 , or InO X1 The conductivity due to GaO X3 Insulation and However, by acting in a complementary manner, it is possible to achieve both a high on-current and a low off-current. can.

[0194] Furthermore, semiconductor devices using CAC-OS have high reliability. display devices, light-emitting devices, lighting devices, power storage devices, storage devices, imaging devices, processors, electronic devices It is suitable for use in various semiconductor devices such as electronic equipment.

[0195] <Method for manufacturing semiconductor device> A method for manufacturing a semiconductor device including the transistor 10 according to one embodiment of the present invention will be described below. An example of this will be described with reference to FIGS. 5 to 10. (A) is a top view of a semiconductor device having a transistor 10. (B) of each figure is a (A) of each figure is a cross-sectional view of the portion indicated by the dashed line A1-A2. , and (A) of each figure is a cross-sectional view of the portion indicated by the dashed line A3-A4. In a manufacturing method of a semiconductor device having a transistor 10, For the specific materials of each component (substrate, insulator, conductor, oxide, etc.), The contents explained in "Components of the Body Device" can be taken into consideration.

[0196] First, a substrate (not shown) is prepared.

[0197] Next, the insulator 100 is formed on the substrate by sputtering. method, chemical vapor deposition (CVD) method , molecular beam epitaxy (MBE) method, Pulsed Laser Deposition (PLD) method, This should be done using ALD (Atomic Layer Deposition) or similar methods. can be done.

[0198] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be classified into the VD method, the photo CVD method, and the photo CVD method. Depending on the source gas used, there are two methods: metal CVD (MCVD), organic metal CVD (C), and VD (MOCVD: Metal Organic CVD) method.

[0199] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0200] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with few defects can be produced. is obtained.

[0201] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases, this is preferable.

[0202] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, any composition can be obtained by adjusting the flow rate ratio of the source gases. In addition, for example, in the CVD method and the ALD method, By changing the flow rate ratio of the source gases, it is possible to form a film with a continuously changing composition. When forming a film while changing the flow rate ratio of the source gases, it is possible to form the film using a plurality of film forming chambers. The time required for film formation is reduced because there is no need for transport or pressure adjustment, as is the case with film formation. Therefore, the productivity of the semiconductor device can be improved in some cases. do.

[0203] In this embodiment, the insulator 100 is formed by depositing silicon oxide by the CVD method. As the insulator 100, for example, silicon oxynitride may be used in addition to silicon oxide. Good too.

[0204] Next, the insulator 102 is formed on the insulator 100. The insulator 102 is formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is deposited by sputtering as the insulator 102. The insulator 102 may have a multilayer structure. For example, the insulator 102 may be formed by a sputtering method. Then, an aluminum oxide film is formed on the aluminum oxide by the ALD method. Alternatively, aluminum oxide may be formed by the ALD method. Then, an aluminum oxide film is formed on the aluminum oxide by a sputtering method. The structure may also be used.

[0205] Next, the insulator 105 is formed on the insulator 102. The insulator 105 is formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 105 by the CVD method. As the insulator 105, other than silicon oxide, for example, silicon oxynitride may be used. good.

[0206] Next, an opening is formed in the insulator 105, reaching the insulator 102. Here, the opening is, for example, For example, grooves and slits are also included. Also, the area where an opening is formed is referred to as an opening. The opening may be formed by wet etching, but dry etching is also preferable. Insulator 102 is preferably formed by etching insulator 105. An insulator that functions as an etching stopper film when etching is performed to form an opening is selected. For example, when a silicon oxide film is used as the insulator 105 for forming the opening, The insulating layer 102 is preferably made of a silicon nitride film, an aluminum oxide film, or a hafnium oxide film. stomach.

[0207] After the opening is formed, a conductor that will become the conductor 185 is formed. A conductor 185a (not shown) having a function of suppressing the permeation of electrons, and a conductive material 185b (not shown) It is preferable that the conductive layer 185 has a laminated structure including a conductive material 185b (not shown) having a higher conductivity than the conductive material 185a. I wish.

[0208] The conductor that becomes the conductor 185a includes a conductive material that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. may be used. Or, tantalum, tungsten, titanium, molybdenum, aluminum, copper, The conductive material 185a can be a laminated film of a molybdenum-tungsten alloy. The film formation of the body is performed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done.

[0209] In this embodiment, the conductor 185a is formed by sputtering nitride. A film of titanium nitride laminated on tantalum chloride or tantalum nitride is formed. By using such a metal nitride as the conductor a, the conductor 18 described later can be Even if a metal that easily diffuses, such as copper, is used for the conductive material 185b, the metal will not diffuse out of the conductive material 185a. This can prevent this.

[0210] Next, a film of a conductor that will become the conductor 185b is formed on the conductor that will become the conductor 185a. The conductive film that becomes the conductive body 185b can be formed by a sputtering method, a CVD method, an MBE method, or a PLD method. In this embodiment, the conductor 185b is formed by the deposition of a conductive material. As the conductor, a film of a low resistance conductive material such as copper is formed.

[0211] Next, chemical mechanical polishing (CMP) By performing the ion implantation process, the conductor that becomes the conductor 185a and the conductor that becomes the conductor 185b are formed. A portion of the conductor 105 is removed to expose the insulator 105. As a result, the conductor 105 is only present in the opening. The conductor that will become 85a and the conductor that will become 185b remain. Therefore, it is possible to form a conductor 185 that is flat and includes conductors 185a and 185b. (See FIG. 5.) It should be noted that the CMP process may remove a part of the insulator 105. There is a match.

[0212] Next, the insulator 110 is formed on the insulator 105 and the conductor 185. The film is formed by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is deposited by the CVD method as the insulator 110. In addition to silicon oxide, the insulator 110 may be, for example, silicon oxynitride. Recon may also be used.

[0213] Here, a first heat treatment may be performed. The first heat treatment is performed at a temperature of 250° C. or higher for 6 hours. The first heat treatment may be performed at a temperature of 50° C. or less. It is preferable to carry out the treatment in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under nitrogen gas. Or, after heat treatment in an inert gas atmosphere, an oxidizing gas is added for 1 minute to compensate for the oxygen that has been released. The heat treatment may be performed in an atmosphere containing 0 ppm or more, 1% or more, or 10% or more. The heat treatment reduces impurities such as hydrogen and water contained in the insulators 110 and 105. Alternatively, in the first heat treatment, a plasma containing oxygen can be used under reduced pressure. The oxygen-containing plasma treatment may be, for example, a high-density plasma treatment using microwaves. It is preferable to use a device having a power source for generating plasma. Alternatively, RF ( The plasma may have a power source that applies high-density plasma. By applying RF to the substrate side, high density oxygen radicals can be generated. The oxygen radicals generated by the high density plasma are efficiently absorbed by the insulator 110 and the insulator 111. Alternatively, this apparatus can be used to perform plasma treatment containing an inert gas. After this, a plasma treatment containing oxygen may be performed to compensate for the desorbed oxygen.

[0214] Next, an opening is formed in the insulator 110, reaching the conductor 185. The opening is formed by wet etching. Although etching may be used, dry etching is preferred for fine processing. stomach.

[0215] After the opening is formed, a conductor that will become the conductor 190 is formed. A conductor 190a (not shown) having a function of suppressing the permeation of electrons, and a conductive material 190b having a conductivity lower than that It is preferable that the insulating layer 190 has a laminated structure including a highly conductive material 190b (not shown).

[0216] The conductor that becomes the conductor 190a includes a conductive material that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. may be used. Or, tantalum, tungsten, titanium, molybdenum, aluminum, copper, The conductive material 190a can be a laminated film of a molybdenum-tungsten alloy. The film formation of the body is performed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done.

[0217] In this embodiment, the conductor 190a is formed by sputtering nitride. A tantalum chloride film is formed.

[0218] Next, a conductor that will become the conductor 190b is formed as a film on the conductor that will become the conductor 190a. The conductive film may be formed by a method such as sputtering, CVD, MBE, PLD, or ALD. This can be done using, for example.

[0219] In this embodiment, titanium nitride is deposited by the ALD method as the conductor that becomes the conductor 190b. A film of titanium nitride is formed, and then a film of tungsten is formed on the titanium nitride by the CVD method.

[0220] Next, a CMP process is performed to form a conductor that will become the conductor 190a and a conductor 190b. The portion of the conductor that will become the opening is removed to expose the insulator 110. As a result, the conductive material is left only in the opening. The conductor that will become the conductor 190a and the conductor that will become the conductor 190b remain. Forming a conductor 190 having a flat upper surface and consisting of conductors 190a and 190b (See FIG. 5.) Note that the CMP process removes a part of the insulator 110. This may be the case.

[0221] Next, the conductor 120a is formed over the insulator 110 and the conductor 190. The film is formed by sputtering, CVD, MBE, PLD, ALD, or the like. The conductor 120a may be made of, for example, tantalum nitride, tungsten, or nitride. Alternatively, a conductor such as titanium dioxide can be used. Titanium nitride, tantalum nitride, or the like, which has the function of suppressing oxygen permeation, is added to the tungsten. A conductive film may be formed. By using this configuration, the conductive material 120a is Oxygen contamination can oxidize tungsten, preventing the electrical resistance from increasing. can.

[0222] Alternatively, the conductor 120a may be made of a conductive oxide, such as indium tin oxide ( ITO (Indium Tin Oxide), indium oxide containing tungsten oxide Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide Indium tin oxide containing titanium oxide, indium zinc oxide, silicon-doped indium Indium tin oxide or nitrogen-containing indium gallium zinc oxide is formed into a film, and the oxide is On top are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, and molyb. Density, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zinc Materials containing one or more metal elements selected from the group consisting of arsenic, beryllium, indium, etc., or Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, Alternatively, a film of silicide such as nickel silicide may be formed.

[0223] The oxide absorbs hydrogen in the oxide 150 and captures hydrogen diffusing from the outside. This may improve the electrical characteristics and reliability of the transistor 10. Alternatively, titanium may be used in place of the oxide to provide the same function.

[0224] In this embodiment, tungsten is deposited by sputtering as the conductor 120a. A film is formed.

[0225] Next, the insulator 130a is formed on the conductor 120a. This can be done using a deposition method, CVD method, MBE method, PLD method, ALD method, or the like. In this embodiment, the insulator 130a is formed by depositing silicon oxide by the CVD method. In addition to silicon oxide, the insulator 130a may be made of, for example, silicon oxynitride. may also be used.

[0226] Here, a second heat treatment may be performed. The second heat treatment may be performed under the same conditions as the first heat treatment. The heat treatment can remove impurities such as hydrogen and water contained in the insulator 130a. It is possible to reduce impurities and to supply oxygen into the insulator 130a. .

[0227] Alternatively, an ion implantation method in which ionized source gas is mass-separated and added, or an ionized Plasma immersion ion doping is an ion doping method that adds raw material gases without mass separation. Oxygen may be supplied into the insulator 130a by implantation or the like.

[0228] The insulator 130a contains excess oxygen by the above-mentioned heat treatment or ion implantation method. The excess oxygen can be supplied to the oxide 150 by a subsequent heat treatment or the like, The electrical properties and reliability of transistor 10 may be improved.

[0229] Next, a conductor 140a is formed on the insulator 130a (see FIG. 6). The film is formed by sputtering, CVD, MBE, PLD, ALD, or the like. The conductor 140a may be made of, for example, tantalum nitride, tungsten, or nitride. Conductors such as titanium dioxide can be used, or for example titanium nitride or tantalum nitride. A conductor having the function of suppressing oxygen permeation, such as tungsten, is formed on the conductor. By adopting such a configuration, the conductor 140a can be prevented from being mixed in from the underside thereof. This can prevent tungsten from being oxidized by oxygen and increasing the electrical resistance.

[0230] Alternatively, the conductor 140a may be aluminum, chromium, copper, silver, gold, platinum, tantalum, Nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese Metal elements selected from the group consisting of magnesium, zirconium, beryllium, and indium or polycrystalline silicon containing impurity elements such as phosphorus. A highly conductive semiconductor, silicide such as nickel silicide, is deposited on top of this. , conductive oxides, such as indium tin oxide (ITO) Indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium with titanium oxide Tin oxide, indium zinc oxide, silicon-doped indium tin oxide, or nitrogen-doped Alternatively, a film of indium gallium zinc oxide containing indium gallium zinc oxide may be formed.

[0231] The oxide absorbs hydrogen in the oxide 150 and captures hydrogen diffusing from the outside. This may improve the electrical characteristics and reliability of the transistor 10. Alternatively, titanium may be used in place of the oxide to provide the same function.

[0232] In this embodiment, tungsten is deposited by sputtering as the conductor 140a. A film is formed.

[0233] Next, the conductor 120a, the insulator 130a, and the conductor 140a is processed to form a conductor on the insulator 110 so as to have an area overlapping with the conductor 190. Then, a metal layer 120b, an insulator 130b, and a conductor 140b are formed (see FIG. 7). For this, dry etching or wet etching can be used, but dry etching is particularly preferred. The etching method is preferable because it is suitable for processing fine shapes. Some of it may be removed.

[0234] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the resist pattern in the developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. It can be processed into the desired shape. For example, KrF excimer laser light, ArF excimer Resist is removed using laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. An immersion technique may be used in which the substrate is exposed to a liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. When using this method, the above-mentioned resist exposure mask is not required because the pattern is drawn directly on the resist. The resist mask is used for dry etching such as ashing. Wet etching is performed, and wet etching is performed after dry etching. or by wet etching followed by dry etching. It is possible.

[0235] In place of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that will be the hard mask material is formed on the conductor 140a. A hard mask is formed on the conductive film, a resist mask is formed thereon, and the hard mask material is etched. A hard mask having a desired shape can be formed by the above steps. The etching of the conductive material 140a and the conductive material 140b may be performed after removing the resist mask. Alternatively, the resist mask may be left in place during etching. The edges of the conductor 120a, the insulator 130a, and the conductor 140a may disappear. After the etching, the hard mask may be removed by etching. If the material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to use a hard mask. There's no need to remove it.

[0236] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate electrodes. A configuration in which a plurality of different high frequency power supplies are applied to the electrodes may also be used. Alternatively, a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a dryer having a high density plasma source may be used. A dry etching apparatus having a high density plasma source can be used. For example, inductively coupled plasma (ICP) A laser etching device or the like can be used.

[0237] In addition, by performing the above-mentioned dry etching or the like, the etching gas or the like may cause The resulting impurities are deposited on the surfaces of the conductor 120b, the insulator 130b, and the conductor 140b. Impurities such as fluorine or chlorine may adhere to or diffuse into the interior. do.

[0238] In order to remove the above-mentioned impurities, cleaning may be carried out. Wet cleaning using a plasma or heat treatment. The above cleaning methods may be combined as appropriate.

[0239] For wet cleaning, oxalic acid, phosphoric acid, or hydrofluoric acid is diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be used. Cleaning may also be performed.

[0240] Next, an insulating layer is formed on the insulator 110, the conductor 120b, the insulator 130b, and the conductor 140b. The insulator 175 is formed by a method such as a sputtering method, a CVD method, an MBE method, or the like. This can be done by using a PLD method, an ALD method, or the like. As the insulator 175, a silicon oxide film is formed by the CVD method. Other than silicon nitride, for example, silicon oxynitride may be used.

[0241] Next, a portion of the insulator 175 is removed to flatten the upper surface of the insulator 175 (FIG. 8). (See reference 1.) The planarization can be performed by CMP processing, dry etching processing, or the like. In this embodiment, the upper surface of the insulator 175 is planarized by CMP. The upper surface of the insulator 175 after treatment is preferably located above the upper surface of the conductor 140b. If the top surface of the insulator 175 after deposition is flat, the above-described flattening process is not required. There are cases where this is not necessary.

[0242] Here, a third heat treatment may be performed. The third heat treatment is performed under the same conditions as the first heat treatment. By this heat treatment, impurities such as hydrogen and water contained in the insulator 175 can be removed. Furthermore, oxygen can be supplied into the insulator 175.

[0243] Next, the insulator 175, the conductor 140b, the insulator 130b, and the conductor 120b are lithographically removed. The opening 145 is formed by a roughing method and reaches the top surface of the insulator 110. Then, a conductive material 130 and a conductive material 140 are formed (see FIG. 9). The exposure is performed by using, for example, KrF excimer laser light or ArF excimer laser light through a mask. The process may be carried out using light, EUV light, or the like, or by using an immersion technique. This is a method of drawing patterns directly onto a resist using an electron beam or ion beam without using a mask. Exposure using electron beams or ion beams is more effective than exposure using light as described above. Since a fine pattern can be drawn on the resist, it is suitable for fine processing. In the case of the resist exposure, an electron beam is used.

[0244] Etching processes in lithography include dry etching and wet etching. In this embodiment, the resist etching using the electron beam described above can be used. After the exposure and development, the insulator 175, the conductor 140b, and The insulator 130b and the conductor 120b are etched. The opening 145 thus formed has an inner wall (side surface) formed substantially perpendicular to the substrate surface. It is preferable that the inner wall (side surface) of the opening 145 is formed at an angle close to perpendicular to the substrate surface. The smaller the etching, the more miniaturized the transistor 10 can be. This may result in removal of a portion of the insulator 110.

[0245] Next, an oxide film that becomes the oxide 150 is formed on the inner wall of the opening 145 and on the insulator 175. The oxide film that becomes Oxide 150 can be formed by sputtering, CVD, MBE, PLD, etc. The deposition can be carried out by using a method such as an ALD method.

[0246] For example, when the oxide 150 is formed by sputtering, Oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the oxygen content of the oxide, the excess oxygen in the oxide film can be increased. In addition, when the oxide is formed into a film by sputtering, the above-mentioned In- A M-Zn oxide target can be used.

[0247] In addition, when the oxide 150 is formed by sputtering, The percentage of oxygen contained in the ring gas is 1% or more and 30% or less, preferably 5% or more and 20% or less. When the film is formed as an oxygen-deficient metal oxide, the oxygen-deficient metal oxide is formed. The transistor used in the channel forming region can obtain a relatively high field effect mobility.

[0248] In this embodiment, the oxide 150 is formed by sputtering. An In-Ga-Zn oxide target with an atomic ratio of n:Ga:Zn=4:2:4.1 was used. The oxide 150 is formed by appropriately selecting the film forming conditions and atomic ratio. In this way, the oxide 150 of the transistor 10 can be formed to have the desired characteristics.

[0249] As mentioned above, the oxide 150 may have a laminated structure of two or more layers. The oxide 150 is made up of an oxide 150a (not shown) and an oxide 150b (not shown) from below. In the case of a two-layer structure consisting of oxide 150a, the oxide to be formed is formed by sputtering. By this method, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=4:2:4.1 was obtained. Using a target, the oxygen content of the sputtering gas is 1% or more and 30% or less. Preferably, the film is formed with a concentration of 5% to 20%. The compound was prepared by sputtering with an atomic ratio of In:Ga:Zn=1:3:4. -Ga-Zn oxide target was used, and the oxygen ratio in the sputtering gas was set to 7. The film may be formed at 0% or more, preferably 80% or more, and more preferably 100%. When the object 150 has this configuration, the oxide 150a mainly functions as a channel of the transistor 10. By configuring the oxide 150 in this manner, the oxide 150b and the The oxygen contained in the oxide to be formed is supplied to the oxide to be formed into the oxide 150a by a fourth heat treatment or the like. Note that the fourth heat treatment can be performed after the oxide film that becomes the oxide 150b is formed. The heat treatment conditions are 400°C in a nitrogen atmosphere for 1 hour. After the above treatment, the material is treated in an oxygen atmosphere at 400°C for 1 hour. is preferred.

[0250] Alternatively, for example, the oxide 150 may be formed by stacking oxide 150a (not shown) and oxide 150b from below. 50b (not shown), the oxide that becomes oxide 150a is By sputtering, In-Ga- Using a Zn oxide target, the oxygen content of the sputtering gas is 70% or more. The film may be formed with a film thickness of preferably 80% or more, more preferably 100%. The oxide to be the object 150b is prepared by sputtering In:Ga:Zn=4:2:4 Using an In-Ga-Zn oxide target with an atomic ratio of 0.1, the sputtering gas The film is formed with the oxygen content set to 1% or more and 30% or less, preferably 5% or more and 20% or less. When the oxide 150 has this structure, the oxide 150b mainly functions as a transistor. The oxide 150 functions as a channel forming region of the gate electrode 10. The oxygen contained in the oxide that will become the oxide 150a is converted into the oxide 150b by a fourth heat treatment or the like. The oxide can be provided as follows.

[0251] The oxide 150 is made up of oxide 150a, oxide 150b, and oxide 150c from the bottom. In the case where the oxide 150a has a three-layer structure consisting of the oxide 150b and the oxide 150c (not shown), The oxide film 150b is formed under the above conditions, and the oxide film 150c is formed by sputtering. By using the talc deposition method, In-Ga-Zn with an atomic ratio of In:Ga:Zn=4:2:4.1 was obtained. Using an n oxide target, the proportion of oxygen in the sputtering gas is 70% or more, Preferably, the film is formed at 80% or more, more preferably 100%. After the oxide film that becomes the oxide 150b is formed, a fourth heat treatment is preferably performed. When the object 150 has this configuration, the oxide 150b is mainly the channel of the transistor 10. By configuring the oxide 150 in this manner, the oxide 150a and the In addition to the oxygen contained in the oxide that becomes oxide 150c, the oxygen contained in the oxide that becomes oxide 150c also It can be supplied to an oxide that becomes oxide 150b by heat treatment or the like.

[0252] Next, an insulator that will become the insulator 160 is formed on the oxide that will become the oxide 150. The insulator film 160 is formed by sputtering, CVD, MBE, PLD, or This can be done by using an ALD method or the like. In this embodiment, The insulator 160 is made of silicon oxide by CVD. For example, silicon oxynitride may be used instead of silicon oxide.

[0253] Here, it is preferable to perform a fifth heat treatment. The fifth heat treatment is a treatment similar to the fourth heat treatment. The heat treatment can be performed under the following conditions. When the oxide has a three-layer structure, the oxygen contained in the oxide (which becomes oxide 150c) is The oxide that becomes oxide 150 (if the oxide has a three-layer structure, the oxide that becomes oxide 150b) can be supplied.

[0254] Next, a conductor that will become the conductor 170 is formed as a film on the insulator that will become the insulator 160. The conductive film 170 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or This can be done by using an ALD method or the like. In this embodiment, the conductor that becomes the conductor 170 is After forming a titanium nitride film by the ALD method, a tungsten film was further formed by the CVD method. In the conductor that becomes the conductor 170, the thickness of the titanium nitride is greater than that of the titanium nitride. It is preferable that the titanium nitride film is thicker than the insulator 160. A film is formed along the inner wall of the opening 145 via an insulator, and the remaining space in the opening 145 is filled with a tongue. It is preferable to form a film so as to fill the conductor 170 with stainless steel. By forming a film of titanium nitride and tungsten, a conductor 170 having a laminated structure of titanium nitride and tungsten can be formed later. It can be formed.

[0255] Next, the conductor 170, the insulator 160, and the conductor 170 are welded together until the top surface of the insulator 175 is exposed. The upper surfaces of the insulator 160 and the oxide 150 are polished to remove the conductor 170 and the insulator 160. 0 and oxide 150 are formed (see FIG. 10). The polishing is performed by CMP processing or the like. In addition, the conductive material 170 is formed by cutting the insulating material 175 until the upper surface of the insulating material 175 is exposed. The top surface of the insulating layer, the insulating layer that will become insulating layer 160, and the oxide that will become oxide 150 are dry etched. By etching, the conductor 170, the insulator 160, and the oxide 150 may be formed. In this embodiment, the conductor 170, the insulator 160, and the oxide 15 are removed by the CMP process. By this CMP process, the height of the top surface of the insulator 175 and the oxide 150 are formed. , the height of the top surfaces of the insulator 160 and the conductor 170 can be formed to be approximately the same (FIG. 10.) Note that the CMP process may remove a portion of the insulator 175. be.

[0256] Next, the top surface of the insulator 175, the oxide 150, the insulator 160, and the top surface of the conductor 170 Insulator 176 is placed on the insulator 176, insulator 178 is placed on the insulator 178, and insulator 180 is placed on the insulator 178. The insulators 176, 178, and 180 are deposited by sputtering. The deposition can be performed by a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 176 by the CVD method. The insulator 178 is formed by sputtering aluminum oxide. As the insulator 176 or the insulator 10, a silicon oxide film is formed by the CVD method. 80 may be made of, for example, silicon oxynitride other than silicon oxide. The body 178 may be made of, for example, silicon nitride or hafnium oxide, other than aluminum oxide. A system may also be used.

[0257] Next, conductor 14 is applied to insulator 180, insulator 178, insulator 176, and insulator 175. The opening may be formed by wet etching, but the driver The use of an etching method is preferable for fine processing.

[0258] After the opening is formed, a conductor that will become the conductor 195 is formed. A conductor 195a (not shown) having a function of suppressing the transmission of electrons and a conductive material 195b. It is preferable that the conductive layer 195 has a laminated structure including a conductive material 195b (not shown) having a higher conductivity than the conductive material 195a. Desirable.

[0259] The conductor that becomes the conductor 195a includes a conductive material that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. may be used. Or, tantalum, tungsten, titanium, molybdenum, aluminum, copper, The conductive material 195a can be a laminated film of a molybdenum-tungsten alloy. The film formation of the body is performed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done.

[0260] In this embodiment, the conductor 195a is formed by sputtering nitride. A tantalum chloride film is formed.

[0261] Next, a conductor that will become the conductor 195b is formed as a film on the conductor that will become the conductor 195a. The conductive film may be formed by a method such as sputtering, CVD, MBE, PLD, or ALD. This can be done using, for example.

[0262] In this embodiment, titanium nitride is deposited by the ALD method as the conductor that becomes the conductor 195b. A film of titanium nitride is formed, and then a film of tungsten is formed on the titanium nitride by the CVD method.

[0263] Next, a CMP process is performed to form a conductor that will become the conductor 195a and a conductor 195b. The portion of the conductor that will become the opening is removed to expose the insulator 180. As a result, the conductor is only left in the opening. The conductor that will become the conductor 195a and the conductor that will become the conductor 195b remain. Forming a conductor 195 having a flat top surface and consisting of conductors 195a and 195b It should be noted that the CMP process may remove a portion of the insulator 180.

[0264] Next, a conductor that will become the conductor 200 is formed on the insulator 180 and the conductor 195. The conductor 200 is made of a conductor 200a (not shown) having a function of suppressing oxygen permeation. ) and a conductor 200b (not shown) having a higher conductivity than the conductor 200a. It is preferable that the laminated structure be used.

[0265] The conductor that becomes the conductor 200a contains a conductive material that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. may be used. Or, tantalum, tungsten, titanium, molybdenum, aluminum, copper, The conductive material 200a can be a laminated film of a molybdenum-tungsten alloy. The film formation of the body is performed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done.

[0266] In this embodiment, the conductor 200a is formed by sputtering a nitride film. A film of titanium nitride laminated on tantalum nitride or tantalum nitride is formed. By using such a metal nitride as the conductor a, the conductor 20 Even if a metal that easily diffuses, such as copper, is used for conductor 200a, conductor 195, the metal Diffusion into the transistor 10 can be prevented through

[0267] Next, a film of a conductor that will become the conductor 200b is formed on the conductor that will become the conductor 200a. The conductive film that becomes the conductive body 200b can be formed by a sputtering method, a CVD method, an MBE method, or a PLD method. In this embodiment, the conductive material 200b is formed by the deposition of a conductive material 200b. As the conductor, a film of a low resistance conductive material such as copper is formed.

[0268] Next, the conductive material 195 is formed by using a lithography method or the like so as to have an area overlapping the conductive material 195. The conductor that will become the conductor 200b and the conductor that will become the conductor 200a are processed, and the conductors are formed on the insulator 180. The conductor 200 can be formed by the conductor 200a and the conductor 200b. Note that this processing may result in the removal of a portion of the insulator 180.

[0269] Through the above steps, a semiconductor device including the transistor 10 according to one embodiment of the present invention can be manufactured. This can be done (see Figure 1).

[0270] As described above, one embodiment of the present invention provides a semiconductor device that can be miniaturized or highly integrated. Alternatively, according to one embodiment of the present invention, it is possible to manufacture the semiconductor device by a lithography method. It is difficult to fabricate multiple transistors with channel lengths of several nanometers or less within the substrate surface. According to one aspect of the present invention, the channel Although the length is small, the short channel effect is not easily manifested, and the transistor has good electrical characteristics. In addition, in one embodiment of the present invention, a semiconductor device having a channel length In addition, semiconductor devices with transistors with minute element sizes including wiring and plugs Alternatively, according to one embodiment of the present invention, a semiconductor having good electrical characteristics can be manufactured. Alternatively, according to one embodiment of the present invention, a transistor with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device having an on-state current can be provided. It is possible to provide a semiconductor device having a transistor with a large current. According to the present invention, a semiconductor device having small variations in electrical characteristics between elements within a substrate surface is provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. Cut.

[0271] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0272] (Embodiment 2) In this embodiment, one mode of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. do.

[0273] [Storage device] The memory device shown in FIG. 11 includes a transistor 3000, a transistor 2000, and a capacitor. It has 1,000 children.

[0274] The transistor 2000 is a transistor in which a channel is formed in a semiconductor layer having a metal oxide. Since the off-state current of the transistor 2000 is small, By using this in a storage device, it is possible to retain stored content for a long period of time. Therefore, no refresh operation is required, or the frequency of refresh operation is extremely low. Therefore, the power consumption of the storage device can be reduced sufficiently.

[0275] In FIG. 11, a first wiring 3001 is electrically connected to the source of a transistor 3000. The second wiring 3002 is electrically connected to the drain of the transistor 3000. The third wiring 3003 is connected to one of the source and drain of the transistor 2000. The fourth wiring 3004 is electrically connected to the gate of the transistor 2000. The gate of the transistor 3000 and the gate of the transistor 2000 are connected to each other. The other of the source and the drain is electrically connected to one of the electrodes of the capacitor 1000. The wiring 3005 is electrically connected to the other electrode of the capacitor 1000 .

[0276] The memory device shown in FIG. 11 has a characteristic that the potential of the gate of the transistor 3000 can be maintained. By having this, it is possible to write, hold, and read information as shown below.

[0277] Writing and holding of data will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 2000 is set to a potential at which it becomes conductive, thereby making the transistor 2000 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3000 and the capacitor The signal is applied to a node FG electrically connected to one of the electrodes of the element 1000. A predetermined charge is applied to the gate of the transistor 3000 (write). The charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) ) is given. After that, the potential of the fourth wiring 3004 is The potential is set to a level at which the transistor 2000 is in a non-conducting state, thereby making the transistor 2000 in a non-conducting state. As a result, charges are held (retained) at the node FG.

[0278] When the off-state current of the transistor 2000 is small, the charge of the node FG is Retained.

[0279] Next, reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the second wiring The line 3002 takes on a potential corresponding to the amount of charge held in the node FG. If the transistor 3000 is an n-channel type, a high level voltage is applied to the gate of the transistor 3000. The apparent threshold voltage V under load th_H The gate of the transistor 3000 The apparent threshold voltage V when a low-level charge is applied to the gate th_L Lower Here, the apparent threshold voltage is the voltage at which the transistor 3000 is turned on. Therefore, the fifth wiring 3005 is a potential required for the fifth wiring 3005 to The potential of 3005 is V th_H and V th_L By setting the potential V0 between For example, in a write operation, a high level is applied to node FG. When a charge is applied, the potential of the fifth wiring 3005 becomes V0 (>V th_H )and On the other hand, if a low level charge is applied to the node FG, the transistor 3000 is in a conductive state. is given, the potential of the fifth wiring 3005 becomes V0( <V th_L ) Therefore, the second wiring 3002 By determining the potential, the data held in the node FG can be read out.

[0280] <Storage device structure> As shown in FIG. 11, a memory device according to one embodiment of the present invention includes a transistor 3000, a transistor The transistor 2000 includes a transistor 30 and a capacitor 1000. 1000, the capacitor element 1000 is provided above the transistor 3000 and the transistor 2 It is located above 000.

[0281] The transistor 3000 is provided on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate A semiconductor region 313 consisting of a portion of the plate 311 and functioning as a source region or a drain region. The resistivity of the conductive film 314 is low, and the resistivity of the conductive film 314 is low.

[0282] The transistor 3000 can be either a p-channel or an n-channel type.

[0283] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Alternatively, the insulating layer 12 may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (gallium aluminum arsenide), or the like. It uses silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 30 may be formed by using GaAs and GaAlAs. 00 stands for HEMT (High Electron Mobility Transistor) r) can also be used.

[0284] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0285] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. a semiconductor material such as silicon containing an element or an element that imparts p-type conductivity, such as boron; A conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0286] In addition, since the work function is determined by the material of the conductor, by changing the material of the conductor, The Vth of the transistor can be adjusted. Specifically, titanium nitride or nitride is used as the conductor. It is preferable to use a material such as tantalum. For this reason, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor. It is preferable to use tungsten, especially from the viewpoint of heat resistance.

[0287] The transistor 3000 shown in FIG. 11 is an example, and the structure is not limited to this. Appropriate transistors may be used depending on the configuration and driving method.

[0288] Covering the transistor 3000 are an insulator 320, an insulator 322, an insulator 324, and an insulator 326. The edge members 326 are stacked in order.

[0289] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0290] The insulator 322 is formed to cover a step formed by the transistor 3000 and the like provided below. For example, the top surface of the insulator 322 may have a function as a planarizing film. In order to improve the flatness, the surface may be planarized by a CMP process or the like.

[0291] The insulator 324 is also provided with a substrate 311 or a transistor 3000 or the like. A film with barrier properties that prevents hydrogen and impurities from diffusing into the area where the star 2000 is provided. It is preferable to use

[0292] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having a metal oxide such as the transistor 2000 can be used. The diffusion of hydrogen into semiconductor elements can cause deterioration of the electrical characteristics of the semiconductor elements. Therefore, the diffusion of hydrogen between the transistor 2000 and the transistor 3000 is suppressed. It is preferable to use a film that suppresses hydrogen diffusion. Specifically, a film that suppresses hydrogen desorption A small amount of film is used.

[0293] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0294] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulating body 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the body 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. can be reduced.

[0295] The insulators 320, 322, 324, and 326 are also provided with capacitive elements. 1000 or the conductor 328 electrically connected to the transistor 2000, and the conductor 33 0 and the like are embedded. The conductors 328 and 330 are plugs or wiring. In addition, the conductor that functions as a plug or wiring has a plurality of structures. In addition, in this specification and the like, the wiring and the wiring The plug electrically connecting the conductor and the wiring may be an integral part. In some cases, the conductor functions as a plug, and in other cases, a part of the conductor functions as a plug.

[0296] The materials for each plug and wiring (the conductor 328, the conductor 330, etc.) are metal materials. A conductive material such as an alloy material, a metal nitride material, or a metal oxide material is formed as a single layer or a laminate. High-melting materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a point material, and it is preferable to use tungsten. It is preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. This allows the wiring resistance to be reduced.

[0297] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. The conductors 328 and 330 can be formed using the same materials.

[0298] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. It is preferable to form a conductor 356 having a barrier property against hydrogen in the opening. With this configuration, the transistor 3000 and the transistor 2000 are separated by a barrier layer. This prevents hydrogen from diffusing from the transistor 3000 to the transistor 2000. It can be controlled.

[0299] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 3000 can be suppressed while maintaining the conductivity of the entire transistor. In this case, the tantalum nitride layer, which has a barrier property against hydrogen, acts as a barrier against hydrogen. It is preferable that the insulating material 350 has a structure in which the insulating material 350 is in contact with the insulating material 350.

[0300] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductors 328 and 330 can be formed using the same materials.

[0301] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. It is preferable to form a conductor 366 having a barrier property against hydrogen in the opening. With this configuration, the transistor 3000 and the transistor 2000 are separated by a barrier layer. This prevents hydrogen from diffusing from the transistor 3000 to the transistor 2000. It can be controlled.

[0302] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductors 328 and 330 can be formed using the same materials.

[0303] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. It is preferable to form a conductor 376 having a barrier property against hydrogen in the opening. With this configuration, the transistor 3000 and the transistor 2000 are separated by a barrier layer. This prevents hydrogen from diffusing from the transistor 3000 to the transistor 2000. It can be controlled.

[0304] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, and 384. The conductor 386 functions as a plug or wiring. The conductors 328 and 330 can be formed using the same materials.

[0305] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. It is preferable to form a conductor 386 having a barrier property against hydrogen in the opening. With this configuration, the transistor 3000 and the transistor 2000 are separated by a barrier layer. This prevents hydrogen from diffusing from the transistor 3000 to the transistor 2000. It can be controlled.

[0306] On the insulator 384 and the conductor 386, the insulator 210, the insulator 100, and the insulator 102 are disposed. The insulator 210, the insulator 100, and the insulator 105 are stacked in this order. Either the insulator 102 or the insulator 105 is made of a film having a barrier property against oxygen or hydrogen. It is preferable that

[0307] For example, the insulator 210 and the insulator 102 may include a substrate 311 or a transistor 300. Hydrogen and impurities diffuse from the region where transistor 0 is provided to the region where transistor 2000 is provided. Therefore, it is preferable to use a film having a barrier property that does not cause the insulator 324 to be broken down. Various materials can be used.

[0308] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, in a semiconductor element having a metal oxide such as a transistor 2000, The diffusion of hydrogen may deteriorate the electrical characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between transistor 2000 and transistor 3000. Specifically, the film that suppresses hydrogen diffusion is a film that has a small amount of hydrogen desorption. The membrane.

[0309] In addition, as a film having a barrier property against hydrogen, for example, the insulator 210 and the insulator 1 02 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0310] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. The membrane has a high blocking effect, preventing both impurities such as oxygen and water from passing through. Aluminum is a material that absorbs impurities such as hydrogen and water during and after the transistor manufacturing process. This can prevent the transistor 2000 from being contaminated with the Therefore, the release of oxygen from the oxide constituting the transistor 2 can be suppressed. Suitable for use as a protective film against 000.

[0311] For example, the insulator 100 and the insulator 105 are made of the same material as the insulator 320. In addition, by using a material with a relatively low dielectric constant for the insulator, For example, the parasitic capacitance between the insulator 100 and the insulator 105 can be reduced. As the insulating film, silicon oxide, silicon oxynitride, or the like can be used.

[0312] In addition, the insulators 210, 100, 102, and 105 are provided with conductors 2. 18, and a conductor (conductor 185) electrically connected to the transistor 2000 is embedded. Note that the conductor 218 is connected to the capacitor 1000 or the transistor 3000. The conductor 218 functions as a plug or wiring for electrical connection. , and can be formed using the same material as the conductor 330.

[0313] In particular, the insulator 210 and the conductor 218 in the region in contact with the insulator 102 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 3000 and the transistor 2000 are connected to a material having a barrier property against oxygen, hydrogen, and water. The layer that separates the transistors 3000 and 2000 can be reliably separated. This can suppress the diffusion of hydrogen.

[0314] A transistor 2000 is provided above the insulator 105 via an insulator 110. The structure of the transistor 2000 is the same as that of the semiconductor device described in the previous embodiment. The transistor 2000 shown in FIG. However, there is no limitation to this structure, and it is possible to use appropriate transistors depending on the circuit configuration and driving method. good.

[0315] Above the transistor 2000, an insulator 175, an insulator 176, and an insulator 178 are provided. establish.

[0316] The insulator 178 is preferably a film that has a barrier property against oxygen and hydrogen. Therefore, the insulator 178 can be made of the same material as the insulator 102. For example, The insulator 178 may be a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide. It is preferable to use

[0317] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. The membrane has a high blocking effect, preventing both impurities such as oxygen and water from passing through. Aluminum is a material that absorbs impurities such as hydrogen and water during and after the transistor manufacturing process. This can prevent the transistor 2000 from being contaminated with the Therefore, the release of oxygen from the oxide constituting the transistor 2 can be suppressed. Suitable for use as a protective film against 000.

[0318] In addition, an insulator 180 is provided on the insulator 178. The insulator 180 is The same material as that of 320 can be used. In addition, the insulator may be made of a material having a relatively low dielectric constant. By using an insulator, it is possible to reduce the parasitic capacitance that occurs between wiring. Silicon oxide, silicon oxynitride, or the like can be used as 80 .

[0319] Also, the insulators 110, 175, 176, 178, and 180 The conductive material 246, the conductive material 248, and the like are embedded in the conductive material 246, the conductive material 248, and the like.

[0320] The conductor 246 and the conductor 248 are the capacitor 1000, the transistor 2000, or the The conductive layer functions as a plug or wiring that is electrically connected to the transistor 3000. The conductor 246 and the conductor 248 are made of the same material as the conductor 328 and the conductor 330. It can be established.

[0321] A capacitor 1000 is provided above the transistor 2000. 00 has a conductor 1100, a conductor 1200, and an insulator 1300.

[0322] The conductor 112 may be provided over the conductor 246 and the conductor 248. 12 is electrically connected to the capacitor element 1000, the transistor 2000, or the transistor 3000. The conductor 1100 functions as a plug or wiring to be connected to the capacitor element 100. The conductor 112 and the conductor 1100 function as electrodes of the conductor 1100. It can be achieved.

[0323] The conductor 112 and the conductor 1100 may be made of molybdenum, titanium, tantalum, tungsten, or the like. metals containing elements selected from the group consisting of silicon, aluminum, copper, chromium, neodymium, and scandium; Or metal nitrides containing the above elements (tantalum nitride, titanium nitride, molybdenum nitride) Indium tin oxide, tungsten oxide, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Conductive materials such as indium tin oxide doped with silicon oxide can also be used. do.

[0324] In FIG. 11, the conductor 112 and the conductor 1100 are shown as having a single-layer structure. The present invention is not limited to this structure, and may be a laminated structure of two or more layers. For example, Conductors with barrier properties between highly conductive conductors and highly conductive conductors A highly adhesive conductor may be formed by using the above method.

[0325] Furthermore, an insulating film is formed on the conductor 112 and the conductor 1100 as a dielectric of the capacitor element 1000. An insulator 1300 is provided. The insulator 1300 may be made of, for example, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, nitride oxide Aluminum, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride The insulating layer may be formed as a single layer or a multilayer, and may be made of silicon nitride, hafnium nitride, or the like.

[0326] For example, if a material with high dielectric strength such as silicon oxynitride is used for the insulator 1300, This configuration improves the dielectric breakdown resistance of the capacitor 1000, Electrostatic damage can be suppressed.

[0327] The conductor 1200 is provided over the insulator 1300 so as to overlap with the conductor 1100. The conductor 1200 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive, can be used. It is preferable to use a conductive material, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures such as the above, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. Minium) or the like can be used.

[0328] An insulator 1500 is provided on the conductor 1200 and the insulator 1300. The insulator 1500 can be made of the same material as the insulator 320. 500 may function as a planarizing film that covers the underlying irregularities.

[0329] The above is a description of a configuration example of a memory device to which a semiconductor device according to one embodiment of the present invention is applied. By using this structure, a semiconductor device using a transistor having a metal oxide can be manufactured. In this case, it is possible to suppress fluctuations in electrical characteristics and improve reliability. It is possible to provide a transistor having a metal oxide with a large on-state current. It is possible to provide a transistor having a metal oxide with low current or low power consumption. Therefore, it is possible to provide a semiconductor device in which the above-mentioned problems are reduced.

[0330] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0331] (Embodiment 3) In this embodiment, a metal oxide according to one embodiment of the present invention will be described with reference to FIGS. 12 and 13. A transistor used in a channel formation region (hereinafter referred to as an OS transistor) and a capacitor As an example of a memory device to which the element is applied, NOSRAM will be described. AM (registered trademark) stands for "Nonvolatile Oxide Semiconductor or RAM" and is a R with gain cell type (2T type, 3T type) memory cells. In the following, we will refer to memory that uses OS transistors such as NOSRAM. The remote device may be called OS memory.

[0332] NOSRAM is a memory device that uses OS transistors in memory cells (hereinafter referred to as The OS memory is composed of at least a capacitive element and a This is a memory that has an OS transistor that controls the charging and discharging of the element. Since it is a transistor with a small off-state current, the OS memory has excellent retention characteristics and is nonvolatile. It can function as a harpoon.

[0333] < <nosram1600>> An example of the configuration of NOSRAM is shown in FIG. 12. NOSRAM 1600 shown in FIG. Cell array 1610, controller 1640, row driver 1650, column driver 1660 , and an output driver 1670. Note that the NOSRAM 1600 can store multiple data in one memory cell. It is a multi-level NOSRAM that stores value data.

[0334] The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, and a plurality of The word line RWL, a plurality of bit lines BL, and a plurality of source lines SL. is the write word line and word line RWL is the read word line. In 600, one memory cell 1611 stores 3-bit (8-value) data.

[0335] The controller 1640 controls the entire NOSRAM 1600 and outputs the data WDA Writes data to [31:0] and reads data from RDA[31:0]. Controller 1 640 is an external command signal (for example, a chip enable signal, a write enable signal, etc.). 16. The row driver 1650, the column driver 1660, and the output driver 1670 are connected to the output terminals 1671 and 1672. 670 control signals are generated.

[0336] The row driver 1650 has the function of selecting a row to access. has a row decoder 1651 and a word line driver 1652.

[0337] The column driver 1660 drives the source lines SL and bit lines BL. 0 is the column decoder 1661, the write driver 1662, and the DAC (digital-to-analog converter). It has a conversion circuit 1663.

[0338] The DAC1663 converts 3-bit digital data into an analog voltage. 3 converts the 32-bit data WDA[31:0] into an analog voltage every 3 bits. .

[0339] The write driver 1662 has a function of precharging the source line SL, A function for electrically floating a source line SL, a function for selecting a source line SL, and a function for selecting a source line SL. This function inputs the write voltage generated by the DAC1663 and precharges the bit line BL. and the function of electrically floating the bit line BL.

[0340] The output driver 1670 includes a selector 1671, an ADC (analog-to-digital conversion circuit), 1672 and an output buffer 1673. The selector 1671 selects the source line to be accessed. SL is selected and the voltage of the selected source line SL is sent to the ADC1672. 72 has the function of converting an analog voltage into 3-bit digital data. The voltage is converted into 3-bit data by the ADC 1672 and output to the output buffer 1673. holds the data output from the ADC1672.

[0341] <Memory cells 1611 to 1614> 13A is a circuit diagram showing a configuration example of the memory cell 1611. 1 is a 2T type gain cell, and the memory cell 1611 is connected to the word line WWL and the word line RWL. , a bit line BL, and a source line SL. The semiconductor memory device 100 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitance element C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a read transistor. The capacitance element is a transistor that is configured, for example, as a p-channel Si transistor. The capacitor C61 is a storage capacitor for holding the voltage of the node SN. The node SN is a data storage capacitor. This node corresponds to the gate of transistor MP61 in this example.

[0342] The write transistor of memory cell 1611 is composed of OS transistor MO61. Therefore, the NOSRAM 1600 can retain data for a long time.

[0343] In the example of FIG. 13(A), the bit line is a common bit line for writing and reading. As shown in FIG. 13(B), a write bit line WBL and a read bit line RBL are set. It is okay to do so.

[0344] 13C to 13E show other configuration examples of memory cells. 13(E) shows an example in which a write bit line and a read bit line are provided. As shown in FIG. 13A, a bit line shared by writing and reading may be provided.

[0345] The memory cell 1612 shown in FIG. 13C is a modified example of the memory cell 1611. The output transistor has been changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor. stomach.

[0346] The memory cell 1613 shown in FIG. 13(D) is a 3T-type gain cell, and is connected to the word line WWL , word line RWL, bit line WBL, bit line RBL, source line SL, and wiring PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, It has a transistor MP62, a transistor MP63, and a capacitance element C62. Transistor MO62 is a write transistor. Transistor MP62 is a read transistor. transistor MP61 is a select transistor.

[0347] The memory cell 1614 shown in FIG. 13(E) is a modified example of the memory cell 1613. The output transistor and the selection transistor are n-channel transistors (MN62, MN6 3). Transistors MN62 and MN63 are OS transistors. The transistor may be a silicon transistor or a silicon-based transistor.

[0348] The OS transistors provided in the memory cells 1611 to 1614 are bottom The transistor may be a gateless transistor or a bottom gate transistor. .

[0349] Since data is rewritten by charging and discharging the capacitance element C61, NOSRAM1600 Theoretically, there is no limit to the number of times it can be rewritten, and data can be written and read with low energy. It is also possible to retain data for a long time, so it is easy to refresh. The frequency can be reduced.

[0350] The semiconductor device shown in the above embodiment is a memory cell 1611, a memory cell 1612, and a memory When used in the cell 1613 and the memory cell 1614, the OS transistor MO61 and the OS transistor MO62 are Transistor MO62 is transistor 2000, transistor MP61, transistor The transistor 3000 can be used as the transistor MN62. Therefore, the area occupied by the memory device according to this embodiment can be reduced. Therefore, the unit surface of the memory device according to this embodiment can be further highly integrated. The storage capacity per product can be increased.

[0351] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0352] (Fourth embodiment) In this embodiment, an OS transistor according to one embodiment of the present invention will be described with reference to FIGS. 14 and 15. As an example of a storage device to which DOSRAM is applied, DOSRAM will be described. AM (registered trademark) stands for Dynamic Oxide Semiconductor RAM is an abbreviation for RAM, which is an RA with 1T (transistor) 1C (capacitance) type memory cells. DOSRAM, like NOSRAM, is also used for OS memory.

[0353] < <dosram1400>> An example of the configuration of the DOSRAM is shown in Figure 14. The DOSRAM 1400 shown in Figure 14 is roller 1405, row circuitry 1410, column circuitry 1415, memory cell and sense amplifier array 1420 (hereinafter referred to as the "MC-SA array 1420").

[0354] The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a 413, and sense amplifier driver circuit 1414. Column circuit 1415 includes a global sense amplifier. The global sense amplifier array 1416 and the input / output circuit 1417 are included. The MC-SA array 1416 includes a plurality of global sense amplifiers 1447. 20 denotes a memory cell array 1422, a sense amplifier array 1423, a global bit line It has a GBLL and a global bit line GBLR.

[0355] (MC-SA Array 1420) The MC-SA array 1420 connects the memory cell array 1422 to the sense amplifier array 142 3. The global bit line GBLL, the global bit line G The BLR is stacked on the memory cell array 1422. In the DOSRAM 1400, The bit line structure is a hierarchical bit line structure consisting of local bit lines and global bit lines. A linear structure is used.

[0356] The memory cell array 1422 is a local memory cell array of N (N is an integer of 2 or more). 1425 <0> to local memory cell array 1425 <n-1>FIG. 15(A ) shows an example of the configuration of the local memory cell array 1425. 425 includes a plurality of memory cells 1445, a plurality of word lines WL, a plurality of bit lines BLL, a plurality of In the example of FIG. 15A, the local memory cell array 142 The structure of 5 is an open bit line type, but it may also be a folded bit line type.

[0357] FIG. 15B shows an example of a circuit configuration of the memory cell 1445. The transistor MW1 has a capacitance element CS1 and a terminal B1. The gate of transistor MW1 is connected to the word line. The first terminal is electrically connected to the bit line, and the second terminal is electrically connected to the capacitor element CS1. The second terminal of the capacitance element CS1 is electrically connected to the first terminal of the capacitance element CS2. A constant potential (for example, a low power supply potential) is input to terminal B1.

[0358] The transistor MW1 may be a transistor having a bottom gate. If the transistor MW1 is a transistor with a bottom gate, for example, the transistor M The bottom gate of W1 is electrically connected to the gate, source, or drain of transistor MW1. A configuration in which they are connected may also be used.

[0359] The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> No To local sense amplifier array 1426 <n-1>A local sense amplifier array The switch array 1426 includes a switch array 1444 and a plurality of sense amplifiers 1446. The sense amplifier 1446 is electrically connected to the bit line pair. functions to precharge the bit line pair, amplify the potential difference between the bit line pair, and The switch array 1444 selects a pair of bit lines and holds the difference. It has the function of bringing the bit line pair and the global bit line pair into a conductive state.

[0360] Here, a bit line pair is a pair of two bit lines that are compared simultaneously by a sense amplifier. The global bit line pair is a pair of lines that are simultaneously compared by a global sense amplifier. A bit line pair is also called a pair of bit lines. and the global bit line pair can be called a pair of global bit lines. In the example, the bit line BLL and the bit line BLR form a bit line pair. The BLL and the global bit line GBLR form a global bit line pair. They are also referred to as a bit line pair (BLL, BLR) and a global bit line pair (GBLL, GBLR).

[0361] (Controller 1405) The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400 . The controller 1405 performs logical operations on command signals input from the outside and determines the operation mode. The row circuit 1410 and the column circuit 1420 are provided to determine the mode of operation. 415 control signal generation function, the function of holding the address signal input from the outside, It has the function of generating an external address signal.

[0362] (row circuit 1410) The row circuit 1410 functions to drive the MC-SA array 1420. 11 has the function of decoding address signals. The word line driver circuit 1412 A selection signal is generated to select the word line WL of the row to be accessed.

[0363] The column selector 1413 and the sense amplifier driver circuit 1414 are connected to the sense amplifier array 14 The column selector 1413 is a circuit for driving the bit line of the column to be accessed. The column selector 1413 has a function of generating a selection signal for selecting the The switch array 1444 of each local sense amplifier array 1426 is controlled by the The control signals of the sense amplifier driver circuit 1414 control the multiple local sense amplifier arrays. I 1426 is driven independently.

[0364] (column circuit 1415) The column circuit 1415 has a function of controlling the input of the data signal WDA[31:0], The data signal WDA[31:0] has the function of controlling the output of RDA[31:0]. The data signal RDA[31:0] is a write data signal, and the data signal RDA[31:0] is a read data signal.

[0365] The global sense amplifier 1447 is connected to the global bit line pair (GBLL, GBLR). The global sense amplifier 1447 is electrically connected to the global bit line pair ( It has the function of amplifying the potential difference between the GBLL and GBLR and the function of maintaining this potential difference. Data is written to and read from the global bit line pair (GBLL, GBLR) as follows: This is done by the input / output circuit 1417.

[0366] The write operation of the DOSRAM 1400 will be briefly described. The data is written to the global bit line pair. The address is held by the global sense amplifier array 1416. The switch array 1444 of the sense amplifier array 1426 switches the global bit line pairs The data is written to the bit line pair of the target column. The designated local memory cell array 14 amplifies and stores the written data. In 25, the row circuit 1410 selects the word line WL of the target row, and the memory The data held in the local sense amplifier array 1426 is written to the memory cell 1445 .

[0367] The outline of the read operation of the DOSRAM1400 is explained below. One row of the local memory cell array 1425 is specified. In row 1425, the word line WL of the target row is selected, and the data of memory cell 1445 is The local sense amplifier array 1426 writes data to the bit lines. The potential difference between the bit line pair is detected as data and stored. By this, the data held in the local sense amplifier array 1426 is The data of the corresponding column is written to the global bit line pair. 1416 detects and holds the data on the global bit line pair. The data held in the data array 1416 is output to the input / output circuit 1417. The work is completed.

[0368] In order to rewrite data by charging and discharging the capacitance element CS1, the DOSRAM1400 In principle, there is no limit to the number of times it can be rewritten, and data can be written and read with low energy. In addition, since the circuit configuration of the memory cell 1445 is simple, it is possible to increase the capacity. is easy.

[0369] The transistor MW1 is an OS transistor. Since the capacitance is small, it is possible to prevent the charge from leaking from the capacitance element CS1. Therefore, the retention time of DOSRAM1400 is longer than that of DRAM using Si transistors. Therefore, the refresh frequency can be reduced, and the refresh operation time can be reduced. Therefore, DOSRAM1400 is used as the frame memory. This reduces the power consumption of the display controller IC and source driver IC. Cut.

[0370] The MC-SA array 1420 has a stacked structure, and thus the local sense amplifier array The bit line can be shortened to a length similar to that of 1426. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell 1445. In addition, the local sense amplifier array 1426 can be provided with a switch array 1444. This reduces the number of long bit lines. Since the load to be driven when accessing 0 is reduced, the display controller IC and the source driver This reduces the energy consumption of the driver IC.

[0371] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0372] (Embodiment 5) In this embodiment, a transistor using a metal oxide for a channel formation region according to one embodiment of the present invention will be described. An example of a semiconductor device to which OS transistors are applied is an FPGA ( The FPGA in this embodiment is a field programmable gate array (FPGA). , configuration memory, and OS memory are applied to registers. calls such FPGAs "OS-FPGAs."

[0373] The OS memory includes at least a capacitance element and an OS transistor that controls the charging and discharging of the capacitance element. Since the OS transistor has a very small off-state current, S memory has excellent retention characteristics and can function as a non-volatile memory.

[0374] An example of the configuration of an OS-FPGA is shown in Fig. 16(A). 3110 is a multi-context architecture that allows for context switching and fine-grained performance for each PLE. NOFF (normally off) computing is possible to perform power gating. The OS-FPGA3110 is a controller 3111, Driver (Word driver) 3112, Data driver (Data driver r) 3113, Programmable area (Programmable area) 3115 It has.

[0375] The programmable area 3115 includes two input / output blocks (IOB) 3117, a core ( The IOB3117 has multiple programmable input / output circuits. The core 3119 is made up of a plurality of logic array blocks (LABs) 3120, a plurality of switches, and The LAB 3120 has a switch array block (SAB) 3130. 21. Figure 16(B) shows an example in which LAB3120 is configured with five PLE3121s. As shown in FIG. 16(C), SAB3130 has a plurality of slots arranged in an array. The LAB3120 has its own input terminal and a SAB It is connected to LAB3120 in four directions (up, down, left, and right) via 3130.

[0376] SB3131 will be described with reference to Figures 17(A) to 17(C). The SB3131 shown in A) has data, datab, signal context[1:0], word[1:0] is input. data and datab are configuration data The logic of data and datab is complementary. The number of contexts is 2, and the signal context[1:0] is the context selection signal. The signal word[1:0] is a word line selection signal. The input wirings are word lines.

[0377] SB3131 is a PRS (Programmable Routing Switch) 3133[0], P PRS3133[0] and PRS3133[1] are complementary devices. It has a configuration memory (CM) that can store data. When there is no distinction between 3[0] and PRS3133[1], it is called PRS3133. The same is true for .

[0378] Figure 17(B) shows an example of the circuit configuration of PRS3133[0]. PRS3133[1] has the same circuit configuration. PRS3133[0] and PRS31 33[1] differs from the input context selection signal and word line selection signal. context[0], signal word[0] is input to PRS3133[0], and signal co ntext[1], signal word[1] is input to PRS3133[1]. For example, In SB3131, when the signal context[0] becomes "H", PRS313 3[0] becomes active.

[0379] PRS3133[0] has CM3135 and Si transistor M31. Transistor M31 is a pass transistor controlled by CM3135. The memory circuit 3137 and the memory circuit 3137B are included. The memory circuit 3137B has the same circuit configuration. The memory circuit 3137B includes a transistor MO31 and an OS transistor MO32. The capacitor CB31, the OS transistor MOB31, and the OS transistor MOB32 are included. .

[0380] OS transistor MO31, OS transistor MO32, OS transistor MOB31 , and the OS transistor MOB32 may have a bottom gate. transistor MO31, OS transistor MO32, OS transistor MOB31, and O If the S-transistor MOB32 has bottom gates, these bottom gates are Each of them may be electrically connected to a power supply line that supplies a fixed potential.

[0381] The gate of the Si transistor M31 is the node N31, and the gate of the OS transistor MO32 is the node N32. The gate of the OS transistor MOB32 is at node N32, and the gate of the OS transistor MOB33 is at node NB32. Nodes N32 and NB32 are charge storage nodes for the CM3135. Transistor MO32 is connected to the signal line for signal context[0] and node N31. The OS transistor MOB32 controls the state of the node N31 and the low-potential power supply line VSS. Controls the conduction state between

[0382] The logic of the data held in memory circuit 3137 and memory circuit 3137B is complementary. Therefore, either the OS transistor MO32 or the OS transistor MOB32 One of them is conductive.

[0383] An example of the operation of PRS3133[0] will be described with reference to FIG. 17(C). Configuration data has already been written to PRS3133[0]. The node N32 is at "H" and the node NB32 is at "L".

[0384] While signal context[0] is low, PRS3133[0] is inactive. During this period, even if the input terminal of PRS3133[0] transitions to "H", the Si transistor The gate of transistor M31 is maintained at "L" and the output terminal of PRS3133[0] is also at "L". is maintained.

[0385] While signal context[0] is high, PRS3133[0] is active. When the signal context[0] transitions to "H", the configuration stored in the CM3135 The gate of the Si transistor M31 transitions to "H" according to the configuration data. .

[0386] When the input terminal transitions to "H" while PRS3133[0] is active, Since the OS transistor MO32 of the memory circuit 3137 is a source follower, The gate potential of the Si transistor M31 rises due to boosting. As a result, the OS transistor MO32 of the memory circuit 3137 loses its driving capability, and the Si transistor The gate of transistor M31 is left floating.

[0387] The CM3135 is a multi-context processor, while the PRS3133 has a multi-context function. It also has the functions of a grass planter.

[0388] Figure 18 shows an example of the configuration of the PLE 3121. The PLE 3121 is a LUT (look-up table) block 3123, register block 3124, selector 3125, CM31 26. The LUT block 3123 has inputs inA-inD The selector 3125 selects and outputs data according to the The output of the LUT block 3123 or the registers are Select the output of stub block 3124.

[0389] The PLE3121 is electrically connected to the power supply line for potential VDD via the power switch 3127. The power switch 3127 is turned on and off according to the configuration stored in CM3128. Each PLE 3121 has a power switch 312 By providing 7, fine-grained power gating is possible. This feature allows unused PLE3121s to be power gated after a context switch. This allows for effective reduction of standby power consumption.

[0390] To achieve NOFF computing, the register block 3124 is The non-volatile registers in the PLE3121 are part of the flash memory that contains the OS memory. It is a flip-flop (hereinafter referred to as "OS-FF").

[0391] The register block 3124 includes OS-FF3140[1] and OS-FF3140[2]. The signals user_res, load, and store are OS-FF3140 [1], the clock signal CLK1 is input to OS-FF3140[2]. 140[1], and the clock signal CLK2 is input to OS-FF3140[2]. FIG. 19(A) shows an example of the configuration of the OS-FF 3140.

[0392] The OS-FF3140 includes an FF3141 and a shadow register 3142. 41 includes a node CK, a node R, a node D, a node Q, and a node QB. A clock signal is input to CK, and a signal user_res is input to node R. The signal user_res is a reset signal. The node D is a data input node. Node Q is a data output node. Node Q and node QB have complementary logic.

[0393] The shadow register 3142 functions as a backup circuit for the FF 3141. The data register 3142 stores the data of the nodes Q and QB in accordance with the signal store. Then, the backed up data is sent to nodes Q and Q in response to the signal load. Write back to node QB.

[0394] The shadow register 3142 includes an inverter circuit 3188, an inverter circuit 3189, and S i transistor M37, Si transistor MB37, memory circuit 3143, memory circuit 3 The memory circuit 3143 and the memory circuit 3143B are the memory circuits of the PRS3133. The memory circuit 3143 has the same circuit configuration as the memory circuit 3137. The memory circuit 3143 includes a capacitance element C36, an OS The memory circuit 3143B includes a transistor MO35 and an OS transistor MO36. Capacitor element CB36, OS transistor MOB35, and OS transistor MOB36 The nodes N36 and NB36 are connected to the OS transistors MO36 and MO The gates of nodes N37 and B36 are charge storage nodes. are the gates of the Si transistor M37 and the Si transistor MB37.

[0395] OS transistor MO35, OS transistor MO36, OS transistor MOB35 , and OS transistor MOB36 may have a bottom gate. transistor MO35, OS transistor MO36, OS transistor MOB35, and O If the S-transistor MOB36 has bottom gates, these bottom gates are Each of them may be electrically connected to a power supply line that supplies a fixed potential.

[0396] An example of the operation method of the OS-FF 3140 will be described with reference to FIG.

[0397] (Backup) When the "H" signal store is input to the OS-FF3140, the shadow register 31 42 backs up the data of FF3141. Node N36 backs up the data of node Q. When the data is written, it becomes "L" and the node NB36 is set to "L" because the data of the node QB is written. After that, power gating is performed and the power switch Turn off 3127. The data on node Q and node QB of FF3141 will be lost, but the power Even when the power is off, the shadow register 3142 holds the backed up data.

[0398] (Recovery) Turn on the power switch 3127 to supply power to the PLE3121. Then, When a "H" signal load is input to the OS-FF 3140, the shadow register 3142 Write the backed up data back to FF3141. Node N36 is "L" so Therefore, the node N37 is maintained at "L" and the node NB36 is at "H", so that the node NB 37 becomes "H". Therefore, node Q becomes "H" and node QB becomes "L". This means that the OS-FF3140 will return to the state it was in when the backup was performed.

[0399] Fine-grained power gating and backup / recovery operation of OS-FF3140 By combining these, the power consumption of the OS-FPGA3110 can be effectively reduced.

[0400] One type of error that can occur in memory circuits is soft errors caused by the incidence of radiation. Soft errors are caused by alpha rays and other particles emitted from the materials that make up the memory and packaging. Primary cosmic rays that enter the atmosphere from space cause nuclear reactions with the nuclei of atoms present in the atmosphere. Secondary cosmic ray neutrons generated by this process are irradiated onto the transistor, generating electron-hole pairs. This is a phenomenon in which malfunction occurs, such as data held in memory being inverted OS memory using an OS transistor has high soft error tolerance. Therefore, by mounting an OS memory, a highly reliable OS-FPGA 3110 can be provided.

[0401] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments as appropriate.

[0402] (Embodiment 6) In this embodiment, an example of a CPU including a semiconductor device according to an aspect of the present invention, such as the storage device described above, will be described below.

[0403] <Configuration of CPU> The semiconductor device 5400 shown in FIG. 20 includes a CPU core 5401, a power management unit 5421, and a peripheral circuit 5422. The power management unit 5421 includes a power controller 5402 and a power switch 5403. The peripheral circuit 5422 includes a cache 5404 having a cache memory, a bus interface (BUS I / F) 5405, and a debug interface (Debug I / F) 5406 . The CPU core 5401 includes a data bus 5423, a control unit (Control Uni t) 5407, a PC (program counter) 5408, a pipeline register (Pipe line Register) 5409, a pipeline register 5410, an ALU (Ar ithmetic logic unit) 5411, and a register file (Regi ster File) 5412. The CPU core 5401 and the cache 5404, etc Data is exchanged with the peripheral circuit 5422 via a data bus 5423 .

[0404] The semiconductor device (cell) includes a power controller 5402, a control device 5407, and many other components. It can be applied to many logic circuits. In particular, it can be configured using standard cells. As a result, the small semiconductor device 5400 can be applied to all logic circuits that can be implemented. In addition, a semiconductor device 5400 that can reduce power consumption can be provided. In addition, it is possible to provide a semiconductor device 5400 capable of improving the operating speed. It is possible to provide a semiconductor device 5400 capable of reducing pressure fluctuations.

[0405] The semiconductor device (cell) includes a p-channel Si transistor and a metal The channel forming region contains a metal oxide (preferably an oxide containing In, Ga, and Zn). By using a transistor and applying the semiconductor device (cell) to the semiconductor device 5400, In this way, a small-sized semiconductor device 5400 can be provided. In addition, the semiconductor device 5400 can be provided, which can improve the operating speed. In particular, by using only p-channel Si transistors, the manufacturing cost can be reduced. can be kept low.

[0406] The control unit 5407 includes a PC 5408, a pipeline register 5409, and a pipeline register 5408. Register 5410, ALU 5411, register file 5412, cache 5404, buffer interface 5405, debug interface 5406, and power control By controlling the operation of the controller 5402 in an integrated manner, the input application and other processes can be It has the ability to decode and execute instructions contained in the program.

[0407] The ALU 5411 has the function of performing various arithmetic operations such as arithmetic operations and logical operations.

[0408] The cache 5404 has a function of temporarily storing frequently used data. PC5408 is a register that has the function of storing the address of the next instruction to be executed. Although not shown in FIG. 20, the cache 5404 includes a cache memory operation A cache controller is provided to control the

[0409] The pipeline register 5409 is a register that has the function of temporarily storing instruction data. It is Ta.

[0410] The register file 5412 has a plurality of registers including general-purpose registers. Data read from the on-chip memory or data obtained as a result of the ALU5411 calculation etc. can be stored.

[0411] The pipeline register 5410 stores data used in the arithmetic processing of the ALU 5411, or It has the function of temporarily storing data obtained as a result of the ALU5411 calculation processing. It is a register.

[0412] The bus interface 5405 is connected to the semiconductor device 5400 and the outside of the semiconductor device 5400. It functions as a data path between various devices. The source 5406 is used to input instructions for controlling debugging to the semiconductor device 5400. It functions as a signal path.

[0413] The power switch 5403 is connected to the power controller 5402 of the semiconductor device 5400. It has the function of controlling the supply of power supply voltage to various circuits other than the above. Each circuit belongs to a different power domain, and various circuits that belong to the same power domain are The power switch 5403 controls whether or not the power supply voltage is supplied. The controller 5402 has a function of controlling the operation of the power switch 5403 .

[0414] The semiconductor device 5400 having the above configuration is capable of performing power gating. The flow of power gating operations will be explained using an example.

[0415] First, the CPU core 5401 determines the timing to stop the supply of power voltage by the power controller. Then, the CPU core 5401 sends the power control Next, a command to start power gating is sent to the controller 5402. The various registers and cache 5404 included in 400 start to save data. The power supply to various circuits other than the power controller 5402 of the semiconductor device 5400 is The voltage supply is stopped by the power switch 5403. Then, an interrupt signal is sent to By inputting the signal to the controller 5402, the signal is transmitted to various circuits of the semiconductor device 5400. The supply of the power supply voltage is started. The timing at which the supply of power voltage starts is determined by the relevant Then, various registers and cache 5404 , begins returning data. Then, execution of instructions in the control unit 5407 resumes. .

[0416] Such power gating can be applied to the entire processor or to one of the components of the processor. Alternatively, it can be performed in a plurality of logic circuits. This allows for fine-grained reduction of power consumption in space and time. Reductions can be made.

[0417] When power gating is performed, the information held by the CPU core 5401 and the peripheral circuit 5422 is It is preferable to be able to save information in a short time. This allows the power to be turned on and off in a short time. This makes it possible to achieve greater power saving effects.

[0418] In order to save the information held by the CPU core 5401 and the peripheral circuit 5422 in a short time, It is preferable that the flip-flop circuit can save data within the circuit (backup possible) (This is called a flip-flop circuit.) Also, the SRAM cell can save data within the cell. It is preferable to use a backup-capable SRAM cell. The flip-flop circuit and the SRAM cell are made of metal oxides (preferably In, Ga, and Zn). It is preferable to have a transistor having a channel formation region including a silicon oxide. Since the transistor has a low off-state current, a flip-flop circuit capable of backing up can be realized. The transistors and SRAM cells can retain information for a long period without power supply. The high switching speed of the transistor makes it possible to use a flip-flop that can be backed up. The flash memory circuit and SRAM cell may be capable of saving and restoring data for a short period of time.

[0419] An example of a flip-flop circuit capable of backing up will be described with reference to FIG.

[0420] The semiconductor device 5500 shown in FIG. 21 is an example of a flip-flop circuit capable of backing up. The semiconductor device 5500 includes a first memory circuit 5501, a second memory circuit 5502, and a The semiconductor device 5500 includes a third memory circuit 5503 and a reading circuit 5504. The potential difference between potential V1 and potential V2 is supplied to the In the following, potential V1 is at a low level, and potential V2 is at a high level. A configuration example of the semiconductor device 5500 will be described below, taking the case where the potential V2 is at a high level as an example. It shall be.

[0421] The first memory circuit 5501 stores the following data during a period when a power supply voltage is supplied to the semiconductor device 5500: When a signal D containing data is input, the data is held. During the period in which the power supply voltage is supplied to the semiconductor device 5500, the first memory circuit 550 A signal Q including the stored data is output from the first memory circuit 55. 01 holds data during the period when power supply voltage is not supplied to the semiconductor device 5500. That is, the first memory circuit 5501 is called a volatile memory circuit. It is possible.

[0422] The second memory circuit 5502 reads the data stored in the first memory circuit 5501. The third memory circuit 5503 has a function of storing (or saving) the second The data held in the memory circuit 5502 is read and stored (or saved). The read circuit 5504 has a function of reading the second memory circuit 5502 or the third memory circuit 5503. The data held in the memory circuit 503 is read out and stored in the first memory circuit 5501 (or restored). ) function.

[0423] In particular, the third memory circuit 5503 is configured to store the data when the power supply voltage is not supplied to the semiconductor device 5500. During this period, the data held in the second memory circuit 5502 is read and stored ( Or evacuate.) function.

[0424] As shown in FIG. 21, the second memory circuit 5502 includes a transistor 5512 and a capacitor The third memory circuit 5503 includes a transistor 5513 and a transistor The read circuit 5504 includes a transistor 5515 and a capacitor 5520. 510, transistor 5518, transistor 5509, and transistor 5517 , has.

[0425] The transistor 5512 outputs a voltage corresponding to the data stored in the first memory circuit 5501. The transistor 5512 has a function of charging and discharging a load to a capacitor 5519. A charge corresponding to the data held in the memory circuit 5501 is quickly transferred to the capacitor element 5519. It is preferable that the transistor 5512 be capable of being charged and discharged. Silicon (preferably polycrystalline silicon, more preferably single crystal silicon) is used as the channel. It is preferable that it is included in the forming region.

[0426] The transistor 5513 is turned on or off depending on the charge held in the capacitor 5519. The transistor 5515 is selected to be in a non-conducting state when the transistor 5513 is in a conducting state. When the potential of the wiring 5544 is high, the capacitor 5520 is charged and discharged. The off-state current of the transistor 5515 is preferably extremely small. , transistor 5515 is made of a metal oxide (preferably an oxide containing In, Ga, and Zn). It is preferable that the channel forming region contains a material such as a fluorine-containing compound.

[0427] To specifically explain the connection relationship of each element, the source and drain of the transistor 5512 One end of the transistor 5512 is connected to the first memory circuit 5501. The other of the drain and the drain is connected to one electrode of a capacitor 5519, the gate of a transistor 5513, and the gate of the transistor 5518. The other electrode of the capacitor 5519 is , and is connected to a wiring 5542. One of the source and drain of the transistor 5513 is , and is connected to a wiring 5544. The other of the source and the drain of the transistor 5513 is , connected to one of the source and drain of the transistor 5515. The other of the source and drain of the capacitor 515 is connected to one electrode of a capacitor element 5520 and a transistor. The other electrode of the capacitor 5520 is connected to the gate of the capacitor 5510. One of the source and drain of the transistor 5510 is connected to a wiring 5541 The other of the source and drain of the transistor 5510 is connected to the transistor The source of the transistor 5518 is connected to one of the source and drain of the transistor 5518. The other of the drain and the source is connected to one of the source and drain of a transistor 5509. The other of the source and drain of the transistor 5509 is connected to the source of the transistor 5517. The source and drain of the transistor 5501 are connected to the first memory circuit 5501. The other of the source and drain of 5517 is connected to a wiring 5540. In this case, the gate of the transistor 5509 is connected to the gate of the transistor 5517. However, the gate of transistor 5509 is not necessarily the gate of transistor 5517. It does not have to be connected to

[0428] The transistor described in the above embodiment can be used as the transistor 5515. Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can be used for a long period of time. It can retain data without power supply. Switching characteristics of the transistor 5515 Because of this, the semiconductor device 5500 is capable of high-speed backup and recovery. can be done.

[0429] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0430] (Embodiment 7) In this embodiment, one mode of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 22 and 23. This will be used to explain.

[0431] <Semiconductor wafers and chips> FIG. 22(A) shows a top view of the substrate 711 before the dicing process is performed. The plate 711 may be, for example, a semiconductor substrate (also called a "semiconductor wafer"). A plurality of circuit regions 712 are provided on the substrate 711. A semiconductor device or the like according to one embodiment of the present invention can be provided.

[0432] Each of the multiple circuit regions 712 is surrounded by an isolation region 713. A separation line (also called a "dicing line") 714 is set at a position where the separation line overlaps with the separation line. By cutting the substrate 711 along 714, chips 715 including circuit regions 712 are formed on the substrate. It can be cut out from the plate 711. An enlarged view of the chip 715 is shown in FIG.

[0433] In addition, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a layer, a semiconductor layer, etc., ESD (Electrostatic Discharge) that may occur during the dicing process can be prevented. -Static Discharge: Reduces static electricity caused by the dicing process In general, the dicing process involves cooling the substrate, Pure carbon dioxide gas is dissolved in the material to reduce the resistivity, for the purpose of removing debris and preventing static electricity. This is done while supplying water to the cutting portion. This reduces the amount of pure water used, thereby reducing the production cost of semiconductor devices. Furthermore, the productivity of the semiconductor device can be improved.

[0434] <Electronic components> An example of an electronic component using the chip 715 will be described with reference to FIGS. 23(A) and 23(B). The electronic components are also called semiconductor packages or IC packages. Sub-components have multiple standards and names depending on the terminal extraction direction, terminal shape, etc. do.

[0435] The electronic component is assembled with the semiconductor device shown in the above embodiment in the assembly process (post-process). The semiconductor device is completed by combining it with other components.

[0436] The post-process will be explained using the flowchart shown in FIG. After forming a semiconductor device according to one embodiment of the present invention on the substrate 711, The back surface (the surface on which semiconductor devices etc. are not formed) is ground (step By thinning the substrate 711 by grinding, it is possible to miniaturize the electronic components. Cut.

[0437] Next, a "dicing step" is performed to separate the substrate 711 into a plurality of chips 715 (step Then, the separated chips 715 are bonded onto individual lead frames (called "Da-Pack"). The die bonding process is then performed (step S723). The bonding between the lead frame and the P715 can be done by resin bonding or tape bonding. Select the appropriate method depending on the product. Note that an interposer substrate may be used instead of a lead frame. A chip 715 may be bonded onto the plate.

[0438] Next, the leads of the lead frame and the electrodes on the chip 715 are connected with thin metal wires (wires). ) and perform the "wire bonding process" to electrically connect (step S724). For the thin wire, silver wire, gold wire, etc. can be used. For example, ball bonding or wedge bonding can be used.

[0439] The wire-bonded chip 715 is sealed with epoxy resin or other materials in the "sealing process." The molding process is then carried out (step S725). The inside of the product is filled with resin, and the wire connecting the chip 715 and the lead is protected from external mechanical force. It can protect the device from moisture, dust, etc., and also reduces the deterioration of electrical characteristics (reduced reliability). It can be reduced.

[0440] Next, a "lead plating process" is carried out to plate the leads of the lead frame (step The plating process prevents the leads from rusting and prevents rust when later mounted on a printed circuit board. Next, the leads are cut and shaped. A molding process is carried out (step S727).

[0441] Next, a "marking process" is carried out, in which printing (marking) is applied to the surface of the package. (Step S728) Then, an "inspection worker" checks whether the external appearance is good or not, whether there is any malfunction, etc. After passing through the "process" (step S729), the electronic component is completed.

[0442] A perspective view of the completed electronic component is shown in FIG. 23(B). As an example of a component, a QFP (Quad Flat Package) is shown in a perspective view. The electronic component 750 shown in FIG. 23(B) has leads 755 and a chip 715. The electronic component 750 may include multiple chips 715.

[0443] The electronic component 750 shown in FIG. 23(B) is mounted on, for example, a printed circuit board 752. A plurality of such electronic components 750 are combined, and each is electrically connected to a printed circuit board 752. By electrically connecting the components together, a substrate (mounting substrate 754) on which electronic components are mounted is completed. The resulting mounting board 754 is used in electronic devices and the like.

[0444] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh.

[0445] (Embodiment 8) <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in various electronic devices. Specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention will be described.

[0446] 24(A) is an external view showing an example of an automobile. The automobile 2980 has a body 2981 , wheels 2982, dashboard 2983, and lights 2984. The car 2980 is equipped with an antenna, a battery, etc.

[0447] The information terminal 2910 shown in FIG. 24B includes a housing 2911, a display unit 2912, a microphone 29 17, speaker unit 2914, camera 2913, external connection unit 2916, and operation switch 2 The display portion 2912 includes a display panel and a touch panel using a flexible substrate. The information terminal 2910 is provided with an antenna, a battery, and a display screen inside the housing 2911. The information terminal 2910 is, for example, a smartphone, a mobile phone, a tablet, Use as a portable information terminal, tablet personal computer, e-book reader, etc. can be done.

[0448] The notebook personal computer 2920 shown in FIG. 24(C) includes a housing 2921, a display The computer 2920 includes a display unit 2922, a keyboard 2923, and a pointing device 2924. The notebook personal computer 2920 has an antenna, a battery, and the like inside the housing 2921. It has a terry, etc.

[0449] The video camera 2940 shown in FIG. 24(D) includes a housing 2941, a housing 2942, a display unit 2 943, an operation switch 2944, a lens 2945, and a connection part 2946. The switch 2944 and the lens 2945 are provided in the housing 2941, and the display unit 2943 The video camera 2940 is provided inside the housing 2941. The housing 2941 and the housing 2942 are provided with an antenna, a battery, etc. 946, and the angle between the housing 2941 and the housing 2942 is 6. The angle of the housing 2942 relative to the housing 2941 Depending on the angle, the orientation of the image displayed on the display unit 2943 can be changed, and the image can be displayed or hidden. Switching can be done.

[0450] An example of a bangle-type information terminal is shown in FIG. 24(E). The information terminal 2950 has a housing 295 The information terminal 2950 includes a housing 2951 and a display unit 2952. The display unit 2952 is supported by a curved housing 2951. The display unit 2952 is provided with a display panel using a flexible substrate. It is possible to provide a flexible, lightweight, and easy-to-use information terminal 2950.

[0451] FIG. 24F shows an example of a wristwatch-type information terminal. The information terminal 2960 has a housing 2961 , display unit 2962, band 2963, buckle 2964, operation switch 2965, input / output The information terminal 2960 is provided with a terminal 2966 and the like. The information terminal 2960 also has an antenna inside the housing 2961. The information terminal 2960 is equipped with a mobile phone, e-mail, text browsing and creation functions. Various applications such as music playback, internet communication, and computer games can be executed.

[0452] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, allowing you to touch the screen with your finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be By touching it, you can start an application. In addition to setting the time, you can also turn the power on and off, turn wireless communication on and off, activate silent mode, and It can have various functions such as turning on and off the power saving mode, turning on and off the power saving mode, etc. The operating system installed in the information terminal 2960 controls the operation of the operation switch 29 You can also set up to 65 functions.

[0453] The information terminal 2960 is also capable of performing standardized short-range wireless communication. For example, by communicating with a wireless headset, hands-free operation is possible. The information terminal 2960 is also provided with an input / output terminal 2966, and can receive other information. Data can be exchanged directly with the terminal via the connector. Charging can also be performed via the input / output terminal 2966. Alternatively, power may be supplied wirelessly without any need for a power supply.

[0454] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used for the control information of the above-described electronic devices. The semiconductor device according to one aspect of the present invention can store information, control programs, and the like for a long period of time. By using the device, highly reliable electronic equipment can be realized.

[0455] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh. [Explanation of symbols]

[0456] 10: transistor, 11: transistor, 12: transistor, 13: transistor , 100: insulator, 102: insulator, 105: insulator, 110: insulator, 112: conductor , 120: conductor, 120_1: conductor, 120_2: conductor, 120a: conductor, 12 0b: conductor, 130: insulator, 130_1: insulator, 130_2: insulator, 130a: Insulator, 130b: insulator, 140: conductor, 140_1: conductor, 140_2: conductor , 140a: conductor, 140b: conductor, 145: opening, 150: oxide, 150_1: Oxide, 150_2: Oxide, 150a: Oxide, 150b: Oxide, 150c: Oxide , 151: oxide, 160: insulator, 161: insulator, 170: conductor, 171: conductor , 175: insulator, 176: insulator, 178: insulator, 180: insulator, 185: conductor , 185_1: conductor, 185_2: conductor, 185a: conductor, 185b: conductor, 1 90: conductor, 190_1: conductor, 190_2: conductor, 190a: conductor, 190b : conductor, 195: conductor, 195_1: conductor, 195_2: conductor, 195a: conductor body, 195b: conductor, 200: conductor, 200_1: conductor, 200_2: conductor, 2 00a: conductor, 200b: conductor, 210: insulator, 218: conductor, 246: conductor , 248: conductor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314 b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 711: substrate, 712: circuit area, 713: separation area, 714: separation line, 715: chip , 750: Electronic components, 752: Printed circuit board, 754: Mounting board, 755: Lead, 10 00: Capacitive element, 1100: Conductor, 1200: Conductor, 1300: Insulator, 1400: DOSRAM, 1405: Controller, 1410: Row circuit, 1411: Decoder, 14 12: Word line driver circuit, 1413: Column selector, 1414: Sense amplifier driver circuit, 1415: column circuit, 1416: global sense amplifier array, 1417: input / output Circuit, 1420: memory cell and sense amplifier array, 1422: memory cell array, 1 423: Sense amplifier array, 1425: Local memory cell array, 1426: Local Sense amplifier array, 1444: switch array, 1445: memory cell, 1446: Sense amplifier, 1447: Global sense amplifier, 1500: Insulator, 1600: NO SRAM, 1610: memory cell array, 1611: memory cell, 1612: memory cell , 1613: memory cell, 1614: memory cell, 1640: controller, 1650: Row driver, 1651: row decoder, 1652: word line driver, 1660: column driver 1661: column decoder, 1662: write driver, 1663: DAC, 1670 : Output driver, 1671: Selector, 1672: ADC, 1673: Output buffer, 2 000: transistor, 2910: information terminal, 2911: housing, 2912: display unit, 29 13: Camera, 2914: Speaker, 2915: Operation switch, 2916: External connection part ,2917: Microphone, 2920: Notebook personal computer, 2921: Housing, 2 922: Display unit, 2923: Keyboard, 2924: Pointing device, 2940 :Video camera, 2941:Housing, 2942:Housing, 2943:Display, 2944:Operation Switch, 2945: Lens, 2946: Connection part, 2950: Information terminal, 2951: Housing ,2952: Display unit, 2960: Information terminal, 2961: Housing, 2962: Display unit, 296 3: Band, 2964: Buckle, 2965: Operation switch, 2966: Input / output terminal, 2 967: Icon, 2980: Car, 2981: Body, 2982: Wheel, 2983: Board, 2984: Light, 3000: Transistor, 3001: Wiring, 3002 : Wiring, 3003: Wiring, 3004: Wiring, 3005: Wiring, 3110: OS-FPGA , 3111: Controller, 3112: Word driver, 3113: Data driver, 3 115: Programmable area, 3117: IOB, 3119: Core, 3120: LAB ,3121: PLE, 3123: LUT block, 3124: Register block, 312 5: Selector, 3126: CM, 3127: Power switch, 3128: CM, 3130 :SAB, 3131:SB, 3133:PRS, 3133[0]:PRS, 3133[1 ]: PRS, 3135: CM, 3137: memory circuit, 3137B: memory circuit, 314 0:OS-FF, 3140[1]:OS-FF, 3140[2]:OS-FF, 3141 :FF, 3142: Shadow register, 3143: Memory circuit, 3143B: Memory circuit , 3188: inverter circuit, 3189: inverter circuit, 5400: semiconductor device, 54 01: CPU core, 5402: Power controller, 5403: Power switch, 540 4: Cache, 5405: Bus interface, 5406: Debug interface 5407: Control unit, 5408: PC, 5409: Pipeline register 5410: Pipeline register, 5411: ALU, 5412: Register file, 5421: Power management unit, 5422: Peripheral circuit, 5423: Data bus, 5500: Semiconductor device, 5501: memory circuit, 5502: memory circuit, 5503: memory circuit, 5504 : readout circuit, 5509: transistor, 5510: transistor, 5512: transistor Transistor, 5513: Transistor, 5515: Transistor, 5517: Transistor, 5518: transistor, 5519: capacitance element, 5520: capacitance element, 5540: wiring, 5541: Wiring, 5542: Wiring, 5543: Wiring 5544 Wiring

Claims

[Claim 1] a first conductor; a first insulator on the first conductor; a second conductor on the first insulator; and an oxide having a region in contact with side surfaces of the first conductor, the first insulator, and the second conductor; a second insulator on the oxide; a third conductor on the second insulator; the second insulator has a region facing side surfaces of the first conductor, the first insulator, and the second conductor with the oxide interposed therebetween; a third conductor having a region facing side surfaces of the first conductor, the first insulator, and the second conductor via the oxide and the second insulator;

Images