Semiconductor package

Abstract

To provide a semiconductor device in which entry of molten plating or the like can be suppressed while the size of the package is reduced.SOLUTION: A semiconductor package includes a substrate, a semiconductor element, a bonding wire, and sealing resin. The substrate includes a base material, a first conductor pattern, a second conductor pattern, a third conductor pattern, a first conductive layer, and a first insulating layer. The base material includes a first main surface and a second main surface, which is opposite to the first main surface, in a first direction that is the thickness direction of the base material. In the base material, a first penetration hole penetrating the base material is formed along the first direction. The first conductor pattern and the second conductor pattern are disposed on the first main surface. The first conductor pattern includes a first land. The second conductor pattern includes a second land. The third conductor pattern is disposed on the second main surface. The first conductive layer is disposed on an inner wall surface of the first penetration hole and connects the first conductor pattern and the third conductor pattern.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor packages. [Background technology]

[0002] For example, Japanese Patent Laid-Open Publication No. 2023-076696 (Patent Document 1) describes a semiconductor package. The semiconductor package described in Patent Document 1 includes a substrate, a semiconductor element, bonding wires, and a sealing resin.

[0003] The substrate includes a base material, a first conductor pattern, a second conductor pattern, a third conductor pattern, a fourth conductor pattern, a first conductor layer, a second conductor layer, and a first insulating layer and a second insulating layer.

[0004] The substrate has a first main surface and a second main surface in a first direction. The first direction is the thickness direction of the substrate. The second main surface is the surface opposite to the first main surface. The first conductor pattern and the second conductor pattern are arranged on the first main surface. The third conductor pattern and the fourth conductor pattern are arranged on the second main surface. The substrate has a first through hole and a second through hole formed therein.

[0005] The first through hole and the second through hole penetrate the substrate along a first direction. The first through hole and the second through hole are located at opposite ends in a second direction in a plan view (when viewed along the first direction). The second direction is perpendicular to the first direction. The first conductor layer is disposed on the inner wall surface of the first through hole and connects the first conductor pattern and the third conductor pattern. The second conductor layer is disposed on the inner wall surface of the second through hole and connects the second conductor pattern and the fourth conductor pattern.

[0006] The first and second conductor patterns have first and second lands, respectively. The semiconductor element is disposed on the second lands. The bonding wires are connected at one end to the semiconductor element and at the other end to the first lands.

[0007] The first insulating layer and the second insulating layer extend along a third direction in a plan view. The third direction is a direction perpendicular to the first and second directions. The first insulating layer partially covers the first conductive pattern, and the second insulating layer partially covers the second conductive pattern. However, the first insulating layer does not cover the first lands, and the second insulating layer does not cover the second lands.

[0008] The sealing resin is disposed on the substrate so as to cover the semiconductor element and the bonding wires, and the outer periphery of the sealing resin overlaps with the first insulating layer and the second insulating layer in a plan view. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2023-076696 A [Summary] A plating layer may be formed on the surfaces of the first conductor pattern, the third conductor pattern, and the first conductor layer (the second conductor pattern, the fourth conductor pattern, and the second conductor layer). The constituent material of the plating layer is, for example, tin or a tin alloy. When the semiconductor package described in Patent Document 1 is mounted, the constituent material of the plating layer melts, and the molten constituent material of the plating layer attempts to penetrate along the interface between the encapsulating resin and the first conductor pattern (the second conductor pattern) to a position inside the outer periphery of the encapsulating resin in a planar view. In the semiconductor package described in Patent Document 1, the penetration of the molten plating layer is stopped by the first insulating layer (the second insulating layer). However, the semiconductor package described in Patent Document 1 results in an increased package size.

[0010] The semiconductor package of the present disclosure is a semiconductor package comprising a substrate, a semiconductor element, a bonding wire, and a sealing resin. The substrate has a base material, a first conductor pattern, a second conductor pattern, and a third conductor pattern, a first conductor layer, and a first insulating layer. The base material has a first main surface and a second main surface opposite the first main surface in a first direction, which is the thickness direction of the base material. A first through hole penetrating the base material along the first direction is formed in the base material. The first conductor pattern and the second conductor pattern are arranged on the first main surface. The first conductor pattern has a first land. The second conductor pattern has a second land. The third conductor pattern is arranged on the second main surface. The first conductor layer is arranged on the inner wall surface of the first through hole and connects the first conductor pattern and the third conductor pattern. The semiconductor element is arranged on the second land. The bonding wire is connected to the semiconductor element at one end and to the first land at the other end. The first insulating layer is disposed on the first conductive pattern between the first conductive layer and the first lands. The sealing resin is disposed on the substrate so as to cover the semiconductor element. The first insulating layer is located inside the outer periphery of the sealing resin in a plan view. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view of a semiconductor package 100. [Figure 2] FIG. 2 is a bottom view of the semiconductor package 100. [Figure 3A] FIG. 2 is a first cross-sectional view of the semiconductor package 100. [Figure 3B] FIG. 2 is a second cross-sectional view of the semiconductor package 100. [Figure 4] This is a method for manufacturing a semiconductor package 100. [Figure 5] FIG. 10 is a plan view illustrating the preparation step S1. [Figure 6] FIG. 10 is a plan view illustrating a semiconductor element mounting step S2. [Figure 7] FIG. 10 is a plan view illustrating the wire bonding step S3. [Figure 8A]FIG. 10 is a first cross-sectional view illustrating a resin sealing step S4. [Figure 8B] FIG. 10 is a second cross-sectional view illustrating the resin sealing step S4. [Figure 9] FIG. 2 is a plan view of a semiconductor package 200. [Figure 10] FIG. 2 is a plan view of a semiconductor package 300.

[0012] [Detailed explanation] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure will be described with reference to the accompanying drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0013] (First embodiment) A semiconductor package according to the first embodiment will be described. The semiconductor package according to the first embodiment is designated as a semiconductor package 100.

[0014] <Configuration of semiconductor package 100> The configuration of the semiconductor package 100 will be described below.

[0015] FIG. 1 is a plan view of the semiconductor package 100. FIG. 2 is a bottom view of the semiconductor package 100. In FIGS. 1 and 2, through holes 11g to 11j and sealing resin 40 are indicated by dotted lines. FIG. 3A is a first cross-sectional view of the semiconductor package 100. FIG. 3B is a second cross-sectional view of the semiconductor package 100. As shown in FIGS. 1, 2, 3A, and 3B, the semiconductor package 100 has a substrate 10, semiconductor elements 20 and 21, bonding wires 30 and 31, and sealing resin 40.

[0016] The substrate 10 has a base material 11. The base material 11 is made of, for example, an electrically insulating material. A specific example of the material of the base material 11 is BT (Bismaleimide Triazine) resin. The base material 11 has a main surface 11a and a main surface 11b. The main surface 11b is the surface opposite to the main surface 11a. The main surface 11a and the main surface 11b are end surfaces of the base material 11 in a first direction DR1. The first direction DR1 is the thickness direction of the base material 11.

[0017] The substrate 11 is rectangular in plan view (when viewed along the first direction DR1). More specifically, the substrate 11 has a side surface 11c, a side surface 11d, a side surface 11e, and a side surface 11f. The side surface 11e is the opposite surface of the side surface 11c, and the side surfaces 11c and 11e are end surfaces of the substrate 11 in the second direction DR2. The side surface 11f is the opposite surface of the side surface 11d, and the side surfaces 11d and 11f are end surfaces of the substrate 11 in the third direction DR3. The second direction DR2 is perpendicular to the first direction DR1, and the third direction DR3 is perpendicular to both the first direction DR1 and the second direction DR2. The third direction DR3 is along the longitudinal direction of the substrate 11 in plan view. The semiconductor package 100 is mounted on a substrate, for example, such that the substrate and the side surface 11c face each other. In other words, the side surface 11c forms the mounting surface of the semiconductor package 100.

[0018] Through holes 11g, 11h, 11i, and 11j are formed in the substrate 11. Through holes 11g to 11j penetrate the substrate 11 along a first direction DR1. Through holes 11g to 11j are respectively arranged at the four corners of the substrate 11 in a plan view. More specifically, through hole 11g is formed in a corner of the substrate 11 where side surface 11c and side surface 11d are connected, and through hole 11h is formed in a corner of the substrate 11 where side surface 11c and side surface 11f are connected. Through hole 11i is formed in a corner of the substrate 11 where side surface 11e and side surface 11d are connected, and through hole 11j is formed in a corner of the substrate 11 where side surface 11e and side surface 11f are connected.

[0019] The substrate 10 further has conductor patterns 12a, 12b, 12c, and 12d. Conductive patterns 12a to 12d are arranged on the main surface 11a. The substrate 10 further has conductor patterns 13a, 13b, 13c, and 13d. Conductive patterns 13a to 13d are arranged on the main surface 11b.

[0020] The substrate 10 further has conductor layers 14a, 14b, 14c, and 14d. Conductor layers 14a to 14d are arranged on the inner wall surfaces of through holes 11g to 11j, respectively. Conductor patterns 12a and 13a are connected by conductor layer 14a. Conductor patterns 12b and 13b are connected by conductor layer 14b. Conductor patterns 12c and 13c are connected by conductor layer 14c. Conductor patterns 12d and 13d are connected by conductor layer 14d.

[0021] The conductor pattern 12a has a land 12aa, a land 12ab, and a connection portion 12ac. The land 12aa is arranged around the through hole 11g and is connected to the conductor layer 14a. The connection portion 12ac connects the land 12aa and the land 12ab. The connection portion 12ac has, for example, a first portion 12ac1 and a second portion 12ac2. The first portion 12ac1 extends from the land 12aa along the third direction DR3. The second portion 12ac2 extends from an end of the first portion 12ac1 opposite the land 12aa to the opposite side of the side surface 11c along the second direction DR2 and is connected to the land 12ab.

[0022] The conductor pattern 12b has a land 12ba, a land 12bb, and a connection portion 12bc. The land 12ba is disposed around the through hole 11h and is connected to the conductor layer 14b. The connection portion 12bc extends along the third direction DR3 and connects the land 12ba and the land 12bb.

[0023] The conductor pattern 12c has a land 12ca, a land 12cb, and a connection portion 12cc. The land 12ca is arranged around the through hole 11i and is connected to the conductor layer 14c. The connection portion 12cc extends along the third direction DR3 and connects the land 12ca and the land 12cb. The conductor pattern 12d has a land 12da, a land 12db, and a connection portion 12dc. The land 12da is arranged around the through hole 11j and is connected to the conductor layer 14d. The connection portion 12dc extends along the third direction DR3 and connects the land 12da and the land 12db.

[0024] The conductive pattern 13a has a land 13aa, a land 13ab, and a connection portion 13ac. The land 13aa is arranged around the through hole 11g and is connected to the conductive layer 14a. The land 13ab is arranged adjacent to the side surface 11e. The connection portion 13ac connects the land 13aa and the land 13ab. The conductive pattern 13b has a land 13ba, a land 13bb, and a connection portion 13bc. The land 13ba is arranged around the through hole 11h and is connected to the conductive layer 14b. The land 13bb is arranged adjacent to the side surface 11e. The connection portion 13bc connects the land 13ba and the land 13bb.

[0025] Conductive pattern 13c has land 13ca. Conductive pattern 13d has land 13da. Land 13ca is arranged around through-hole 11i and is connected to conductive layer 14c. Land 13da is arranged around through-hole 11j and is connected to conductive layer 14d.

[0026] Conductive patterns 12a to 12d and 13a to 13d each have, for example, a copper layer disposed on the main surfaces (main surfaces 11a and 11b) of substrate 11, a nickel layer disposed on the copper layer, and a gold layer disposed on the nickel layer. However, conductive patterns 12a to 12d and 13a to 13d located below insulating layers 15a to 15f (described later) may not have the nickel layer or gold layer. The constituent material of conductor layers 14a to 14d is, for example, copper.

[0027] The substrate 10 further includes insulating layers 15a, 15b, 15c, 15d, 15e, and 15f. The insulating layers 15a to 15f are made of an insulating resin material. Specific examples of the material of the insulating layers 15a to 15f include resists such as solder resist. The insulating layer 15a is disposed on the main surface 11a so as to cover the connection portion 12ac. More specifically, the insulating layer 15a is disposed on the main surface 11a so as to cover the first portion 12ac1.

[0028] Insulating layer 15b is disposed on main surface 11a to cover connecting portion 12bc. Insulating layer 15c is disposed on main surface 11a to cover connecting portion 12cc, and insulating layer 15d is disposed on main surface 11a to cover connecting portion 12dc. Insulating layer 15e is disposed on main surface 11b to cover connecting portion 13cc, and insulating layer 15f is disposed on main surface 11b to cover connecting portion 13bc.

[0029] The semiconductor element 20 is, for example, an LED (Light Emitting Diode). However, the semiconductor element 20 is not limited thereto. The semiconductor element 20 has a main surface 20a and a main surface 20b in the first direction DR1 (i.e., in the thickness direction of the semiconductor element 20). The main surface 20b is the surface opposite to the main surface 20a. The semiconductor element 20 has an electrode 22 and an electrode 23 on the main surface 20a and the main surface 20b, respectively. The semiconductor element 20 is disposed on the land 12bb such that the main surface 20b (electrode 23) faces the land 12bb. A bonding material 24 is interposed between the land 12bb and the electrode 23. The bonding material 24 is, for example, a conductive adhesive, and electrically connects the semiconductor element 20 and the land 12bb (conductor pattern 12b).

[0030] The semiconductor element 21 is, for example, an LED. However, the semiconductor element 20 is not limited to this. The semiconductor element 21 has a main surface 21a and a main surface 21b in the first direction DR1 (i.e., in the thickness direction of the semiconductor element 20). The main surface 21b is the surface opposite to the main surface 21a. The semiconductor element 21 has an electrode 25 and an electrode 26 on the main surface 21a and the main surface 21b, respectively. The semiconductor element 21 is disposed on the land 12db such that the main surface 21b (electrode 26) faces the land 12db. A bonding material 27 is interposed between the land 12db and the electrode 26. The bonding material 27 is, for example, a conductive adhesive, and electrically connects the semiconductor element 21 and the land 12db (conductor pattern 12d).

[0031] The bonding wire 30 has a ball portion at one end. The bonding wire 30 is connected to the semiconductor element 20 (electrode 22) at one end, and to the land 12ab at the other end. The bonding wire 31 has a ball portion at one end. The bonding wire 31 is connected to the semiconductor element 21 (electrode 25) at one end, and to the land 12bb at the other end. The bonding wires 30 and 31 are made of, for example, gold.

[0032] The sealing resin 40 is disposed on the substrate 10 so as to cover the semiconductor element 20, the semiconductor element 21, the bonding wire 30, and the bonding wire 31. Insulating layers 15a to 15d are located inside the outer periphery of the sealing resin 40 in a plan view. The outer periphery of the sealing resin 40 in a plan view overlaps with, for example, the lands 12aa, 12ba, 12ca, and 12da. The constituent material of the sealing resin 40 is, for example, a transparent resin.

[0033] The surfaces of the conductive patterns 12a to 12d are preferably the farthest from the main surface 11b in the first direction DR1 on the substrate 10. The maximum width of each connection portion of the conductive patterns 12a to 12d is, for example, 80 μm or less.

[0034] Although not shown, a plating layer may be disposed on the surfaces of the conductor patterns 12a to 12d, the conductor patterns 13a to 13d, and the conductor layers 14a to 14d. However, this plating layer is not disposed on the surfaces of the conductor patterns 12a to 12d that are located inside the outer periphery of the sealing resin 40 in plan view. The constituent material of this plating layer is a solder such as tin or a tin alloy.

[0035] (Method of manufacturing semiconductor package 100) A method for manufacturing the semiconductor package 100 will be described below.

[0036] Fig. 4 shows a method for manufacturing the semiconductor package 100. As shown in Fig. 4, the method for manufacturing the semiconductor package 100 includes a preparation step S1, a semiconductor element mounting step S2, a wire bonding step S3, and a resin sealing step S4.

[0037] Fig. 5 is a plan view illustrating the preparation step S1. As shown in Fig. 5, in the preparation step S1, a substrate 10 is prepared. After the preparation step S1, a semiconductor element mounting step S2 is performed.

[0038] 6 is a plan view illustrating the semiconductor element mounting step S2. In the semiconductor element mounting step S2, as shown in FIG. 6, the semiconductor element 20 is mounted on the substrate 10. More specifically, in the semiconductor element mounting step S2, the electrodes 23 and the lands 12bb are bonded with the bonding material 24, thereby mounting the semiconductor element 20 on the lands 12bb. Similarly, in the semiconductor element mounting step S2, the semiconductor element 21 is also mounted on the lands 12db. After the semiconductor element mounting step S2, the wire bonding step S3 is performed.

[0039] 7 is a plan view illustrating the wire bonding step S3. As shown in FIG. 7, in the wire bonding step S3, the electrode 22 and the land 12ab are connected by wire bonding using a bonding wire 30. In the wire bonding, after the ball portion at one end of the bonding wire 30 is connected to the electrode 22, the other end of the bonding wire 30 is connected to the land 12ab. Similarly, in the wire bonding step S3, the electrode 25 and the land 12cb are connected by wire bonding using a bonding wire 31. After the wire bonding step S3, a resin sealing step S4 is performed.

[0040] FIG. 8A is a first cross-sectional view illustrating the resin sealing step S4. FIG. 8B is a second cross-sectional view illustrating the resin sealing step S4. As shown in FIGS. 8A and 8B, in the resin sealing step S4, sealing resin 40 is formed on substrate 10 so as to cover semiconductor element 20, semiconductor element 21, bonding wire 30, and bonding wire 31. Sealing resin 40 is formed, for example, by transfer molding. At this time, insulating layers 15a to 15d are disposed in an internal space defined by a mold used in the transfer molding method. Therefore, insulating layers 15a to 15d are located inside the outer periphery of sealing resin 40 in a plan view.

[0041] After the resin sealing step S4 is performed, the substrate 10 is cut to obtain the semiconductor package 100 having the structure shown in FIGS. 1 to 3B.

[0042] (Effects of Semiconductor Package 100) The effects of the semiconductor package 100 will be described below.

[0043] As described above, a plating layer may be formed on the surface of each conductor pattern and on the surface of each conductor layer in the semiconductor package 100. Because this plating layer is made of tin or a tin alloy, the constituent material of the plating layer melts when the semiconductor package 100 is mounted, and the molten constituent material of the plating layer tends to penetrate between the sealing resin 40 and each conductor pattern on the main surface 11a, and into a region inside the outer periphery of the sealing resin 40 in a plan view.

[0044] Furthermore, if the constituent material of the molten plating layer penetrates, it can cause the bonding wire 30 (bonding wire 31) to peel off from the land (land 12ab, land 12cb) or the semiconductor element 20 (semiconductor element 21) to peel off from the land (land 12bb, land 12db) on the main surface 11a.

[0045] The penetration of the constituent material of the molten plating layer can be suppressed by disposing insulating layers (insulating layer 15a, insulating layer 15b, insulating layer 15c, and insulating layer 15d) on the connection portions (connection portions 12ac, 12bc, 12cc, and 12dc) of each conductor pattern. However, if such insulating layers are located outside the outer periphery of sealing resin 40 in a planar view or overlap with the outer periphery of sealing resin 40 in a planar view, the distance between the outer periphery and the through holes (through hole 11g, through hole 11h, through hole 11i, and through hole 11j) formed in base material 11 must be increased, which increases the package size.

[0046] In this regard, in the semiconductor package 100, each insulating layer (insulating layer 15a, insulating layer 15b, insulating layer 15c, and insulating layer 15d) is arranged on the connection portion of each conductor pattern (connection portion 12ac, connection portion 12bc, connection portion 12cc, and connection portion 12dc) inside the outer peripheral edge of the sealing resin 40 in a planar view, so that it is possible to prevent the intrusion of the constituent material of the molten plating layer as described above while avoiding an increase in package size.

[0047] In the semiconductor package 100, the maximum width of each connection portion from the conductor patterns 12a to 12d is 80 μm or less. This allows the connection portions of the conductor patterns to be bent midway, as in the case of connection pattern 12ac. As a result, the distance between the lands (lands 12aa and 12ca) on the through-hole side and the bonding wires (bonding wires 30 and 31) can be increased, and even if the constituent material of the molten plating layer penetrates, it is unlikely to reach the lands (lands 12ab and 12cb) on the bonding wire side.

[0048] In the semiconductor package 100, the outer periphery of the sealing resin 40 in a plan view overlaps with the lands 12aa, 12ba, 12ca, and 12da. In addition, in the semiconductor package 100, for example, the copper layer of the conductor patterns 12a to 12d is formed thick, so that the surfaces of the conductor patterns 12a to 12d are furthest from the main surface 11b in the first direction DR1 on the substrate 10. Therefore, in the resin sealing step S4, the mold comes into strong contact with the surfaces of the conductor patterns 12a to 12d, which makes it possible to prevent the constituent material of the sealing resin 40 from leaking toward the through holes (from the through hole 11g to the through hole 11j) formed in the base material 11.

[0049] (Second embodiment) A semiconductor package according to the second embodiment will be described. The semiconductor package according to the second embodiment is referred to as a semiconductor package 200. Here, differences from the semiconductor package 100 will be mainly described, and overlapping descriptions will not be repeated.

[0050] 9 is a plan view of the semiconductor package 200. In FIG. 9, the through holes 11g to 11j and the sealing resin 40 are indicated by dotted lines. As shown in FIG. 9, the semiconductor package 200 has a substrate 10, a semiconductor element 20, bonding wires 30 and 31, and the sealing resin 40. In this respect, the configuration of the semiconductor package 200 is common to the configuration of the semiconductor package 100.

[0051] In the semiconductor package 200, the conductor pattern 12b has a land 12bd instead of the land 12bb, and a connection portion 12be instead of the connection portion 12bc. The connection portion 12be has a third portion 12be1 and a fourth portion 12be2. The third portion 12be1 extends from the land 12ba along the third direction DR3. The fourth portion 12be2 extends from an end of the third portion 12be1 opposite the land 12ba along the second direction DR2 to the side opposite the side surface 11c and is connected to the land 12bd.

[0052] In the semiconductor package 200, the conductor pattern 12d further includes a land 12dd. The land 12dd is disposed adjacent to the land 12db and is connected to the land 12db. In the semiconductor package 200, the semiconductor element 20 is disposed on the land 12dd so that the main surface 20b faces the land 12dd with the bonding material 24 interposed therebetween. Note that in the semiconductor package 200, the semiconductor element 20 does not include electrodes 23, and the bonding material 24 does not electrically connect the semiconductor element 20 to the land 12dd.

[0053] In the semiconductor package 200, the semiconductor element 20 has electrodes 22a and 22b instead of the electrode 22. In the semiconductor package 200, a bonding wire 30 is connected at one end to the electrode 22a and at the other end to the land 12ab. The semiconductor package 200 further has a bonding wire 32. The bonding wire 32 has a ball portion at one end. The bonding wire 32 is connected at one end (ball portion) to the electrode 22b and at the other end to the land 12bd.

[0054] In the semiconductor package 200, the sealing resin 40 is disposed on the substrate 10 so as to cover the semiconductor element 20, the semiconductor element 21, the bonding wire 30, the bonding wire 31, and the bonding wire 32. In these respects, the configuration of the semiconductor package 200 differs from the configuration of the semiconductor package 100.

[0055] In the semiconductor package 200, insulating layers (insulating layer 15a, insulating layer 15b, insulating layer 15c, and insulating layer 15d) are also arranged on each connection portion from the conductor pattern 12a to the conductor pattern 12d, and the insulating layers are located inside the outer edge of the sealing resin 40 in a planar view. Therefore, similar to the semiconductor package 100, it is possible to reduce the package size while suppressing the penetration of the molten plating layer.

[0056] (Third embodiment) A semiconductor package according to the third embodiment will be described. The semiconductor package according to the third embodiment is designated as semiconductor package 300. Here, differences from semiconductor package 200 will be mainly described, and overlapping descriptions will not be repeated.

[0057] 10 is a plan view of the semiconductor package 300. In FIG. 10, the through holes 11g to 11j and the sealing resin 40 are indicated by dotted lines. As shown in FIG. 10, the semiconductor package 300 has a substrate 10, a semiconductor element 20, a bonding wire 30, a bonding wire 31, and a bonding wire 32, and the sealing resin 40. In this respect, the configuration of the semiconductor package 300 is common to the configuration of the semiconductor package 200.

[0058] In the semiconductor package 300, the substrate 10 does not have a conductor pattern 12b or an insulating layer 15b. In the semiconductor package 200, the conductor pattern 12d further has a land 12de. The land 12de is disposed adjacent to the land 12dd and connected to the land 12dd. In the semiconductor package 300, one end (ball portion) of the bonding wire 32 is connected to the electrode 22b and the other end is connected to the land 12de. In the semiconductor package 200, the main surface 21b is disposed on the land 12db so as to face the land 12db with the bonding material 27 interposed therebetween. In the semiconductor package 300, the semiconductor element 21 does not have an electrode 26, and the bonding material 27 does not electrically connect the semiconductor element 21 and the land 12db.

[0059] In the semiconductor package 200, the semiconductor element 21 has electrodes 25a and 25b instead of the electrode 25. In the semiconductor package 200, a bonding wire 31 is connected at one end to the electrode 25a and at the other end to the land 12cb. The semiconductor package 300 further has a bonding wire 33. The bonding wire 33 has a ball portion at one end. The bonding wire 33 is connected at one end (ball portion) to the electrode 25b and at the other end to the land 12de.

[0060] In the semiconductor package 300, insulating layers (insulating layer 15a, insulating layer 15c, and insulating layer 15d) are also arranged on each connection portion from the conductor pattern 12a to the conductor pattern 12c, and the insulating layers are located inside the outer edge of the sealing resin 40 in a planar view. Therefore, similar to the semiconductor package 200, it is possible to reduce the package size while suppressing the penetration of the molten plating layer.

[0061] (Addendum) Each embodiment of the present disclosure includes the following configurations.

[0062] <Appendix 1> A semiconductor package comprising: A substrate; A semiconductor element; A bonding wire; and a sealing resin. the substrate includes a base material, a first conductor pattern, a second conductor pattern, a third conductor pattern, a first conductor layer, and a first insulating layer; the substrate has a first main surface and a second main surface opposite to the first main surface in a first direction that is a thickness direction of the substrate, a first through hole penetrating the base material along the first direction is formed in the base material; the first conductor pattern and the second conductor pattern are disposed on the first main surface; the first conductor pattern has a first land; the second conductor pattern has a second land, the third conductor pattern is disposed on the second principal surface, the first conductor layer is disposed on an inner wall surface of the first through hole and connects the first conductor pattern and the third conductor pattern; the semiconductor element is disposed on the second land, the bonding wire is connected to the semiconductor element at one end and to the first land at the other end; the first insulating layer is disposed on the first conductor pattern between the first conductor layer and the first land; the sealing resin is disposed on the substrate so as to cover the semiconductor element; The semiconductor package, wherein the first insulating layer is located inside the outer periphery of the sealing resin in a plan view.

[0063] <Appendix 2> the base material has a first side surface that is an end surface in a second direction perpendicular to the first direction, and a second side surface that is an end surface in a third direction perpendicular to both the first direction and the second direction, 2. The semiconductor package of claim 1, wherein the first through hole is formed in a corner of the base where the first side surface and the second side surface are connected.

[0064] <Appendix 3> the substrate has a third side surface opposite the first side surface, 3. The semiconductor package of claim 2, wherein the third side surface forms a mounting surface of the semiconductor package.

[0065] <Appendix 4> the substrate has a second insulating layer; a second through hole penetrating the base material along the thickness direction is formed in the base material; the substrate has a fourth conductor pattern and a second conductor layer; the fourth conductor pattern is disposed on the second principal surface, the second conductor layer is disposed on an inner wall surface of the second through hole and connects the second conductor pattern and the fourth conductor pattern; the second insulating layer is disposed on the second conductor pattern between the second conductor layer and the second lands; 2. The semiconductor package of claim 1, wherein the second insulating layer is located inside the outer periphery of the sealing resin in a plan view.

[0066] <Appendix 5> the base material has a first side surface which is an end surface in a second direction perpendicular to the first direction, a second side surface which is an end surface in a third direction perpendicular to both the first direction and the second direction, a third side surface which is an opposite surface to the first side surface, and a fourth side surface which is an opposite surface to the second side surface; 5. The semiconductor package of claim 4, wherein the second through hole is formed in a corner of the base where the first side surface and the fourth side surface are connected.

[0067] <Appendix 6> 6. The semiconductor package of claim 5, wherein the third side surface forms a mounting surface of the semiconductor package.

[0068] <Appendix 7> the substrate has a plating layer; the plating layer is made of tin or a tin alloy; 7. The semiconductor package of claim 1, wherein the plating layer is disposed on the first conductor pattern, the third conductor pattern, and the first conductor layer.

[0069] <Appendix 8> 10. The semiconductor package of claim 1, wherein the surface of the first conductor pattern is located at a position on the substrate farthest from the second main surface in the first direction.

[0070] <Appendix 9> the first conductor pattern has a third land and a connection portion, the third land is disposed around the first through hole and connected to the first conductor layer; the connection portion connects the first land and the third land, 9. The semiconductor package of any one of Supplementary Note 1 to Supplementary Note 8, wherein the first insulating layer is disposed on the connection portion.

[0071] <Appendix 10> The connection portion is the connecting portion has a first portion and a second portion, the first portion extends from the third land along a third direction perpendicular to both the first direction and a second direction perpendicular to the first direction; the first portion extends from an end of the first portion opposite to the third land along the second direction and is connected to the first land; 10. The semiconductor package of claim 9, wherein the first insulating layer is disposed on the first portion.

[0072] <Appendix 11> 11. The semiconductor package of claim 10, wherein the maximum width of the connection portion is 80 μm or less.

[0073] <Appendix 12> 12. The semiconductor package of any one of Supplementary Notes 1 to 11, wherein the semiconductor element is an LED.

[0074] Although the embodiments of the present disclosure have been described above, the above-described embodiments can be modified in various ways. Furthermore, the scope of the present invention is not limited to the above-described embodiments. The scope of the present invention is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0075] 100 semiconductor package, 10 substrate, 11 base material, 11a main surface, 11b main surface, 11c, 11d, 11e, 11f side surface, 11g, 11h, 11i, 11j through holes, 12a conductive pattern, 12aa, 12ab lands, 12ac connection portion, 12ac2 second portion, 12ac1 first portion, 12b conductive pattern, 12ba, 12bb lands, 12bc connection portion, 12bd lands, 12be connection portion, 12be1 third portion, 12be2 fourth portion, 12c conductive pattern, 12ca, 12cb lands, 12cc connection portion, 12da, 12db lands, 12dc connection portion, 12dd, 12de lands, 13a conductive pattern, 13aa, 13ab lands, 13ac connection portion, 13a Conductive pattern, 13ba, 13bb lands, 13bc connection portion, 13c conductor pattern, 13ca land, 13d conductor pattern, 13da land, 14a, 14b, 14c, 14d conductor layer, 15a, 15b, 15c, 15d, 15e, 15f insulating layer, 20 semiconductor element, 20a, 20b main surface, 21 semiconductor element, 21a, 21b main surface, 22, 22a, 22b, 23 electrode, 24 bonding material, 25, 25a, 25b, 26 electrode, 27 bonding material, 30, 31, 32, 33 bonding wire, 40 sealing resin, 200, 300 semiconductor package, DR1 first direction, DR2 second direction, DR3 third direction, S1 preparation process, S2 semiconductor element mounting process, S3 wire bonding process, S4 Resin sealing process.

Claims

1. A semiconductor package comprising: A substrate; A semiconductor element; A bonding wire; and a sealing resin. the substrate includes a base material, a first conductor pattern, a second conductor pattern, a third conductor pattern, a first conductor layer, and a first insulating layer; the substrate has a first main surface and a second main surface opposite to the first main surface in a first direction that is a thickness direction of the substrate, a first through hole penetrating the base material along the first direction is formed in the base material; the first conductor pattern and the second conductor pattern are disposed on the first main surface; the first conductor pattern has a first land; the second conductor pattern has a second land, the third conductor pattern is disposed on the second principal surface, the first conductor layer is disposed on an inner wall surface of the first through hole and connects the first conductor pattern and the third conductor pattern; the semiconductor element is disposed on the second land, the bonding wire is connected to the semiconductor element at one end and to the first land at the other end; the first insulating layer is disposed on the first conductor pattern between the first conductor layer and the first land; the sealing resin is disposed on the substrate so as to cover the semiconductor element; The semiconductor package, wherein the first insulating layer is located inside the outer periphery of the sealing resin in a plan view.

2. the base material has a first side surface that is an end surface in a second direction perpendicular to the first direction, and a second side surface that is an end surface in a third direction perpendicular to both the first direction and the second direction, The semiconductor package according to claim 1 , wherein the first through hole is formed in a corner of the base material where the first side surface and the second side surface are connected.

3. the substrate has a third side surface opposite the first side surface, The semiconductor package according to claim 2 , wherein the third side surface forms a mounting surface of the semiconductor package.

4. the substrate has a second insulating layer; a second through hole penetrating the base material along the thickness direction is formed in the base material; the substrate has a fourth conductor pattern and a second conductor layer; the fourth conductor pattern is disposed on the second principal surface, the second conductor layer is disposed on an inner wall surface of the second through hole and connects the second conductor pattern and the fourth conductor pattern; the second insulating layer is disposed on the second conductor pattern between the second conductor layer and the second lands; The semiconductor package according to claim 1 , wherein the second insulating layer is located inside an outer periphery of the sealing resin in a plan view.

5. the base material has a first side surface which is an end surface in a second direction perpendicular to the first direction, a second side surface which is an end surface in a third direction perpendicular to both the first direction and the second direction, a third side surface which is an opposite surface to the first side surface, and a fourth side surface which is an opposite surface to the second side surface; The semiconductor package according to claim 4 , wherein the second through hole is formed in a corner of the base material where the first side surface and the fourth side surface are connected.

6. The semiconductor package according to claim 5 , wherein the third side surface forms a mounting surface of the semiconductor package.

7. the substrate has a plating layer; the plating layer is made of tin or a tin alloy; 2. The semiconductor package according to claim 1, wherein the plating layer is disposed on the first conductor pattern, the third conductor pattern, and the first conductor layer.

8. The semiconductor package according to claim 1 , wherein a surface of the first conductor pattern is located at a position on the substrate farthest from the second main surface in the first direction.

9. the first conductor pattern has a third land and a connection portion, the third land is disposed around the first through hole and connected to the first conductor layer; the connection portion connects the first land and the third land, The semiconductor package according to claim 1 , wherein the first insulating layer is disposed on the connecting portion.

10. The connection portion is the connecting portion has a first portion and a second portion; the first portion extends from the third land along a third direction perpendicular to both the first direction and a second direction perpendicular to the first direction; the first portion extends from an end of the first portion opposite to the third land along the second direction and is connected to the first land; The semiconductor package of claim 9 , wherein the first insulating layer is disposed on the first portion.

11. 11. The semiconductor package according to claim 10, wherein the maximum width of the connection portion is 80 [mu]m or less.

12. The semiconductor package according to claim 1 , wherein the semiconductor element is an LED.

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