Semiconductor device
By employing stacked insulating layers and connecting conductors, the semiconductor device achieves a substantial increase in fringe capacitance, addressing the challenge of capacitance limitations in existing designs.
Patent Information
- Application Number
- JP2024020615
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-14
- Publication Date
- 2025-08-26
AI Technical Summary
Existing semiconductor devices face challenges in achieving a larger fringe capacitance when formed by a pair of wirings.
The semiconductor device incorporates three or more stacked insulating layers with pairs of wirings extending in-plane and connecting conductors that electrically connect adjacent layers, allowing for fringe capacitance generation between both wirings and connecting conductors.
This configuration results in a significantly larger fringe capacitance compared to devices without connecting conductors, enhancing capacitive performance.
Smart Images
Figure 2025124510000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to semiconductor devices. [Background technology]
[0002] Patent document 1 describes a semiconductor device in which a metal fringe capacitance is composed of a first electrode and a second electrode that face each other in the planar direction with an interlayer insulating film sandwiched therebetween, and further, the first electrode and the second electrode are composed of four-layer plugs that connect each of the wirings stacked in the vertical direction between the first layer wiring (the wiring in the lowest layer) and the fifth layer wiring (the wiring in the highest layer). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-86701 Summary of the Invention [Problem to be solved by the invention]
[0004] In a semiconductor device in which a fringe capacitance is formed by a pair of wirings, it is sometimes required to obtain a larger fringe capacitance.
[0005] The present disclosure aims to obtain a large fringe capacitance in a semiconductor device in which a fringe capacitance is formed by a pair of wirings. [Means for solving the problem]
[0006] The semiconductor device of the present disclosure comprises three or more stacked insulating layers, a pair of wirings provided in each of the insulating layers, extending in an in-plane direction of the insulating layer and including wiring opposing portions that face each other in-plane, and a connecting conductor that electrically connects the wirings of adjacent insulating layers and extends in the direction in which the wirings extend. [Effects of the Invention]
[0007] According to the present disclosure, a large fringe capacitance can be obtained in a semiconductor device in which a fringe capacitance is formed by a pair of wirings. [Brief explanation of the drawings]
[0008] [Figure 1A] FIG. 1A is a plan view showing a semiconductor device according to a first embodiment. [Figure 1B] FIG. 1B is a cross-sectional view of the semiconductor device of the first embodiment taken along line BB in FIG. 1A. [Figure 2A] FIG. 2A is a plan view showing a semiconductor device of a comparative example. [Figure 2B] FIG. 2B is a cross-sectional view of the semiconductor device of the comparative example taken along line BB in FIG. 2A. [Figure 3A] FIG. 3A is a plan view showing a semiconductor device according to a second embodiment. [Figure 3B] FIG. 3B is a cross-sectional view of the semiconductor device according to the second embodiment taken along line BB in FIG. 3A. [Figure 4A] FIG. 4A is a plan view showing a semiconductor device according to a third embodiment. [Figure 4B] FIG. 4B is an enlarged plan view showing the semiconductor device of the third embodiment. [Figure 5] FIG. 5 is a plan view showing a semiconductor device according to the fourth embodiment. [Figure 6] FIG. 6 is a plan view showing a semiconductor device according to the fifth embodiment. [Figure 7] FIG. 7 is a plan view showing a semiconductor device according to the sixth embodiment. [Figure 8A] FIG. 8A is a plan view showing a semiconductor device according to a seventh embodiment. [Figure 8B] FIG. 8B is a cross-sectional view taken along line BB in FIG. 8A, showing the semiconductor device according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0009] Hereinafter, a semiconductor device according to the present disclosure will be described with reference to the drawings.
[0010] Fig. 1A shows a plan view of a schematic configuration of a semiconductor device 102 according to a first embodiment, and Fig. 1B shows a cross-sectional view of the semiconductor device 102 taken along line BB in Fig. 1A.
[0011] As shown in FIG. 1B, the semiconductor device 102 of the disclosed technology has three or more insulating layers 22. These insulating layers 22 are stacked. In the example shown in FIG. 1B, there are three insulating layers 22. When distinguishing between the three insulating layers 22, they are referred to as insulating layer 22-1, insulating layer 22-2, and insulating layer 22-3. The insulating layers 22 are film-like members having insulating properties, and may be made of, for example, silicon oxide film (SiO2), silicon nitride film (Si3N4), or the like.
[0012] Wiring 24 is provided on each insulating layer 22. In the example shown in Figures 1A and 1B, two wirings are provided as a pair on one insulating layer 22. When distinguishing between the two wirings 24, they are referred to as wiring 24A and wiring 24B.
[0013] As shown in Fig. 1A, each of the wirings 24 has a wiring trunk 24M and wiring branches 24E, and is formed in a comb-like shape in a plan view. The wiring trunk 24M extends in one direction (the direction of arrow Y in Fig. 1A). Multiple wiring branches 24E (four in Fig. 1A) branch off at right angles from one wiring trunk 24M. The multiple wiring branches 24E have the same length and are parallel to each other.
[0014] Two wirings 24 located on one insulating layer 22 are arranged such that wiring branch 24E of one wiring 24B is located between wiring branch 24E of the other wiring 24A. As shown in Fig. 1B, wiring branch 24E of one wiring 24A faces wiring branch 24E of the other wiring 24B in each insulating layer 22. As a result, a predetermined fringe capacitance is generated between wiring branch 24E of wiring 24A and wiring branch 24E of the other wiring 24B in each insulating layer 22.
[0015] 1B, connecting conductors 26 are provided between adjacent insulating layers 22, between insulating layer 22-1 and insulating layer 22-2, and between insulating layer 22-2 and insulating layer 22-3. The connecting conductors 26 electrically connect the wirings 24 of the two adjacent insulating layers 22. Hereinafter, the connecting conductor connecting wiring 24A will be referred to as connecting conductor 26A, and the connecting conductor connecting wiring 24B will be referred to as connecting conductor 26B, as appropriate.
[0016] 1A, the connecting conductor 26 has a rectangular shape in a plan view. In the first embodiment, the connecting conductor 26 has a rectangular shape in a plan view that overlaps with the wiring branch portion 24E and whose longitudinal direction is the same as the extension direction of the wiring branch portion 24E. In other words, the longitudinal direction of the wiring branch portion 24E and the longitudinal direction of the connecting conductor 26 coincide with each other as indicated by arrow X.
[0017] The connecting conductors 26A and 26B are arranged parallel to each other within the same range in the longitudinal direction (the direction of the arrow X). Therefore, the connecting conductors 26A and 26B face each other across the entire longitudinal direction with a constant distance D2 therebetween.
[0018] The surfaces of the connecting conductors 26A and 26B that face each other are referred to as conductor facing surfaces 26F. In the first embodiment, the conductor facing surfaces 26F have a flat shape. In the first embodiment, the entire conductor facing surfaces 26F are the facing portions in the technology disclosed herein.
[0019] Next, the operation of this embodiment will be described.
[0020] In the semiconductor device 102 of the first embodiment, the wiring branches 24E of the two wirings 24A and 24B located on one insulating layer 22 face each other. Therefore, fringe capacitance occurs between the wiring branches 24E, and the semiconductor device 102 acts as a capacitive element.
[0021] Furthermore, in the semiconductor device 102 of the first embodiment, the connecting conductors 26A and 26B located on one insulating layer 22 also face each other. Therefore, fringe capacitance is also generated between the connecting conductors 26A and 26B, and the semiconductor device 102 acts as a capacitive element.
[0022] 2A and 2B show a semiconductor device 92 of the comparative example. In the semiconductor device 92 of the comparative example, a connection conductor 94 that electrically connects the wirings 24 is provided between adjacent insulating layers 22. In the semiconductor device 92 of the comparative example, the connection conductor 94 is square in plan view and does not extend in the longitudinal direction of the wirings 24 (the direction of arrow X). Furthermore, the semiconductor device 92 of the comparative example does not have a connection conductor that is rectangular in plan view, like the connection conductor 26 of the semiconductor device 102 of the first embodiment.
[0023] In the semiconductor device 92 of the comparative example, fringe capacitance occurs between the two wirings 24A and 24B on one insulating layer 22. However, no fringe capacitance occurs between the connecting conductors 94.
[0024] More specifically, when the length of the portion where the wiring 24A and the wiring 24B face each other is L1, the height of the facing portion is H1, and the distance between the wiring 24A and the wiring 24B is D1, the dielectric constant of a vacuum is ε0 and the relative dielectric constant of the insulating layer is ε r Using the above, the fringe capacitance Cm of the wirings 24A and 24B per layer is given by Cm=ε0×ε r ×L1×H1 / D1 Since the actual fringe capacitance is proportional to the number of layers n of the wirings 24A and 24B (n=3 in the example shown in FIG. 1B), the fringe capacitance of the n-layer wirings 24A and 24B is given by Cm=n×ε0×ε r ×L1×H1 / D1 This is equal to the overall fringe capacitance Cf in the semiconductor device 92 of the comparative example.
[0025] In contrast, in the semiconductor device 102 of the first embodiment, a fringe capacitance also occurs between the connecting conductors 26A and 26B. Therefore, a larger fringe capacitance can be obtained compared to the semiconductor device 102 of the comparative example. Specifically, assuming that the length of the portion where the connecting conductors 26A and 26B face each other is L2, the height of the facing portion is H2, and the distance between the connecting conductors 26A and 26B is D2, the fringe capacitance Cv of the connecting conductors 26A and 26B per layer is Cv=ε0×ε r ×L2×H2 / D2 Since the number of layers of the connecting conductors 26A and 26B is (n-1), the fringe capacitance Cv of the connecting conductors 26A and 26B in the (n-1)th layer is given by Cv=(n-1)×ε0×εr×L2×H2 / D2 The overall fringe capacitance Cf of the semiconductor device 102 of the first embodiment is given by: Cf=Cm+Cv is.
[0026] As described above, the semiconductor device 102 of the first embodiment has a larger fringe capacitance than the semiconductor device 92 of the comparative example.
[0027] Furthermore, in the semiconductor device 102 of the first embodiment, wiring 24 is provided in each of the three or more insulating layers 22, and the number of wiring 24 is also three or more. Furthermore, connecting conductors 26 are present between the layers of the wiring 24. The fringe capacitance of the semiconductor device 102 is obtained by combining the fringe capacitance generated by the wiring 24 in each layer and the fringe capacitance generated by the connecting conductors 26 between the layers. Therefore, a larger fringe capacitance can be obtained compared to, for example, a configuration in which the wiring 24 is in two layers or a configuration in which there are no connecting conductors between the layers of the wiring 24. Furthermore, in the semiconductor device 102 of the first embodiment, the wiring 24 and the connecting conductors 26 are essentially stacked alternately, and by generating fringe capacitance in each of these layers, it can be said that a structure is realized in which the semiconductor device 102 as a whole can obtain a large fringe capacitance.
[0028] The width W2 of the connecting conductor 26 is not particularly limited, but for example, by making it narrower than the width W1 of the wiring branch portion 24E, peeling from the wiring branch portion 24E can be suppressed. The connecting conductor 26 can be formed, for example, by a process similar to that used to form various elements on the insulating layer 22 by photolithography.
[0029] Next, a second embodiment will be described. In the following embodiments, the same elements, members, etc. as those in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted.
[0030] 3A and 3B, the semiconductor device 202 of the second embodiment has a polysilicon layer 28 below the insulating layer 22-1. Wirings 30A and 30B are provided on the polysilicon layer 28. Furthermore, connecting conductors 32A and 32B are provided to electrically connect the wirings 30A and 30B to the wiring 24 of the insulating layer 22-3. The shapes of the connecting conductors 32A and 32B in a plan view are similar to those of the connecting conductors 26A and 26B, for example.
[0031] An isolation film 34 is formed below the polysilicon layer 28. The semiconductor device 202 is electrically isolated from other semiconductor devices by the isolation film 34. Examples of the isolation film 34 include LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation). The semiconductor device 202 of the second embodiment is applied to, for example, a MOS transistor.
[0032] In the semiconductor device 202 of the second embodiment configured as described above, fringe capacitance also occurs in the wirings 30A and 30B of the polysilicon layer 28. Furthermore, fringe capacitance also occurs in the connecting conductors 32A and 32B of the polysilicon layer 28. In the semiconductor device 202 of the second embodiment, if the fringe capacitance of the wirings 30A and 30B is Cp and the fringe capacitance of the connecting conductors 32A and 32B is Cc, then the overall fringe capacitance Cf is Cf=Cm+Cv+Cc This becomes:
[0033] Next, a third embodiment will be described.
[0034] 4A and 4B, in a semiconductor device 302 of the third embodiment, the connecting conductors 26A and 26B are provided with protrusions 36. The protrusions 36 are provided on the surfaces of the connecting conductors 26A and 26B that face the other connecting conductors 26A and 26B.
[0035] The provision of the protrusions 36 increases the area of each of the connecting conductors 26A, 26B facing the other connecting conductors 26A, 26B. This makes it possible to ensure a larger fringe capacitance compared to a configuration without the protrusions 36. Furthermore, in order to obtain the desired fringe capacitance, it is possible to reduce the size by shortening the length of the connecting conductors 26A, 26B, for example.
[0036] In this way, the shape of each of the connecting conductors 26A, 26B for widening the area facing the other connecting conductor 26A, 26B is not limited to the convex portion 36. For example, a concave portion may be provided instead of the convex portion 36, or a convex portion and a concave portion may be used together. The number of convex portions and concave portions is also not limited, and even if there is only one, a wide facing area can be ensured.
[0037] Next, a fourth embodiment will be described.
[0038] As shown in FIG. 5, a semiconductor device 402 according to the fourth embodiment includes connecting conductors 38A and 38B in addition to connecting conductors 26A and 26B (see FIGS. 2A and 2B, etc.).
[0039] The connecting conductor 38A connects the upper and lower trunk wiring portions 24M of the wiring 24A. The connecting conductor 38A is rectangular in plan view, and its longitudinal direction is the same as the longitudinal direction of the trunk wiring portion 24M, that is, the arrow Y direction.
[0040] The connecting conductor 38B connects the upper and lower trunk wiring portions 24M of the wiring 24B. The connecting conductor 38B is rectangular in plan view, and its longitudinal direction is the same as the longitudinal direction of the trunk wiring portion 24M, ie, the arrow Y direction.
[0041] In the semiconductor device 402 of the fourth embodiment, a portion of the side surface of the connecting conductor 38A faces the end surface 26BT of each connecting conductor 26B. This causes fringe capacitance between the connecting conductor 38A and the connecting conductor 26B. Similarly, a portion of the side surface of the connecting conductor 38B faces the end surface 26AT of each connecting conductor 26A. This causes fringe capacitance between the connecting conductor 38B and the connecting conductor 26A. Therefore, it is possible to ensure a larger fringe capacitance compared to a configuration in which the connecting conductors 38A and 38B are not provided.
[0042] Next, a fifth embodiment will be described.
[0043] As shown in Fig. 6, in the semiconductor device 502 of the fifth embodiment, the connecting conductors 26A and 26B are shorter than, for example, the connecting conductors 26A and 26B of the semiconductor device 102 of the first embodiment. As can be seen from Fig. 6, the connecting conductor 26A of the fifth embodiment is offset toward the tip of each of the wiring branch portions 24E. The connecting conductor 26B is offset toward the tip of each of the wiring branch portions 24E. When viewed in the direction of arrow Y, the connecting conductors 26A and 26B form a conductor-facing surface 26F at a part of their longitudinal direction.
[0044] In the semiconductor device 502 of the fifth embodiment, the connecting conductors 26A and 26B are opposed to each other only partially, rather than entirely, in the longitudinal direction. Even with this configuration, it is possible to ensure a larger fringe capacitance than in a configuration in which the connecting conductors 26A and 26B are not provided.
[0045] Next, a sixth embodiment will be described.
[0046] 7, in a semiconductor device 602 of the sixth embodiment, the connecting conductors 26A and 26B are even shorter than the connecting conductors 26A and 26B of the semiconductor device 502 of the fifth embodiment. In the sixth embodiment, the connecting conductors 26A and 26B have no portions that face each other when viewed in the direction of arrow Y.
[0047] Even in the semiconductor device 602 of the sixth embodiment configured as described above, fringe capacitance occurs in the region E1 between the connecting conductors 26A and 26B (a parallelogram region inclined in the direction of arrow X with respect to the direction of arrow Y), as shown by the two-dot chain line in Fig. 7. Therefore, it is possible to ensure a larger fringe capacitance compared to a configuration in which the connecting conductors 26A and 26B are not provided.
[0048] Next, a seventh embodiment will be described.
[0049] As shown in Figures 8A and 8B, in a semiconductor device 702 of the seventh embodiment, connecting conductors 26A and 32A are provided but connecting conductors 26B and 32B are not provided. Wirings 24A on adjacent layers are electrically connected to each other by connecting conductor 26A. Wirings 30A and 24A are electrically connected to each other by connecting conductor 32A. In contrast, wirings 24B on adjacent layers are connected to each other by connecting conductor 44 instead of connecting conductor 26B. Similarly, wirings 30B and 24B are also connected by connecting conductor 44. Connecting conductor 44 has a square shape in a plan view. Connecting conductor 44 is located away from connecting conductor 26A in the direction of arrow X.
[0050] In the semiconductor device 702 of the seventh embodiment configured as described above, a fringe capacitance occurs in a region E2 (a region of a substantially parallelogram inclined in the direction of arrow Z with respect to the direction of arrow Y) between the connecting conductor 26A and the wiring branch portions 24E of the wiring 24B above and below it, as shown by the two-dot chain line in Fig. 8B. Therefore, even in a configuration in which the connecting conductor 26B is not provided, the provision of the connecting conductor 26A makes it possible to ensure a larger fringe capacitance.
[0051] Furthermore, the following notes are disclosed: (Appendix 1) Three or more laminated insulating layers; a pair of wirings each provided in the insulating layer, extending in an in-plane direction of the insulating layer, and including wiring opposing portions opposing each other in the plane; a connecting conductor electrically connecting the wirings of the adjacent insulating layers and extending in the direction in which the wirings extend; A semiconductor device having: (Appendix 2) 2. The semiconductor device according to claim 1, wherein the wiring opposing portions of the wiring are parallel to each other. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the connecting conductors are provided in pairs in one of the insulating layers. (Appendix 4) 4. The semiconductor device according to claim 3, wherein the pair of connecting conductors has opposing portions that face each other in one of the insulating layers. (Appendix 5) 5. The semiconductor device according to claim 4, wherein the facing portion has a flat shape in the facing direction. (Appendix 6) 5. The semiconductor device according to claim 4, wherein the opposing portions have a shape having a convex portion or a concave portion in the opposing direction. (Appendix 7) A semiconductor device as described in Appendix 1, wherein each of the pair of wirings in one of the insulating layers is comb-shaped and has a wiring trunk extending in one direction and wiring branch portions that branch off from the wiring trunk and extend parallel to and face each other. (Appendix 8) 8. The semiconductor device according to claim 7, wherein the connection conductor includes a portion extending in the same direction as the wiring branch portion. (Appendix 9) 9. The semiconductor device according to claim 8, wherein the connecting conductor includes a portion extending in the same direction as the wiring trunk. [Explanation of symbols]
[0052] 22 Insulating layer 24 Wiring 24E Wiring branch 24M Wiring Executive 26 Connecting conductor 26F Conductor facing surface 28 Polysilicon layer 30A, 30B wiring 32A, 32B connecting conductor 34 Element isolation film 36 Convex part 38A, 38B connecting conductor 102 Semiconductor devices 202 Semiconductor devices 302 Semiconductor devices 402 Semiconductor devices 502 Semiconductor devices 602 Semiconductor devices 702 Semiconductor devices
Claims
1. Three or more insulating layers stacked together; a pair of wirings each provided in the insulating layer, extending in an in-plane direction of the insulating layer, and including wiring opposing portions opposing each other in the plane; a connecting conductor electrically connecting the wirings of the adjacent insulating layers and extending in the direction in which the wirings extend; A semiconductor device having:
2. 2. The semiconductor device according to claim 1, wherein the opposing portions of the wirings are parallel to each other.
3. 2. The semiconductor device according to claim 1, wherein the connecting conductors are provided in pairs on one of the insulating layers.
4. 4. The semiconductor device according to claim 3, wherein the pair of connecting conductors has opposing portions that face each other on one of the insulating layers.
5. 5. The semiconductor device according to claim 4, wherein the facing portion has a flat shape in the facing direction.
6. The semiconductor device according to claim 4 , wherein the facing portions have a shape having a convex portion or a concave portion in the facing direction.
7. 2. The semiconductor device according to claim 1, wherein each of the pair of wirings in one of the insulating layers is comb-shaped and includes a wiring trunk extending in one direction and wiring branch portions branching off from the wiring trunk and extending parallel to and facing each other.
8. 8. The semiconductor device according to claim 7, wherein said connecting conductor includes a portion extending in the same direction as said wiring branch portion.
9. 9. The semiconductor device according to claim 8, wherein said connecting conductor includes a portion extending in the same direction as said wiring trunk.
Citation Information
Patent Citations
Semiconductor device and method for manufacturing the same
JP2011086701A
Cited By
Game machine
JP2026056552A