Module configurations for integrated iii-nitride devices

Abstract

To provide electronic modules and half-bridge circuits allowing higher circuit stability, improved performance, and lower production costs.SOLUTION: An electronic module 500 for a half-bridge circuit includes a base substrate 510 with an insulating layer between a first metal layer and a second metal layer. A trench 514 formed through the first metal layer electrically isolates a first portion 511, a second portion 512 and a third portion 513 from one another. A high-side switch 582 includes an enhancement (E)-mode transistor and a depletion (D)-mode transistor. The D-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode 636 is connected to the first portion. A source electrode 651 of the E-mode transistor is connected to the second portion. A drain electrode of the E-mode transistor is connected to a source electrode 634 of the D-mode transistor. A gate electrode of the D-mode transistor is connected to the electrically conductive substrate. The electrically conductive substrate is connected to the second portion.SELECTED DRAWING: Figure 5A

Description

[Technical Field]

[0001] The disclosed technology relates to semiconductor electronic modules designed to achieve improved performance and reliability. [Background technology]

[0002] [background] Currently, typical power semiconductors (including devices such as transistors, diodes, power MOSFETs, and insulated gate bipolar transistors (IGBTs)) are fabricated with silicon (Si) semiconductor materials. More recently, wide bandgap materials (SiC, III-N, III-O, and diamond) have been considered for power devices due to their superior properties. III-nitride or III-N semiconductor devices (such as gallium nitride (GaN) devices) are emerging as attractive candidates for carrying large currents, supporting high voltages, and offering ultra-low on-resistance with fast switching times.

[0003] FIG. 1A shows a half-bridge circuit schematic 100 including a high-side switching transistor 102 and a low-side switching transistor 103. The half-bridge circuit has a high-potential node 111 and a low-potential or ground node 113. The output node 112 of the half-bridge (between the source of high-side transistor 102 and the drain of low-side transistor 103) is connected to the load motor (inductive component 104). To ensure proper operation of the circuit of FIG. 1A, the DC high-potential node 111 must be maintained as an AC ground. That is, node 111 may be capacitively coupled to DC ground 113 by connecting one terminal of capacitor 106 to the high-potential node 111 and the other terminal of the capacitor to ground 113. Thus, when either transistor 102 or 103 is switched on or off, capacitor 106 can be charged or discharged appropriately to provide the current necessary to maintain substantially constant voltages on the high and low sides of the circuit.

[0004] A circuit schematic of a three-phase full-bridge circuit 120 configured to drive a three-phase motor is shown in Figure 1B. Three half-bridges 122, 124, and 126 in circuit 120 each include two transistors (141-146) (such as the half-bridges in Figure 1A). Each of the three half-bridges has an output node 137, 138, and 139. Each transistor in the circuit is capable of blocking voltage in a first direction and conducting current in a first direction (or optionally bidirectionally).

[0005] One type of transistor that shows promising advantages when used in the circuits of FIGS. 1A and 1B is the III-N high electron mobility transistor (HEMT). It can be used as transistor 102 and / or transistor 103 in the half bridge of FIG. 1A, or as any of the transistors in the bridge circuit of FIG. 1B, etc. Most common III-N HEMTs and related transistors are normally-on (i.e., have a negative threshold voltage), meaning they conduct current at zero gate voltage. These devices with negative threshold voltages are known as depletion-mode (D-mode) devices. In power electronics, it is preferable to have normally-off devices (i.e., devices with a positive threshold voltage) that are off when zero volts are applied to the gate relative to the source to prevent accidental turn-on of the device (which could lead to damage to the device or other circuit components). Normally-off devices are commonly referred to as enhancement-mode (E-mode) devices.

[0006] To date, reliable fabrication and operation of high-voltage III-N E-mode transistors has proven extremely difficult. One alternative to a single high-voltage E-mode transistor is to combine a high-voltage D-mode III-N transistor with a low-voltage silicon E-mode FET in a cascode configuration. As shown in FIG. 2 , cascode configuration 200 includes a high-voltage D-mode transistor 223 and a low-voltage E-mode transistor 222 housed in a package 205. A source electrode 234 of transistor 223 is connected to a drain electrode 213 of transistor 222. A gate electrode 235 of transistor 223 and a source electrode 211 of transistor 222 are connected together and to a source lead 207 of package 205. A gate electrode 212 of transistor 222 is connected to a gate lead 208 of package 205. A drain electrode 236 of transistor 223 is connected to a drain lead 209 of package 205. The E-mode FET transistor 222 includes a built-in body diode 237 formed between the source 211 and drain 213. Each device configured in the cascode configuration 200 of FIG. 2 can operate in the same manner as a single high voltage E-mode transistor, with leads 207, 208, and 209 acting as the source, gate, and drain of the device, respectively, often achieving the same or similar output characteristics as a single high voltage E-mode transistor.

[0007] A common method of operation of the circuits of FIGS. 1A and 1B involves hard switching of switches (i.e., transistors or cascode switches). A hard-switching circuit configuration is one in which a high current (e.g., greater than 10 A) flows through each switch as soon as it is switched on and a high voltage appears across it as soon as it is switched off. Switches that switch under these conditions are said to be “hard-switched.” An alternative circuit configuration utilizes additional passive and / or active components (alternatively, signal timing techniques) to allow the switches to be “soft-switched.” A soft-switching circuit configuration is one in which the switches switch on during zero-current (or near-zero current) conditions and switch off during zero-voltage (or near-zero voltage) conditions. Soft-switching methods and configurations have been developed to address the high levels of electromagnetic interference (EMI) and associated ringing observed in hard-switched circuits, particularly in high-current and / or high-voltage applications. While soft switching can often avoid these problems, the circuitry required for soft switching typically includes many additional components, resulting in increased overall cost and complexity. Soft switching also typically requires that the circuit be configured to switch only at specific times when a zero-current or zero-voltage condition is met, which often limits the applicable control signals and reduces circuit performance. Therefore, alternative configurations and methods for hard-switched power switch circuits are desirable to reduce circuit inductance and improve switching speed stability while maintaining sufficiently low levels of EMI.

[0008] [Summary] Described herein is a modular configuration for integrated III-N devices, in which low-voltage enhancement-mode devices and high-voltage depletion-mode III-N devices are integrated into a single electronic component module to form half-bridge and full-bridge power switching circuits. The term "device" is used generally for any transistor, switch, or diode when there is no need to distinguish one from the other.

[0009] In a first aspect, an electronic module is described. The electronic module includes a base substrate with an insulating layer between a first metal layer and a second metal layer, the first metal layer including a first portion, a second portion, and a third portion, and a trench formed through the first metal layer electrically insulating the first portion, the second portion, and the third portion of the first metal layer from each other. The electronic module further includes a high-side switch including an enhancement-mode transistor and a depletion-mode transistor, the depletion-mode transistor including a III-N material structure on a conductive substrate. The electronic module further includes a low-side switch. The drain electrode of the depletion-mode transistor is electrically connected to the first portion of the first metal layer, the source electrode of the enhancement-mode transistor is electrically connected to the second portion of the first metal layer, the drain electrode of the enhancement-mode transistor is electrically connected to the source electrode of the depletion-mode transistor, the gate electrode of the depletion-mode transistor is electrically connected to the conductive substrate, and the conductive substrate is electrically connected to the second portion of the first metal layer.

[0010] In a second aspect, a half-bridge circuit is described. The half-bridge circuit includes a high-side switch and a low-side switch, each of which is housed in a single electronic package, the package including a high-voltage terminal, an output terminal, and a ground terminal. The high-side switch includes a first enhancement-mode transistor and a first depletion-mode transistor arranged in a cascode configuration. The low-side switch includes a second enhancement-mode transistor and a second depletion-mode transistor arranged in a cascode configuration. A drain electrode of the first III-N transistor is electrically connected to the high-voltage terminal, a conductive substrate of the first depletion-mode III-N transistor is electrically connected to the output terminal, a drain electrode of the second III-N transistor is electrically connected to the output terminal, and a conductive substrate of the second depletion-mode III-N transistor is electrically connected to the ground terminal.

[0011] In a third aspect, a half-bridge circuit is described. The half-bridge circuit includes a high-side switch and a low-side switch, each housed in a single electronic package. The high-side switch is connected to a high-voltage node, the low-side switch is connected to a ground node, and an inductor is connected to an output terminal of the package between the high-side switch and the low-side switch. The low-side switch includes a low-voltage enhancement-mode transistor and a high-voltage III-N depletion-mode transistor arranged in a cascode configuration. The half-bridge circuit is configured such that, in a first operating mode, current flows through the high-side switch in a first direction and through the inductor while the high-side switch is biased on and the low-side switch is biased off. In a second operating mode, current flows through the low-side switch in a second direction and through the inductor while the high-side switch is biased off and the low-side switch is biased off. In a third mode of operation, current flows through the low-side switch in a second direction and through the inductor while the high-side switch is biased off and the low-side switch is biased on. During the second mode of operation, the low-side switch is configured to conduct a reverse DC current greater than 50 A, and during the third mode of operation, the increase in on-resistance of the III-N depletion-mode transistor relative to the first mode is less than 5%.

[0012] Each of the electronic modules and / or transistors described herein may include one or more of the following features: The high-side switch and the low-side switch may form a half-bridge circuit. The depletion-mode transistor may be configured to block at least 600 V when the high-side switch is biased off and to conduct a current greater than 30 A while the high-side switch is biased on. The electronic module may include a capacitor, wherein a first terminal of the capacitor is electrically connected to a first portion of the first metal layer and a second terminal of the capacitor is electrically connected to a third portion of the first metal layer. The capacitor may be formed orthogonally above the trench. The capacitor may be a hybrid capacitor having series-connected resistive and capacitive components. The resistive component may be greater than 0.1 ohms, and the capacitive component may be greater than 0.1 nF. The gate electrode, source electrode, and drain electrode may be on an opposite side of the III-N material structure from the conductive substrate. The III-N material structure may include a via hole formed through the substrate, and the gate electrode of the depletion-mode transistor is electrically connected to the substrate through the via hole. The electronic module may include a package, in which the substrate, the high-side switch, and the low-side switch are enclosed within the package. The electronic module may include a gate driver enclosed within the package, in which a first terminal of the gate driver is connected to a gate electrode of the high-side switch and a second terminal of the gate driver is connected to a gate electrode of the low-side switch. The gate driver may be integrated with each E-mode transistor of the low-side switch and the low-side switch. A second high-side switch may be connected in parallel with the high-side switch, and a second low-side switch may be connected in parallel with the low-side switch. The second portion of the first metal layer is connected to an output node of the electronic module. The module is configured such that, during operation, the first portion of the first metal layer is connected to a DC voltage source and the third portion of the first metal layer is connected to DC ground. A ferrite bead having a first terminal and a second terminal, the first terminal of the ferrite bead is connected to the second portion of the first metal layer, and the second terminal is connected to the output terminal.The substrate of each of the first and / or second depletion-mode III-N transistors is a silicon-doped p-type substrate with a hole concentration of 1×10 19 Hole / cm 3 During the second mode of operation, reverse DC current flows through the parasitic body diode of the enhancement-mode transistor and through the device channel of the III-N depletion-mode transistor. During the third mode of operation, reverse DC current flows through the channel of the enhancement-mode transistor and through the device channel of the III-N depletion-mode transistor.

[0013] As used herein, a "hybrid enhancement-mode electronic device or component" (or simply "hybrid device or component") refers to an electronic device or component formed from a depletion-mode transistor and an enhancement-mode transistor, where the depletion-mode transistor is capable of a higher operating voltage and / or breakdown voltage compared to the enhancement-mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement-mode transistor having a breakdown voltage and / or operating voltage approximately as high as the breakdown voltage and / or operating voltage of the depletion-mode transistor. That is, a hybrid enhancement-mode device or component includes at least three nodes having the following characteristics: When a first node (source node) and a second node (gate node) are maintained at the same voltage, the hybrid enhancement-mode device or component can block a high positive voltage (i.e., a voltage greater than the maximum voltage that the enhancement-mode transistor can block) applied to a third node (drain node) relative to the source node. When the gate node is maintained at a sufficiently positive voltage with respect to the source node (i.e., a voltage greater than the threshold voltage of the enhancement-mode transistor), current passes from the source node to the drain node, or when a sufficiently positive voltage with respect to the source node is applied to the drain node, current passes from the drain node to the source node. If the enhancement-mode transistor is a low-voltage device and the depletion-mode transistor is a high-voltage device, the hybrid component can operate similarly to a single high-voltage enhancement-mode transistor. The depletion-mode transistor may have a breakdown voltage and / or maximum operating voltage that is at least two times, at least three times, at least five times, at least ten times, or at least twenty times that of the enhancement-mode transistor.

[0014] As used herein, the term Group III nitride or III-N materials, layers, devices, etc. refers to materials having the stoichiometric formula B w Al x In y Ga z III-N refers to a material or device made of a semiconductor composite according to III-N, where w+x+y+z is about 1, and 0≦w≦1, 0≦x≦1, 0≦y≦1, and 0≦z≦1. III-N materials, layers, or devices can be formed or prepared by direct growth on a suitable substrate (e.g., by metalorganic chemical vapor deposition), or by growth on a suitable substrate, detachment from the original substrate, and bonding to another substrate.

[0015] As used herein, two or more contacts or other elements (such as conductive channels or components) are "electrically connected" means that they are connected by sufficient conductive material to ensure that the potential of each of the contacts or elements is intended to be the same (e.g., nearly the same) at all times under any bias condition.

[0016] As used herein, "blocking a voltage" refers to the ability of a transistor, device, or component to prevent substantial current (e.g., current greater than 0.001 times the operating current during normal conduction) from flowing through the transistor, device, or component when a voltage is applied to the transistor, device, or component. In other words, while the transistor, device, or component is blocking a voltage applied to the transistor, device, or component, the total current passing through the transistor, device, or component is no greater than 0.001 times the operating current during normal conduction. Devices with off-state currents greater than this value exhibit high losses and low efficiency and are typically unsuitable for many applications, particularly power switching applications.

[0017] As used herein, a "high voltage device" (e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four-quadrant switch (FQS)) is an electronic device that is optimized for high voltage applications. That is, when the device is off, it is capable of blocking high voltages (e.g., greater than about 300 V, greater than about 600 V, or greater than about 1200 V), and when the device is on, it has a sufficiently low on-resistance (R ON ) (e.g., the conduction losses experienced when a substantial current passes through the device are sufficiently low). A high voltage device is capable of blocking a voltage at least equal to the high voltage supply or maximum voltage in the circuit in which it is used. A high voltage device may be capable of blocking 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, a high voltage device is capable of blocking a voltage between 0V and V max It can block all voltages up to V max is the maximum voltage that can be supplied by the circuit or power supply, and V max may be, for example, 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltage as required by the application. For bidirectional or four-quadrant switches, when the switch is off, the blocked voltage may be of any polarity below a certain maximum (±300V or ±600V, ±1200V, etc.). max ), when the switch is on, the current may be in any direction.

[0018] As used herein, a "III-N device" refers to a device having a conductive channel formed in III-N material. III-N devices can be designed to operate as transistors or switches (where the state of the device is controlled by a gate terminal) or as two-terminal devices (where the device blocks current in one direction and conducts current in the other direction without a gate terminal). III-N devices may also be high-voltage devices suitable for high-voltage applications. In such high-voltage devices, when the device is biased off (e.g., when the voltage of the gate relative to the source is less than the device threshold voltage), the device can support at least all source-drain voltages up to the high voltage of the application for which the device is used (e.g., 100 V, 300 V, 600 V, 1200 V, 1700 V, 2500 V, or higher). When a high-voltage device is biased on (e.g., when the voltage of the gate relative to the source or associated power terminal is greater than the device threshold voltage), the device can conduct substantial current at low on-voltages (i.e., low voltages between the source and drain or both power terminals). The maximum allowable voltage is the maximum on-state voltage that can be sustained in the application in which the device is used.

[0019] As used herein, the terms "over," "under," "between," and "on" refer to the relative position of one layer with respect to another layer. Thus, for example, a layer disposed above or below another layer may be in direct contact with the other layer, or one or more layers may be interposed therebetween. Furthermore, a layer disposed between two layers may be in direct contact with the two layers, or one or more layers may be interposed therebetween. Conversely, a first layer "on" a second layer contacts the second layer. Furthermore, the relative positions of one layer with respect to each other are provided with the assumption that operations are performed on a substrate, without regard to the absolute orientation of the substrate.

[0020] In a typical power switching application using a high-voltage switching transistor, the transistor is in one of two states most of the time. In the first state (commonly referred to as the "on state"), the voltage of the gate electrode relative to the source electrode is greater than the transistor threshold voltage, allowing substantial current to flow through the transistor. In this state, the voltage difference between the source and drain is typically low, usually a few volts or less (e.g., about 0.1 to 5 volts). In the second state (commonly referred to as the "off state"), the voltage of the gate electrode relative to the source electrode is less than the transistor threshold voltage, allowing substantial current to flow through the transistor (excluding off-state leakage current). In this second state, the voltage difference between the source and drain can vary anywhere from about 0 V to the value of the circuit high-voltage supply (possibly 100 V, 300 V, 600 V, 1200 V, 1700 V, or higher, but less than the breakdown voltage of the transistor). In some applications, inductive elements in the circuit may cause the source-drain voltage to be even higher than the circuit high-voltage supply. In addition, immediately after the gate is switched on or off, there is a brief period during which the transistor is in a transition mode between the two aforementioned states. When a transistor is in its off state, it is said to be "blocking voltage" across its source and drain. As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent substantial current (e.g., current greater than 0.001 times the average operating current during normal on-state conduction) from flowing through the transistor, device, or component when a voltage is applied to the transistor, device, or component. In other words, while the transistor, device, or component is blocking a voltage applied to the transistor, device, or component, the total current passing through the transistor, device, or component is no greater than 0.001 times the average operating current during normal on-state conduction.

[0021] The accompanying drawings and the following description set forth details of one or more disclosed implementations of the subject matter described herein. Additional features and variations may also be included in the implementations. Other features, aspects, and advantages will be apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0022] [Figure 1A] Circuit schematic of a half-bridge circuit. [Figure 1B] Circuit schematic of a three-phase bridge circuit. [Figure 2] Schematic of a hybrid normally-off device arranged in a cascode configuration. [Figure 3A] FIG. 1 is a plan view of an electronic module featuring a half-bridge. [Figure 3B] 3B is a cross-sectional view along a portion of the electronic module of FIG. 3A. [Figure 4A] FIG. 10 is a plan view of a low-voltage enhancement-mode transistor coupled to a high-voltage depletion-mode III-N transistor to form a cascode switch. [Figure 4B] 4B is a cross-sectional view along a portion of the cascode switch of FIG. 4A. [Figure 5A] FIG. 1 is a plan view of an electronic module featuring a half-bridge. [Figure 5B] 5B is a cross-sectional view of a portion of the electronic module of FIG. 5A. [Figure 6] FIG. 10 is a plan view of a low-voltage enhancement-mode transistor coupled to a high-voltage depletion-mode III-N transistor to form a cascode switch. [Figure 7A] Circuit schematic for half-bridge operating mode. [Figure 7B] Circuit schematic for half-bridge operating mode. [Figure 7C] Circuit schematic for half-bridge operating mode. [Figure 7D] Circuit schematic for half-bridge operating mode. [Figure 7E] Circuit schematic for half-bridge operating mode. [Figure 8] FIG. 1 is a plan view of an electronic module featuring a half-bridge. [Figure 9] FIG. 1 is a plan view of an electronic module featuring a half-bridge in an SMPT-type package. [Figure 10] FIG. 1 is a plan view of an electronic module featuring a half-bridge in an SMPT-type package. [Figure 11] FIG. 1 is a plan view of an electronic module featuring a half-bridge in an SMPT-type package. [Figure 12] FIG. 1 is a plan view of an electronic module featuring a half-bridge in an SMPT-type package. [Figure 13A] Side view of an encapsulated SMPD type package. [Figure 13B] Top view of an encapsulated SMPD type package. [Figure 14] Top view of an electronic module featuring two half-bridges configured in parallel. [Figure 15] FIG. 1 is a plan view of an electronic module featuring a three-phase bridge circuit. [Figure 16] FIG. 1 is a plan view of an electronic module featuring a half-bridge with integrated gate drivers. [Figure 17] FIG. 1 is a plan view of an electronic module featuring a half-bridge with integrated gate drivers.

[0023] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0024] Described herein is an electronic module and method of operation suitable for maintaining low levels of EMI, thereby enabling high circuit stability and improved performance. The design of the module (coupled with the design of the switches used within the module) can result in reduced inductance and other parasitics, thereby leading to the performance improvements described above. The electronic module can also have a reduced size and be easier to assemble than conventional modules, thereby enabling lower manufacturing costs.

[0025] Figures 3A and 3B show plan and cross-sectional views, respectively, of electronic module 300. Module 300 includes cascode switches 382 and 383 connected in the half-bridge configuration shown in Figure 1. Plan and cross-sectional views, respectively, of cascode switch 400 that can be used for each of switches 382 and 383 are shown in Figures 4A and 4B (other cascode configurations may alternatively be used in place of cascode switch 400).

[0026] 4A and 4B, cascode switch 400 includes a low-voltage E-mode transistor 422 attached directly to the source pad 434 of a high-voltage D-mode transistor 423, with the drain pad 453 of E-mode transistor 422 bonded directly to the source electrode 434 of D-mode transistor 423. E-mode transistor 422 may be, for example, a silicon FET, and the D-mode transistor may be, for example, a III-N HEMT. Cascode switch 400 can operate in the same manner as a single high-voltage E-mode III-N transistor and, in many cases, achieves the same or similar output characteristics as a single high-voltage E-mode III-N transistor. D-mode transistor 423 has a larger breakdown voltage than E-mode transistor 422 (e.g., at least three times larger). The maximum voltage that cascode switch 400 can block while biased in the off state is at least as large as the maximum blocking or breakdown voltage of D-mode transistor 423.

[0027] E-mode transistor 422 includes semiconductor body layer 455. Transistor 422 further includes FET source electrode 451 and FET gate electrode 452 on a first side of semiconductor body layer 455, and FET drain electrode 453 on a second side of semiconductor body layer 455 (opposite FET source electrode 451).

[0028] The D-mode transistor 423 includes a III-N material structure 418 (e.g., a combination of GaN and AlGaN) grown on a suitable substrate 411, which may be a conductive semiconductor (e.g., silicon (e.g., p-type or n-type Si), GaN (e.g., p-type or n-type GaN)), or any other sufficiently conductive substrate, or an insulating (e.g., sapphire) substrate, or a semi-insulating substrate (e.g., semi-insulating silicon carbide).

[0029] The III-N material structure 418 can include a III-N buffer layer 412 (e.g., GaN or AlGaN) grown on a substrate 411. The buffer layer 412 can be rendered insulating or substantially free of unintended n-type carriers. The buffer layer 412 can have a substantially uniform composition throughout, or the composition can vary. The thickness and composition of the buffer layer 412 can be optimized for high-voltage applications. That is, the buffer layer can block voltages equal to the maximum voltage or high-voltage supply in the circuit in which it is used. For example, the buffer layer 412 can block voltages greater than 600 V or greater than 900 V. The thickness of the buffer layer 412 can be greater than 2 μm. For example, the III-N buffer layer can have a thickness between 5 μm and 10 μm.

[0030] The III-N material structure may further include a III-N channel layer 413 (e.g., GaN) above the III-N buffer layer 412 and a III-N barrier layer 414 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 413. The bandgap of the III-N barrier layer 414 is larger than the bandgap of the III-N channel layer 413. The III-N channel layer 413 has a different composition than the III-N barrier layer 414, and the thickness and composition of the III-N barrier layer 414 are selected such that a two-dimensional electron gas (2DEG) channel 419 (shown by the dashed line in FIG. 4B ) is induced in the III-N channel layer 413 adjacent the interface of the layers 414 and 413.

[0031] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown in a reactor by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). As shown in FIG. 4B, the III-N material structure may be grown with a group-III polarity (e.g., Ga polarity) orientation (e.g., [0 0 0 1] (C-face) orientation). Alternatively, III-N HEMTs may be formed on III-N material structures grown with an N-polarity (i.e., N-face) orientation (e.g., [0 0 0 -1] orientation (not shown)). In N-polar devices, a III-N barrier layer may be above a III-N buffer layer, and a III-N channel layer may be above the III-N barrier layer. N-polar III-N materials have a polarization field in the opposite direction to group-III polarity III-N materials, thus enabling the implementation of III-N device structures that cannot be formed using group-III polarity structures.

[0032] An insulating layer 415 (e.g., a dielectric layer) is grown or deposited over the upper surface of the III-N material structure 418. The insulating layer 415 may be, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), Si x N y , Al 1-x Si x N, Al 1-x Si x O, Al1-x Si x The insulator 115 may be formed from or include an O / N or any other wide bandgap insulator. Although the insulator 115 is illustrated as a single layer, it may alternatively be formed from several layers and / or materials deposited during various processing steps to form a single composite insulator layer.

[0033] A source electrode 434 and a drain electrode 436 are formed on the opposite side of the D-mode transistor 423 from the substrate such that the device 423 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between the source 434 and the drain 436). The source electrode 434 and the drain electrode 436 make ohmic contact and are electrically connected to the device 2DEG channel 419 formed in layer 413. The source and drain electrodes 434, 436 may each be formed from a stack of multiple metal layers. Each metal stack may be, for example, Ti / Al / Ni / Au, Ti / Al, or other suitable metal layer stack.

[0034] The D-mode transistor 423 further includes a gate electrode 435. The gate electrode 435 can be formed such that an insulating layer 415 extends between and separates the gate electrode 435 from the III-N material structure 418, as shown in FIG. 4B . Alternatively, the gate electrode 435 can be formed in contact with the III-N material structure 418 (not shown). The gate electrode 435 can be formed from a suitable conductive material, such as a metal stack (e.g., titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au)). Alternatively, the gate electrode 435 can be another conductive material or material stack including one or more materials with a high work function, such as a semiconductor material with a high work function (e.g., p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0035] The low-voltage E-mode device 422 is electrically connected to the high-voltage D-mode III-N device 423 to form the cascode switch 400, which may be a hybrid III-N device. Here, the drain electrode 453 of the E-mode transistor 422 is electrically connected in direct contact with (e.g., attached to) the source electrode 434 of the III-N transistor 423. The drain electrode 453 of the E-mode transistor 422 may be connected to the source electrode 434 of the D-mode transistor 423 (e.g., by solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment method that provides a high-quality mechanical, thermal, and electrical connection between the FET drain electrode 453 and the D-mode transistor source electrode 434). The E-mode transistor 422 may be attached above the 2DEG channel 419 as shown in FIG. 4B, or the device 422 may be attached partially or entirely to a region outside the active area of ​​the device such that the FET 422 is not above the 2DEG channel layer. The gate node of cascode switch 400 may be connected to gate electrode 452 of E-mode device 422. The D-mode and E-mode transistors in a conventional cascode switch are typically packed side-by-side together on a ceramic insulating substrate (such as an AlN shim), requiring an external wire connector to make the FET drain-to-HEMT source connection required in the cascode configuration. However, by mounting E-mode device 422 directly on D-mode device 423, as shown in Figures 4A and 4B, the external wire connector and ceramic substrate are eliminated. This dramatically reduces the parasitic inductance of the circuit, enabling higher current ratings and faster switching speeds.

[0036] Although not shown in Figures 4A or 4B, gate electrode 435 of D-mode transistor 423 should be connected to source electrode 451 of E-mode transistor 422 (required for proper operation of the cascode switch), and these two electrodes are in fact electrically connected (because they are both bonded to a common metal layer) when cascode switch 400 is mounted in module 300 of Figures 3A and 3B. This can be seen in Figures 3A and 3B and is explained in more detail below.

[0037] Returning to Figures 3A and 3B, module 300 includes a direct-bond copper (DBC) substrate 310 (best shown in Figure 3B), which may serve as the module's base substrate. DBC substrates are formed by direct bonding of pure copper to a ceramic insulator (such as AlN or Al2O3) in a high-temperature melt diffusion process. DBC substrate 310 includes an insulating (e.g., ceramic or AlN) substrate 315 on which a top metal layer (e.g., copper or nickel) is patterned into at least a first portion 311 that functions as a high-voltage plate, a second portion 312 that functions as an output plate, and a third portion 313 that functions as a ground plate. Each portion 311, 312, and 313 is electrically isolated from one another by a groove 314 formed through the metal layer. As shown in Figure 3B, the DBC substrate may also include a backside metal layer 316 (e.g., copper or nickel) on the opposite side of insulating substrate 315 from the top metal layer (311 / 312 / 313). Optionally, ground plate 313 may be electrically connected to backside metal layer 316 by forming metal via holes 317 through insulating substrate 315. High-side switch 382 and low-side switch 383 are cascode switches shown in Figures 4A and 4B, respectively. High-side switch 382 is mounted directly on output plate 312, and low-side switch 383 is mounted directly on ground plate 313.

[0038] For high-side switch 382, ​​drain electrode 436 of the D-mode transistor is electrically connected to high-voltage plate 311 via connector 341, and gate electrode 435 of the D-mode transistor and source electrode 451 of the E-mode transistor are both electrically connected to output plate 312 via wire connectors 340 and 342, respectively. For low-side switch 383, drain electrode 436' of the D-mode transistor is electrically connected to output plate 312 via connector 343, and gate electrode 435' of the D-mode transistor and source electrode 451' of the E-mode transistor are both electrically connected to ground plate 313 via wire connectors 346 and 348, respectively.

[0039] Optionally, electronic module 300 includes a package in which the electronic components are encased, the package including first input lead 372, second input lead 373, high voltage lead 391, ground lead 383, and output lead 392. First input lead 372 is connected to gate electrode 452 of the E-mode transistor of high-side switch 382, ​​second input lead 373 is connected to gate electrode 452′ of the E-mode transistor of low-side switch 383, high voltage lead 391 is connected to high voltage plate 311, ground lead 393 is connected to ground plate 313, and output lead 392 is connected to output plate 312.

[0040] To ensure proper operation of the half-bridge circuit formed by electronic module 300 of FIGS. 3A and 3B, high-voltage node 391 should be maintained at AC ground. That is, node 391 can be capacitively coupled to DC ground node 393 by connecting a first terminal of capacitor 375 to high-voltage plate 311 and a second terminal of capacitor 375 to ground plate 393. As shown in FIG. 3A, capacitor 375 can be placed directly over a portion of via 314. As either switch 382 or 383 is turned on or off, capacitor 375 can be charged or discharged appropriately to provide the current necessary to maintain substantially constant voltages on the high and low sides of the circuit. Furthermore, capacitor 375 can be a hybrid capacitor including capacitive and resistive components. For example, capacitor 375 can be configured as a series-connected capacitor and resistor. Due to the large di / dt required for high-current operation, ringing and voltage spikes can occur during turn-off of the high-side or low-side switch. Typically, ringing frequencies are observable in the 100 mHz range. This ringing is effectively damped with a series resistor and capacitor rather than just a decoupling capacitor. At operating currents around 30 A, capacitance values ​​can range from 0.01 nF to 100 nF, and resistance values ​​can range from 0.1 ohms to 100 ohms. Designers may choose higher resistance and capacitance values ​​to bias toward a less damped condition.

[0041] 5A and 5B show plan and cross-sectional views, respectively, of another electronic module 500 that may provide improved performance and reliability and reduced complexity compared to module 300. Module 500 utilizes cascode switches 600, shown in FIG. 6, for its high-side and / or low-side switches (582 and 583), respectively. As described in more detail below, the design of cascode switches 600 used for switches 582 and 583 allows module 500 to eliminate certain external connectors, resulting in both reduced complexity and improved performance and reliability of module 500.

[0042] 6, the cascode switch 600 used in module 500 is similar to the cascode switch 400 used in module 300, but with the addition of new features. First, the substrate 611 on which the III-N material structure 618 is formed is a conductive substrate (e.g., formed from p-type silicon, n-type silicon, p-type GaN, n-type GaN, or n-type SiC), and the substrate is electrically connected (i.e., shorted) to the top metal layer of module 500 to which it is attached.

[0043] Additionally, gate electrode 635 of high-voltage D-mode transistor 623 is electrically connected to conductive substrate 611 by a via hole 638 (e.g., a through-epi-via or TEV) formed through a portion of III-N material structure 618. Via hole 638 can be formed through the entire thickness of III-N material structure 618 and extend all the way to substrate 611, as shown by dashed region 638 in FIG. 6 . The metal of gate electrode 635 is formed at least partially within via hole 638 and makes ohmic contact with conductive substrate 611, thereby electrically connecting gate electrode 635 of III-N transistor 623 to conductive substrate 611. The dashed region in FIG. 6 shows via hole 638 passing through 2DEG channel 619, but via hole 638 is formed in such a way that 2DEG channel 619 is continuous between source and drain electrodes 634 and 636 of the D-mode device (e.g., the via hole may be formed within a portion of the III-N material that is outside the active region of the III-N transistor).

[0044] Finally, a backside metal layer 617 (e.g., Ti / Ni / Ag) may optionally be formed on the opposite or backside of the conductive substrate 611 from the III-N material structure 618. The backside metal layer 617 may be used as an adhesive layer to allow the substrate 611 to be attached to an underlying metal plate in the module 500 by solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment method that allows high-quality mechanical, thermal, and electrical connection to the metal layers of the device substrate 611.

[0045] 5A and 5B, to form half-bridge module 500, a first cascode switch (e.g., switch 600) is attached directly to output plate 512 to form high-side switch 582, and a second cascode switch (e.g., switch 600) is attached directly to ground plate 513 to form low-side switch 583. For high-side switch 582, gate electrode 635 of the D-mode transistor is electrically connected to conductive substrate 611 by via hole 638, which is attached directly to output plate 512, thereby electrically attaching gate electrode 635 to output plate 512 without the need for an external connector (e.g., connector 340 in FIGS. 3A and 3B ). Similarly, for low-side switch 583, gate electrode 635′ of the D-mode transistor is electrically connected to conductive substrate 611 by via hole 638, which is attached directly to ground plate 513, thereby electrically attaching gate electrode 635′ to ground plate 513 without the need for an external connector (e.g., connector 346 in FIGS. 3A and 3B ). As a result, assembly of the module 500 is simplified, circuit inductance is reduced, and switching noise and EMI are reduced.

[0046] For completeness, other aspects and features of module 500 and cascode switch 600 used therein are as follows. Referring to FIG. 6 , cascode switch 600 includes a low-voltage E-mode transistor 622 mounted directly on a source pad 634 of a high-voltage D-mode transistor 623, with the drain pad 653 of E-mode transistor 622 bonded directly to the source electrode 634 of D-mode transistor 623. E-mode transistor 622 is, for example, a silicon FET, and the D-mode transistor is, for example, a III-N HEMT. Cascode switch 600 can operate similarly to a single high-voltage E-mode III-N transistor and, in many cases, achieves the same or similar output characteristics as a single high-voltage E-mode III-N transistor. D-mode transistor 623 has a larger breakdown voltage than E-mode transistor 622 (e.g., at least three times larger). The maximum voltage that cascode switch 600 can block while biased in the off state can be at least as large as the maximum blocking or breakdown voltage of D-mode transistor 623.

[0047] E-mode transistor 622 includes semiconductor body layer 655. Transistor 622 further includes FET source electrode 651 and FET gate electrode 652 on a first side of semiconductor body layer 655, and FET drain electrode 653 on a second side of semiconductor body layer 655 (opposite FET source electrode 651).

[0048] The D-mode transistor 623 includes a III-N material structure 618 (e.g., a combination of GaN and AlGaN) grown on a conductive substrate 611, which may be, for example, silicon (e.g., p-type or n-type Si), GaN (e.g., p-type or n-type GaN), n-type SiC, or any other sufficiently conductive substrate.

[0049] The III-N material structure 618 can include a III-N buffer layer 612 (e.g., GaN or AlGaN) grown on a substrate 611. The buffer layer 612 can be rendered insulating or substantially free of unintended n-type carriers. The buffer layer 612 can have a substantially uniform composition throughout, or the composition can vary. The thickness and composition of the buffer layer 612 can be optimized for high-voltage applications. That is, the buffer layer can block voltages equal to the maximum voltage or high-voltage supply in the circuit in which it is used. For example, the buffer layer 612 can block voltages greater than 600 V or greater than 900 V. The thickness of the buffer layer 612 can be greater than 2 μm. For example, the III-N buffer layer can have a thickness between 5 μm and 10 μm.

[0050] The III-N material structure may further include a III-N channel layer 613 (e.g., GaN) above the III-N buffer layer 612 and a III-N barrier layer 614 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 613. The bandgap of the III-N barrier layer 614 is larger than the bandgap of the III-N channel layer 613. The III-N channel layer 613 has a different composition than the III-N barrier layer 614, and the thickness and composition of the III-N barrier layer 614 are selected such that a two-dimensional electron gas (2DEG) channel 619 (shown by the dashed line in FIG. 6 ) is induced in the III-N channel layer 613 adjacent the interface of layers 614 and 613.

[0051] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown in a reactor by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). As in the device shown in FIG. 6 , the III-N material structure may be grown with a group-III polar (e.g., Ga-polar) orientation (e.g., a [0 0 0 1] (C-face) orientation). Alternatively, III-N HEMTs may be formed on III-N material structures grown with an N-polar (i.e., N-face) orientation (e.g., a [0 0 0 -1] orientation (not shown)). In N-polar devices, a III-N barrier layer may be above a III-N buffer layer, and a III-N channel layer may be above the III-N barrier layer. N-polar III-N materials have a polarization field in the opposite direction to group-III polar III-N materials, thus enabling the implementation of III-N device structures that cannot be formed using group-III polar structures.

[0052] An insulating layer 615 (e.g., a dielectric layer) is grown or deposited over the upper surface of the III-N material structure 618. The insulating layer 615 may be, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), Si x N y , Al 1-x Si x N, Al 1-x Si x O, Al 1-x Si x The insulating layer 115 may be formed from or include an N-type or any other wide bandgap insulator. While insulating layer 115 is illustrated as a single layer, it may alternatively be formed from several layers and / or materials deposited during various processing steps to form a single composite insulating layer. Insulating layer 18 may be uniform throughout or may be formed from a variety of insulating materials.

[0053] A source electrode 634 and a drain electrode 636 are formed on the opposite side of the D-mode transistor 623 from the substrate such that the device 623 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between the source 634 and the drain 636). The source and drain electrodes 634, 636 may each be formed from a stack of multiple metal layers. Each metal stack may be, for example, Ti / Al / Ni / Au, Ti / Al, or other suitable metal layer stack.

[0054] 6, the gate electrode 635 may be formed such that an insulating layer 615 is at least partially between the gate electrode and the III-N material structure 618. The gate electrode 635 may be formed from a suitable conductive material, such as a metal stack (e.g., titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au)).

[0055] A low-voltage E-mode device 622 is electrically connected to a high-voltage D-mode III-N device 623 to form a cascode switch 600, where a drain electrode 653 of the E-mode transistor 622 is in direct contact with (e.g., attached to) and electrically connected to a source electrode 634 of the III-N transistor 623. The drain electrode 653 of the E-mode transistor 622 may be connected to the source electrode 634 of the D-mode transistor 623 (e.g., by solder, solder paste, conductive epoxy, conductive tape, or other suitable attachment method that provides a high-quality mechanical, thermal, and electrical connection between the FET drain electrode 653 and the D-mode transistor source electrode 634). The E-mode transistor 622 may be attached above the 2DEG channel 619 as shown in FIG. 6, or the device 622 may be attached partially or entirely to a region outside the active area of ​​the device such that the FET 622 is not above the 2DEG channel layer.

[0056] 5A and 5B, module 500 includes a direct bond copper (DBC) substrate 510 (best shown in FIG. 5B), which may serve as the module's base substrate. DBC substrate 510 includes an insulating (e.g., ceramic) substrate 515 on which a top metal layer (e.g., copper) is patterned into at least a first portion 511 that functions as a high-voltage plate, a second portion 512 that functions as an output plate, and a third portion 513 that functions as a ground plate. Each of portions 511, 512, and 513 is electrically isolated from one another by a groove 514 formed through the top metal layer. DBC substrate 510 may optionally include a backside metal layer 516 on the opposite side of insulating substrate 515 from the top metal layer (511 / 512 / 513). Optionally, ground plate 513 may be electrically connected to backside metal layer 516 by forming a metal via hole 517 through insulating substrate 515. High-side switch 582 and low-side switch 583 are each cascode switches as shown in Figure 6. High-side switch 582 is mounted directly on output plate 512, and low-side switch 583 is mounted directly on ground plate 513.

[0057] For high-side switch 582, drain electrode 636 of the D-mode transistor is electrically connected to high-voltage plate 511 via connector 541, and source electrode 651 of the E-mode transistor is electrically connected to output plate 512 via wire connector 542. For low-side switch 583, drain electrode 636' of the D-mode transistor is electrically connected to output plate 512 via connector 543, and source electrode 651' of the E-mode transistor is electrically connected to ground plate 513 via wire connector 544. Connectors 541-544 may comprise a single wire bond (as shown), multiple parallel wire bonds, ribbons, conductive metal clips, or other connectors comprising a conductive material (e.g., aluminum (Al), gold (Au), copper (Cu), or other suitable material).

[0058] Optionally, electronic module 500 includes a package in which the electronic components are encased, the package including first input lead 572, second input lead 573, high voltage lead 591, ground lead 593, and output lead 592. First input lead 572 is connected to gate electrode 652 of the E-mode transistor of high-side switch 582, second input lead 573 is connected to gate electrode 652′ of the E-mode transistor of low-side switch 583, high voltage lead 591 is connected to high voltage plate 511, ground lead 593 is connected to ground plate 513, and output lead 592 is connected to output plate 512.

[0059] To ensure proper operation of the half-bridge circuit formed by electronic module 500 of FIGS. 5A and 5B, high-voltage node 591 should be maintained at AC ground. That is, node 591 can be capacitively coupled to DC ground node 593 by connecting a first terminal of capacitor 575 to high-voltage plate 511 and a second terminal of capacitor 575 to ground plate 593. As shown in FIG. 5A, capacitor 575 can be placed directly over a portion of via 514. As either switch 582 or 583 is turned on or off, capacitor 575 can be charged or discharged appropriately to provide the current necessary to maintain substantially constant voltages on the high and low sides of the circuit. Furthermore, capacitor 575 can be a hybrid capacitor including capacitive and resistive components. For example, capacitor 575 can be configured as a single component including a series-connected capacitor and resistor. Due to the large di / dt required for high-current operation, ringing and voltage spikes can occur during turn-off of the high-side or low-side switch. Typically, the ringing frequency is observable in the 100 mHz range. This ringing is effectively damped with a series resistor and capacitor rather than just a decoupling capacitor. At operating currents around 30 A, the capacitance value can be greater than 0.1 nF, for example, in the range of 0.1 nF to 100 nF, and the resistance value can be greater than 0.1 ohms, for example, in the range of 0.1 ohms to 100 ohms. Designers may choose higher resistance and capacitance values ​​to bias toward a weaker damping condition.

[0060] 7A, 7B, and 7C show three different modes for operating a half-bridge buck converter circuit similar to the half-bridge of FIG. 1A. The half-bridge circuit includes a high-side switch 102 connected to a high voltage node 111 and a low-side switch 103 connected to a ground node 113. An inductor 104 is connected between node 112 (between low-side switch 103 and high-side switch 102) and the output node V of the circuit.OUT A first capacitor 106 is connected between the high voltage node 111 and DC ground 113. A second capacitor 107 is connected between the output node V of the circuit. OUT and DC ground 113. The low-side switch 103 and the high-side switch 102 are selected to have properties that improve the efficiency of the buck converter circuit. Specifically, switches 102 and 103 have low on-resistance (R DS(ON) ) and low switching losses. Switches 102 and / or 103 may be formed with, for example, cascode switch 200 of FIG. 2. Alternatively, switches 102 and / or 103 may be implemented as cascode switch 600 of FIG. 6 assembled within half-bridge module 500 of FIG. 5A.

[0061] The buck converter half-bridge of Figures 7A-7C can be operated as follows: Referring to Figure 7A, in a first mode of operation, the gate of the high-side switch 102 is biased on (i.e., V GS 102>V TH ), the gate of the low-side switch 103 is biased off (i.e., V GS 103 <V TH ). Current 97 flows forward from high voltage node 111 through high side switch 102 to node 112. This current is blocked by low side switch 103 and flows through inductor 104 as shown by current path 97. While the device is operating in the first mode of operation, the gate-source voltage of high side switch 102 is switched low or off (i.e., V GS 102 <V TH ), if the gates of both switches 102 and 103 are biased off, the half-bridge switches to a second mode of operation shown in Figure 7B. Current must continue to flow through inductor 104.

[0062] 7D and 7E show a circuit schematic of a cascode switch (such as cascode switch 200 of FIG. 2) and also illustrate various parasitic inductances and capacitances inherent in the cascode configuration. The parasitic gate-drain capacitance (C GD ) is shown as capacitor 57. The built-in body diode of E-mode FET 222 is shown by diode 237. The parasitic inductance of the source connection of E-mode FET 222 is shown as inductor 54, and the parasitic inductance of the gate connection of D-mode III-N transistor 223 is shown as inductor 53. When the circuit of FIGS. 7D and 7E is implemented as a low-side switch 383 in a half-bridge module (similar to module 300 of FIG. 3A ), inductor 54 represents the inductance of a wire (e.g., wire 348 in FIG. 3A ) connecting the source 451′ of the E-mode transistor to ground plate 313. To connect gate electrode 435′ of the D-mode transistor of switch 383 to source electrode 451′ of the E-mode transistor of switch 383, external gate wire connector 346 is used to connect gate electrode 435′ of the D-mode transistor to ground plate 313. As a result of this gate wire connector 346, a substantial inductance (represented by inductor 53 in FIG. 7D) is introduced between the gate electrode 435 of the D-mode transistor and the ground plate 313. Parasitic inductances 53 and 54 can slow the turn-on and turn-off times of the module and increase switching losses, thereby degrading circuit performance.

[0063] 7D shows the detailed current path through the cascode configuration of low-side switch 103 during transition time T1 between the first and second operating modes shown in FIGS. 7A and 7B. During transition time T1, the voltage at node 112 (shown in FIGS. 7A-7B) drops negative, resulting in current path I ACAs shown by V, a displacement current flows through the parasitic gate-drain capacitor 57 of the D-mode III-N transistor 223. When the voltage at node 112 becomes sufficiently negative, the gate of the low-side switch 102, while biased off (i.e., V GS <V TH ), the built-in body diode 237 of E-mode FET transistor 222 switches on, and switch 103 goes from off to reverse conducting. This is called reverse conducting mode (i.e., freewheeling diode mode). At the end of transition time T1, switch 103 transitions from off to reverse conducting, and current flows from a displacement current through gate-drain capacitor 57 of D-mode transistor 223 (as shown in FIG. 7D) to a reverse DC current flowing through the built-in body diode 237 of E-mode transistor 222 and the channel of D-mode transistor 223 (as shown in FIG. 7E). DC (denoted by

[0064] When the operating current through inductor 104 is high, the current path transition can cause a voltage spike and ringing across the gate of D-mode transistor 223. This voltage spike injects charge into the gate dielectric (e.g., insulating layer 415 or 615) of the D-mode transistor, increasing the channel on-resistance (R ON ), thereby increasing the on-resistance of cascode switch 383. Because the current in inductor 104 must be continuous, reverse conduction of switch 103 occurs in the circuit of FIG. 7B even when the gate of switch 103 is biased off.

[0065] Returning to FIG. 7C, after the gate of the high-side 102 is switched off as shown in FIG. 7B, the low-side switch 103 is switched on (i.e., V GS >V TH), the buck converter operates in a third mode of operation, with current 98 continuing to flow through low-side switch 103 in the same (reverse) direction as in the second mode, except that low-side switch 103 is biased on. By biasing the low-side switch on during the third mode of operation, the reverse voltage drop across E-mode transistor 222 is reduced compared to the second mode of operation, allowing for higher efficiency compared to the second mode of operation. To prevent the high-voltage node 111 from accidentally shorting to ground node 113, sufficient dead time is used between the time the high-side switch 102 is turned off and the time the low-side switch 103 is turned on.

[0066] The design of the cascode switch and associated module can be an important factor in determining the performance of the low-side switch 103 during reverse conduction mode. By implementing device 600 as the low-side device 103 within half-bridge module 500, and thereby eliminating the need for an external gate wire connection (such as wire 346 in FIG. 3A ) between the D-mode transistor of switch 583 and ground plate 513 within module 500 (because the gate of the D-mode transistor is connected to ground plate 513 through via hole 638), parasitic inductance within the half-bridge module (shown by inductor 53 in FIG. 7D ) is reduced. This reduces voltage spikes and ringing experienced by the gate of the D-mode transistor of switch 583 during current path transitions between the first and second operating modes. Surprisingly, it has been shown that degradation (i.e., increase) of the channel on-resistance of the switch is substantially reduced when operating at very high reverse DC currents compared to conventional modules with external gate wires. This result was unexpected. The contribution of the gate wire inductance from the depletion-mode transistor to module switching performance was considered negligible by the inventors because there is no DC current flowing through this path and the gate voltage of the depletion-mode transistor in the low-side switch is typically pinned to ground. This degradation in on-resistance, commonly referred to as current collapse or distribution, is a major concern for the implementation of III-N devices in half-bridge circuits. When the cascode switch 600 is implemented as the low-side switch 583 in the half-bridge module 500, the switch 583 can operate with reverse DC currents greater than 50 A (or even 70 A) during the second and third operating modes while exhibiting little increase in on-resistance. For example, the increase in on-resistance can be less than 5% compared to the first operating mode. Conventional modules with external gate wire connections can typically exhibit an increase in on-resistance of 30% or more, even when operating with reverse DC currents of 30 A or less. The low-side switch 583 can block voltages greater than 600 V during the first operating mode.

[0067] Additionally, the high-side switch 582 can operate in reverse conduction mode during certain switching procedures, where the gate connection of the D-mode III-N transistor of the cascode switch 582 to the output plate 512 is connected through a via hole 638, further reducing the parasitic inductance of the electronic module. This further reduces the voltage spikes and ringing experienced by the cascode switch 582 during the current path transition when switching to reverse conduction mode.

[0068] FIG. 8 is a top view of an integrated electronic module 800 forming a half-bridge circuit similar to integrated electronic half-bridge module 500 of FIG. 5A with an alternative DBC 810 layout that allows for a more compact arrangement of high-voltage plate 811, output plate 812, and ground plate 813 compared to module 500 of FIG. 5A. This reduces the electronic module size and footprint, thereby reducing costs. Module 800 also includes a high-side source sense node 896 and a low-side source sense node 897. Although not shown in FIG. 5A, module 500 may also include sense nodes 896 and 897. High-side source sense node 896 is connected to output plate 812, and low-side source sense node 897 is connected to ground plate 813. A first input lead 872, a high-side source sense node 896, a second input lead 873, and a low-side source sense node 897 (collectively, gate nodes) extend from a first side of the module 800, with all gate nodes extending from the same side of the module and configured to connect to an external gate driver. In some examples, the high-side gate node may be connected to a high-side gate driver and the low-side gate node may be connected to a low-side gate driver. A high-voltage node 891, a ground node 893, and an output node 892 extend from a second side, opposite the first side, of the module 800, with the high-voltage node 891 configured to connect to a circuit high-voltage supply, the ground node 893 configured to connect to a circuit ground, and the output node 892 configured to connect to an inductive element or a circuit load. The high-side switch 882 is positioned at a 90° rotation relative to the low-side switch 883 of the module 800, allowing for a more compact arrangement of the module components and also allowing for shorter wirebond connections to the DBC 810. In particular, in the high-side switch 882, the source and drain electrodes 634 and 634′ are positioned along a first axis, while in the low-side switch 883, the source and drain electrodes 634′ and 634′ are positioned along a second axis that is orthogonal to the first axis.

[0069] FIG. 9 is a top view of an integrated electronic module 900 forming a half-bridge circuit integrated into a surface-mounted power device (i.e., SMPD) type package. The half-bridge circuit configured in electronic module 600 is similar to module 500 of FIG. 5A but includes an additional metal routing layer on DBC 910 and connector leads accommodating source sense pins and gate-connected ferrite beads. Electronic module 900 includes high-side switch 582 and low-side switch 583, which may be identical to module 500 of FIG. 5A. Module 900 includes DBC 910 including high-voltage plate 911, output plate 912, and ground plate 913, each plate separated by grooves 914 formed in the top metal layer of DBC 910. DBC 910 can be constructed in a manner similar to DBC 510 of FIGS. 5A and 5B, but with an alternative top metal layer configuration resulting from the separation pattern from grooves 914. Electronic module 900 further includes a high voltage lead 991 connected to high voltage plate 911, an output lead 992 connected to output plate 912, and a ground lead 993 connected to ground plate 913. Electronic module 900 further includes a first input lead 961 (which may be multiple leads), a high side source sense lead 962, a second input lead 963 (which may be multiple leads), and a low side source sense lead 964. Module 900, similar to module 500 of FIG. 5A, includes a hybrid capacitor 575 connected between high voltage plate 911 and ground plate 913.

[0070] 9 further includes an optional high-side ferrite bead 68 and an optional low-side ferrite bead 69. The high-side ferrite bead 68 includes a first terminal electrically coupled to the first input lead 961 and a second terminal electrically coupled to a first side of the high-side gate connector 65. The high-side gate connector 65 includes a second side connected to the gate electrode of the E-mode transistor of the cascode switch 582. The low-side ferrite bead 69 includes a first terminal electrically coupled to the second input lead 963 and a second terminal electrically coupled to a first side of the low-side gate connector 67. The low-side gate connector 67 includes a second side connected to the gate electrode of the E-mode transistor of the cascode switch 583. The electronic module 900 further includes a source sense connector 66 having a first side electrically connected to the high-side source sense node 962 and a second side electrically connected to the output plate 912. Connector 66 is used to bridge ground plate 913 so that high-side source sense node 962 is at the same potential as the source of high-side switch 582. Connectors 65, 66, and 67 may comprise a single wire bond (as shown), multiple parallel wire bonds, ribbons, conductive metal clips, or other connectors comprising a conductive material (e.g., aluminum (Al), gold (Au), copper (Cu), or other suitable material).

[0071] 9 , high-side switch 582 is attached directly to output plate 912, such that the gate of the D-mode III-N transistor of cascode switch 582 is electrically connected directly to output plate 912 through the substrate of cascode switch 582 without an external wire connector. Low-side switch 583 is attached directly to ground plate 913, such that the gate of the D-mode III-N transistor of cascode switch 583 is electrically connected to ground plate 912 through the substrate of switch 583 without an external wire connector. Hybrid capacitor 575 is connected to the input side of module 900 between first input lead 931 and high-side switch 582. Integrating cascode switches 582 and 583 into an SMPD-type package allows for simplified and efficient integration of the half-bridge circuit into an industry-standard power device package.

[0072] FIG. 10 is a top view of an integrated electronic module 1000, similar to electronic module 900 of FIG. 9, except that, compared to the input side of the module shown in FIG. 9, module 1000 connects a hybrid capacitor 1075 between a ground plate 1013 and a high-voltage plate 1011 on the output side of module 1000. Module 1000 includes a DBC 1010 including a high-voltage plate 1011, an output plate 1012, and a ground plate 1013, with each plate separated by a groove 1014 formed in the top metal layer of DBC 1010. DBC 1010 can be constructed in a manner similar to DBC 510 of FIGS. 5A and 5B, but with an alternative top metal layer configuration as a result of the separation pattern from groove 1014. Here, high-side switch 582 and source sense lead 962 are both connected directly to first output plate 1012, and connector 66 of FIG. 6 is omitted. Connector 66' of module 1000 has a first side that connects to output plate 1012 and a second side that connects to output plate 1012'. Output node 992 is in direct contact with second output plate 1012', which places output node 992 and the source of cascode switch 582 at the same potential.

[0073] FIG. 11 is a top view of an integrated electronic module 1100, similar to electronic module 1000 of FIG. 10, except that module 1100 includes a capacitor 1174 and a resistor 1175 as two separate components connected in series to connect high voltage plate 1111 and ground plate 1113 (unlike module 1000, which uses a single hybrid component 1075), thereby maintaining high voltage plate 1111 at the AC ground of DBC 1110. The use of two separate components allows for the selection of additional components to be used by the circuit designer to modify the performance of the package. Additionally, the relative order of capacitor 1174 and resistor 1175 is interchangeable.

[0074] 12 is a top view of an integrated electronic module 1200, similar to electronic module 1000 of FIG. 10, except that module 1200 is implemented with a source ferrite bead 1266 (having a first terminal electrically coupled to the source voltage of high-side switch 582 and a second terminal electrically coupled to output lead 992). Source ferrite bead 1266 can be implemented such that the ferrite bead bridges high voltage plate 1011, similar to connector 66' of FIG. 10. Implementing module 1200 with source ferrite bead 1266 instead of using connector 66' can help suppress voltage ringing and other noise at the output node, further improving operation of the half-bridge module.

[0075] 13A and 13B show side and top views, respectively, of an external rendering of a fully encapsulated SMPD-type package that can be used for modules 900-1200. The encapsulated package includes a molding compound 1311 (plastic, epoxy, metal, or other suitable material for hermetically sealing and electrically encapsulating each component of an integrated electronic module).

[0076] Although integrated electronic modules 900, 1000, 1100, and 1200 illustrate surface mounted power device (SMPD) package types, alternative module packages may be used, such as quad flat no-lead (QFN) or loss-free package (LFPAK), or other types of suitable module packages capable of adequately housing high-side 582 and low-side switches 583 to form a half-bridge circuit. Each component of modules 900-1200 may be arranged or arranged in a manner that best suits the needs of the designer and package type.

[0077] 14 is a top view of an integrated electronic module 1400, similar to electronic module 500 of FIG. 5A, except that module 1400 is implemented with two high-side switches (582 and 582a) connected in parallel and two low-side switches (583 and 583a) connected in parallel. Connector 41a connects high-voltage plate 11 to drain electrode 36a of each D-mode transistor of high-side switch 582a. Connector 42a connects source electrode 51a of the E-mode transistor of high-side switch 582a to output plate 12. Connector 43a connects output plate 12 to drain electrode 36a' of the D-mode transistor of low-side switch 583a, and connector 44a connects source electrode 51a' of the E-mode transistor of low-side switch 583a to ground plate 13. First input lead 572 is connected to the gate electrode of the E-mode transistor in each of high-side switches 582 and 582a, and second input lead 573 is connected to the gate electrode of the E-mode transistor in each of low-side switches 583 and 583a. Note that the substrate of first high-side switch 582 and the substrate of second high-side switch 582a are both electrically connected to and contact the same portion of the top metal layer of DBC 1410 that forms output plate 12. Also, the substrate of first low-side switch 583 and the substrate of second low-side switch 583a are both electrically connected to and contact the same portion of the top metal layer of DBC 1410 that forms ground plate 13. Configuring module 1400 with multiple switches connected in parallel and mounted on the same portion of the top metal layer improves module performance and enables much higher overall power ratings.

[0078] During operation of module 1400, when first input lead 572 is switched on or off, both switches 582 and 582a are switched on or off simultaneously. Similarly, when second input lead 573 is switched on or off, both switches 583 and 583a are switched on or off simultaneously. Typically, paralleling half-bridge circuits using multiple distributed components involves external routing wires that can cause circuit matching issues when switched at high speeds. Integrating these switching transistors into the same electronic module can mitigate switching mismatch issues and improve overall circuit performance. While FIG. 14 shows two high-side switches and two low-side switches, for example, three or four high-side and low-side switches may be connected in parallel. Theoretically, there is no limit to the number of switches that can be paralleled in this manner.

[0079] 1B, there is shown a circuit schematic of a three-phase full-bridge circuit 120. Each of the three half-bridges 122, 124, and 126 in circuit 120 can be implemented using an integrated electronic module (e.g., electronic modules 300-1400 described herein).

[0080] FIG. 15 is a top view of an electronic module 1500 that includes an integrated three-phase full-bridge circuit (e.g., circuit 120 of FIG. 1B) in a single package. The first-phase half-bridge circuit includes a high-side switch 82 and a low-side switch 83. The second-phase half-bridge circuit includes a high-side switch 82′ and a low-side switch 83′. The third-phase half-bridge circuit includes a high-side switch 82″ and a low-side switch 83″. The high-side and low-side switches can all be implemented using the cascode switch 600 of FIG. 6. The module 1500 includes a DBC layer 1510 whose top metal layer is patterned into at least five sections separated by grooves 1514 formed through the top metal layer of the DBC 1510. The first section serves as the high-voltage plate 14, which is configured to be connected to a DC high voltage via a high-voltage lead 91. The second section serves as the output plate 15, which is connected to the first-phase output node 92. The third portion functions as output plate 16, which is connected to phase-2 output node 92'. The fourth portion functions as output plate 17, which is connected to phase-3 output node 92''. The fifth portion functions as ground plate 18, which is configured to be connected to DC ground via ground lead 93.

[0081] The substrates of high-side switches 82, 82', and 82'' are electrically connected to output plates 15, 16, and 17, respectively. The substrates of low-side switches 83, 83', and 83'' are electrically connected to ground plate 18, and all of the low-side switches are electrically connected to the same metal part of DBC1510. The substrates of high-side switches 82, 82', and 82'' are electrically isolated from each other. The drain electrode 36 of the D-mode transistor node of high-side switch 82 is connected to high-voltage plate 14 at connector 41, the drain electrode 36' of the D-mode transistor of high-side switch 82' is connected to high-voltage plate 14 at connector 41', and the drain electrode 36'' of the D-mode transistor of high-side switch 82'' is connected to high-voltage plate 14 at connector 41''. Source electrode 34 of the E-mode transistor node of high-side switch 82 is connected to output plate 15 at connector 42, source electrode 34' of the E-mode transistor of high-side switch 82' is connected to output plate 16 at connector 42', and source electrode 34'' of the E-mode transistor of high-side switch 82'' is connected to output plate 17 at connector 42''. Drain electrode 56 of the D-mode transistor of low-side switch 83 is connected to first-phase output plate 15 at connector 43, drain electrode 56' of the D-mode transistor of low-side switch 83' is connected to second-phase output plate 16 at connector 43', and drain electrode 56'' of the D-mode transistor of low-side switch 83'' is connected to third-phase output plate 17 at connector 43''. The source electrode 54 of the E-mode transistor node of low-side switch 83 is connected to ground plate 18 by connector 44, the source electrode 54' of the E-mode transistor of low-side switch 83' is connected to ground plate 18 by connector 44', and the source electrode 54'' of the E-mode transistor of low-side switch 83'' is connected to ground plate 18 by connector 44''.

[0082] The gate driver operates the module 1500 using three independent gate signals for operating each high-side switch and three independent gate signals for operating each low-side switch. Each independent high-side gate signal from the gate driver can be connected to gate input nodes 94, 94', and 94'', and each low-side gate signal from the gate driver can be connected to gate input nodes 95, 95', and 95''. Integrating the three-phase full-bridge circuit 120 of FIG. 1B into a single integrated electronic device module 1500 can significantly improve switching efficiency while simultaneously reducing circuit complexity. Although not shown for simplicity, the module 1500 can include an integrated gate driver in the same package as a component of the module 1500. The gate driver can be configured in a manner similar to that described below with respect to FIG. 16.

[0083] FIG. 16 is a top view of an integrated electronic module 1600 forming a half-bridge circuit similar to the integrated electronic half-bridge module 500 of FIG. 5A. However, the module 1600 also includes a gate driver 1620 integrated within the same module package as the high-side switch 582 and the low-side switch 583. Like-numbered components include the same or similar features as in the module 500. The module 1600 includes a DBC 1610. The DBC 1610 includes a high-voltage plate 511, an output plate 512, and a ground plate 513, and optionally a driver plate 515, all separated by a groove 516. The gate driver 1620 may be attached to the driver plate 515, or alternatively, the gate driver 1620 may be attached directly to the module's structural package base (e.g., a copper or Ni lead frame (not shown)). The driver plate 515 may be configured in multiple sections to accommodate and mount multiple leads extending from or connected to the gate driver 1620. The gate driver 1620 includes at least a first terminal 1622 (V IN582). The gate driver 1620 includes a second terminal 1623, which is a high-side source current sense node, which is connected to the output plate 512, or optionally connected directly to the source electrode 651 of the E-mode transistor of the high-side switch 582 (not shown). The gate driver 1620 includes a third terminal 1624 (V IN 583). The gate driver 1620 includes a fourth terminal 1626, which is a low-side source current sense node, connected to the ground plate 513 or, optionally, directly to the source electrode 651′ of the E-mode transistor of the high-side switch 583 (not shown). By integrating the gate driver 1620 into the module 1600, cost and complexity increase relative to the module 500, but the overall performance of the module 1600 may be better than a module 500 operating with an external gate driver. Additionally, the overall size of the electronic circuit components into which the module 1600 may be incorporated may be reduced, resulting in cost savings and other advantages. Although not shown, the gate driver 1620 may be two separate gate drivers, whereby a first gate driver is connected to the high-side switch and a second gate driver is connected to the low-side switch.

[0084] FIG. 17 is a top view of an integrated electronic module 1700 forming a half-bridge circuit similar to integrated electronic half-bridge module 1600 of FIG. 16 . However, module 1700 includes a gate driver 1720 in which the E-mode transistor of high-side switch 582 and the E-mode transistor of low-side switch 583 are integrated within gate driver 1720. High-side D-mode III-N transistor 1782 is attached to output plate 512, and low-side D-mode III-N transistor 1783 is attached to ground plate 513. Gate driver 1720 includes at least a first terminal 1721 connecting the source of the integrated E-mode transistor of the high-side switch to output plate 512. This connection couples the source of the E-mode transistor to output terminal 592 and to the conductive substrate of high-side D-mode III-N transistor 1782. Gate driver 1722 includes a second terminal 1722 connecting the drain of the integrated E-mode transistor of the high-side switch to the source electrode 634 of high-side D-mode III-N transistor 1782. Gate driver 1720 includes a third terminal 1724 connecting the source of the integrated E-mode transistor of the low-side switch to ground plate 513. This connection couples the source of the E-mode transistor to ground terminal 593 and to the conductive substrate of low-side D-mode III-N transistor 1783. Gate driver 1722 includes a fourth terminal 1725 connecting the drain of the integrated E-mode transistor of the low-side switch to the source electrode 634' of low-side D-mode III-N transistor 1783. Integrating the E-mode transistors of the high-side and low-side switches into gate driver 1720 reduces the complexity of module 1700 compared to module 1600, thereby reducing overall assembly costs. Although not shown, the gate driver 1720 may alternatively be two separate gate drivers, with the first gate driver connected to the high-side switch and the second gate driver connected to the low-side switch.

[0085] Although several embodiments have been described, it will be understood that various modifications can be made without departing from the spirit and scope of the techniques and devices described herein. Accordingly, other implementations are within the scope of the following claims.

Claims

1. 1. An electronic module comprising: a package and a conductive lead frame, the conductive lead frame comprising a first portion configured to be connected to a high voltage node, a second portion configured to be connected to an output node, and a third portion configured to be connected to a ground node, each of the first portion, the second portion, and the third portion being electrically isolated from one another; a high-side switch comprising an enhancement-mode transistor and a III-N depletion-mode transistor in a cascode configuration, the III-N depletion-mode transistor comprising a III-N material structure on a conductive substrate; Low-side switch; Equipped with a drain electrode of the III-N depletion-mode transistor electrically connected to the first portion of the lead frame, a source electrode of the enhancement-mode transistor electrically connected to the second portion of the lead frame, a gate electrode of the depletion-mode transistor electrically connected to the conductive substrate of the depletion-mode transistor, and the substrate of the depletion-mode transistor electrically connected to the second portion of the lead frame. Electronic module.

2. the low-side switch comprises a second enhancement-mode transistor and a second III-N depletion-mode transistor, the second III-N depletion-mode transistor comprising a second III-N material structure on a second conductive substrate; a drain electrode of the second depletion-mode transistor electrically connected to the second portion of the lead frame, a source electrode of the second enhancement-mode transistor electrically connected to the third portion of the lead frame, a gate electrode of the second III-N depletion-mode transistor electrically connected to a second conductive substrate, and the second substrate electrically connected to the third portion of the lead frame. The electronic module of claim 1 .

3. The electronic module of claim 2 , wherein the high-side switch and the low-side switch form a half-bridge circuit.

4. 4. The electronic module of claim 3, wherein the depletion-mode transistor is configured to block at least 600 V while the high-side switch is biased off and to be capable of conducting greater than 30 A of current while the high-side switch is biased on.

5. 4. The electronic module of claim 3, further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the first portion of the lead frame, and a second terminal of the capacitor is electrically connected to the third portion of the lead frame.

6. 2. The electronic module of claim 1, further comprising a second high-side switch and a second low-side switch, wherein the first high-side switch and the second high-side switch are electrically connected in parallel, and the first low-side switch and the second low-side switch are electrically connected in parallel.

7. 6. The electronic module according to claim 5, wherein the capacitor is a hybrid capacitor having a resistive element and a capacitive element connected in series.

8. the gate, source, and drain electrodes of the first III-N depletion-mode transistor are on an opposite side of the III-N material structure from the conductive substrate; the III-N material structure having a via hole formed therein; the metal layer forming the gate electrode is electrically connected to the conductive substrate through the via hole; The electronic module of claim 1 .

9. 2. The electronic module of claim 1, further comprising a gate driver contained within the package, a first terminal of the gate driver connected to a gate electrode of the first enhancement mode transistor and a second terminal of the gate driver connected to a gate electrode of the second enhancement mode transistor.

10. The electronic module of claim 9 , wherein the first enhancement mode transistor or the second enhancement mode transistor is internally integrated within the gate driver.

11. A half-bridge circuit, a high-side switch and a low-side switch each housed within a single electronic package, the package having a high voltage terminal, an output terminal, and a ground terminal; the high-side switch comprises a first enhancement-mode transistor and a first depletion-mode III-N transistor arranged in a cascode configuration; the low-side switch comprises a second enhancement-mode transistor and a second depletion-mode III-N transistor arranged in a cascode configuration; a first drain electrode of the first III-N transistor electrically connected to the high voltage terminal, a first gate electrode of the first depletion mode III-N transistor electrically connected to the output terminal, a second drain electrode of the second III-N transistor electrically connected to the output terminal, and a second gate electrode of the second depletion mode III-N transistor electrically connected to the ground terminal; Half-bridge circuit.

12. 12. The circuit of claim 11 , wherein the first gate electrode of the first depletion mode III-N transistor is electrically connected to the substrate of the first depletion mode III-N transistor, and the substrate of the first depletion mode III-N transistor is electrically connected to the output terminal.

13. 13. The circuit of claim 12, wherein the second gate electrode of the second depletion mode III-N transistor is electrically connected to the substrate of the second depletion mode III-N transistor, and the substrate of the second depletion mode III-N transistor is electrically connected to the ground terminal.

14. 14. The circuit of claim 13, wherein the half-bridge circuit further comprises a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being connected to the high voltage terminal and the second terminal being connected to the ground terminal.

15. 15. The circuit of claim 14, wherein the half-bridge circuit further comprises a gate driver contained within the package, a first terminal of the gate driver connected to a gate electrode of the first enhancement mode transistor and a second terminal of the gate driver connected to a gate electrode of the second enhancement mode transistor.

16. 16. The circuit of claim 15, wherein the first enhancement mode transistor and the second enhancement mode transistor are integrated within the gate driver.

17. 15. The circuit of claim 14, wherein the half-bridge circuit further comprises a second high-side switch and a second low-side switch, the first high-side switch and the second high-side switch being electrically connected in parallel, and the first low-side switch and the second low-side switch being electrically connected in parallel.

18. The circuit of claim 11 , wherein the circuit comprises: η high-side switches connected in parallel; and η low-side switches connected in parallel.

19. 1. An electronic module comprising: first, second, and third high-side switches; first, second, and third low-side switches; a single common electronic package housing each of the first, second, and third high-side switches and the first, second, and third low-side switches, the electronic package comprising a first metal layer electrically connected to a high voltage terminal and a second metal layer electrically connected to a ground terminal; Equipped with the first, second, and third low-side switches each comprise an enhancement-mode transistor and a depletion-mode III-N transistor arranged in a cascode configuration, each depletion-mode III-N transistor comprising a respective III-N material structure formed on a respective conductive substrate, each conductive substrate of the first, second, and third low-side switches electrically connected to the second metal layer of the electronic package, and each gate electrode of the first, second, and third depletion-mode III-N transistor electrically connected to its respective conductive substrate; the first, second, and third high-side switches and the first, second, and third low-side switches form a three-phase bridge circuit; Electronic module.

20. 20. The electronic module of claim 19, wherein the package further comprises third, fourth, and fifth metal layers, a substrate of the first high-side switch connected to the third metal layer, a substrate of the second high-side switch connected to the fourth metal layer, and a substrate of the third high-side switch connected to the fifth metal layer, and the first, second, third, fourth, and fifth metal layers are all electrically isolated from one another.

21. 21. The electronic module of claim 20, further comprising a first output terminal, a second output terminal, and a third output terminal, wherein the first output terminal is electrically connected to the third metal layer, the second output terminal is electrically connected to the fourth metal layer, and the third output terminal is electrically connected to the fifth metal layer.

22. 22. The electronic module of claim 21 , wherein in the first low-side switch, the gate electrode of the III-N depletion-mode transistor is on an opposite side of the III-N material structure from the conductive substrate, the III-N material structure having a via hole formed therein, and a metal layer forming the gate electrode is electrically connected to the conductive substrate through the via hole.

23. 20. The electronic module of claim 19, further comprising a capacitor, a first terminal of the capacitor electrically connected to the first metal layer and a second terminal of the capacitor electrically connected to the second metal layer.

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