Semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A semiconductor device including an oxide semiconductor which is a first semiconductor, a silicon which is a second semiconductor, and a plurality of memory cells connected in a first direction, in which one memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, and a part of the first semiconductor functions as a channel formation region of the writing transistor, and a part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements, are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, electronic devices, and the like may include semiconductor elements or semiconductor circuits. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, electronic devices, and the like may also be called semiconductor devices. [Background technology]

[0004] In recent years, with the increase in the amount of data handled, there has been a demand for semiconductor devices with larger storage capacities. To increase storage capacity per unit area, a three-dimensional storage device formed by stacking memory cells is known (Patent Document 1). In three-dimensional storage devices, semiconductor layers are often provided extending in the stacking direction of the memory cells. Furthermore, in three-dimensional storage devices, semiconductors containing many grain boundaries, such as polycrystalline silicon, are often used for the semiconductor layers.

[0005] Polycrystalline silicon and the like have many grain boundaries, making it difficult to improve operating speed and reduce the variation in characteristics between memory cells. A crystallization technique for producing crystalline silicon using nickel (Ni) or other catalyst elements to reduce grain boundaries and increase crystal grain size is known (Patent Document 2). Patent Document 2 also discloses the crystal growth mechanism using a catalyst element and the technical concept of fixing the catalyst element used for crystallization in a gettering region.

[0006] Patent Document 3 discloses a technical concept of applying crystallization technology using catalytic elements to a memory device with a three-dimensional structure. Furthermore, oxide semiconductors, which are a type of metal oxide, have been attracting attention in recent years. Non-Patent Document 1 discloses CAAC-IGZO as an oxide semiconductor. Non-Patent Document 1 also discloses the growth mechanism of CAAC-IGZO. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US Patent Publication No. 2011 / 0065270A1 [Patent Document 2] Japanese Patent Application Laid-Open No. 2000-133594 [Patent Document 3] Japanese Patent Application Publication No. 2019-054220 [Non-patent literature]

[0008] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO” FUNDAMENTALS (USA), Wiley-SID Series in Display Technology, 2017, p.94-97 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a highly reliable memory device. Another object is to provide a memory device with a large storage capacity. Another object is to provide a memory device with a small occupancy area. Another object is to provide a memory device with high operating speed. Another object is to provide a memory device with low manufacturing cost. Another object is to provide a novel memory device. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with a small occupancy area. Another object is to provide a semiconductor device with high operating speed. Another object is to provide a semiconductor device with low manufacturing cost. Another object is to provide a novel semiconductor device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a semiconductor device comprising a first semiconductor extending in a first direction, a second semiconductor extending in the first direction, and a plurality of memory cells arranged in the first direction, wherein the memory cells comprise a first transistor and a second transistor, a portion of the first semiconductor functions as a channel formation region of the first transistor, and a portion of the second semiconductor functions as a channel formation region of the second transistor, the first semiconductor includes an oxide semiconductor, the second semiconductor includes silicon, the second semiconductor has a region in contact with the first layer, and the first layer includes a first metal element.

[0012] Another aspect of the present invention is a semiconductor device comprising: a structure extending in a first direction; a plurality of first conductors extending in a second direction intersecting the first direction; and a plurality of second conductors extending in the second direction; the structure comprising a third conductor, a first insulator, a plurality of fourth conductors, a first semiconductor, a second insulator, a second semiconductor, and a third insulator; at each intersection of the plurality of first conductors and the structure, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are each concentrically arranged outside the third conductor; at each intersection of the plurality of second conductors and the structure, the first insulator, the fourth conductor, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are each concentrically arranged outside the third conductor; the first semiconductor includes an oxide semiconductor; the second semiconductor includes silicon; the second semiconductor has a region in contact with the first layer; and the first layer includes a first metal element.

[0013] The first metal element is an element that functions as a catalytic element. For example, nickel can be used as the first metal element. The first layer may contain impurity elements such as phosphorus.

[0014] The oxide semiconductor preferably contains at least one of indium and zinc. In particular, it is preferable that the oxide semiconductor contains both indium and zinc. In addition, various crystalline oxide semiconductors such as CAAC-OS, nc-OS, and a-like OS can be used as the oxide semiconductor. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a highly reliable memory device can be provided. Alternatively, a memory device with a large storage capacity can be provided. Alternatively, a memory device with a small occupancy area can be provided. Alternatively, a memory device with a high operating speed can be provided. Alternatively, a memory device with low manufacturing cost can be provided. Alternatively, a novel memory device can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with a small occupancy area can be provided. Alternatively, a semiconductor device with a high operating speed can be provided. Alternatively, a semiconductor device with low manufacturing cost can be provided. Alternatively, a novel semiconductor device can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a perspective view of a storage device. [Figure 2] FIG. 2 is a cross-sectional view of the storage device. [Figure 3] FIG. 3 is a cross-sectional view of a memory string. [Figure 4] FIG. 4 is a cross-sectional view of a memory string. [Figure 5] 5A and 5B are cross-sectional views of a memory string. [Figure 6] 6A and 6B are cross-sectional views of a memory string. [Figure 7] 7A and 7B are cross-sectional and perspective views of a memory element. [Figure 8] 8A and 8B are cross-sectional views of a memory string. [Figure 9]9A to 9F are cross-sectional views of memory strings. [Figure 10] 10A and 10B are cross-sectional views of a memory string. [Figure 11] Fig. 11A is a diagram illustrating the classification of the crystal structure of oxide semiconductors, Fig. 11B is a diagram illustrating the XRD spectrum of a CAAC-IGZO film, and Fig. 11C is a diagram illustrating the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 12] 12A to 12C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A to 13C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A to 14C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A to 15C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A to 16C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A to 17C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A to 18C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A to 19C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A to 20C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A to 21C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A to 22C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 23]23A to 23C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A to 24C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A to 25D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A to 26C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A to 27C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 28] 28A to 28C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 29] 29A to 29C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 30] 30A to 30C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 31] 31A to 31C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 32] 32A to 32C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 33] 33A to 33C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 34] 34A to 34C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 35 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 36] FIG. 36 is an equivalent circuit diagram of the memory element MC. [Figure 37] FIG. 37 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 38]FIG. 38 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 39] FIG. 39 is a timing chart illustrating an example of a write operation of a memory string. [Figure 40] 40A and 40B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 41] 41A and 41B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 42] 42A and 42B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 43] 43A and 43B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 44] 44A and 44B are timing charts illustrating an example of a read operation of a memory string. [Figure 45] 45A and 45B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 46] 46A and 46B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 47] 47A and 47B are diagrams illustrating the Id-Vg characteristics of a transistor. [Figure 48] FIG. 48 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 49] 49A to 49C are perspective views illustrating configuration examples of a semiconductor device. [Figure 50] FIG. 50 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 51] 51A to 51E are diagrams for explaining an example of a storage device. [Figure 52] 52A to 52G are diagrams for explaining an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0019] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0020] In addition, in the drawings and the like, the illustration of some components may be omitted in order to make the explanation easier to understand.

[0021] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wirings" are integrally formed.

[0022] In this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0023] In this specification, the terms "above" and "below" do not limit the positional relationship between components to directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0024] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current flow changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0025] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only wiring may be extended.

[0026] Furthermore, in this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.

[0027] In this specification and elsewhere, when referring to counting values ​​and measurement values, or to objects, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "same," "equal," or "uniform" are intended to include an error of plus or minus 20%, unless otherwise specified.

[0028] Furthermore, in this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0029] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0030] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0031] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0032] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0033] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0034] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0035] In this specification, the high power supply potential VDD (hereinafter simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter simply referred to as "VSS," "L potential," or "L"). VSS refers to a power supply potential that is lower than VDD. Ground potential (hereinafter simply referred to as "GND" or "GND potential") can also be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0036] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field-effect transistors. Therefore, their threshold voltages (also referred to as "Vth") are assumed to be greater than 0 V. Unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." Unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0037] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0038] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0039] In this specification, the term "drain" refers to a part or all of the drain region, drain electrode, and drain wiring. The term "drain region" refers to a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or another wiring.

[0040] In addition, in drawings and the like, to make it easier to understand the potential of a wiring, electrode, conductor, etc., an "H" indicating an H potential or an "L" indicating an L potential may be written next to the wiring, electrode, conductor, etc. Furthermore, a wiring, electrode, conductor, etc. in which a potential change has occurred may be written with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be written over the transistor.

[0041] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0042] Furthermore, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "a," "A," "_1," "_2," "[m, n]," etc. For example, one of two wirings GL may be described as wiring GLa, and the other as wiring GLb.

[0043] (Embodiment 1) FIG. 1 shows a perspective view of a storage device 100 according to one embodiment of the present invention. The storage device 100 is a storage device having a three-dimensional stacked structure. FIG. 2 is a cross-sectional view of a portion A1-A2 indicated by a dashed line in FIG. 1. Note that in FIG. 1 and other figures, arrows indicating the X, Y, and Z directions may be added. The X, Y, and Z directions are mutually orthogonal. In this specification and other figures, the direction perpendicular to the top surface of a base 121, which will be described later, is defined as the Z direction.

[0044] In this specification and elsewhere, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining may be referred to as the "third direction" or "third direction."

[0045] Fig. 2 shows a cross section of the XZ plane. As mentioned above, some components may be omitted in Fig. 1 and Fig. 2 for ease of explanation.

[0046] <Storage device configuration example> A memory device 100 according to one embodiment of the present invention includes a memory cell array 110 (see FIG. 1). The memory cell array 110 includes a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane. FIG. 3 shows an example of a cross-sectional configuration of the memory string 120.

[0047] The memory string 120 includes a plurality of storage elements MC (also referred to as "memory cells") arranged in the Z direction. In other words, the memory string 120 includes a plurality of storage elements MC connected in series. While FIG. 3 shows a case where five storage elements MC are connected in series, the number of storage elements MC included in the memory string 120 is not limited to five. If the number of storage elements MC included in the memory string 120 is n, n may be an integer equal to or greater than 2.

[0048] 3, the five memory elements MC are denoted as memory elements MC_1 to MC_5. Note that when describing matters common to the memory elements MC_1 to MC_5, they are simply referred to as "memory element MC." The same applies to other components such as the conductor WWL, the conductor RWL, and the insulator 123.

[0049] The memory string 120 includes a transistor STr1 electrically connected to the storage element MC_1 and a transistor STr2 electrically connected to the storage element MC_5.

[0050] The memory device 100 also has a plurality of conductors WWL, a plurality of conductors RWL, and a conductor SG above the base 121. The plurality of conductors WWL, the plurality of conductors RWL, and the conductor SG extend in the X direction (see FIGS. 1 and 2). The conductors WWL, the conductors RWL, and the conductor SG have regions that overlap with the memory cell array 110. The conductors WWL, the conductors RWL, and the conductor SG are stacked in a stepped manner outside the memory cell array 110.

[0051] The conductor SG is provided below the plurality of conductors WWL and the plurality of conductors RWL. In FIG. 3, a layer 122 is provided on a base 121, an insulator 123_1 is provided on the layer 122, and the conductor SG is provided on the insulator 123_1. The conductors WWL and RWL are alternately stacked with the insulator 123 interposed therebetween. For example, in FIG. 3, an insulator 123_2 is provided on the conductor SG, a conductor RWL_1 is provided on the insulator 123_2, an insulator 123_3 is provided on the conductor RWL_1, a conductor WWL_1 is provided on the insulator 123_3, and an insulator 123_4 is provided on the conductor WWL_1. As will be described in detail later, the layer 122 functions as a gettering layer.

[0052] The memory string 120 has a structure 160. The structure 160 is provided so as to penetrate the conductor WWL, the conductor RWL, the conductor SG, and the insulator 123. The structure 160 also has a region in contact with the layer 122. An example of the cross-sectional configuration of the structure 160 is shown in FIG. 4. Note that FIGS. 4 and 3 are cross-sectional views of the same portion. In FIG. 4, the conductor WWL, the conductor RWL, the conductor SG, the insulator 123, the layer 122, the base 121, and the like are indicated by dashed lines.

[0053] The structure 160 has a columnar structure including a conductor 130, an insulator 129, a semiconductor 127, an insulator 126, a semiconductor 125, an insulator 124, and a plurality of conductors 128. In FIG. 4 , a central axis 169 of the memory string 120 extending in the Z direction is indicated by a two-dot chain line. More specifically, the conductor 130 extends along the central axis 169, and the insulator 129 is provided adjacent to a side surface of the conductor 130. The semiconductor 127 is provided adjacent to the insulator 129, and the insulator 126 is provided adjacent to the semiconductor 127. The semiconductor 125 is provided adjacent to the insulator 126, and the insulator 124 is provided adjacent to the semiconductor 125. The semiconductor 125 has a region in contact with the layer 122. The structure 160 also includes a conductor 128 provided between the insulator 129 and the semiconductor 127 at an intersection of the conductor RWL and the structure 160.

[0054] 5A shows a cross-sectional view of the portion B1-B2 indicated by the dashed dotted line in FIG. 3 as viewed from the Z direction. FIG. 5A is a cross-sectional view of the intersection between the conductor WWL and the structure 160. At the intersection, the insulator 129, the semiconductor 127, the insulator 126, the semiconductor 125, and the insulator 124 are each provided concentrically outside the conductor 130.

[0055] 5B shows a cross-sectional view of the portion C1-C2 indicated by the dashed dotted line in FIG. 3 as viewed from the Z direction. FIG. 5B is a cross-sectional view of the intersection of the conductor RWL and the structure 160. At the intersection, the insulator 129, the conductor 128, the semiconductor 127, the insulator 126, the semiconductor 125, and the insulator 124 are each provided concentrically outside the conductor 130.

[0056] 5A and 5B show a cross section (XY cross section) of one memory string 120, while Figures 6A and 6B show an example in which multiple memory strings 120 are provided. The multiple memory strings 120 may be arranged side by side in the X direction, or may be arranged side by side in the Y direction, or may be arranged in a matrix.

[0057] 7A shows an enlarged view of the region 105 indicated by the two-dot chain line in FIG. 3. FIG. 7A corresponds to a cross-sectional view of the memory element MC. FIG. 7B shows a perspective cross-sectional view of the memory element MC. Note that in order to make the structure of the memory element MC easier to understand, the insulator 123 is omitted from FIG. 7B.

[0058] The intersection of the conductor WWL and the structure 160 functions as the transistor WTr. The intersection of the conductor RWL and the structure 160 functions as the transistor RTr. Specifically, the conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the backgate electrode of the transistor WTr. A portion of the semiconductor 127 functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via portions of the insulator 126, the semiconductor 125, and the insulator 124. Note that, in the present embodiment and the like, an example is shown in which a portion of the conductor WWL functions as the gate electrode, but the gate electrode and the conductor WWL may be provided independently and electrically connected to each other.

[0059] The conductor 128 functions as the gate electrode of the transistor RTr. The conductor RWL functions as the back gate electrode of the transistor RTr. A part of the semiconductor 125 functions as a semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the gate electrode (conductor 128) via a part of the insulator 126. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the back gate electrode (conductor RWL) via a part of the insulator 124. Note that in the present embodiment and the like, an example is shown in which a part of the conductor RWL functions as the back gate electrode, but the back gate electrode and the conductor RWL may be provided independently and electrically connected to each other.

[0060] Furthermore, dividing the memory string 120 along the Z direction is preferable because it increases the storage capacity per unit area. When dividing the memory string 120 along the Z direction, the conductors WWL and RWL may also be divided.

[0061] FIG. 8A shows how the conductor WWL and the memory string 120 are divided by the insulator 153 provided along the XZ plane, and FIG. 8B shows how the conductor RWL and the memory string 120 are divided by the insulator 153 provided along the XZ plane. Note that FIG. 8A corresponds to a modified example of the cross section shown in FIG. 5A. FIG. 8B corresponds to a modified example of the cross section shown in FIG. 5B. In FIG. 8 and other figures, the symbols of the divided components are suffixed with "a" or "b."

[0062] As shown in FIG. 8A , the region where the conductor WWL_a and the conductor 130_a overlap functions as the transistor WTr_a. Specifically, the region where the conductor WWL_a, the insulator 124_a, the semiconductor 125_a, the insulator 126_a, the semiconductor 127_a, the insulator 129_a, and the conductor 130_a overlap functions as the transistor WTr_a. The conductor WWL_a functions as the gate electrode of the transistor WTr_a, and the conductor 130_a functions as the backgate electrode of the transistor WTr_a. A portion of the semiconductor 127_a functions as a semiconductor layer in which the channel of the transistor WTr_a is formed. The semiconductor layer in which the channel of the transistor WTr_a is formed overlaps with the gate electrode (conductor WWL_a) via a portion of the insulator 124_a, a portion of the semiconductor 125_a, and a portion of the insulator 126_a.

[0063] Furthermore, the region where the conductor WWL_b and the conductor 130_b overlap functions as the transistor WTr_b. Specifically, the region where the conductor WWL_b, the insulator 124_b, the semiconductor 125_b, the insulator 126_b, the semiconductor 127_b, the insulator 129_b, and the conductor 130_b overlap functions as the transistor WTr_b. The conductor WWL_b functions as the gate electrode of the transistor WTr_b, and the conductor 130_b functions as the backgate electrode of the transistor WTr_b. Furthermore, a portion of the semiconductor 127_b functions as a semiconductor layer in which the channel of the transistor WTr_b is formed. The semiconductor layer in which the channel of the transistor WTr_b is formed overlaps with the gate electrode (conductor WWL_a) via a portion of the insulator 124_b, a portion of the semiconductor 125_b, and a portion of the insulator 126_b.

[0064] As shown in FIG. 8B, the region where the conductor RWL_a and the conductor 130_a overlap functions as the transistor RTr_a. Specifically, the RWL_a, the insulator 124_a, the semiconductor 125_a, the insulator 126_a, the semiconductor 127_a, the conductor 128_a, the insulator 129_a, and the conductor 130_a function as the transistor RTr_a. The conductor RWL_a functions as the gate electrode of the transistor RTr_a. The conductor 130_a functions as the backgate electrode of the transistor RTr_a. A portion of the semiconductor 125_a functions as a semiconductor layer in which the channel of the transistor RTr_a is formed. The semiconductor layer in which the channel of the transistor RTr_a is formed overlaps with the gate electrode (conductor RWL_a) via the insulator 124_a. The semiconductor layer in which the channel of the transistor RTr_a is formed overlaps with the back gate electrode (conductor 130_a) via part of the insulator 126_a, part of the semiconductor 127_a, part of the conductor 128_a, and part of the insulator 129_a.

[0065] Furthermore, the region where the conductor RWL_b and the conductor 130_b overlap functions as the transistor RTr_b. Specifically, RWL_b, the insulator 124_b, the semiconductor 125_b, the insulator 126_b, the semiconductor 127_b, the conductor 128_b, the insulator 129_b, and the conductor 130_b function as the transistor RTr_b. The conductor RWL_b functions as the gate electrode of the transistor RTr_b. The conductor 130_b functions as the backgate electrode of the transistor RTr_b. A portion of the semiconductor 125_b functions as a semiconductor layer in which the channel of the transistor RTr_b is formed. The semiconductor layer in which the channel of the transistor RTr_b is formed overlaps with the gate electrode (conductor RWL_b) via the insulator 124_b. The semiconductor layer in which the channel of the transistor RTr_b is formed overlaps with the back gate electrode (conductor 130_b) via part of the insulator 126_b, part of the semiconductor 127_b, part of the conductor 128_b, and part of the insulator 129_b.

[0066] As described above, by dividing the conductors WWL, RWL, and memory strings 120, the memory capacity per unit area can be doubled. The method of dividing the memory strings 120 is not limited to the above. In FIGS. 8A and 8B, the memory strings 120 are divided by the insulators 153 extending in the X direction. However, as shown in FIGS. 9A and 9B, the insulators 153 may extend in a direction different from the X direction. Furthermore, as shown in FIGS. 9C to 9F, the memory strings 120 may be divided into three or more parts. FIGS. 9C and 9D show an example in which the memory strings 120 are divided into three parts, and FIGS. 9E and 9F show an example in which the memory strings 120 are divided into four parts. In this way, the memory capacity per unit area can be increased.

[0067] 9A to 9F, the insulator 153 is preferably arranged so as not to interfere with the conduction of the conductors WWL and RWL in the X direction.

[0068] Here, we will explain the back gate. The gate and back gate are arranged so that they overlap with each other via the channel formation region of the semiconductor layer. The back gate can function in the same way as the gate. In addition, by changing the potential of the back gate, the threshold voltage of the transistor can be changed. Either the gate or the back gate may be called the "first gate" or "first gate," and the other may be called the "second gate" or "second gate."

[0069] The gate and back gate are formed from conductive layers or semiconductor layers with low resistivity, and therefore have the function of preventing external electric fields from acting on the semiconductor layer where the channel is formed (particularly, electrostatic shielding against static electricity). In other words, it is possible to prevent fluctuations in the electrical characteristics of the transistor due to the influence of external electric fields such as static electricity.

[0070] The threshold voltage of the transistor can be controlled by controlling the potential of the back gate, which may be the same potential as the gate, the ground potential (GND potential), or any other potential.

[0071] The semiconductor layers in which the channels of the transistors WTr and RTr are formed can be made of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used. The same applies to the transistors STr1 and STr2.

[0072] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for the respective layers.

[0073] The transistor RTr is turned on when data stored in the memory device 100 is read. Therefore, it is preferable to use a semiconductor material with high mobility as the semiconductor layer of the transistor RTr. As such a semiconductor, it is preferable to use, for example, a semiconductor with improved crystallinity using a catalytic element, as disclosed in Patent Document 2. A semiconductor with improved crystallinity using a catalytic element reduces crystal grain boundaries, thereby increasing the operating speed of the transistor. Furthermore, since the characteristic variation of the transistor is reduced, the operation of the semiconductor device is stabilized and the reliability is improved. Furthermore, since the characteristic variation of the transistor is reduced, the number of memory elements MC provided in one memory string can be increased. Therefore, the memory capacity per unit area can be increased. Therefore, the occupied area of ​​the semiconductor device can be reduced.

[0074] In this embodiment, the semiconductor layer of the transistor RTr is made of silicon with improved crystallinity (reduced grain boundaries) using nickel (Ni) as a catalytic element. A manufacturing method will be described later.

[0075] The transistor WTr is a transistor for writing data to the memory device 100 and for retaining the written data. The transistor WTr is turned on during a data write operation, but is mainly used in an off state. Therefore, the transistor RTr is preferably a transistor with low off-state current. An oxide semiconductor, which is a type of metal oxide, is preferably used as a semiconductor material for a transistor with low off-state current.

[0076] Since an oxide semiconductor has a band gap of 2 eV or more, a transistor (also referred to as an "OS transistor") using an oxide semiconductor for a semiconductor layer in which a channel is formed has an extremely low off-state current. When an OS transistor is used as the transistor WTr, data written to the memory element MC can be retained for a long period of time. When an OS transistor is used as the transistor constituting the memory element MC, the memory element MC can be called an "OS memory." Furthermore, the memory string 120 including the memory element MC can also be called an "OS memory." Furthermore, the memory device 100 can also be called an "OS memory." Furthermore, an OS memory is a type of memory device. Therefore, the memory element MC and the memory string 120 are also types of memory devices.

[0077] The OS memory can retain written data for more than one year, or even more than ten years, even if the power supply is cut off, so the OS memory can also be considered non-volatile memory.

[0078] Furthermore, since the data (amount of charge) written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1 bit) information, but also multi-value (multi-bit) or analog value information.

[0079] Furthermore, because OS memory writes charge to nodes via transistors, it does not require the high voltages required by conventional flash memory, enabling high-speed write operations. Furthermore, OS memory does not require the erase operation required by flash memory before rewriting data. Furthermore, because no charge is injected or extracted from the floating gate or charge trapping layer, OS memory allows for virtually unlimited data write and read operations. OS memory is less susceptible to degradation than conventional flash memory, making it highly reliable.

[0080] In addition, OS memory does not involve atomic-level structural changes like magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), and therefore has better rewrite endurance than magnetoresistive random access memory and resistive random access memory.

[0081] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory operates stably and has high reliability even in a high-temperature environment. Furthermore, an OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that operates stably and has high reliability even in a high-temperature environment can be realized.

[0082] In this embodiment and the like, IGZO (a metal oxide containing In, Ga, and Zn) is used as an oxide semiconductor for a semiconductor layer of the transistor WTr. As the oxide semiconductor for the transistor WTr, various crystalline oxide semiconductors such as CAAC-OS, nc-OS, and a-like OS can be used. Oxide semiconductors will be described in detail later.

[0083] The transistor WTr that writes and holds data is preferably an enhancement type (normally off type) transistor to ensure an off state. The transistor RTr that reads data is preferably a depletion type (normally on type) transistor with a small threshold voltage to achieve faster operation. Therefore, the threshold voltage of the transistor RTr is preferably smaller than that of the transistor WTr.

[0084] Depending on the purpose or application, the semiconductor 125 and the semiconductor 127 may be made of the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. Alternatively, the semiconductor 125 and the semiconductor 127 may each be a semiconductor in which the grain boundaries are reduced by using a catalytic element. Alternatively, the semiconductor 125 may be an oxide semiconductor, and the semiconductor 127 may be a semiconductor in which the grain boundaries are reduced by using a catalytic element.

[0085] The transistors STr1 and STr2 may be OS transistors or Si transistors (transistors using silicon in a semiconductor layer in which a channel is formed) that can operate at higher speed than OS transistors.

[0086] 5A corresponds to the XY plane at or near the center of the transistor WTr, and FIG. 5B corresponds to the XY plane at or near the center of the transistor RTr. In FIG. 5A and FIG. 5B, when the cross-sectional shape of the conductor 130 as viewed from the Z direction is circular, the insulator 129 is provided concentrically outside the conductor 130, the semiconductor 127 is provided concentrically outside the insulator 129, the insulator 126 is provided concentrically outside the semiconductor 127, the semiconductor 125 is provided concentrically outside the insulator 126, and the insulator 124 is provided concentrically outside the semiconductor 125. The conductor 128 is provided concentrically between the insulator 129 and the semiconductor 127.

[0087] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. As shown in Fig. 10A, the cross-sectional shape of the conductor 130 may be rectangular. As shown in Fig. 10B, the cross-sectional shape of the conductor 130 may be triangular. Therefore, the cross-sectional shape of the structure 160 when viewed from the Z direction is not limited to a circle.

[0088] [Constituent materials of semiconductor device] Next, constituent materials that can be used for the storage device 100 will be described.

[0089] [substrate] The memory device 100 can be provided on a substrate. Examples of the substrate include an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include an insulating substrate with a conductor or semiconductor provided thereon, a semiconductor substrate with a conductor or insulator provided thereon, and a conductive substrate with a semiconductor or insulator provided thereon. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0090] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0091] In this specification and the like, the term "oxynitride" refers to a material that contains more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material that contains more oxygen than nitrogen. In this specification and the like, the term "nitride oxide" refers to a material that contains more nitrogen than oxygen, and the term "aluminum nitride oxide" refers to an aluminum material that contains more nitrogen than oxygen.

[0092] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0093] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0094] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0095] Furthermore, the electrical characteristics of an OS transistor can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0096] When an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 125 and / or the semiconductor 127, oxygen vacancies in the semiconductor 125 and / or the semiconductor 127 can be compensated for.

[0097] [conductor] The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0098] Furthermore, a semiconductor with increased electrical conductivity due to the addition of p-type or n-type impurities can be used as the conductor. For example, when silicon is used as the conductor, a silicide containing titanium, cobalt, nickel, or the like can also be used.

[0099] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0100] When an oxide semiconductor, which is a type of metal oxide, is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0101] In particular, a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed is preferably used as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0102] [Oxide semiconductor] The oxide semiconductor preferably contains at least one of indium and zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0103] Here, we consider a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is one or more selected from aluminum, gallium, yttrium, and tin. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, a combination of two or more of the above elements may be used as the element M.

[0104] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0105] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 11A, which is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO.

[0106] As shown in FIG. 11A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0107] The structure within the bold frame in Figure 11A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be described as a structure that is completely different from "crystal" or the energetically unstable "amorphous."

[0108] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 11B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 11B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 11B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 11B is 500 nm.

[0109] As shown in Figure 11B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 11B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0110] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 11C. Figure 11C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 11C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0111] As shown in Figure 11C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0112] [Oxide semiconductor structure] Note that oxide semiconductors may be classified differently from those shown in FIG. 11A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0113] Next, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be explained in detail.

[0114] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0115] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0116] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0117] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0118] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0119] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0120] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0121] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the decrease in electron mobility due to grain boundaries is unlikely to occur in CAAC-OS. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0122] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0123] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0124] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0125] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0126] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0127] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0128] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0129] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0130] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0131] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0132] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0133] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0134] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is preferably 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3It is more preferable that the carrier concentration of the oxide semiconductor film is less than 1000 . Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. In addition, being highly purified intrinsic or substantially highly purified intrinsic may be referred to as an i-type or substantially i-type.

[0135] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0136] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0137] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0138] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0139] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0140] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0141] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17atoms / cm 3 Do the following:

[0142] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0143] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0144] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 125 and the semiconductor 127 is not limited to the oxide semiconductors described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor 125 and the semiconductor 127. For example, a semiconductor of an element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may also be used as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0145] In this specification, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0146] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0147] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as semiconductor 125 and semiconductor 127. Specific examples of transition metal chalcogenides that can be used as semiconductor 125 and semiconductor 127 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0148] <Example of how to make a memory device> Next, an example of a method for fabricating a memory device according to the present invention will be described with reference to FIGS. 12 to 34. In each of FIGS. 12 to 34, A in each of the drawings is a top view seen from the Z direction, and B in each of the drawings is a cross-sectional view of the portion indicated by the dashed line A1-A2 in A. In each of FIGS. 12 to 34, C in each of the drawings is a cross-sectional view of the portion indicated by the dashed line A3-A4 in A. Also, FIG. 25D is an enlarged cross-sectional view of the portion surrounded by the dashed line in FIG. 25B. Note that, in this fabrication method, one memory string 120 having two memory elements MC (also referred to as "two stages") is illustrated, but this embodiment is not limited to this. The memory string 120 may have three or more stages of memory elements MC. For example, the memory string 120 may have 32 or more stages, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages of memory elements MC.

[0149] First, a layer 122 is formed on a substrate 121 having an insulating surface, and an insulator 132 is formed around the layer 122 (see FIGS. 12A to 12C).

[0150] First, a conductive film is formed and then processed using lithography to form the layer 122. Next, an insulating film is formed on the substrate 121 so as to cover the layer 122. Next, a planarization process is preferably performed on the insulating film. In this planarization process, the insulating film is preferably polished until the surface of the layer 122 is exposed. The insulator 132 can be formed by the above method, but the method for forming the layer 122 and the insulator 132 is not limited to this. Alternatively, the insulator 132 may be formed on the substrate 121, and unnecessary portions of the insulator 132 may be removed to form grooves and openings, and the layer 122 may be embedded in the grooves and openings. Such a method for forming a conductor is sometimes called a damascene method (single damascene method, dual damascene method). The above method can obtain the structure of the layer 122 and the insulator 132 shown in Figures 12A to 12C.

[0151] The layer 122 and the insulator 132 can be formed by sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0152] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0153] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0154] The ALD method is also a film formation method that can reduce plasma damage to the workpiece, and because no plasma damage occurs during film formation, the ALD method also produces films with fewer defects.

[0155] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0156] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened by the time required for transport and pressure adjustment compared to when forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0157] In the lithography method, a resist is first exposed through a photomask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique can also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam can also be used instead of the light described above. When an electron beam or ion beam is used, a photomask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0158] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched, whereby a hard mask having a desired shape can be formed.

[0159] This processing can be performed by dry etching or wet etching, and dry etching is suitable for fine processing.

[0160] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high density plasma source.

[0161] When a hard mask is used for etching a conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0162] The layer 122 can be, for example, a conductive film containing a metal element formed by a sputtering method. Alternatively, the conductive film can be formed by a CVD method. The layer 122 may be a semiconductor. For example, when a gettering process related to a crystallinity improvement process using a catalytic element (also referred to as "catalytic crystallization") described later is performed, a conductive film with many crystal defects is preferably used as the layer 122. Note that the layer 122 can also be called a "gettering layer."

[0163] Furthermore, in order to perform the gettering treatment described later more effectively, it is preferable that the layer 122 contains an impurity element. As the impurity element, for example, a Group 15 element such as phosphorus (P), arsenic (As), nitrogen (N), antimony (Sb), or bismuth (Bi) may be used. In addition to the Group 15 element, a Group 13 element (typically, boron (B), aluminum (Al), gallium (Ga), or indium (In) may also be used. The concentration of the impurity contained in the layer 122 is 1×10 19 atoms / cm 3 More than 1×10 21 atoms / cm 3 The following may be performed. Note that it is not essential to add an impurity element to the layer 122 for the gettering treatment. Furthermore, the impurity element contained in the layer 122 may be a Group 18 element (typically, helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), etc.). The impurity element contained in the layer 122 may be a combination of a Group 15 element, a Group 13 element, and a Group 18 element.

[0164] In this embodiment, amorphous silicon containing phosphorus is used for the layer 122. For example, after forming an amorphous silicon film, phosphorus may be introduced into the amorphous silicon film by a plasma doping method, an ion implantation method, or the like. When the layer 122 is formed by a CVD method or the like, a gas containing an impurity element may be mixed into a material gas.

[0165] If necessary, the surface of the insulator 132 is preferably subjected to planarization processing, which can be performed by chemical mechanical polishing (CMP) or reflow processing.

[0166] An insulating film 123A, a conductive film 134A, and a conductive film 136A are alternately stacked over the layer 122 and the insulator 132. In this embodiment, an example is shown in which the insulating film 123A is formed over the insulator 132, the conductive film 134A is formed over the insulating film 123A, the insulating film 123A is formed over the conductive film 134A, and the conductive film 136A is formed over the insulating film 123A (see FIGS. 12A to 12C). The conductive film 134A, the conductive film 136A, and the insulating film 123A can be formed by a CVD method. Alternatively, a sputtering method may be used.

[0167] The conductive film 134A and the conductive film 136A can be made of the above-described conductors. The conductive film 136A is preferably made of a different material from the layer 122 and the conductive film 134A because selective etching is required with respect to the layer 122 and the conductive film 134A in a later step. The layer 122 and the conductive film 134A may be made of the same material or different materials. The layer 122, the conductive film 134A, and the conductive film 136A may be made of conductors having different crystallinity.

[0168] The above-described insulators can be used for the insulator 132 and the insulating film 123A. For example, an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used.

[0169] Although the present embodiment has shown an example in which six insulating films 123A, three conductive films 134A, and two conductive films 136A are formed, the number of stacked layers is not limited to this. Each of these layers can be formed depending on the desired performance of the semiconductor device. If the number of stacked conductive films 134A is m (m is an integer of 2 or more), the number of stacked insulating films 123A is 2×m, and the number of stacked conductive films 136A is m−1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and even more preferably 257 or more.

[0170] Next, a mask (not shown) is formed on the insulating film 123A, and the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed using lithography to form a first opening 141 to expose the layer 122 (see Figures 13A to 13C).

[0171] Next, isotropic etching is performed on the conductive film 136A, causing the side surface of the conductive film 136A in the first opening 141 to recede from the side surfaces of the insulating film 123A and the conductive film 134A (see FIGS. 14A to 14C). This process results in the diameter of the first opening 141 overlapping the conductive film 136A in a direction perpendicular to the Z direction being larger than the diameters of the first opening 141 overlapping the insulating film 123A and the conductive film 134A in a direction perpendicular to the Z direction. Therefore, unevenness is formed on the side surface of the first opening 141. For this process, isotropic etching by dry etching using gas, radicals, plasma, etc., or isotropic etching by wet etching using a liquid can be used. The liquid used in wet etching is sometimes called an etchant. When performing isotropic etching using dry etching, gas, radicals, plasma, etc. containing at least one of chlorine, bromine, and fluorine can be used. The isotropic etching is preferably performed without removing the mask used to form the first opening 141.

[0172] Next, an insulating film 124A is formed on the insulating film 123A and inside the first opening 141 (see FIGS. 15A to 15C). Although not shown, the insulating film 124A may have a layered structure. The insulating film 124A can be formed using a CVD method or an ALD method. The ALD method is particularly preferable because it allows a film of uniform thickness to be formed even in a groove or opening with a large aspect ratio. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. When the insulating film 124A has a layered structure, each insulating film may be formed using the same film formation apparatus or different film formation apparatuses.

[0173] The insulating film 124A formed by the above method has good coverage and can be formed even on the uneven shape of the side surface of first opening 141. That is, the insulating film 124A can be formed so as to contact not only the side surfaces of insulating film 123A, conductive film 134A, and conductive film 136A, but also part of the upper surface and part of the lower surface of insulating film 123A.

[0174] Next, insulating film 124A formed on the bottom of first opening 141 is removed to obtain insulator 124. Anisotropic etching is preferably used to remove insulating film 124A. At this time, insulating film 124A on insulating film 123A is also removed, so insulator 124 is provided only on the sidewall of first opening 141 (see FIGS. 16A to 16C). By removing insulating film 124A on the bottom of first opening 141, layer 122 is exposed again.

[0175] Next, a semiconductor film 125A and an insulating film 126A are formed inside the first opening (see FIGS. 17A to 17C).

[0176] The semiconductor film 125A and the insulating film 126A can be formed using a CVD method or an ALD method. The ALD method is particularly preferable because it allows for the formation of a film with a uniform thickness even in a groove or opening with a large aspect ratio. Alternatively, the semiconductor film 125A and the insulating film 126A may be formed by combining the ALD method and the CVD method. Furthermore, different film formation methods or different film formation apparatuses may be used for each film to be formed.

[0177] In this embodiment, amorphous silicon is formed as the semiconductor film 125A, and silicon oxynitride is formed as the insulating film 126A.

[0178] Next, a portion of the insulating film 126A is removed, leaving behind a region where the insulating film 126A overlaps with the first opening 141 and its vicinity (see FIGS. 18A to 18C). In this embodiment, the portion of the insulating film 126A is removed so that, as viewed from the Z direction, a region that overlaps with the first opening 141 and a portion that will later function as the transistor STr2 remain. In the region where the insulating film 126A has been removed, the semiconductor film 125A is exposed. This region is also referred to as a "catalytic element-added region."

[0179] Next, a catalyst layer 185 containing a catalytic element is formed on the semiconductor film 125A and the insulating film 126A (see FIGS. 19A to 19C). The catalyst layer 185 may be formed by a sputtering method, a CVD method, an ALD method, or the like, or by a coating method in which a solution containing a catalytic element is applied by a spin coating method or the like. The catalyst layer 185 may be, for example, a silicide containing a catalytic element.

[0180] The catalytic element may be an element selected from metal elements such as nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), and germanium (Ge).

[0181] In this embodiment, nickel is used as the catalytic element. When the catalytic layer 185 is formed by a coating method, a solution containing nickel salts such as nickel bromide, nickel acetate, nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, or nickel sulfate as the solute and water, alcohol, acid, or ammonia as the solvent can be used. Alternatively, a solution containing nickel element as the solute and a solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform, and ether can be used. Alternatively, even if the nickel is not completely dissolved, a material such as an emulsion in which nickel is dispersed in a medium can be used.

[0182] Next, in order to diffuse the catalytic element from the catalytic layer 185 containing the catalytic element into the semiconductor film 125A, a heat treatment is performed under conditions of 450 to 650°C for 4 to 24 hours. Note that prior to this heat treatment, a dehydrogenation treatment may be performed at 450°C for about 1 hour. By performing the dehydrogenation treatment, the hydrogen concentration in the semiconductor film 125A is reduced. Reducing the hydrogen concentration by the heat treatment makes it easier to form silicide.

[0183] Silicon in contact with the catalytic element bonds with the catalytic element to form silicide. Catalytic elements tend to bond with areas with many defects, such as amorphous states. For this reason, the catalytic element contained in the silicide reacts with amorphous silicon to form new silicide. In this way, crystallization progresses as the silicide moves. This is because the interatomic distance between the catalytic element and silicon is very close to the interatomic distance of single-crystal silicon, with the Ni-Si distance being the closest to the single-crystal Si-Si distance, about 0.6% shorter. Crystallization using a catalytic element increases the crystal grain size and reduces defects in the semiconductor.

[0184] 20 and 21 show the migration of silicide 188 from the catalytic element-added region to the semiconductor film 125A. FIG. 20 shows the initial stage of the heat treatment. First, silicide is formed in the semiconductor film 125A in contact with the catalytic element-added region. Because the insulating film 126A functions as a mask, the catalytic element is not added to the semiconductor film 125A in the region overlapping with the insulating film 126A. As the heat treatment progresses, the silicide 188 migrates in a direction away from the catalytic element-added region. The portion of the semiconductor film 125A that has undergone catalytic crystallization (the portion whose crystallinity has been enhanced by the catalytic element) is shown as semiconductor film 125Ac. The semiconductor film 125A, which is an amorphous semiconductor, is transformed into a crystalline semiconductor as the silicide 188 passes through it.

[0185] 21 shows the state of the heat treatment in the middle stage. As the heat treatment progresses, the silicide 188 moves toward the layer 122. In this embodiment, since amorphous silicon containing phosphorus is used as the layer 122, when the silicide 188 reaches the layer 122 during the heat treatment, the crystallinity of the layer 122 is also promoted.

[0186] Finally, the catalytic element contained in the silicide 188 is contained in the layer 122 (gettering process). By containing an impurity element such as a Group 15 element or a Group 13 element in the layer 122, re-diffusion of the catalytic element that has migrated into the layer 122 can be reduced.

[0187] The concentration of catalytic elements remaining in the semiconductor film 125Ac is 5 × 10 17 atoms / cm 3 The following is preferable: When the layer 122 contains an impurity element such as a Group 15 element, the catalyst element remaining in the semiconductor film 125Ac can be moved (absorbed) into the layer 122 by performing a heat treatment at a higher temperature after the heat treatment of the semiconductor film 125A using the catalyst element is completed. By containing the impurity element in the layer 122, the effect of the gettering treatment can be enhanced.

[0188] Next, the catalyst layer 185 is removed (see FIGS. 22A to 22C), and the semiconductor film 127A and the conductive film 128A are formed inside the first opening 141 (see FIGS. 23A to 23C).

[0189] The semiconductor film 127A and the conductive film 128A can be formed using a CVD method or an ALD method. The ALD method is particularly preferable because it allows for the formation of a film with a uniform thickness even in a groove or opening with a large aspect ratio. Alternatively, the semiconductor film 127A and the conductive film 128A may be formed by combining the ALD method and the CVD method. Furthermore, different film formation methods or different film formation apparatuses may be used for each film to be formed.

[0190] The conductive film 128A only needs to be formed so as to fill the recessed portion on the side surface of the first opening 141 (the intersection of the first opening 141 and the conductive film 136A in a direction perpendicular to the Z direction) via at least the insulator 124, the semiconductor film 125Ac, the insulating film 126A, and the semiconductor film 127A, but does not necessarily need to fill the entire interior of the first opening. The conductive film 128A can be formed using a CVD method or an ALD method. The ALD method is particularly preferable because it allows the formation of a film of uniform thickness even in grooves or openings with a large aspect ratio. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0191] The semiconductor film 127A is preferably an oxide semiconductor, such as CAAC-OS, nc-OS, or a-like OS.

[0192] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 24A to 24C). The conductive film 128A can be processed by isotropic etching or anisotropic etching. In forming the conductive film 128A, the conductive film 128A fills the recesses on the side surfaces of the first opening 141. However, if the first opening 141 is not completely filled (see FIG. 23), it is preferable to use isotropic etching to process the conductive film 128A. On the other hand, if the conductive film 128A is formed so as to completely fill the first opening 141, it is preferable to use anisotropic etching. By the above-described processing, the conductor 128 can be formed in the recesses on the side surfaces of the first opening 141.

[0193] Next, an insulating film 129A is formed on the semiconductor film 127A and inside the conductor 128. Subsequently, using the conductor 128 as a mask, a part of the semiconductor film 127A is made highly resistive to form a high-resistance region (I-type region) (see FIGS. 25A to 25D). One method for forming the high-resistance region is to irradiate the semiconductor film 127A with microwaves 144 through the insulating film 129A to remove hydrogen contained in the semiconductor film 127A. It is preferable to irradiate the semiconductor film 127A with microwaves 144 in an oxygen-containing atmosphere, since oxygen is supplied to the semiconductor film 127A. In this embodiment, a part of the semiconductor film 127A is irradiated with microwaves 144 through the insulating film 129A in an atmosphere containing oxygen and argon, thereby making a region 146, which is part of the semiconductor film 127A, highly resistive (see FIG. 25D).

[0194] Here, heat treatment may be performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0195] Heat treatment reduces the resistance of the semiconductor film 127A in contact with the conductor 128, thereby forming a low-resistance region (n-type region) in the region 148. By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact with each other, a metal compound layer containing a metal element contained in the conductor 128 and a component of the semiconductor film 127A may be formed at the interface between the conductor 128 and the semiconductor film 127A. Forming the metal compound layer is preferable because it reduces the resistance of the semiconductor film 127A in the region in contact with the conductor 128. Furthermore, the conductor 128 may absorb oxygen contained in the semiconductor film 127A. By performing heat treatment while the semiconductor film 127A and the conductor 128 are in contact with each other, the resistance of the semiconductor film 127A can be further reduced. The heat treatment may be performed before the microwave treatment. The region 148 whose resistance has been reduced by the heat treatment is covered with the conductor 128, and therefore is not affected by the microwave 144, and can maintain a low resistance value even after the microwave treatment.

[0196] The carrier concentration of the region 146 after the microwave treatment and heat treatment is 1×10 18 / cm 3 Less than 1 x 10, preferably 17 / cm 3 or less, more preferably 1×10 16 / cm 3 The carrier concentration of the region 148 is preferably 1×10 18 / cm 3 More than 1×10 19 / cm 3 More preferably, 1×10 20 / cm 3 It is preferable that this is equal to or greater than this.

[0197] Next, the conductive film 130A is formed (see FIGS. 26A to 26C). The conductive film 130A can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in a groove or opening with a large aspect ratio. Alternatively, the conductive film 130A may be formed by combining the ALD method and the CVD method.

[0198] Next, heat treatment is performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0199] Next, the conductive film 130A is removed by CMP or the like until the surface of the insulating film 129A is exposed, thereby obtaining the conductor 130 (see FIGS. 27A to 27C). Note that the heat treatment described above may be performed after the conductor 130 is formed.

[0200] Next, the semiconductor film 125A, the insulating film 126A, the semiconductor film 127A, and the insulating film 129A are processed to obtain the semiconductor 125, the insulator 126, the oxide film 127B, and the insulating film 129B (see FIGS. 28A to 28C). This processing can be performed by dry etching or wet etching.

[0201] Next, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form an insulator 123B, a conductor 134B, and a conductor 136B that overlap each other in a stepped manner at the edge portions as shown in Fig. 29B (see Figs. 29A to 29C). In processing the insulating film 123A, the conductive film 134A, and the conductive film 136A, etching of the insulating film 123A, the conductive film 134A, and the conductive film 136A and slimming of a mask are alternately performed, thereby forming a stepped edge portion.

[0202] Next, the insulator 150 is formed (see FIG. 29). The insulator 150 can be formed using a CVD method. It is preferable that the surface of the insulator 150 is planarized using a CMP method or a reflow method.

[0203] Next, the insulator 150, the insulator 123B, the conductor 134B, and the conductor 136B are processed to form the insulator 123, the conductor 134, and the conductor 136 (see FIGS. 30A to 30C).

[0204] Next, insulator 152 is formed to fill the portions removed during the formation of insulator 123, conductor 134, and conductor 136 (see FIG. 30). Insulator 152 can be formed using a CVD method or an ALD method. In particular, ALD is preferred because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. Alternatively, insulator 152 may be formed by combining ALD and CVD. It is preferable that insulator 152 be planarized using a CMP method or a reflow method.

[0205] Next, the oxide film 127B and the insulating film 129B are processed using lithography to obtain the semiconductor 127 and the insulator 129 (see FIGS. 31A to 31C). This processing can be performed by dry etching or wet etching. At this time, a part of the insulator 126 is exposed.

[0206] Next, the conductor 154 is formed so as to overlap with a portion of the semiconductor 125 via the insulator 126 (see FIGS. 32A to 32C). The conductor 154 is obtained by forming a conductive film on the insulators 126, 150, and 152, and processing the conductive film using lithography. Note that in FIG. 32A, the conductor 154 does not exist on the dashed line A1-A2, but in FIG. 32B, the conductor 154 is indicated by a dashed line. The conductor 154 is similarly indicated in FIGS. 33 and 34, which will be described later.

[0207] Next, the insulator 156 is formed to cover the conductor 154, the insulator 126, the insulator 150, and the insulator 152 (see FIGS. 33A to 33C). The insulator 156 can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0208] Next, insulator 156, insulator 126, insulator 129, semiconductor 127, and insulator 150 are processed using lithography to form second openings so as to expose conductor 134, conductor 136, conductor 130, conductor 154, and semiconductor 125. Second openings are formed for conductor 134 and conductor 136, which are formed in a stepped shape (see FIG. 33).

[0209] Next, conductor 161 electrically connected to conductor 134, conductor 162 electrically connected to conductor 136, conductor 163 electrically connected to conductor 130, conductor 164 electrically connected to conductor 154, conductor 165 electrically connected to semiconductor 125, and conductor 166 electrically connected to semiconductor 125 and semiconductor 127 are formed so as to fill the second opening (see FIGS. 34A to 34C). Conductors 161, 162, 163, conductor 164, conductor 165, and conductor 166 can be formed using a CVD method or an ALD method. ALD is particularly preferred because it allows for the formation of a film with a uniform thickness even in grooves or openings with a large aspect ratio. Alternatively, the conductors may be formed using a combination of ALD and CVD. Furthermore, the conductors 161, 162, 163, 164, 165, and 166 may have a layered structure made up of multiple layers. The conductors 161, 162, 163, 164, 165, and 166 can be formed by forming a conductive film on the insulator 156 and inside the second opening, and then removing unnecessary conductive film using CMP or the like.

[0210] Next, conductor 171 electrically connected to conductor 161, conductor 172 electrically connected to conductor 162, conductor 173 electrically connected to conductor 163, conductor 174 electrically connected to conductor 164, and conductor 175 electrically connected to conductor 165 are formed (see FIG. 34). Conductors 171, 172, 173, conductor 174, and conductor 175 can be formed by forming a conductive film on insulator 156 and processing it using lithography. This processing can be performed using dry etching or wet etching.

[0211] Conductor 171, conductor 161, and conductor 134 function as conductor SG or conductor WWL. Conductor 172, conductor 162, and conductor 136 function as conductor RWL. Conductor 173, conductor 163, and conductor 130 function as conductor BG. Conductor 174, conductor 164, and conductor 154 function as conductor SEL. Conductor 175 and conductor 165 function as BL. A memory device can be manufactured by the above process.

[0212] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0213] (Embodiment 2) In this embodiment, a circuit configuration and operation of a memory string 120, which is a storage device, will be described. An example of the circuit configuration of the memory string 120 is shown in FIG.

[0214] <Memory string circuit configuration example> 35 shows an example of a circuit configuration in which the number n of storage elements MC included in the memory string 120 is 5. As described in the above embodiment, the storage element MC has a transistor WTr and a transistor RTr.

[0215] In an equivalent circuit diagram, the symbol "OS" may be added to the circuit symbol of a transistor to indicate that the transistor is an OS transistor. Similarly, the symbol "Si" may be added to the circuit symbol of a transistor to indicate that the transistor is a Si transistor (a transistor that uses silicon in the semiconductor layer in which the channel is formed). In FIG. 35, the transistor WTr is an OS transistor, and the transistor RTr is a Si transistor.

[0216] FIG. 36 shows an equivalent circuit diagram of the memory element MC. As shown in FIG. 36, the transistor WTr can be represented by replacing it with a capacitance Cs and a transistor Tr. The gate of the transistor Tr is electrically connected to the conductor WWL via the capacitance Cs. The memory element MC exemplified in this embodiment is a "2Tr1C type" memory cell consisting of two transistors and one capacitance.

[0217] 35, the transistor WTr included in the memory element MC_1 is shown as transistor WTr_1, and the transistor RTr included in the memory element MC_1 is shown as transistor RTr_1. Therefore, the memory string 120 shown in FIG. 35 has transistors WTr_1 to WTr_5 and transistors RTr_1 to RTr_5. The memory string 120 shown in FIG. 35 also has transistors STr1 and STr2. The memory string 120 is a NAND-type memory device.

[0218] A NAND-type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device with multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0219] One of the source or drain of transistor RTr_1 is electrically connected to one of the source or drain of transistor STr1, and the other is electrically connected to one of the source or drain of transistor RTr_2. One of the source or drain of transistor WTr_1 is electrically connected to the gate of transistor RTr_1, and the other is electrically connected to one of the source or drain of transistor WTr_2. The back gate of transistor RTr_1 is electrically connected to conductor RWL_1. The gate of transistor WTr_1 is electrically connected to conductor WWL_1. The back gate of transistor WTr_1 is electrically connected to conductor BG. The other of the source or drain of transistor STr1 is electrically connected to layer 122, and the gate is electrically connected to conductor SG.

[0220] In addition, one of the source or drain of transistor RTr_5 is electrically connected to the other of the source or drain of transistor RTr_4, and the other is electrically connected to one of the source or drain of transistor STr2. The gate of transistor RTr_5 is electrically connected to one of the source or drain of transistor WTr_5. The other of the source or drain of transistor WTr_5 is electrically connected to one of the source or drain of transistor STr2. The back gate of transistor RTr_5 is electrically connected to conductor RWL_5. The gate of transistor WTr_5 is electrically connected to conductor WWL_5. In addition, the back gate of transistor WTr_5 is electrically connected to conductor BG. In addition, the other of the source or drain of transistor STr2 is electrically connected to conductor BL, and the gate is electrically connected to conductor SEL.

[0221] When the memory string 120 includes n memory elements MC, in the ith memory element MC_i (i is an integer between 1 and n) excluding the first and nth memory elements MC, one of the source or drain of the transistor RTr_i is electrically connected to the other of the source or drain of the transistor RTr_i-1, and the other is electrically connected to one of the source or drain of the transistor RTr_i+1. The gate of the transistor RTr_i is electrically connected to one of the source or drain of the transistor WTr_i. The other of the source or drain of the transistor WTr_i is electrically connected to one of the source or drain of the transistor WTr_i+1. The back gate of the transistor RTr_i is electrically connected to the conductor RWL_i. The gate of the transistor WTr_i is electrically connected to the conductor WWL_i. The back gate of the transistor WTr_i is electrically connected to the conductor BG.

[0222] Also, the node where the gate of the transistor RTr and either the source or the drain of the transistor WTr are electrically connected is referred to as a node ND. That is, the node where the gate of the transistor RTr_i and either the source or the drain of the transistor WTr_i are electrically connected is referred to as a node ND_i. In FIG. 35, the node ND included in the memory element MC_1 is referred to as a node ND_1.

[0223] The transistors STr1 and STr2 may be, for example, OS transistors or Si transistors. One of the transistors STr1 and STr2 may be an OS transistor and the other may be a Si transistor.

[0224] 37, depending on the purpose or application, a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr. Also, FIG. 37 shows an example in which OS transistors are used as the transistors STr1 and STr2.

[0225] Depending on the purpose or application, the transistor WTr may not be provided with a back gate, as shown in Fig. 38. Fig. 38 shows an example in which OS transistors are used as the transistors STr1 and STr2.

[0226] <Memory string operation example> Next, an example of the operation of the memory string 120 shown in FIG. 35 will be described.

[0227] [Write operation] In this embodiment, an example of an operation in which an H potential is written to the memory element MC_1 and the memory element MC_3 and an L potential is written to the other memory elements MC will be described. Fig. 39 is a timing chart illustrating the write operation. Figs. 40A to 43B are circuit diagrams illustrating the write operation. Note that reference numerals and the like not shown in Figs. 40A to 43B may refer to Fig. 35 and the like.

[0228] In an initial state, an L potential is written to the memory elements MC_1 to MC_5. Also, an L potential is supplied to the conductors WWL_1 to WWL_5, the conductors RWL_1 to RWL_5, the conductor SEL, the conductor BG, the conductor BL, the conductor SG, and the layer 122. The threshold value of the transistor RTr can be controlled by adjusting the potential supplied to the conductor BG. The potential supplied to the conductor BG may be appropriately adjusted so that the transistor RTr becomes a desired normally-on transistor.

[0229] [Period T1] In a period T1, an H potential is supplied to the conductors WWL_1 to WWL_5, the conductor BL, and the conductor SEL (see FIG. 40A). As a result, the potentials of the nodes ND_1 to ND_5 become H potentials.

[0230] [Period T2] In a period T2, an L potential is supplied to the conductor WWL_1 (see FIG. 40B). Then, the transistor WTr_1 is turned off, and the charge written to the node ND_1 is held. Here, a charge equivalent to an H potential is held.

[0231] [Period T3] In the period T3, an L potential is supplied to the conductor BL (see FIG. 40B). Then, the potentials of the nodes ND_2 to ND_5 become L potential. In this case, the gates of the transistors RTr_2 to RTr_5 also become L potential. However, because the transistors RTr are normally-on transistors, the transistors RTr_2 to RTr_5 are not turned off.

[0232] [Period T4] In a period T4, an L potential is supplied to the conductor WWL_2 (see FIG. 41A). Then, the transistor WTr_2 is turned off, and the charge written to the node ND_2 is held. Here, a charge equivalent to the L potential is held.

[0233] [Period T5] In a period T5, an H potential is supplied to the conductor BL (see FIG. 41B), so that the potentials of the nodes_3 to 5 become H potentials.

[0234] [Period T6] In a period T6, an L potential is supplied to the conductor WWL_3 (see FIG. 42A). Then, the transistor WTr_3 is turned off, and the charge written to the node ND_3 is held. Here, a charge equivalent to an H potential is held.

[0235] [Period T7] In a period T7, an L potential is supplied to the conductor BL (see FIG. 42B), causing the potentials of the nodes ND_4 and ND_5 to become L potentials.

[0236] [Period T8] In a period T8, an L potential is supplied to the conductor WWL_4 (see FIG. 43A). Then, the transistor WTr_4 is turned off, and the charge written to the node ND_4 is held. Here, a charge equivalent to the L potential is held.

[0237] [Period T9] In a period T9, the conductor BL remains at the L potential, so the potential of the node ND_5 also remains at the L potential.

[0238] [Period T10] In a period T10, an L potential is supplied to the conductor WWL_5 (see FIG. 43B). Then, the transistor WTr_5 is turned off, and the charge written to the node ND_5 is held. Here, a charge equivalent to the L potential is held. Also, an L potential is supplied to the conductor SEL.

[0239] In this way, information can be written to the memory element MC.

[0240] Note that when writing data to the i-th memory element MC (excluding i=1) among the multiple memory elements MC, the data write operation to the i-1th memory elements MC can be omitted. For example, when data is to be written to the memory element MC_4, data write operations to the memory elements MC_1 to MC_3 do not need to be performed. In other words, the data write operations from the period T1 to the period T6 described in this embodiment can be omitted. Therefore, the time and power consumption required for the write operation of the memory device can be reduced.

[0241] [Read operation] An example of a read operation of the memory string 120 having the above circuit configuration will be described. As an initial state, assume that an H potential is held in the memory elements MC_1 and MC_3, and an L potential is held in the memory elements MC_2, MC_4, and MC_5. Also assume that an L potential is supplied to the conductors WWL_1 to WWL_5, the conductors RWL_1 to RWL_5, the conductor SEL, the conductor BG, the conductor BL, the conductor SG, and the layer 122. Figures 44A and 44B are timing charts illustrating the read operation. Figures 45A, 45B, and 46 are circuit diagrams illustrating the read operation. Note that reference numerals and the like not shown in Figures 45A, 45B, and 46 may refer to Figure 35 and the like.

[0242] <When the holding potential is H potential> First, the read operation of the memory element MC_3 in which the H potential is held will be described.

[0243] [Period T11] In a period T11, an H potential is supplied to the conductors RWL_1 to RWL_5 and the conductor SEL (see FIG. 45A). Then, the transistor STr2 is turned on, and the semiconductor 125 and the conductor BL included in the transistor RTr are brought into electrical continuity. In this state, the conductor BL and the semiconductor 125 are precharged with an H potential, and both are brought into a floating state.

[0244] Here, the Id-Vg characteristics of a transistor will be explained. Figures 47A and 47B are diagrams illustrating the Id-Vg characteristics of a transistor. The horizontal axis of Figures 47A and 47B represents gate voltage (Vg), and the vertical axis represents drain current (Id). Figure 47A shows the Id-Vg characteristics of a normally-off transistor, and Figure 47B shows the Id-Vg characteristics of a normally-on transistor.

[0245] The H potential is a potential higher than the L potential. If the L potential is 0V, the H potential is a positive voltage. In a normally-off transistor, when Vg is at the L potential (0V), the channel resistance (resistance between the source and drain) is extremely large, and Id hardly flows. Furthermore, when Vg becomes the H potential, the channel resistance decreases and Id increases (see Figure 47A).

[0246] In a normally-on transistor, the channel resistance is small even when Vg is at a low potential, and a larger amount of Id flows than in a normally-off transistor. When Vg reaches a high potential, the channel resistance becomes even smaller, and Id increases even more (see Figure 47B).

[0247] Because the transistor RTr is a normally-on transistor, the semiconductor 125 can be precharged even if the potential of the conductor RWL remains at L potential. However, supplying H potential to the conductor RWL further reduces the channel resistance of the transistor RTr. This reduces the time and power consumption required for precharging.

[0248] [Period T12] In a period T12, an L potential is supplied to the conductor RWL_3 (see FIG. 45B). The node ND_3 is held at an H potential. Therefore, even if the potential of the conductor RWL_3 becomes an L potential, the channel resistance value of the transistor RTr_3 is smaller than when the node ND_3 is held at an L potential.

[0249] [Period T13] During period T13, an H potential is supplied to conductor SG, turning on transistor STr1 (see FIG. 46A). This brings conductor BL and layer 122 into a conductive state. At this time, because an H potential is supplied to conductors RWL_1, RWL_2, RWL_4, and RWL_5, the channel resistance values ​​of transistors RTr_1, RTr_2, RTr_4, and RTr_5 become small regardless of the potential of node ND. As described above, although an L potential is supplied to conductor RWL_3, because an H potential is maintained at node ND_3, the channel resistance value of transistor RTr_3 becomes small. Therefore, the potential of conductor BL, which is in a floating state, suddenly changes from an H potential to an L potential (see FIG. 44A).

[0250] [T14 period] In a period T14, an L potential is supplied to the conductor SEL, the conductor RWL, and the conductor SG (see FIG. 46B).

[0251] <When the holding potential is L potential> Next, the read operation of the memory element MC_2 holding an L potential will be described. When reading information (potential) held in the memory element MC_2, the potential of the conductor RWL_2 is set to an L potential in period T12 (see FIG. 44B). At this time, since the L potential is held at the node ND_2, the channel resistance value of the transistor RTr_2 is larger than when the H potential is held at the node ND_2.

[0252] Subsequently, in period T13, an H potential is supplied to the conductor SG, establishing a conductive state between the conductor BL and the layer 122. At this time, since the channel resistance value of the transistor RTr_2 is large, the potential of the conductor BL changes gradually from the H potential to the L potential.

[0253] In this way, in the period T13, the potential of the conductor RWL corresponding to the memory element MC to be read is set to the L potential, and the change in the potential of the conductor BL is detected, thereby making it possible to know the information stored in the memory element MC.

[0254] In addition, during periods other than the write operation, it is preferable to supply a potential (also referred to as an "LL potential") lower than the L potential to the conductor BG. By supplying the LL potential to the conductor BG, the transistor WTr can be turned off more reliably. Therefore, data written to the node ND can be retained for a longer period.

[0255] Furthermore, a potential higher than the L potential may be supplied to the conductor BG during a write operation. For example, an H potential may be supplied to the conductor BG during a write operation. By supplying an H potential to the conductor BG during a write operation, the resistance value of the semiconductor 127 is reduced, and the write speed can be increased.

[0256] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0257] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device 200 including a memory device 100 will be described.

[0258] 48 is a block diagram illustrating a configuration example of a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 illustrated in FIG. 48 includes a driver circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. FIG. 48 illustrates an example in which the memory array 220 includes a plurality of memory devices 100 arranged in a matrix.

[0259] The drive circuit 210 has a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 has a peripheral circuit 211 (row decoder), a control circuit 212, and a voltage generation circuit 228. The semiconductor device 200 has elements or circuits having various functions, such as a memory array 220, PSWs 241 and 242, the peripheral circuit 211, the control circuit 212, and the voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or a subsystem.

[0260] In the semiconductor device 200, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0261] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 212.

[0262] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0263] The voltage generation circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 228. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0264] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory device 100. The peripheral circuit 211 has a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0265] The row decoder 221 and the column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying a row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The row driver 223 has the function of selecting the wiring specified by the row decoder 221. The column driver 224 has the function of writing data to the memory device 100, reading data from the memory device 100, and holding the read data.

[0266] The input circuit 225 has a function of holding a signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is data (Din) to be written to the memory device 100. The data (Dout) read from the memory device 100 by the column driver 224 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. In addition, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is a signal RDA.

[0267] The PSW 241 has a function of controlling the supply of VDD to the peripheral circuit 215. The PSW 242 has a function of controlling the supply of VHM to the row driver 223. In this example, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 241 is controlled by a signal PON1, and the on / off of the PSW 242 is controlled by a signal PON2. In FIG. 48, the number of power domains to which VDD is supplied in the peripheral circuit 215 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0268] The drive circuit 210 and the memory array 220 may be provided on the same plane. Alternatively, as shown in FIG. 49A, the drive circuit 210 and the memory array 220 may be provided overlapping each other. By providing the drive circuit 210 and the memory array 220 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 49B, the memory array 220 may be provided in multiple layers on the drive circuit 210.

[0269] Furthermore, as shown in FIG. 49C , memory arrays 220 may be provided above and below the drive circuit 210. FIG. 49C shows an example in which one memory array 220 is provided above and one memory array 220 below the drive circuit 210. By arranging the drive circuit 210 so that the multiple memory arrays 220 sandwich the drive circuit 210, the signal propagation distance can be further shortened. Note that the number of memory arrays 220 stacked above the drive circuit 210 and the number of memory arrays 220 stacked below the drive circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 stacked above the drive circuit 210 is equal to the number of memory arrays 220 stacked below the drive circuit 210.

[0270] <Example of cross-sectional structure of semiconductor device> Fig. 50 shows an example of a cross-sectional configuration of the semiconductor device 200 shown in Fig. 49A. Fig. 50 shows a part of the semiconductor device 200 shown in Fig. 49A.

[0271] FIG. 50 illustrates transistors 301, 302, and 303 included in the driver circuit 210. The transistors 301 and 302 function as part of a sense amplifier 304. The transistor 303 functions as a column selection switch. Specifically, a conductor BL included in the memory array 220 is electrically connected to one of the source and drain of the transistor 301, the gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302, and the gate of the transistor 302 is electrically connected to the other of the source and drain of the transistor 301. The one of the source and drain of the transistor 301 and the other of the source and drain of the transistor 302 are electrically connected to one of the source and drain of the transistor 303, which functions as a column selection switch. This enables the layout area of ​​the semiconductor device 200 to be reduced. FIG. 50 illustrates an example in which seven memory elements MC are provided per memory string. However, the number of memory elements MC provided in one memory string is not limited to this. For example, the number of storage elements MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0272] The conductor BL of the memory array 220 is electrically connected to the sense amplifier 304 and the transistor 303 functioning as a column selection switch via a conductor 752 formed so as to be embedded in the insulators 726 and 722, a conductor 705, a conductor 714, and a conductor 715. Note that the circuits and transistors included in the driver circuit 210 are merely examples, and are not limited to the circuit configuration and transistor structure. In addition to the above, appropriate circuits and transistors, such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit, can be provided depending on the configuration of the semiconductor device 200 and its driving method.

[0273] The transistors 301, 302, and 303 are provided on a substrate 311, and each includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region. Note that, as shown in FIG. 50, one low-resistance region may be shared by the transistors 301 and 302 as both the source region or the drain region of one and the source region or the drain region of the other.

[0274] In the transistors 301, 302, and 303, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. The transistors 301, 302, and 303 are also called FIN transistors because they utilize the convex portions of the semiconductor substrate. An insulator that functions as a mask for forming the convex portions may be provided in contact with the tops of the convex portions. While the case where the convex portions are formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0275] The transistors 301, 302, and 303 may each be either a p-channel type or an n-channel type, but it is preferable that the transistors 301 and 302 have opposite conductivity types.

[0276] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs, the transistors 301, 302, and 303 may be configured as HEMTs (High Electron Mobility Transistors).

[0277] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0278] The insulator 315 functions as a gate insulating film for the transistor 301 , the transistor 302 , and the transistor 303 .

[0279] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0280] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0281] An insulator 317, which functions as an etch stopper, is preferably provided above the conductor 316. An insulator 318, which functions as a spacer, is preferably provided on the side of the insulator 315. By providing the insulators 317 and 318, the regions where the low-resistance regions 314a and 314b are electrically connected to the conductor 328 can be determined in a self-aligned manner. Therefore, even if misalignment occurs when forming openings to expose portions of the low-resistance regions 314a and 314b, openings can be formed to expose the intended regions. Forming the conductor 328 in the openings thus formed results in good contact with the conductor 328, with reduced contact resistance, and thus a contact between the low-resistance regions 314a and 314b and the conductor 328. The contact formed in this manner between the low-resistance regions 314a and 314b and the conductor 328 is sometimes referred to as a self-aligned contact. In addition, a conductor 329 electrically connected to the conductor 316 may be provided so as to be embedded in the insulator 317 and the insulator 322 .

[0282] An insulator 320, an insulator 322, an insulator 324, an insulator 326, and an insulator 327 are stacked in this order to cover the transistor 301, the transistor 302, and the transistor 303.

[0283] The insulators 320, 322, 324, 326, and 327 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0284] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 301 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0285] The insulator 324 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 311 or the transistor 301 to a region where the memory array 220 is provided.

[0286] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the memory element MC, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the memory element MC and the transistor 301 or the like. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0287] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0288] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulators 326 and 327 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0289] Furthermore, conductors 328, 329, 330, etc., which are electrically connected to the memory array 220, are embedded in the insulators 320, 322, 324, 326, and 327. The conductors 328, 329, and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0290] The materials for each plug and wiring (such as conductor 328, conductor 329, and conductor 330) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0291] A wiring layer may be provided over the insulator 327 and the conductor 330. For example, in FIG. 50, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. The conductor 356 can be formed using a material similar to that of the conductors 328, 329, and 330.

[0292] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0293] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 301 and the like while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0294] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 50, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328, 329, and 330.

[0295] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0296] An insulator 722 is provided on the insulator 364 and the conductor 366, and the memory array 220 is provided above the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0297] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0298] (Fourth embodiment) In this embodiment, an application example of a semiconductor device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 51A to 51E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0299] 51A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1105 or the like.

[0300] FIG. 51B is a schematic diagram of the appearance of an SD card, and FIG. 51C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1114 or the like.

[0301] FIG. 51D is a schematic diagram of the appearance of an SSD, and FIG. 51E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The storage device or semiconductor device described in the previous embodiments can be incorporated into memory chip 1154 or the like.

[0302] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0303] (Embodiment 5) 52A to 52G illustrate specific examples of electronic devices equipped with a memory device or a semiconductor device according to one embodiment of the present invention.

[0304] <Electronic devices and systems> The memory device or semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of the electronic devices include information terminals, computers, smartphones, e-book readers, televisions, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, and audio playback devices. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0305] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0306] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0307] The electronic device of one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display portion, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0308] [Information terminal] A memory device for storing programs of a microcontroller can be formed using a memory device or a semiconductor device according to one embodiment of the present invention, and therefore, according to one embodiment of the present invention, the size of a microcontroller chip can be reduced.

[0309] FIG. 52A illustrates a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 includes a housing 5101 and a display portion 5102. As input interfaces, a touch panel is provided on the display portion 5102 and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one embodiment of the present invention may be used for storage of the mobile phone. This allows the storage capacity per unit area of ​​the storage to be increased.

[0310] 52B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space inside the notebook information terminal can be effectively utilized. Furthermore, a storage device according to one embodiment of the present invention may be used for storage of the notebook information terminal. This allows the storage capacity per unit area of ​​the storage to be increased.

[0311] In the above description, a smartphone and a notebook information terminal are illustrated as examples of electronic devices in Figures 52A and 52B, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0312] [Game consoles] FIG. 52C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connection portion 5305 of the housing 5301 to another housing (not shown), the video displayed on the display portion 5304 can be output to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation portion. This allows multiple players to play a game simultaneously. A memory device or a semiconductor device according to one embodiment of the present invention can be incorporated into chips or the like provided on the substrates of the housings 5301, 5302, and 5303.

[0313] 52D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wired connection.

[0314] By using a miniaturized microcontroller according to one embodiment of the present invention in a game console such as a portable game console 5300 or a stationary game console 5400, it is possible to effectively utilize the limited space inside the game console. Furthermore, a storage device or a semiconductor device according to one embodiment of the present invention may be used for storage in the portable game console. This allows the storage capacity per unit area of ​​the storage to be increased.

[0315] 52C and 52D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the microcontroller of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the microcontroller of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0316] [Mainframe Computer] A memory device or a semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer.

[0317] 52E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 52F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0318] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a microcontroller according to one embodiment of the present invention can be mounted on the board. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space of a large computer can be effectively utilized. Furthermore, a storage device or a semiconductor device according to one embodiment of the present invention may be used for storage of the large computer. This allows the storage capacity per unit area of ​​the storage to be increased.

[0319] 52E and 52F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the microcontroller according to an embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the microcontroller according to an embodiment of the present invention is applied include a computer (server) that provides services, a large general-purpose computer (mainframe), etc.

[0320] [electric appliances] 52G shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0321] A memory device or a semiconductor device according to one embodiment of the present invention can also be applied to an electric refrigerator-freezer 5800. For example, by applying a miniaturized microcontroller according to one embodiment of the present invention to the electric refrigerator-freezer 5800, the limited space of the electric refrigerator-freezer can be effectively utilized.

[0322] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0323] The electronic devices, functions, effects, and the like described in this embodiment can be combined as appropriate with descriptions of other electronic devices.

[0324] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes. [Explanation of symbols]

[0325] 100: memory device, 105: region, 110: memory cell array, 120: memory string, 121: substrate, 122: layer, 123: insulator, 124: insulator, 125: semiconductor, 126: insulator, 127: semiconductor, 128: conductor, 129: insulator, 130: conductor, 132: insulator, 134: conductor, 136: conductor

Claims

1. a structure extending in a first direction; a plurality of first conductors extending in a second direction intersecting the first direction; a plurality of second conductors extending in the second direction; the structure includes a third conductor, a first insulator, a plurality of fourth conductors, a first semiconductor, a second insulator, a second semiconductor, and a third insulator; in a first region corresponding to each intersection of the plurality of first conductors and the structure, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are concentrically arranged in this order outside the third conductor; In the first region, a portion of the first conductor functions as a first gate electrode of a first transistor, a channel of the first transistor is formed in the first semiconductor, and a portion of the third conductor functions as a second gate electrode of the first transistor; in a second region corresponding to each intersection of the plurality of second conductors and the structure, the first insulator, any one of the plurality of fourth conductors, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are concentrically arranged in this order outside the third conductor, and any one of the plurality of fourth conductors is in contact with the first semiconductor; In the second region, a portion of the second conductor functions as a first gate electrode of a second transistor, a channel of the second transistor is formed in the second semiconductor, and a portion of any one of the plurality of fourth conductors functions as a second gate electrode of the second transistor; the first semiconductor includes an oxide semiconductor; the second semiconductor includes polycrystalline silicon; the second semiconductor has a region in contact with the first layer; The first layer includes a first metal element.

2. In claim 1, The semiconductor device wherein the first metal element is nickel.

3. In claim 1 or claim 2, The first layer includes silicon and phosphorus.

4. In any one of claims 1 to 3, The oxide semiconductor device includes at least one of indium and zinc.

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