Semiconductor device, and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device that can prevent faulty solder attachment when mounted on a wiring board.SOLUTION: A semiconductor device A10 comprises: a first semiconductor element 11 that has an element principal surface 111 and an element back surface 112 facing opposite sides to each other in a z-direction; a sealing resin 7 that covers the first semiconductor element 11; a first terminal 51 that is electrically connected with the first semiconductor element 11 and projects from the sealing resin 7; and a leading end plating layer 26 that is arranged on a leading end surface 511 that is an end face of the first terminal 51 on a side projecting from the sealing resin 7.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of an SOP (Small Outline Package) type semiconductor device. The semiconductor device disclosed in this document includes a semiconductor element, a die pad, terminals, and a sealing resin. The semiconductor element is mounted on the die pad and is electrically connected to the terminals via bonding wires. The semiconductor element, the die pad, and a portion of the terminals are covered with a sealing resin. An exterior plating layer made of an alloy containing Sn is formed on the portion of the terminal exposed from the sealing resin to improve solder adhesion when the terminal is joined to a wiring board by solder. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-207714 Summary of the Invention [Problem to be solved by the invention]

[0004] Because the outer plating layer is formed before the terminal is separated from the lead frame, no outer plating layer is formed on the tip surface of the terminal. Therefore, when the terminal is joined to the wiring board by soldering, the solder does not adhere well to the tip surface of the terminal, and a solder fillet may not be formed. In this case, a visual inspection will determine that the solder adhesion is poor.

[0005] SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor device that can suppress poor solder adhesion when mounted on a wiring board. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure includes a semiconductor element having an element main surface and an element back surface facing opposite each other in the thickness direction, a sealing resin covering the semiconductor element, a terminal that is electrically connected to the semiconductor element and protrudes from the sealing resin, and a tip plating layer disposed on a tip surface, which is the end surface of the terminal that protrudes from the sealing resin.

[0007] The method for manufacturing a semiconductor device provided by the present disclosure comprises the steps of preparing a lead frame including a terminal portion, forming a plating layer on the terminal portion, and cutting the terminal portion with a cutting mold, wherein the cutting mold comprises a cutting die and a cutting punch, and the cutting punch comprises a first edge portion that cuts the terminal portion, and the first edge portion has a curved surface. [Effects of the Invention]

[0008] A semiconductor device according to the present disclosure can suppress poor solder adhesion when mounted on a wiring board.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor device of FIG. 1, seen through the sealing resin. [Figure 3] FIG. 3 is a front view showing the semiconductor device of FIG. [Figure 4] FIG. 4 is a left side view showing the semiconductor device of FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a partially enlarged view of FIG. [Figure 8] FIG. 8 is a partially enlarged view of FIG. [Figure 9] 9A to 9C are plan views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 10] 10A to 10C are plan views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 11] FIG. 11 is a plan view showing a process according to the method for manufacturing the semiconductor device of FIG. [Figure 12] 12A to 12C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 13] 13A to 13C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 14] FIG. 14 is a partially enlarged view of FIG. [Figure 15] FIG. 15 is a partially enlarged cross-sectional view showing the semiconductor device of FIG. 1 mounted on a wiring board. [Figure 16] FIG. 16 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0012] First Embodiment 1 to 8 show an example of a semiconductor device according to the present disclosure. The semiconductor device A10 of this embodiment includes a first semiconductor element 11, a second semiconductor element 12, an insulating element 13, a conductive member 2, a plurality of wires 61 to 64, and a sealing resin 7. The conductive member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, a plurality of second terminals 52, a plurality of pad portions 53 and 55, a pair of connecting portions 54, and a pair of connecting portions 56. The semiconductor device A10 is surface-mounted on a wiring board of an inverter device of, for example, an electric vehicle or a hybrid vehicle. The application and function of the semiconductor device A10 are not limited. The package format of the semiconductor device A10 is a small outline package (SOP). However, the package format of the semiconductor device A10 is not limited to an SOP.

[0013] FIG. 1 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. FIG. 3 is a front view showing the semiconductor device A10. FIG. 4 is a left side view showing the semiconductor device A10. FIG. 5 is a cross-sectional view taken along line VV in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a partially enlarged view of FIG. 5. FIG. 8 is a partially enlarged view of FIG. 4.

[0014] The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (plan view). For convenience of explanation, the thickness direction (plan view) of the semiconductor device A10 is defined as the z direction, the direction along one side of the semiconductor device A10 perpendicular to the z direction (the left-right direction in FIGS. 1 and 2) is defined as the x direction, and the direction perpendicular to the z direction and the x direction (the up-down direction in FIGS. 1 and 2) is defined as the y direction. One side of the z direction (the upper side in FIGS. 3 and 4) is defined as the z1 side, and the other side (the lower side in FIGS. 3 and 4) is defined as the z2 side. One side of the x direction (the left side in FIGS. 1 and 2) is defined as the x1 side, and the other side (the right side in FIGS. 1 and 2) is defined as the x2 side. One side of the y direction (the upper side in FIGS. 1 and 2) is defined as the y1 side, and the other side (the lower side in FIGS. 1 and 2) is defined as the y2 side. The z direction corresponds to the "thickness direction" in this disclosure, the z2 side corresponds to the "first side" in this disclosure, and the z1 side corresponds to the "second side" in this disclosure. Note that the shape and dimensions of the semiconductor device A10 are not limited.

[0015] The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are elements that are the core of the function of the semiconductor device A10.

[0016] As shown in FIG. 2 , the first semiconductor element 11 is mounted on a portion of the conductive member 2 (a first die pad 3 described later) and is disposed in the center of the semiconductor device A10 in the y direction, toward the x1 side in the x direction. When viewed in the z direction, the first semiconductor element 11 has a rectangular shape that is elongated in the y direction. The first semiconductor element 11 is a control element. The first semiconductor element 11 includes a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the second semiconductor element 12, and a reception circuit that receives an electrical signal from the second semiconductor element 12. The first semiconductor element 11 has an element main surface 111 and an element back surface 112 that face opposite each other in the z direction. The element main surface 111 faces the z1 side in the z direction. The element back surface 112 faces the z2 side in the z direction. A plurality of electrodes 11A are provided on the element main surface 111. The plurality of electrodes 11A are electrically connected to a circuit configured in the first semiconductor element 11.

[0017] As shown in FIG. 2 , the second semiconductor element 12 is mounted on a portion of the conductive member 2 (a second die pad 4, described later) and is disposed in the center of the semiconductor device A10 in the y direction, toward the x2 side in the x direction. The second semiconductor element 12 has a rectangular shape elongated in the y direction when viewed in the z direction. The second semiconductor element 12 is a driving element. The second semiconductor element 12 includes a receiving circuit that receives a PWM control signal transmitted from the first semiconductor element 11, a circuit (gate driver) that generates and outputs a driving signal for a switching element (e.g., an IGBT or a MOSFET) based on the received PWM control signal, and a transmitting circuit that transmits an electrical signal to the first semiconductor element 11. The second semiconductor element 12 has an element main surface 121 and an element back surface 122 that face opposite each other in the z direction. The element main surface 121 faces the z1 side in the z direction. The element back surface 122 faces the z2 side in the z direction. A plurality of electrodes 12A are provided on the element main surface 121. The plurality of electrodes 12A are electrically connected to a circuit formed in the second semiconductor element 12.

[0018] As shown in FIG. 2 , the insulating element 13 is mounted on a portion of the conductive member 2 (first die pad 3) and is disposed at the center of the semiconductor device A10 in the y direction. The insulating element 13 is located on the x2 side of the first semiconductor element 11 in the x direction and on the x1 side of the second semiconductor element 12 in the x direction. That is, the insulating element 13 is located between the first semiconductor element 11 and the second semiconductor element 12 in the x direction. When viewed in the z direction, the insulating element 13 has a rectangular shape that is elongated in the y direction. The insulating element 13 is an element for transmitting PWM control signals and other electrical signals in an insulated state. The insulating element 13 receives a PWM control signal from the first semiconductor element 11 via a wire 63 and transmits the received PWM control signal to the second semiconductor element 12 via a wire 64 in an insulated state. The insulating element 13 also receives an electrical signal from the second semiconductor element 12 via a wire 64 and transmits the received electrical signal to the first semiconductor element 11 via the wire 63 in an insulated state. In other words, insulating element 13 relays signals between first semiconductor element 11 and second semiconductor element 12, while insulating first semiconductor element 11 and second semiconductor element 12 from each other.

[0019] In this embodiment, the insulating element 13 is an inductive insulating element. An inductive insulating element transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The insulating element 13 has a substrate made of Si, and an inductor made of Cu is formed on the substrate. The inductors include a transmitting inductor and a receiving inductor, and these inductors are stacked on top of each other in the thickness direction (z direction) of the insulating element 13. A dielectric layer made of SiO2 or the like is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor. In this embodiment, the insulating element 13 is an inductive type, but the insulating element 13 may also be a capacitive type. An example of a capacitive insulating element is a capacitor.

[0020] The insulating element 13 has an element principal surface 131 and an element rear surface 132 facing opposite to each other in the z direction. The element principal surface 131 faces the z1 side in the z direction. The element rear surface 132 faces the z2 side in the z direction. A plurality of first electrodes 13A and a plurality of second electrodes 13B are provided on the element principal surface 131. Each of the plurality of first electrodes 13A and the plurality of second electrodes 13B is electrically connected to either the transmitting inductor or the receiving inductor. In the insulating element 13, the plurality of first electrodes 13A are arranged along the y direction near the x1 side in the x direction. The plurality of second electrodes 13B are arranged along the y direction near the center in the x direction.

[0021] The first semiconductor element 11 transmits a PWM control signal to the second semiconductor element 12 via the insulating element 13. The first semiconductor element 11 may transmit a signal other than the PWM control signal to the second semiconductor element 12. The second semiconductor element 12 transmits an electrical signal to the first semiconductor element 11 via the insulating element 13. The information indicated by the electrical signal transmitted from the second semiconductor element 12 to the first semiconductor element 11 is not limited.

[0022] Motor driver circuits in inverter devices, such as those used in hybrid vehicles, typically use half-bridge circuits, in which low-side and high-side switching elements are connected in a totem-pole configuration. In an isolated gate driver, only one of the low-side or high-side switching elements is turned on at any given time. In the high-voltage range, the source of the low-side switching element and the reference potential of the isolated gate driver that drives the low-side switching element are connected to ground, so the gate-source voltage operates based on ground. Meanwhile, the source of the high-side switching element and the reference potential of the isolated gate driver that drives the high-side switching element are connected to the output node of the half-bridge circuit. The potential of the output node of the half-bridge circuit changes depending on whether the low-side or high-side switching element is on, so the reference potential of the isolated gate driver that drives the high-side switching element also changes. When the high-side switching element is on, the reference potential becomes a voltage equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher). The first semiconductor element 11 and the second semiconductor element 12 are ground-isolated to ensure insulation. When the semiconductor device A10 is used as an isolated gate driver that drives a high-side switching element, a voltage of 600 V or more is transiently applied to the second semiconductor element 12 compared to the ground of the first semiconductor element 11. Because a significant potential difference occurs between the first semiconductor element 11 and the second semiconductor element 12, in the semiconductor device A10, an input-side circuit including the second semiconductor element 12 and an output-side circuit including the first semiconductor element 11 are insulated by an insulating element 13. In other words, the insulating element 13 insulates the input-side circuit, which has a relatively low potential, from the output-side circuit, which has a relatively high potential.

[0023] In the semiconductor device A10, the conductive member 2 is a member that forms a conductive path between the first semiconductor element 11 and the second semiconductor element 12 and the wiring board of the inverter device. The conductive member 2 is made of, for example, an alloy containing Cu. The conductive member 2 is formed from a lead frame 81, which will be described later. The first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 are mounted on the conductive member 2. As shown in FIG. 2 , the conductive member 2 includes a first die pad 3, a second die pad 4, a plurality of first terminals 51, a plurality of second terminals 52, a plurality of pad portions 53 and 55, a pair of connecting portions 54, and a pair of connecting portions 56.

[0024] The first die pad 3 is disposed in the center of the semiconductor device A10 in the y direction, closer to the x1 side in the x direction. The second die pad 4 is disposed on the x2 side of the first die pad 3 in the x direction, spaced apart from the first die pad 3.

[0025] As shown in FIGS. 2 and 5, the first die pad 3 has a first semiconductor element 11 and an insulating element 13 mounted thereon. The first die pad 3 is electrically connected to the first semiconductor element 11 and is one element of the input circuit described above. The first die pad 3 has, for example, a substantially rectangular shape when viewed in the z direction. The first die pad 3 has a main surface 31 and a back surface 32. The main surface 31 and the back surface 32 are spaced apart in the z direction as shown in FIGS. 5 and 6. The main surface 31 faces the z1 side, and the back surface 32 faces the z2 side. The first semiconductor element 11 and the insulating element 13 are mounted on the main surface 31.

[0026] 6 and 8, the first semiconductor element 11 and the insulating element 13 are bonded to the main surface 31 of the first die pad 3 by a conductive bonding material 19. In this embodiment, the conductive bonding material 19 is, for example, solder. However, the conductive bonding material 19 is not limited to this and may be a metal paste, a sintered metal, or the like.

[0027] As shown in FIGS. 2 and 5, the second die pad 4 has a second semiconductor element 12 mounted thereon. The second die pad 4 is electrically connected to the second semiconductor element 12 and is one element of the output circuit described above. The second die pad 4 has, for example, a substantially rectangular shape when viewed in the z direction. The second die pad 4 has a main surface 41 and a back surface 42. As shown in FIG. 5, the main surface 41 and the back surface 42 are spaced apart from each other in the z direction. The main surface 41 faces the z1 side, and the back surface 42 faces the z2 side. The second semiconductor element 12 is mounted on the main surface 41.

[0028] The multiple first terminals 51 are bonded to a wiring board of an inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each first terminal 51 is appropriately electrically connected to the first semiconductor element 11 and is an element of the aforementioned input-side circuit. As shown in FIGS. 1, 2, and 4, the multiple first terminals 51 are spaced apart from one another and arranged at equal intervals along the y direction. Each of the multiple first terminals 51 is located on the x1 side of the first die pad 3 in the x direction and protrudes from the sealing resin 7 (a resin side surface 73 described below) toward the x1 side in the x direction. The multiple first terminals 51 include a power supply terminal to which a voltage is supplied, a ground terminal, an input terminal to which a control signal is input, an input terminal to which other electrical signals are input, and an output terminal to which other electrical signals are output. In this embodiment, the semiconductor device A10 includes ten first terminals 51. The number of first terminals 51 is not limited. Furthermore, the signals input and output by each first terminal 51 are not limited.

[0029] Each first terminal 51 has a rectangular shape extending along the x direction and includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIGS. 3 and 5 , the portion of each first terminal 51 exposed from the sealing resin 7 is bent in a gull-wing shape toward the z-direction z2. As shown in FIG. 7 , each first terminal 51 has a bottom surface 512. The bottom surface 512 is a surface that faces and is bonded to a wiring board when the semiconductor device A10 is surface-mounted on the wiring board of an inverter device, and faces the z-direction z2. A plating layer 25 is disposed on the entire portion of each first terminal 51 exposed from the sealing resin 7, except for a tip surface 511 (described later). The plating layer 25 contains, for example, Sn. The material of the plating layer 25 is not limited. When the semiconductor device A10 is surface-mounted on the wiring board of an inverter device by solder bonding, the plating layer 25 improves the adhesion of solder to the exposed portion while preventing erosion of the exposed portion due to the solder bonding.

[0030] As shown in FIGS. 7 and 8 , each first terminal 51 has a tip surface 511. The tip surface 511 is the end surface of the first terminal 51 that protrudes from the sealing resin 7. The tip surface 511 is a cross section formed by cutting the lead frame in a cutting process described below. A tip plating layer 26 is disposed on a portion of the tip surface 511. In FIG. 8 , the tip plating layer 26 is indicated by stipple marks. In this embodiment, as described below, the edge portion 852a of the cut punch 852 of the cutting mold 85 used in the cutting process has a curved surface. Therefore, when the lead frame is cut, a portion of the plating layer disposed on the lead frame extends and is disposed as the tip plating layer 26 on the tip surface 511, which is a cross section of the cut lead frame. Therefore, the tip plating layer 26 is made of the same material as the plating layer 25.

[0031] The tip surface 511 has a first region 511a and a second region 511b. The first region 511a is a region of the tip surface 511 where the tip plating layer 26 is disposed. The second region 511b is a region of the tip surface 511 where the tip plating layer 26 is not disposed. As will be described later, in this embodiment, cutting is performed from the z-direction z2 side to the z1 side in the cutting process, so the first region 511a is located on the z-direction z2 side of the second region 511b. The z-direction dimension L1 of the first region 511a is approximately 1 / 4 to 3 / 4 of the z-direction dimension L2 of the tip surface 511. Furthermore, the area S1 of the first region 511a is approximately 1 / 4 to 3 / 4 of the area of ​​the tip surface 511.

[0032] 7 and 8, the tip surface 511 has a burr 511c protruding toward the z-direction z1. Also, as shown in Fig. 7, the tip surface 511 has an inclined region 511d that is connected to the bottom surface 512. The inclined region 511d is inclined with respect to the z-direction.

[0033] The plurality of first terminals 51 include first terminal 51a and first terminal 51b. Among the plurality of first terminals 51, first terminal 51a is arranged closest to the y1 side in the y direction. Among the plurality of first terminals 51, first terminal 51b is arranged closest to the y2 side in the y direction.

[0034] The pads 53 are connected to the x2 side of the first terminals 51 other than the first terminals 51a and 51b in the x direction. The shape of each pad 53 as viewed in the z direction is not limited. The upper surface (the surface facing the z1 side) of each pad 53 is substantially flat, and a wire 61 (described later) is bonded to the upper surface of each pad 53. The upper surface of each pad 53 may be plated. A plating layer formed by the plating process is made of a metal containing Ag, for example, and covers the upper surface of the pad 53. The plating layer increases the bonding strength of the wire 61 while protecting a lead frame 81 (described later) from impacts during wire bonding of the wire 61. The pad 53 is entirely covered with a sealing resin 7.

[0035] The pair of connection portions 54 are respectively connected to the first terminal 51a or the first terminal 51b and the first die pad 3. The connection portion 54 connected to the first terminal 51a extends in the y direction, and its end on the y2 side in the y direction is connected to the end of the first die pad 3 on the y1 side in the y direction, near the center in the x direction of the end of the first die pad 3 on the y1 side in the y direction. The connection portion 54 connected to the first terminal 51b extends in the y direction, and its end on the y1 side in the y direction is connected to the end of the first die pad 3 on the y2 side in the y direction, near the center in the x direction of the end of the first die pad 3 on the y2 side in the y direction. In this way, the first terminal 51a and the first terminal 51b are connected to the first die pad 3 via the pair of connection portions 54 and support the first die pad 3. The upper surface (the surface facing the z1 side) of each connection portion 54 is substantially flat, and a wire 61 (described later) is joined to the upper surface of each connection portion 54. Like the upper surface of the pad portion 53, the upper surface of each connection portion 54 may be covered with a plating layer (e.g., a metal containing Ag). The entire surface of the connection portion 54 is covered with the sealing resin 7.

[0036] Like the first terminals 51, the second terminals 52 are bonded to the wiring board of the inverter device to form a conductive path between the semiconductor device A10 and the wiring board. Each second terminal 52 is electrically connected to the second semiconductor element 12 and is an element of the output circuit described above. As shown in FIGS. 1 and 2 , the second terminals 52 are spaced apart from one another and arranged at equal intervals along the y direction. Each of the second terminals 52 is located on the x2 side of the second die pad 4 in the x direction and protrudes from the sealing resin 7 (the resin side surface 74 described below) toward the x2 side in the x direction. The second terminals 52 include a power supply terminal to which a voltage is supplied, a ground terminal, an output terminal to output a drive signal, an input terminal to which other electrical signals are input, and an output terminal to output other electrical signals. In this embodiment, the semiconductor device A10 includes ten second terminals 52. The number of second terminals 52 is not limited. Furthermore, the signals input and output by each second terminal 52 are not limited.

[0037] Each second terminal 52 has an elongated rectangular shape extending along the x direction and includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIGS. 3 and 5 , the portion of each second terminal 52 exposed from the sealing resin 7 is bent into a gull-wing shape bent toward the z-direction z2. As shown in FIG. 5 , each second terminal 52 has a bottom surface 522. The bottom surface 522 is a surface that faces and is bonded to a wiring board when the semiconductor device A10 is surface-mounted on a wiring board of an inverter device, and faces the z-direction z2. Similar to the first terminal 51, a plating layer 25 is arranged on the entire portion of each second terminal 52 exposed from the sealing resin 7, except for a tip surface 521 (described later).

[0038] 5, each second terminal 52 has a tip surface 521. The tip surface 521 is the end surface of the second terminal 52 that protrudes from the sealing resin 7. Like the tip surface 511, the tip surface 521 is a cross section formed by cutting the lead frame, and a tip plating layer 26 is disposed on a part of the tip surface 521.

[0039] Like the first terminal 51, the tip surface 521 has a first region 521a and a second region 521b. The first region 521a is a region of the tip surface 521 where the tip plating layer 26 is disposed. The second region 521b is a region of the tip surface 521 where the tip plating layer 26 is not disposed. The tip surface 521 has a burr 521c protruding toward the z-direction z1. The tip surface 521 also has an inclined region 521d that connects to the bottom surface 522. The inclined region 521d is inclined with respect to the z-direction.

[0040] The plurality of second terminals 52 include second terminal 52a and second terminal 52b. The second terminal 52a is arranged second from the y1 side in the y direction among the plurality of second terminals 52. The second terminal 52b is arranged second from the y2 side in the y direction among the plurality of second terminals 52.

[0041] The multiple pad portions 55 are connected to the x1 side of the multiple second terminals 52 other than the second terminals 52a and 52b in the x direction. The shape of each pad portion 55 as viewed in the z direction is not limited. The upper surface (the surface facing the z1 side) of each pad portion 55 is approximately flat, and a wire 62, which will be described later, is joined to it. The upper surface of each pad portion 55 may be covered with a plating layer (for example, a metal containing Ag), similar to the upper surface of the pad portion 53. The pad portion 55 is entirely covered with sealing resin 7.

[0042] The pair of connection portions 56 are respectively connected to the second terminal 52a or the second terminal 52b and the second die pad 4. The connection portion 56 connected to the second terminal 52a has an end portion on the y2 side in the y direction connected to the second die pad 4 near the center in the x direction of the end portion on the y1 side in the y direction. The connection portion 56 connected to the second terminal 52b has an end portion on the y1 side in the y direction connected to the second die pad 4 near the center in the x direction of the end portion on the y2 side in the y direction. In this way, the second terminal 52a and the second terminal 52b are connected to the second die pad 4 via the pair of connection portions 56 and support the second die pad 4. The upper surface (the surface facing the z1 side) of each connection portion 56 is substantially flat, and a wire 62 (described later) is joined to the upper surface of each connection portion 56. The upper surface of each connection portion 56 may be covered with a plating layer (e.g., a metal containing Ag), similar to the upper surface of the pad portion 53. The entire surface of the connection portion 56 is covered with the sealing resin 7.

[0043] The shape of the conductive member 2 is not limited to the above. For example, the first die pad 3 may be supported by any of the first terminals 51. That is, the pair of connection portions 54 may be connected to the first die pad 3 and any of the first terminals 51. Furthermore, the second die pad 4 may be supported by any of the second terminals 52. That is, the pair of connection portions 56 may be connected to any of the second terminals 52 and the second die pad 4.

[0044] 2, the plurality of wires 61-64, together with the conductive member 2, form a conductive path that enables the first semiconductor element 11, the second semiconductor element 12, and the insulating element 13 to perform predetermined functions. The material of each of the plurality of wires 61-64 is a metal containing, for example, Au, Cu, or Al.

[0045] As shown in FIGS. 2 and 5, the plurality of wires 61 form a conductive path between the first semiconductor element 11 and the plurality of first terminals 51. The plurality of wires 61 electrically connect the first semiconductor element 11 to at least one of the plurality of first terminals 51. The plurality of wires 61 are one element of the input side circuit described above. As shown in FIG. 2, one end of each of the plurality of wires 61 is electrically connected to one of the electrodes 11A of the first semiconductor element 11, and the other end is electrically connected to one of the plurality of pad portions 53 and a pair of connecting portions 54. The number of wires 61 connected to each pad portion 53 and each connecting portion 54 is not limited.

[0046] As shown in FIGS. 2 and 5, the plurality of wires 62 form a conductive path between the second semiconductor element 12 and the plurality of second terminals 52. The plurality of wires 62 electrically connect the second semiconductor element 12 to at least one of the plurality of second terminals 52. The plurality of wires 62 are one element of the output circuit described above. As shown in FIG. 2, one end of each of the plurality of wires 62 is electrically connected to one of the electrodes 12A of the second semiconductor element 12, and the other end is electrically connected to one of the plurality of pad portions 55 and a pair of connecting portions 56. The number of wires 62 connected to each pad portion 55 and each connecting portion 54 is not limited.

[0047] 2 and 5, the plurality of wires 63 form a conductive path between the first semiconductor element 11 and the insulating element 13. The first semiconductor element 11 and the insulating element 13 are electrically connected to each other by the plurality of wires 63. The plurality of wires 63 are one element of the input side circuit described above. Each of the plurality of wires 63 is electrically connected to one of the electrodes 11A of the first semiconductor element 11 and one of the first electrodes 13A of the insulating element 13, as shown in FIG.

[0048] 2 and 5, the plurality of wires 64 form a conductive path between the second semiconductor element 12 and the insulating element 13. The second semiconductor element 12 and the insulating element 13 are electrically connected to each other by the plurality of wires 64. The plurality of wires 64 is one element of the output side circuit described above. As shown in FIG. 2, each of the plurality of wires 64 is electrically connected to one of the electrodes 12A of the second semiconductor element 12 and one of the second electrodes 13B of the insulating element 13.

[0049] As shown in FIG. 1 , the sealing resin 7 covers the first semiconductor element 11, the second semiconductor element 12, the insulating element 13, the first die pad 3, the second die pad 4, the pair of connecting portions 54, the pair of connecting portions 56, the plurality of pad portions 53, 55, the plurality of wires 61 to 64, and a portion of each of the plurality of first terminals 51 and second terminals 52. The sealing resin 7 has electrical insulation properties. The sealing resin 7 is made of a material containing, for example, black epoxy resin. The sealing resin 7 is rectangular when viewed in the z direction.

[0050] As shown in FIGS. 3 and 4, the sealing resin 7 has a resin top surface 71, a resin bottom surface 72, and resin side surfaces 73 to .

[0051] The resin top surface 71 and the resin bottom surface 72 are located apart from each other in the z direction. The resin top surface 71 and the resin bottom surface 72 face opposite each other in the z direction. The resin top surface 71 is located on the z1 side in the z direction and faces the z1 side, just like the main surface 31 of the first die pad 3. The resin bottom surface 72 is located on the z2 side in the z direction and faces the z2 side, just like the back surface 32 of the first die pad 3. Each of the resin top surface 71 and the resin bottom surface 72 is approximately flat.

[0052] Each of the resin side surfaces 73 to 76 is connected to the resin top surface 71 and the resin bottom surface 72 and is sandwiched between the resin top surface 71 and the resin bottom surface 72 in the z direction. The resin side surface 73 and the resin side surface 74 are spaced apart from each other in the x direction. The resin side surface 73 and the resin side surface 74 face opposite each other in the x direction. The resin side surface 73 is located on the x1 side of the x direction, and the resin side surface 74 is located on the x2 side of the x direction. The resin side surface 75 and the resin side surface 76 are spaced apart from each other in the y direction and are connected to the resin side surface 73 and the resin side surface 74. The resin side surface 75 and the resin side surface 76 face opposite each other in the y direction. The resin side surface 75 is located on the y1 side of the y direction, and the resin side surface 76 is located on the y2 side of the y direction. As shown in FIG. 1 , a portion of each of the multiple first terminals 51 protrudes from the resin side surface 73. Furthermore, a portion of each of the multiple second terminals 52 protrudes from the resin side surface 74.

[0053] As shown in FIGS. 3 and 4 , the resin side surface 73 includes a resin first region 731, a resin second region 732, and a resin third region 733. One end of the resin first region 731 in the z direction is connected to the resin top surface 71, and the other end in the z direction is connected to the resin third region 733. The resin first region 731 is inclined with respect to the resin top surface 71 and the yz plane. One end of the resin second region 732 in the z direction is connected to the resin bottom surface 72, and the other end in the z direction is connected to the resin third region 733. The resin second region 732 is inclined with respect to the resin bottom surface 72 and the yz plane. One end of the resin third region 733 in the z direction is connected to the resin first region 731, and the other end in the z direction is connected to the resin second region 732. The resin third region 733 is aligned along the yz plane. When viewed in the z direction, third resin region 733 is located outward from resin top surface 71 and resin bottom surface 72. From third resin region 733, a portion of each of the plurality of first terminals 51 is exposed.

[0054] As shown in FIG. 3 , the resin side surface 74 includes a fourth resin region 741, a fifth resin region 742, and a sixth resin region 743. One end of the fourth resin region 741 in the z direction is connected to the resin top surface 71, and the other end in the z direction is connected to the sixth resin region 743. The fourth resin region 741 is inclined with respect to the resin top surface 71 and the yz plane. One end of the fifth resin region 742 in the z direction is connected to the resin bottom surface 72, and the other end in the z direction is connected to the sixth resin region 743. The fifth resin region 742 is inclined with respect to the resin bottom surface 72 and the yz plane. One end of the sixth resin region 743 in the z direction is connected to the fourth resin region 741, and the other end in the z direction is connected to the fifth resin region 742. The sixth resin region 743 is aligned along the yz plane. When viewed in the z direction, the resin sixth region 743 is located outward from the resin top surface 71 and the resin bottom surface 72. From the resin sixth region 743, a portion of each of the plurality of second terminals 52 is exposed.

[0055] As shown in FIG. 4, the resin side surface 75 includes a seventh resin region 751, an eighth resin region 752, and a ninth resin region 753. One end of the seventh resin region 751 in the z direction is connected to the resin top surface 71, and the other end in the z direction is connected to the ninth resin region 753. The seventh resin region 751 is inclined with respect to the resin top surface 71 and the xz plane. One end of the eighth resin region 752 in the z direction is connected to the resin bottom surface 72, and the other end in the z direction is connected to the ninth resin region 753. The eighth resin region 752 is inclined with respect to the resin bottom surface 72 and the xz plane. One end of the ninth resin region 753 in the z direction is connected to the seventh resin region 751, and the other end in the z direction is connected to the eighth resin region 752. The ninth resin region 753 is aligned along the xz plane. When viewed in the z direction, the ninth resin region 753 is located outward from the resin top surface 71 and the resin bottom surface 72.

[0056] As shown in FIGS. 3 and 4 , the resin side surface 76 includes a tenth resin region 761, an eleventh resin region 762, and a twelfth resin region 763. One end of the tenth resin region 761 in the z direction is connected to the resin top surface 71, and the other end in the z direction is connected to the twelfth resin region 763. The tenth resin region 761 is inclined with respect to the resin top surface 71 and the xz plane. The eleventh resin region 762 is inclined with respect to the resin bottom surface 72 and the xz plane. The twelfth resin region 763 is inclined with respect to the tenth resin region 761 and the xz plane. One end of the twelfth resin region 763 in the z direction is connected to the tenth resin region 761, and the other end in the z direction is connected to the eleventh resin region 762. The twelfth resin region 763 is aligned along the xz plane. When viewed in the z direction, the twelfth resin region 763 is located outward from the resin top surface 71 and the resin bottom surface 72.

[0057] Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to Figures 9 to 14. Figures 9 to 11 are plan views showing steps in the method for manufacturing the semiconductor device A10. Figures 12 and 13 are cross-sectional views showing steps in the method for manufacturing the semiconductor device A10, showing a cross section corresponding to the cross section along line VV in Figure 2. Figure 14 is a partial enlarged view of Figure 13. Note that the x, y, and z directions shown in these figures are the same as those in Figures 1 to 8.

[0058] First, as shown in FIG. 9 , a lead frame 81 is prepared. The lead frame 81 is a plate-shaped material. In this embodiment, the base material of the lead frame 81 is Cu. The lead frame 81 may be formed by etching a metal plate or by punching a metal plate. In this embodiment, the lead frame 81 is formed by etching. The lead frame 81 has a main surface 81A and a back surface 81B spaced apart in the z direction. The lead frame 81 also includes an outer frame 811, a first die pad 812A, a second die pad 812B, a plurality of first leads 813, a plurality of second leads 814, a plurality of connection portions 815, and a dam bar 816. Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A10. The first die pad 812A is a portion that will later become the first die pad 3. The second die pad 812B is a portion that will later become the second die pad 4. The plurality of first leads 813 are portions that will later become the plurality of first terminals 51 and pad portion 53. The plurality of second leads 814 are portions that will later become the plurality of second terminals 52 and pad portion 55. The plurality of connecting portions 815 are portions that will later become the pair of connecting portions 54 and the pair of connecting portions 56.

[0059] 10, the first semiconductor element 11 and the insulating element 13 are bonded to the first die pad 812A by die bonding, and the second semiconductor element 12 is bonded to the second die pad 812B by die bonding. Then, each of the plurality of wires 61 to 64 is formed by wire bonding.

[0060] Next, as shown in FIG. 11, the sealing resin 7 is formed. The sealing resin 7 is formed by transfer molding. In this process, the lead frame 81 is placed in a mold having multiple cavities. At this time, the portion of the lead frame 81 that will become the conductive member 2 covered by the sealing resin 7 in the semiconductor device A10 is placed in one of the multiple cavities. Then, fluidized resin is poured from the pot via a runner into each of the multiple cavities. After the fluidized sealing resin 7 in the multiple cavities is solidified, resin burrs located outside each of the multiple cavities are removed using high-pressure water or the like. This completes the formation of the sealing resin 7.

[0061] Next, a plating layer 82 is formed on the lead frame 81 exposed from the sealing resin 7. As a result, the plating layer 82 is disposed on a terminal portion 813a including a portion of the first lead 813 that will become the first terminal 51, and on a terminal portion 814a including a portion of the second lead 814 that will become the second terminal 52.

[0062] 12, the terminal portions 813a and 814a are bent. In this step, a forming die is used to bend the terminal portions 813a and 814a. As a result, the terminal portions 813a and 814a are formed into a gull-wing shape bent toward the z-direction z2.

[0063] Next, as shown in FIGS. 13 and 14 , the lead frame 81 is cut. In this step, the terminal portions 813a and 814a are cut using a cutting mold 85. In this embodiment, the cutting mold 85 employs a so-called upper cut method, which cuts the terminal portions 813a and 814a from the z-direction z2 side. The cutting mold 85 includes a cutting die 851, a cutting punch 852, and a stripper block 853. The lead frame 81 covered with the sealing resin 7 is placed on the stripper block 853. The cutting die 851 presses and fixes the terminal portions 813a and 814a between itself and the stripper block 853. The cutting punch 852 is fixed, and the cutting die 851 and the stripper block 853 move toward the z-direction z2 side. As a result, cut punch 852 moves in the z direction from side z2 to side z1 relative to cut die 851 and stripper block 853. Between cut punch 852 and cut die 851, terminal portion 813a and terminal portion 814a protruding outside cut die 851. By cutting terminal portion 813a, first terminal 51 is separated from first lead 813, and by cutting terminal portion 814a, second terminal 52 is separated from second lead 814.

[0064] As shown in FIG. 14, the cutting punch 852 has an edge portion 852a that cuts the terminal portion 813a. In this embodiment, the edge portion 852a has a curved surface. The edge portion 852a has a larger radius of curvature than the edge portion 851a that the cutting die 851 has and that cuts the terminal portion 813a. By cutting with the curved edge portion 852a, a portion of the plating layer 82 that was disposed on the terminal portion 813a extends and is disposed on the cut surface. As a result, the tip plating layer 26 is disposed on the tip surface 511 (see FIG. 7). The tip plating layer 26 is also disposed on the tip surface 521.

[0065] By going through the steps described above, the semiconductor device A10 is manufactured.

[0066] 15 is a partially enlarged cross-sectional view showing the semiconductor device A10 mounted on the wiring board 9. The mounting of the semiconductor device A10 on the wiring board 9 will now be described.

[0067] 15, the semiconductor device A10 is mounted on a wiring board 9, and a plurality of first terminals 51 and second terminals 52 are joined to wiring (not shown) formed on the wiring board 9 with solder 95. At this time, since the tip plating layer 26 is arranged on the tip surface 511 of the first terminal 51, the solder 95 is also attached to the tip surface 511, forming a solder fillet. Similarly, the tip plating layer 26 is arranged on the tip surface 521 of the second terminal 52, and therefore the solder 95 is also attached to the tip surface 521, forming a solder fillet.

[0068] Next, the effects of the semiconductor device A10 will be described.

[0069] According to the present embodiment, the tip plating layer 26 is disposed in the first region 511a located on the z-direction z2 side of the tip surface 511. Therefore, when the first terminal 51 is joined to the wiring board 9 with solder 95 during mounting of the semiconductor device A10, the solder 95 also adheres to the tip surface 511, forming a solder fillet. Similarly, the solder 95 also adheres to the tip surface 521, forming a solder fillet. This makes it possible to suppress poor solder adhesion when the semiconductor device A10 is mounted on the wiring board 9.

[0070] Furthermore, in this embodiment, in the cutting process, terminal portion 813a and terminal portion 814a are cut from the z-direction z2 side by an upper-cut cutting die 85. Therefore, tip plating layer 26 is disposed in first region 511a on the z-direction z2 side of tip surface 511. As a result, tip plating layer 26 that is continuous with plating layer 25 on bottom surface 512 is disposed on tip surface 511. Similarly, tip plating layer 26 that is continuous with plating layer 25 on bottom surface 522 is disposed on tip surface 521. Therefore, a good solder fillet is easily formed. Furthermore, burrs 511c (521c) protrude in the z-direction z1 side and therefore do not interfere with joining first terminal 51 (second terminal 52) to wiring board 9.

[0071] There are no particular limitations on the package format of the semiconductor device A10, the type and number of semiconductor elements mounted thereon, the shape and arrangement of the conductive member 2, the number of terminals, etc. The semiconductor device A10 may be any type as long as the terminals protrude from the sealing resin 7 and are surface-mounted on a wiring board or the like.

[0072] 16 shows another embodiment of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment.

[0073] Second Embodiment FIG. 16 is a diagram illustrating a semiconductor device A20 according to a second embodiment of the present disclosure. FIG. 16 is a partially enlarged cross-sectional view showing the semiconductor device A20, and corresponds to FIG. 7. The semiconductor device A20 of this embodiment differs from the first embodiment in that a tip plating layer 26 is disposed over the entire tip surface 511. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first embodiment described above may be combined in any desired manner.

[0074] In this embodiment, the tip plating layer 26 is disposed on the tip surface 511 and the entire surface of the tip surface 511. The manufacturing method of the semiconductor device A20 according to the second embodiment differs from that of the first embodiment. In the manufacturing method according to the second embodiment, after the sealing resin 7 is formed, the terminal portions 813a and 814a are bent and cut before the plating layer 82 is formed. The edge portion 852a of the cutting punch 852 of the cutting mold 85 used in the cutting process does not have an intended curved surface like in the first embodiment. Therefore, the tip surface 511 does not have the burrs 511c and inclined regions 511d like in the first embodiment. The same applies to the tip surface 521. After the terminal portions 813a and 814a are cut, the plating layer 82 is formed on the first terminals 51 and second terminals 52 exposed from the sealing resin 7. The plating layer 82 formed on the tip surface 511 and the tip surface 521 is the tip plating layer 26 , and the plating layer 82 formed in a location other than the tip surface 511 and the tip surface 521 is the plating layer 25 .

[0075] In this embodiment, too, the tip plating layer 26 is disposed on the tip surface 511. Therefore, when the first terminal 51 is joined to the wiring board 9 with solder 95 during mounting of the semiconductor device A20, the solder 95 also adheres to the tip surface 511, forming a solder fillet. Similarly, the solder 95 also adheres to the tip surface 521, forming a solder fillet. This makes it possible to prevent poor solder adhesion when the semiconductor device A20 is mounted on the wiring board 9.

[0076] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the method for manufacturing the semiconductor device according to the present disclosure can be freely designed in various ways.

[0077] [Appendix 1] a semiconductor element (11) having a main surface (111) and a back surface (112) of the element facing in opposite directions in the thickness direction (z direction); a sealing resin (7) that covers the semiconductor element; a terminal (51) that is electrically connected to the semiconductor element and protrudes from the sealing resin; a tip plating layer (26) disposed on a tip surface (511) which is an end surface of the terminal protruding from the sealing resin; A semiconductor device (A10) comprising: [Appendix 2] The tip surface has a first region (511a) in which the tip plating layer is arranged and a second region (511b) in which the tip plating layer is not arranged. 2. The semiconductor device according to claim 1. [Appendix 3] The area (S1) of the first region is equal to or greater than 1 / 4 and equal to or less than 3 / 4 of the area (S2) of the tip surface. 3. The semiconductor device according to claim 2. [Appendix 4] The dimension (L1) of the first region in the thickness direction is 1 / 4 or more and 3 / 4 or less of the dimension (L2) of the tip surface in the thickness direction. 3. The semiconductor device according to claim 2. [Appendix 5] the terminal is bent toward the first side in the thickness direction (the z2 side in the z direction), The first region is located on the first side of the second region. 5. The semiconductor device according to any one of appendixes 2 to 4. [Appendix 6, Figures 7 and 8] The tip end surface has a burr (511c) protruding toward a second side (z-direction z1 side) opposite to the first side in the thickness direction. 6. The semiconductor device according to claim 5. [Appendix 7, Figure 7] the terminal has a first surface (512) facing the first side; The tip surface has a one-side region (511d) connected to the first surface, the one-side region is inclined with respect to the thickness direction; 7. The semiconductor device according to claim 5 or 6. [Appendix 8] The tip plating layer contains Sn. 8. The semiconductor device according to any one of appendices 1 to 7. [Appendix 9] Further, a first plating layer (25) is disposed on the terminal, The tip plating layer and the first plating layer are made of the same material. 9. The semiconductor device according to any one of appendices 1 to 8. [Appendix 10, Figure 15] the first plating layer is disposed on the entire portion of the terminal exposed from the sealing resin except for the tip end surface; 10. The semiconductor device according to claim 9. [Appendix 11, Figures 13 and 14] providing a lead frame (81) including a terminal portion; forming a plating layer (82) on the terminal portion (813a); a step of cutting the terminal portion by a cutting die (85); Equipped with The cutting mold includes a cutting die (851) and a cutting punch (852), The cut punch has a first edge portion (852a) that cuts the terminal portion, The first edge portion has a curved surface. A method for manufacturing a semiconductor device. [Appendix 12] the cutting die has a second edge portion (851a) that cuts the terminal portion, The first edge portion has a larger radius of curvature than the second edge portion. 12. A method for manufacturing a semiconductor device according to claim 11. [Appendix 13] The method further includes a step of bending the terminal portion before the cutting step. 13. A method for manufacturing a semiconductor device according to claim 11 or 12. [Explanation of symbols]

[0078] A10, A20: Semiconductor device 11: First semiconductor element 111: Element main surface 112: Back of element 11A: Electrode 12: Second semiconductor element 121: Element main surface 122: Back of element 12A: Electrode 13: Isolation element 131: Element main surface 132: Back of element 13A: 1st electrode 13B: 2nd electrode 19: Conductive bonding material 2: Conductive material 25: Plating layer 26: Tip plating layer 3: First die pad 31: Main surface 32: Back side 4: Second die pad 41: Main surface 42: Back side 51,51a,51b: 1st terminal 511: Tip surface 511a: First area 511b:Second area 511c: Bali 511d: Slope area 512: Bottom 53: Pad section 54: Connection 52,52a,52b: 2nd terminal 521: Tip surface 521a: First area 521b:Second area 521c: Bali 521d: Slope area 522: Bottom 55: Pad section 56: Connection 61~64: Wire 7: Sealing resin 71:Resin top surface 72: Resin bottom 73~76: Resin side 731:Resin 1st area 732: Resin 2nd area 733:Resin third area 741:Resin 4th area 742:Resin 5th area 743:Resin 6th area 751:Resin 7th area 752:Resin 8th area 753:Resin 9th area 761:Resin 10th area 762:Resin 11th area 763:Resin 12th area 81: Lead frame 81A: Main surface 81B: Back 811: Outer frame 812A: 1st die pad 812B: Second die pad 813: 1st lead 813a:Terminal part 814: Second Lead 814a:Terminal part 815: Connection 816:Dambar 82: Plating layer 85: Cutting mold 851: Cut die 851a: Edge part 852: Cut punch 852a: Edge part 853: Stripper block 9: Wiring board 95: Solder

Claims

1. a semiconductor element having a main surface and a back surface facing opposite to each other in a thickness direction; a sealing resin that covers the semiconductor element; a terminal that is electrically connected to the semiconductor element and protrudes from the sealing resin; a tip plating layer disposed on a tip surface, which is an end surface of the terminal on a side protruding from the sealing resin; A semiconductor device comprising:

2. The tip surface has a first region in which the tip plating layer is disposed and a second region in which the tip plating layer is not disposed. The semiconductor device according to claim 1 .

3. The area of ​​the first region is equal to or greater than ¼ and equal to or less than ¾ of the area of ​​the tip surface. The semiconductor device according to claim 2 .

4. The dimension of the first region in the thickness direction is equal to or greater than ¼ and equal to or less than ¾ of the dimension of the tip surface in the thickness direction. The semiconductor device according to claim 2 .

5. the terminal is bent toward a first side in the thickness direction, The first region is located on the first side of the second region. The semiconductor device according to claim 2 .

6. the tip end surface has a burr protruding to a second side opposite to the first side in the thickness direction, The semiconductor device according to claim 5 .

7. the terminal has a first surface facing the first side; the tip surface has one side region connected to the first surface, the one-side region is inclined with respect to the thickness direction; 7. The semiconductor device according to claim 5.

8. The tip plating layer contains Sn. The semiconductor device according to claim 1 .

9. a first plating layer disposed on the terminal; The tip plating layer and the first plating layer are made of the same material. The semiconductor device according to claim 1 .

10. the first plating layer is disposed on the entire portion of the terminal exposed from the sealing resin except for the tip end surface; The semiconductor device according to claim 9 .

11. providing a lead frame including a terminal portion; forming a plating layer on the terminal portion; cutting the terminal portion with a cutting die; Equipped with The cutting mold includes a cutting die and a cutting punch, the cut punch has a first edge portion that cuts the terminal portion; The first edge portion has a curved surface. A method for manufacturing a semiconductor device.

12. the cutting die has a second edge portion that cuts off the terminal portion, The first edge portion has a larger radius of curvature than the second edge portion. The method for manufacturing a semiconductor device according to claim 11.

13. The method further includes a step of bending the terminal portion before the cutting step. The method for manufacturing a semiconductor device according to claim 11 or 12.

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