Transparent display device

Abstract

To provide a transparent display device that can improve transparency by increasing the transmission area.SOLUTION: The transparent display device may comprise a first layer including a first power wire and a second power wire along a first direction, a second layer disposed on the first layer and including a third power wire, a fourth power wire, a first data signal wire, a second data signal wire, and a plurality of connecting wires along the first direction, a driving IC disposed between the third power wire and the fourth power wire, and a light-emitting element disposed between the third power wire and the fourth power wire. The first power wire and the third power wire may overlap vertically, and the second power wire and the fourth power wire may overlap vertically.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiment relates to a transparent display device. [Background technology]

[0002] 2. Description of the Related Art A variety of display devices for displaying images have been developed, including liquid crystal displays (LCDs), light-emitting element displays, and organic light-emitting diode (OLED) displays.

[0003] Meanwhile, AM (active matrix) transparent display devices, which can display images without obstructing the view by transmitting light from the front and back, are gaining attention. To realize an AM (active matrix) transparent display device, various opaque components such as driving ICs, light-emitting elements such as LEDs (light-emitting diodes), power wiring, signal wiring, etc. are arranged.

[0004] These various opaque members cause a problem of reducing the transparency of the transparent display device. Summary of the Invention [Problem to be solved by the invention]

[0005] The embodiments are directed to solving the above-mentioned problems and other problems.

[0006] Another object of the embodiment is to provide a transparent display device that can increase the transmission area and improve transparency.

[0007] The technical problems of the embodiments are not limited to those described in this section, but include those that can be understood from the description of the invention. [Means for solving the problem]

[0008] In order to achieve the above or another object, according to one aspect of the embodiment, a transparent display device includes: a first layer including a first power wiring and a second power wiring along a first direction; a second layer disposed on the first layer and including a third power wiring, a fourth power wiring, a first data signal wiring, a second data signal wiring, and a plurality of connecting wirings along the first direction; a driving IC disposed between the third power wiring and the fourth power wiring; and a light-emitting element disposed between the third power wiring and the fourth power wiring, wherein the driving IC is electrically connected to one of the first power wiring and the third power wiring, one of the second power wiring and the fourth power wiring, the first data signal wiring, the second data signal wiring, and the plurality of connecting wirings; the light-emitting element is electrically connected to the second power wiring and one of the fourth power wiring and the plurality of connecting wirings; the first power wiring and the third power wiring vertically overlap each other, and the second power wiring and the fourth power wiring vertically overlap each other.

[0009] The transparent display device may further include a substrate having a lower surface on which the first layer is disposed and an upper surface on which the second layer is disposed.

[0010] The first power supply wiring and the second power supply wiring may be low-potential wiring, and the third power supply wiring and the fourth power supply wiring may be high-potential wiring.

[0011] The first layer may further include a connection portion that crosses the second data signal wiring along a second direction to electrically connect the first power supply wiring and the second power supply wiring, and a connection pattern that crosses the first data signal wiring along the second direction to electrically connect the third power supply wiring and the fourth power supply wiring through first vias and second vias on the substrate.

[0012] The second power wiring is electrically connected to the driving IC and the light emitting element through vias on the substrate, and the third power wiring is electrically connected to the driving IC.

[0013] The first power supply wiring and the second power supply wiring may be high-potential wiring, and the third power supply wiring and the fourth power supply wiring may be low-potential wiring.

[0014] The first layer may further include a connection portion that crosses the first data signal wiring along a second direction to electrically connect the first power supply wiring and the second power supply wiring, and a connection pattern that crosses the second data signal wiring along the second direction to electrically connect the third power supply wiring and the fourth power supply wiring through first vias and second vias on the substrate.

[0015] The connection part is electrically connected to the driving IC through a via on the substrate, and the fourth power wiring is electrically connected to the driving IC and the light emitting element.

[0016] The first power supply wiring and the fourth power supply wiring may be low-potential wirings, and the second power supply wiring and the third power supply wiring may be high-potential wirings.

[0017] The first layer may further include a first connection portion that crosses the first data signal wiring along a second direction and electrically connects the first power supply wiring and the fourth power supply wiring through a first via on the substrate, and a second connection portion that crosses the second data signal wiring along the second direction and electrically connects the second power supply wiring and the third power supply wiring through a second via on the substrate.

[0018] The third power supply wiring is electrically connected to the driving IC, and the fourth power supply wiring is electrically connected to the driving IC and the light emitting element.

[0019] The transparent display device further includes a first substrate having a lower surface on which the first layer is disposed, and a second substrate having an upper surface on which the second layer is disposed, and the driving IC and the light-emitting element are disposed between the first substrate and the second substrate.

[0020] The transparent display device may further include a conductive spacer between the first substrate and the second substrate.

[0021] The light emitting device may include a plurality of light emitting devices stacked vertically and electrically connected to the plurality of connecting wires.

[0022] The light emitting device may include a plurality of light emitting devices arranged horizontally along a second direction and connected to the plurality of connecting wires. [Effects of the Invention]

[0023] The effects of the transparent display device according to the embodiment will be described as follows.

[0024] According to at least one of the embodiments, the first power wiring and the second power wiring on the lower surface of the substrate are vertically overlapped with the third power wiring and the fourth power wiring on the upper surface of the substrate, respectively, which has the advantage of increasing the transmission area and improving transparency.

[0025] According to at least one of the embodiments, the third power supply wiring and the fourth power supply wiring on the upper surface of the substrate are electrically connected via a connection pattern arranged on the lower surface of the substrate, which has the advantage of preventing the first data signal wiring and the second data signal wiring arranged between the third power supply wiring and the fourth power supply wiring on the upper surface of the substrate from being electrically short-circuited with the third power supply wiring and the fourth power supply wiring.

[0026] According to at least one of the embodiments, a capacitor is formed by the first power wiring, the substrate, and the third power wiring, which are vertically overlapping each other, and by the second power wiring, the substrate, and the fourth power wiring, which are vertically overlapping each other, thereby achieving a noise reduction effect that is insensitive to noise, thereby preventing signal distortion due to noise and preventing poor image quality.

[0027] Further scope of applicability of the embodiments will become apparent from the following detailed description. However, it should be understood that the detailed description and specific embodiments, such as the preferred embodiment, are merely illustrative, as various changes and modifications within the spirit and scope of the embodiments will be apparent to those skilled in the art. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a cross-sectional view of a transparent display device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the transparent display device according to the first embodiment. [Figure 3A] FIG. 3A illustrates the first layer illustrated in FIG. [Figure 3B] FIG. 3B illustrates the second layer illustrated in FIG. [Figure 4] FIG. 4 illustrates the connection relationship between a driving IC and a plurality of light-emitting device chips. [Figure 5] FIG. 5 is a plan view of a transparent display device according to the second embodiment. [Figure 6A] FIG. 6A illustrates the first layer illustrated in FIG. [Figure 6B] FIG. 6B illustrates the second layer illustrated in FIG. [Figure 7] FIG. 7 is a plan view of a transparent display device according to the third embodiment. [Figure 8A] FIG. 8A is a cross-sectional view of the transparent display device shown in FIG. 7 taken along line AA'. [Figure 8B] FIG. 8B is a cross-sectional view of the transparent display device shown in FIG. 7 taken along line BB'. [Figure 9] FIG. 9 illustrates a state in which the second power wiring of the first layer and the third power wiring of the second layer are electrically connected to each other along a first direction in the transparent display device illustrated in FIG. [Figure 10]FIG. 10 illustrates a state in which the first power wiring of the first layer and the fourth power wiring of the second layer are electrically connected to each other along a first direction in the transparent display device illustrated in FIG. [Figure 11] FIG. 11 is a plan view of a transparent display device according to the fourth embodiment. [Figure 12A] FIG. 12A illustrates the first layer illustrated in FIG. [Figure 12B] FIG. 12B illustrates the second layer illustrated in FIG. [Figure 13] FIG. 13 is a cross-sectional view of a transparent display device according to the second embodiment. [Figure 14A] FIG. 14A is a cross-sectional view illustrating an example of a transparent display device according to the third embodiment. [Figure 14B] FIG. 14B is a cross-sectional view illustrating another example of the transparent display device according to the third embodiment.

[0029] The size, shape, and numerical values ​​of components illustrated in the drawings do not necessarily correspond to the actual size, shape, and numerical values ​​of the same components. Furthermore, even if the same components are illustrated with different sizes, shapes, and numerical values ​​between the drawings, this is merely an example on the drawings, and the same components may have the same size, shape, and numerical values ​​between the drawings. DETAILED DESCRIPTION OF THE INVENTION

[0030] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, identical or similar components will be designated by the same reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "section" used in the following description are used interchangeably to facilitate the preparation of the specification and do not have any distinguishing meaning or function. The accompanying drawings are provided solely for the purpose of facilitating understanding of the embodiments disclosed herein, and are not intended to limit the technical ideas disclosed herein. Furthermore, when an element, such as a layer, region, or substrate 110, is referred to as being "on" another element, this includes whether it is directly on the other element or whether other intermediate elements may exist therebetween.

[0031] Fig. 1 is a cross-sectional view of a transparent display device according to a first embodiment. Fig. 2 is a plan view of the transparent display device according to the first embodiment. Fig. 3A illustrates the first layer illustrated in Fig. 2, and Fig. 3B illustrates the second layer illustrated in Fig. 2.

[0032] 2, the transparent display device is illustrated as including one pixel, but the transparent display device may be configured with a plurality of pixels as illustrated in FIG.

[0033] 1 and 2, the transparent display device according to the first embodiment may include a substrate 110, a first layer 120, a second layer 130, a driving IC 140, and a light-emitting element chip 150. The driving IC 140 may be a chip or a die.

[0034] The substrate 110 may be a transparent substrate, a flexible substrate, or a rigid substrate. The substrate 110 may be a transparent flexible substrate. The substrate 110 may be a transparent rigid substrate.

[0035] The substrate 110 may be made of a transparent material, a flexible or rigid material, or a material such as plastic, polymer resin, or glass.

[0036] A plurality of vias 111 to 113 are formed in the substrate 110. Each of the vias 111 to 113 may refer to a hole penetrating the substrate 110 or a conductor such as a metal having excellent electrical conductivity that is filled in the corresponding hole. Each of the vias 111 to 113 may serve to electrically connect the first layer 120 and the second layer 130 by penetrating the substrate 110.

[0037] The first layer 120 is disposed on the bottom surface of the substrate 110 and the second layer 130 is disposed on the top surface of the substrate 110 .

[0038] In the first layer 120, a first power supply wiring 121 and a second power supply wiring 122 are arranged along a first direction Y. The first power supply wiring 121 and the second power supply wiring 122 may be arranged parallel to each other along the first direction Y, but are not limited thereto.

[0039] The first power supply wiring 121 may be a low-potential wiring that supplies a low-potential voltage. The first power supply wiring 121 may have a mesh shape or a ladder shape. The second power supply wiring 122 may be a low-potential wiring that supplies a low-potential voltage. The second power supply wiring 122 may have a mesh shape or a ladder shape.

[0040] The first layer 120 may include a connecting portion 123. The connecting portion 123 is disposed between the first power supply wiring 121 and the second power supply wiring 122.

[0041] The connecting unit 123 may electrically connect the first power supply wiring 121 and the second power supply wiring 122 along the second direction X. When the low potential voltage supplied to the first power supply wiring 121 is higher than the low potential voltage supplied to the second power supply wiring 122, the low potential voltage supplied to the first power supply wiring 121 is supplied to the second power supply wiring 122 via the connecting unit 123. The low potential voltage supplied to the first power supply wiring 121 is supplied to the second power supply wiring 122 via the connecting unit 123 until the low potential voltage supplied to the first power supply wiring 121 and the low potential voltage supplied to the second power supply wiring 122 become the same. Therefore, the connecting unit 123 may be an equipotential power supply wiring that makes the low potential voltage supplied to the first power supply wiring 121 and the low potential voltage supplied to the second power supply wiring 122 the same.

[0042] The first power supply wiring 121, the second power supply wiring 122, and the connecting portion 123 may be integrally formed of the same metal, but the present invention is not limited thereto.

[0043] The first layer 120 may include a connecting pattern 124. The connecting pattern 124 is disposed between the first power supply wiring 121 and the second power supply wiring 122.

[0044] The connecting pattern 124 is disposed elongatedly along the second direction X. The connecting pattern 124 is disposed to be spaced apart from the first power supply wiring 121 and the second power supply wiring 122. As will be described later, the connecting pattern 124 can electrically connect the third power supply wiring 131 and the fourth power supply wiring 132 of the second layer 130. The first data signal wiring 133 of the second layer 130 is disposed between the third power supply wiring 131 and the fourth power supply wiring 132. The connecting pattern 124 of the first layer 120 can electrically connect the third power supply wiring 131 and the fourth power supply wiring 132 without electrically shorting with the first data signal wiring 133 of the second layer 130.

[0045] The first power wiring 121, the second power wiring 122, the connecting portion 123, and the connecting pattern 124 may be formed of the same metal using the same photolithography process, but the present invention is not limited thereto.

[0046] Meanwhile, the second layer 130 may include a third power supply wiring 131, a fourth power supply wiring 132, a first data signal wiring 133, a second data signal wiring 134, a plurality of connecting wirings 135-138, a plurality of pads 181-187, 191-194, etc. along the first direction Y.

[0047] The third power supply wiring 131, the fourth power supply wiring 132, the first data signal wiring 133, the second data signal wiring 134, and the plurality of connecting wirings 135 to 138 may be formed of the same metal using the same photolithography process, but this is not a limitation.

[0048] The third power supply wiring 131 and the fourth power supply wiring 132 may be arranged parallel to each other along the first direction Y, but are not limited thereto. The first data signal wiring 133 and the second data signal wiring 134 may be arranged in a line along the first direction Y. The first data signal wiring 133 and the second data signal wiring 134 may be arranged parallel to the third power supply wiring 131 or the fourth power supply wiring 132 along the first direction Y, but are not limited thereto.

[0049] The third power supply wiring 131 may be a high-potential wiring that supplies a high potential voltage. The third power supply wiring 131 may have a mesh shape or a ladder shape.

[0050] The fourth power supply wiring 132 may be a high-potential wiring that supplies a high potential voltage. The fourth power supply wiring 132 may have a mesh shape or a ladder shape.

[0051] As described above, the first layer 120 may include the connecting pattern 124. The connecting pattern 124 may electrically connect the third power wiring 131 and the fourth power wiring 132 through the first via 111 and the second via 112. That is, one side of the connecting pattern 124 of the first layer 120 is electrically connected to the third power wiring 131 of the second layer 130 through the first via 111, and the other side of the connecting pattern 124 of the first layer 120 is electrically connected to the fourth power wiring 132 of the second layer 130 through the second via 112.

[0052] When the high potential voltage supplied to the third power supply wiring 131 is higher than the high potential voltage supplied to the fourth power supply wiring 132, the high potential voltage supplied to the third power supply wiring 131 is supplied to the fourth power supply wiring 132 via the connecting pattern 124 of the first layer 120. When the high potential voltage supplied to the third power supply wiring 131 and the high potential voltage supplied to the fourth power supply wiring 132 are the same, the high potential voltage supplied to the third power supply wiring 131 is not supplied to the fourth power supply wiring 132 via the connecting pattern 124, and the high potential voltage supplied to the fourth power supply wiring 132 is not supplied to the third power supply wiring 131 via the connecting pattern 124. In other words, the connecting pattern 124 may be an equipotential power supply wiring that makes the high potential voltage supplied to the third power supply wiring 131 and the high potential voltage supplied to the fourth power supply wiring 132 the same.

[0053] In some embodiments, the high potential voltage is greater than the low potential voltage. The high potential voltage may be referred to as a VDD voltage and the low potential voltage may be referred to as a VSS voltage. The low potential voltage may be referred to as a first power supply voltage and the high potential voltage may be referred to as a second power supply voltage, or vice versa.

[0054] Meanwhile, since the first power wiring 121, the second power wiring 122, the third power wiring 131, and the fourth power wiring 132 are typically arranged on the same surface at a distance from each other to prevent electrical short circuits, there is a problem in that the transmission area of ​​the transparent substrate 110 is reduced, thereby reducing transparency.

[0055] However, in the embodiment, the first power supply wiring 121 of the first layer 120 and the third power supply wiring 131 of the second layer 130 can be vertically overlapped. The first power supply wiring 121 of the first layer 120 and the third power supply wiring 131 of the second layer 130 can be vertically overlapped with the substrate 110 in between. The second power supply wiring 122 of the first layer 120 and the fourth power supply wiring 132 of the second layer 130 can be vertically overlapped. The third power supply wiring 131 of the first layer 120 and the fourth power supply wiring 132 of the second layer 130 can be vertically overlapped with the substrate 110 in between. As a result, the first power supply wiring 121 and the second power supply wiring 122 on the bottom surface of the substrate 110 vertically overlap with the third power supply wiring 131 and the fourth power supply wiring 132 on the top surface of the substrate 110, respectively, thereby increasing the transmission area and improving transparency.

[0056] In addition, in the embodiment, the substrate 110 may have a dielectric constant. In this case, a first capacitor is formed by the first power wiring 121, the third power wiring 131, and the substrate 110 between the first power wiring 121 and the third power wiring 131, and a second capacitor is formed by the second power wiring 122, the fourth power wiring 132, and the substrate between the second power wiring 122 and the fourth power wiring 132. As a result, the first capacitor and the second capacitor provide a noise reduction effect that makes the device insensitive to noise. Therefore, signal distortion due to noise does not occur, preventing poor image quality.

[0057] Meanwhile, the first data signal wiring 133 and the second data signal wiring 134 may serve to supply data signals. As will be described later, the first data signal wiring 133 and the second data signal wiring 134 are connected to the driving IC 140. In this case, the first data signal wiring 133 may be an input data signal wiring for inputting a data signal to the driving IC 140, and the second data signal wiring 134 may be an output data signal wiring for outputting a data signal from the driving IC 140 to the driving IC 140 of the next pixel.

[0058] A first data signal line 133 and a second data signal line 134 electrically connected to the driving IC 140 are arranged for each of a plurality of pixels (not shown) arranged along the first direction Y.

[0059] The first data signal wiring 133 and the second data signal wiring 134 are respectively disposed between the third power supply wiring 131 and the fourth power supply wiring 132. As described above, the connecting pattern 124 can electrically connect the third power supply wiring 131 and the fourth power supply wiring 132 through the first via 111 and the second via 112 on the substrate 110. This prevents the third power supply wiring 131 and the fourth power supply wiring 132 from being electrically shorted with the first data signal wiring 133.

[0060] Since the second data signal wiring 134 is disposed on the second layer 130, even if the connecting portion 123 on the first layer 120 crosses the second data signal wiring 134, the connecting portion 123 on the first layer 120 prevents an electrical short circuit of the second data signal wiring 134.

[0061] Meanwhile, the plurality of connecting wires 135 to 138 are disposed between the third power supply wire 131 and the fourth power supply wire 132. The plurality of connecting wires 135 to 138 can electrically connect the driving IC 140 and the light-emitting element chip 150 to each other.

[0062] The fourth connecting wire 138 is electrically connected to the second power supply wire 122 through the via 113 on the substrate 110. The fourth connecting wire 138 is also electrically connected to the driving IC 140 and the light emitting device chip 150.

[0063] The pads 181 to 187 and 191 to 194 are arranged in an area where the driving IC 140 is located and an area where the light emitting element chip 150 is located.

[0064] The plurality of pads 181-187 are arranged on a first region of the substrate 110 between the third power supply wiring 131 and the fourth power supply wiring 132. The driving IC 140 is arranged in the first region and is physically attached to and electrically connected to the plurality of pads 181-187. The plurality of pads 181-187 are electrically connected to the third power supply wiring 131, the first data signal wiring 133, the second data signal wiring 134, and the plurality of connecting wirings 135-138.

[0065] The plurality of pads 191 to 194 are disposed on the second region of the substrate 110 between the third power wiring 131 and the fourth power wiring 132. The light emitting device chip 150 is disposed in the second region and is physically attached to and electrically connected to the plurality of pads 191 to 194. The physical attachment may be performed using a die bonding method, but is not limited thereto.

[0066] The first pad 191 in the second region is electrically connected to the fifth pad 185 in the first region via the first connecting wire 135, the second pad 192 in the second region is electrically connected to the sixth pad 186 in the first region via the second connecting wire 136, and the third pad 193 in the second region is electrically connected to the seventh pad 187 in the first region via the third connecting wire 137. The fourth pad 194 in the second region is electrically connected to the second pad 182 in the first region via the fourth connecting wire 138. The fourth pad 194 is electrically connected to the second power supply wire 122 in the first layer 120 via the fourth connecting wire 138 and the via 113 on the substrate 110. As a result, a low potential voltage is supplied from the second power supply wire 122 to the second pad 182 in the first region and the fourth pad 194 in the second region.

[0067] Meanwhile, the third power supply wiring 131 is electrically connected to the first pad 181 of the first region, and a high potential voltage is supplied from the third power supply wiring 131 to the first pad 181. The first data signal wiring 133 is electrically connected to the third pad 183 of the first region, and a data signal is transmitted to the driving IC 140 via the third pad 183. The driving IC 140 generates a driving signal in response to the data signal and transmits it to the light emitting device chip 150, and the light emitting device chip 150 emits light in response to the driving signal. The driving signal may be, but is not limited to, a driving current. The second data signal wiring 134 is electrically connected to the fourth pad 184 of the first region, and a data signal is transmitted to the next pixel via the second data signal wiring 134.

[0068] The light emitting device chip 150 may be a member that emits light. In an embodiment, the light emitting device chip 150 may be a semiconductor light emitting device chip 150 made of an inorganic semiconductor material.

[0069] As shown in FIG. 1, the light-emitting device chip 150 may include a plurality of light-emitting devices 151 to 153 stacked vertically.

[0070] The first light-emitting element 151 may include a red light-emitting element that emits red light, the second light-emitting element 152 may include a green light-emitting element that emits green light, and the third light-emitting element 153 may include a blue light-emitting element that emits blue light, but is not limited thereto.

[0071] The second light emitting element 152 is disposed above the upper side of the first light emitting element 151, and the third light emitting element 153 is disposed above the upper side of the second light emitting element. In this case, the red light generated by the first light emitting element 151 is emitted forward via the second light emitting element 152 and the third light emitting element 153, the green light generated by the second light emitting element 152 is emitted forward via the third light emitting element 153, and the blue light generated by the third light emitting element 153 is emitted directly forward.

[0072] As described above, the driving IC 140 generates a driving signal (or a driving current) in response to a data signal and transmits the driving signal to the light emitting device chip 150. The brightness changes depending on the intensity of the driving signal (or the driving current), enabling gray scale expression.

[0073] The drive signals may be a first drive signal, a second drive signal, and a third drive signal, which may be different from each other.

[0074] The first light-emitting element 151 can emit red light in response to a first drive signal, the second light-emitting element 152 can emit green light in response to a second drive signal, and the third light-emitting element 153 can emit blue light in response to a third drive signal.

[0075] The first pad 191 to the third pad 193 are electrically connected to the anode electrodes of the vertically stacked first light emitting element 151, second light emitting element 152, and third light emitting element 153. The anode electrode of the first light emitting element 151 is electrically connected to the first connecting wire 135 via the first pad 191, the anode electrode of the second light emitting element 152 is electrically connected to the second connecting wire 136 via the second pad 192, and the anode electrode of the third light emitting element 153 is electrically connected to the third connecting wire 137 via the third pad 193.

[0076] The fourth pad 194 may be commonly connected to the cathode electrodes of the vertically stacked first light emitting element 151, second light emitting element 152, and third light emitting element 153. As such, the fourth pad 194 may be called a common pad, but is not limited thereto.

[0077] The driving IC 140 and the light-emitting element chip 150 may be surrounded by the first power wiring 121 (or the third power wiring 131), the second power wiring 122 (or the fourth power wiring 132), the connecting portion 123, and the connecting pattern 124. That is, based on the driving IC 140 and the light-emitting element chip 150, the first power wiring 121 may be disposed on the left side thereof, the second power wiring 122 may be disposed on the right side thereof, the connecting portion 123 may be disposed in front thereof, and the connecting pattern 124 may be disposed behind thereof.

[0078] In the embodiment, the light emitting device chip 150 may be a single chip or die in which a plurality of light emitting devices 151 to 153 are stacked and packaged. Although the drawing shows one light emitting device chip 150 in which a plurality of light emitting devices 151 to 153 are stacked and packaged, two or more light emitting device chips may be provided. That is, two or more light emitting device chips may be provided between the third power wiring 131 and the fourth power wiring 132.

[0079] 4, the light emitting device chip 150' may include a first light emitting device chip 151', a second light emitting device chip 152', and a third light emitting device chip 153', each configured as an individual chip or die. In this case, the first light emitting device chip 151', the second light emitting device chip 152', and the third light emitting device chip 153' may be arranged horizontally along the second direction X. To this end, the plurality of common pads 194a, 194b, and 194c are electrically connected to the fourth connecting wire 138. For example, the fourth connecting wire 138 is arranged long along the second direction X, and the first, second, and third regions of the fourth connecting wire 138 are assigned to the plurality of common pads 194a, 194b, and 194c.

[0080] The first pad 191 to the third pad 193 are arranged to horizontally correspond to the plurality of common pads 194a, 194b, and 194c, respectively. In this case, the first light-emitting element chip 151' is physically attached to and electrically connected to the first pad 191 and the common pad 194a. The second light-emitting element chip 152' is physically attached to and electrically connected to the second pad 192 and the common pad 194b. The third light-emitting element chip 153' is physically attached to and electrically connected to the third pad 193 and the common pad 194c.

[0081] Fig. 5 is a plan view of a transparent display device according to a second embodiment, Fig. 6A illustrates the first layer illustrated in Fig. 5, and Fig. 6B illustrates the second layer illustrated in Fig. 5.

[0082] Although the transparent display device is illustrated as including one pixel in Fig. 5, the transparent display device may be configured with a plurality of pixels as illustrated in Fig. 5.

[0083] Although a cross-sectional view of the transparent display device according to the second embodiment is not shown, the cross-sectional view is the same as the cross-sectional view shown in FIG.

[0084] The second embodiment is the same as the first embodiment (FIGS. 2-3B) except that the first power supply wiring 121 and the second power supply wiring 122 are high-potential wirings, and the third power supply wiring 131 and the fourth power supply wiring 132 are low-potential wirings. In the second embodiment, components having the same shape, structure, and / or function as those in the first embodiment (FIGS. 2-3B) are given the same reference numerals, and detailed descriptions thereof will be omitted. The following omitted descriptions of the second embodiment will be easily understood from the description of the first embodiment (FIGS. 2-3B).

[0085] 1 and 5, the transparent display device according to the second embodiment may include a substrate 110, a first layer 120, a second layer 130, a driving IC 140, a light-emitting device chip 150, and the like.

[0086] The first layer 120 is disposed on the bottom surface of the substrate 110 and the second layer 130 is disposed on the top surface of the substrate 110 .

[0087] As shown in FIG. 6A, the first layer 120 may include a first power wiring 121, a second power wiring 122, a connecting portion 125, a connecting pattern 126, and the like.

[0088] The first power supply wiring 121 and the second power supply wiring 122 are arranged along the first direction Y, and the connecting portion 125 and the connecting pattern 126 are arranged along the second direction X. The connecting portion 125 and the connecting pattern 126 are arranged between the first power supply wiring 121 and the second power supply wiring 122.

[0089] The connecting portion 125 may cross the first data signal wiring 133 of the second layer 130 along the second direction X to electrically connect the first power supply wiring 121 and the second power supply wiring 122. The connecting pattern 126 may cross the second data signal wiring 134 along the second direction X to electrically connect the third power supply wiring 131 and the fourth power supply wiring 132 of the second layer 130 through the first via 114 and the second via 115 on the substrate 110. This prevents the third power supply wiring 131 and the fourth power supply wiring 132 from being electrically shorted with the second data signal wiring 134.

[0090] The connection unit 125 is electrically connected to the driving IC 140 through the vias 116, pads 181, etc. on the substrate 110. As a result, the first power supply wiring 121 and the second power supply wiring 122 of the first layer 120 are electrically connected to the driving IC 140 through the connection unit 125. The high potential voltage supplied to the first power supply wiring 121 and the second power supply wiring 122 is supplied to the driving IC 140 through the connection unit 125.

[0091] The fourth power supply wiring 132 is electrically connected to the driving IC 140 and the light-emitting element chip 150. The fourth power supply wiring 132 is electrically connected to the light-emitting element chip 150 via a fourth connecting wiring 138a, a fourth pad 194, etc. The low potential voltage supplied to the fourth power supply wiring 132 is supplied to the light-emitting element chip 150 via the fourth connecting wiring 138a. The fourth power supply wiring 132 is further electrically connected to the driving IC 140 via another fourth connecting wiring 138b, a second pad 192, etc. The low potential voltage supplied to the fourth power supply wiring 132 is further supplied to the driving IC 140 via another fourth connecting wiring 138b.

[0092] As shown in FIG. 6B, the second layer 130 may include a third power supply wiring 131, a fourth power supply wiring 132, a first data signal wiring 133, a second data signal wiring 134, a plurality of connecting wirings 135-138, a plurality of pads 181-187, 191-194, etc.

[0093] The third power supply wiring 131, the fourth power supply wiring 132, the first data signal wiring 133, and the second data signal wiring 134 are arranged along the first direction Y.

[0094] The first data signal wiring 133 and the second data signal wiring 134 are disposed between the third power supply wiring 131 and the fourth power supply wiring 132 .

[0095] As described above, in the first embodiment (FIGS. 2 to 3B), the first power supply wiring 121 and the second power supply wiring 122 may be low-potential wiring, and the third power supply wiring 131 and the fourth power supply wiring 132 may be high-potential wiring.

[0096] However, as shown in Figures 5, 6A and 6B, in the second embodiment, the first power supply wiring 121 and the second power supply wiring 122 may be high-potential wiring, and the third power supply wiring 131 and the fourth power supply wiring 132 may be low-potential wiring.

[0097] Meanwhile, in the embodiment, the first power supply wiring 121 of the first layer 120 and the third power supply wiring 131 of the second layer 130 may be vertically overlapped. The first power supply wiring 121 of the first layer 120 and the third power supply wiring 131 of the second layer 130 may be vertically overlapped with the substrate 110 in between. The second power supply wiring 122 of the first layer 120 and the fourth power supply wiring 132 of the second layer 130 may be vertically overlapped. The third power supply wiring 131 of the first layer 120 and the fourth power supply wiring 132 of the second layer 130 may be vertically overlapped with the substrate 110 in between. As a result, the first power supply wiring 121 and the second power supply wiring 122 on the lower surface of the substrate 110 vertically overlap with the third power supply wiring 131 and the fourth power supply wiring 132 on the upper surface of the substrate 110, respectively, thereby increasing the transmission area and improving transparency.

[0098] In addition, in the embodiment, the substrate 110 may have a dielectric constant. In this case, a first capacitor is formed by the first power wiring 121, the third power wiring 131, and the substrate 110 between the first power wiring 121 and the third power wiring 131, and a second capacitor is formed by the second power wiring 122, the fourth power wiring 132, and the substrate between the second power wiring 122 and the fourth power wiring 132. As a result, the first capacitor and the second capacitor provide a noise reduction effect that makes the device insensitive to noise. Therefore, signal distortion due to noise does not occur, preventing poor image quality.

[0099] Fig. 7 is a plan view of a transparent display device according to a third embodiment. Fig. 8A is a cross-sectional view of the transparent display device shown in Fig. 7 taken along line A-A'. Fig. 8B is a cross-sectional view of the transparent display device shown in Fig. 7 taken along line B-B'. Fig. 9 illustrates the transparent display device shown in Fig. 7, in which the second power wiring of the first layer and the third power wiring of the second layer are electrically connected to each other along a first direction.

[0100] FIG. 10 illustrates a state in which the first power wiring of the first layer and the fourth power wiring of the second layer are electrically connected to each other along a first direction in the transparent display device illustrated in FIG.

[0101] Referring to FIGS. 7, 8A and 8B, the transparent display device according to the third embodiment may include a substrate 110, a first layer 120, a second layer 130, and the like.

[0102] The first layer 120 is disposed on the lower surface of the substrate 110, and the second layer 130 is disposed on the upper surface of the substrate 110. The first layer 120 may include a plurality of first power supply wirings 121, a plurality of second power supply wirings 122, etc., and the second layer 130 may include a plurality of third power supply wirings 131, a plurality of fourth power supply wirings 132, etc.

[0103] Although not shown, a plurality of pixels may be provided between a plurality of third power supply wirings 131 and a plurality of fourth power supply wirings 132. That is, a plurality of pixels may be provided along the first direction Y between adjacent third power supply wirings 131 and fourth power supply wirings 132. Furthermore, a plurality of pixels may be provided along the first direction Y between other adjacent third power supply wirings 131 and fourth power supply wirings 132.

[0104] Although not shown, each of the pixels may be provided with a driving IC 140 and a light-emitting element chip 150. The driving IC 140 and the light-emitting element chip 150 may be provided on the upper surface of the substrate 110.

[0105] The plurality of first power supply wirings 121 and the plurality of second power supply wirings 122 are arranged on the lower surface of the substrate 110. The plurality of first power supply wirings 121 and the plurality of second power supply wirings 122 may be arranged parallel to each other along the first direction Y, but are not limited thereto.

[0106] The plurality of third power supply wirings 131 and the plurality of fourth power supply wirings 132 are arranged on the upper surface of the substrate 110. The plurality of third power supply wirings 131 and the plurality of fourth power supply wirings 132 may be arranged parallel to each other along the first direction Y, but are not limited thereto.

[0107] In the embodiment, the plurality of first power supply wires 121 on the first layer 120 and the plurality of third power supply wires 131 on the second layer 130 may be vertically overlapped with each other. The plurality of first power supply wires 121 on the first layer 120 and the plurality of third power supply wires 131 on the second layer 130 may be vertically overlapped with each other with the substrate 110 in between. The plurality of second power supply wires 122 on the first layer 120 and the plurality of fourth power supply wires 132 on the second layer 130 may be vertically overlapped with each other with the substrate 110 in between. As a result, the multiple first power supply wirings 121 on the lower surface of the substrate 110 each vertically overlap with the multiple third power supply wirings 131 on the upper surface of the substrate 110, and the multiple third power supply wirings 131 on the lower surface of the substrate 110 each vertically overlap with the multiple fourth power supply wirings 132 on the upper surface of the substrate 110, thereby increasing the transmission area and improving transparency.

[0108] In addition, in the embodiment, the substrate 110 may have a dielectric constant. In this case, a first capacitor is formed by the first power wiring 121, the third power wiring 131, and the substrate 110 between the first power wiring 121 and the third power wiring 131, and a second capacitor is formed by the second power wiring 122, the fourth power wiring 132, and the substrate between the second power wiring 122 and the fourth power wiring 132. As a result, the first capacitor and the second capacitor provide a noise reduction effect that makes the device insensitive to noise. Therefore, signal distortion due to noise does not occur, preventing poor image quality.

[0109] Meanwhile, the plurality of first power supply wirings 121 and the plurality of second power supply wirings 122 may be alternately arranged on the lower surface of the substrate 110 along the second direction X. The plurality of third power supply wirings 131 and the plurality of fourth power supply wirings 132 may be alternately arranged on the upper surface of the substrate 110 along the second direction X.

[0110] In the embodiment, the first power supply wiring 121 and the fourth power supply wiring 132 may be low-potential wirings, and the second power supply wiring 122 and the fourth power supply wiring 132 may be high-potential wirings, but the opposite is also possible.

[0111] 8A and 9, a plurality of second power supply wirings 122 in the first layer 120 are electrically connected to a plurality of third power supply wirings 131 in the second layer 130 through a plurality of first vias 118 and a plurality of second vias 118' on the substrate 110. For example, the third power supply wiring 131 in the second layer 130 is electrically connected to one side of the second power supply wiring 122 in the first layer 120 through the first via 118 on the substrate 110. The other side of the second power supply wiring 122 in the first layer 120 is electrically connected to one side of a further third power supply wiring 131 in the second layer 130 through the second via 118' on the substrate 110. One side of the further third power supply wiring 131 in the second layer 130 is connected to one side of a further second power supply wiring 122 in the first layer 120 through the first via 118. As a result, a first supply path is formed through which a high potential voltage is alternately supplied to the upper and lower surfaces of the substrate 110 along the second direction X.

[0112] 8B and 10 , a plurality of first power supply wirings 121 in the first layer 120 are electrically connected to a plurality of fourth power supply wirings 132 in the second layer 130 through a plurality of first vias 117 and a plurality of second vias 117′ on the substrate 110. For example, the first power supply wiring 121 in the first layer 120 is electrically connected to one side of the fourth power supply wiring 132 in the second layer 130 through the first via 117 on the substrate 110. The other side of the fourth power supply wiring 132 in the second layer 130 is electrically connected to one side of another first power supply wiring 121 in the first layer 120 through a second via 117′ on the substrate 110. One side of the yet another fourth power supply wiring 132 in the first layer 120 is connected to one side of the yet another fourth power supply wiring 132 in the second layer 130 through the first via 117. As a result, a second supply path is formed through which the low potential voltage is alternately supplied to the upper and lower surfaces of the substrate 110 along the second direction X.

[0113] Of the first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 that overlap each other perpendicularly along the first direction Y, the first power wiring 121 is electrically connected to the fourth power wiring 132 of the adjacent second layer 130, and the third power wiring 131 is electrically connected to the second power wiring 122 of the adjacent first layer 120, alternately formed by row lines.

[0114] Of the second power supply wiring 122 of the first layer 120 and the fourth power supply wiring 132 of the second layer 130 that overlap each other perpendicularly along the first direction Y, the second power supply wiring 122 is electrically connected to the third power supply wiring 131 of the adjacent second layer 130, and the fourth power supply wiring 132 is electrically connected to the first power supply wiring 121 of the adjacent first layer 120, alternately.

[0115] Meanwhile, at one end of the substrate 110, the first power supply wiring 121 and the fourth power supply wiring 132 are electrically connected to a low voltage supply unit (or low voltage supply pad) that supplies a low potential voltage, and the second power supply wiring 122 and the third power supply wiring 131 are electrically connected to a high potential supply unit (or high potential supply pad) that supplies a high potential voltage. The low potential supply unit and the high potential supply unit are arranged on the upper surface of the substrate 110. In this case, the first power supply wiring 121 and the second power supply wiring 122 arranged on the lower surface of the substrate 110 are electrically connected to the low potential supply unit and the high potential supply unit through their corresponding vias on the substrate 110, respectively.

[0116] On the other hand, the greater the number of vias, the greater the IR drop due to resistance loss. However, in this embodiment, among the plurality of first power wirings 121 arranged on the lower surface of the substrate 110, only the first power wiring 121 electrically connected to the fourth power wiring 132 arranged on the upper surface of the substrate 110 requires a corresponding via to be electrically connected to the low potential supply unit on the upper surface of the substrate 110. Also, among the plurality of second power wirings 122 arranged on the lower surface of the substrate 110, only the second power wiring 122 electrically connected to the third power wiring 131 arranged on the upper surface of the substrate 110 requires a corresponding via to be electrically connected to the high potential supply unit on the upper surface of the substrate 110. As a result, the number of vias is reduced, and IR drop is mitigated or minimized.

[0117] In particular, even if the first power supply wiring 121 and / or the second power supply wiring 122 arranged on the lower surface of the substrate 110 and the third power supply wiring 131 and / or the fourth power supply wiring 132 arranged on the upper surface of the substrate 110 have different thicknesses, the resistance in the first supply path and the resistance in the second supply path can be equalized due to the connection structure between the first power supply wiring 121 and the fourth power supply wiring 132 and the connection structure between the second power supply wiring 122 and the third power supply wiring 131. As a result, IR drop is used symmetrically not only in the pixels but also within the upper and lower surfaces of the substrate 110, ensuring uniform image quality.

[0118] Fig. 11 is a plan view of a transparent display device according to a fourth embodiment, Fig. 12A illustrates the first layer illustrated in Fig. 11, and Fig. 12B illustrates the second layer illustrated in Fig. 11.

[0119] 11, the transparent display device is illustrated as including one pixel, but the transparent display device may be configured with a plurality of pixels as illustrated in FIG.

[0120] Although a cross-sectional view of the transparent display device according to the fourth embodiment is not shown, the cross-sectional view is the same as the cross-sectional view shown in FIG.

[0121] 1 and 11, the transparent display device according to the fourth embodiment may include a substrate 110, a first layer 120, a second layer 130, a driving IC 140, a light-emitting device chip 150, and the like.

[0122] The first layer 120 is disposed on the bottom surface of the substrate 110 and the second layer 130 is disposed on the top surface of the substrate 110 .

[0123] As shown in FIG. 12A, the first layer 120 may include a first power wiring 121, a second power wiring 122, a first connector 127, a second connector 128, and the like.

[0124] The first power supply wiring 121 and the second power supply wiring 122 are arranged along the first direction Y, and the first connecting portion 127 and the second connecting portion 128 are arranged along the second direction X. The first connecting portion 127 and the second connecting portion 128 are arranged between the first power supply wiring 121 and the second power supply wiring 122.

[0125] As shown in FIG. 12B, the second layer 130 may include a third power supply wiring 131, a fourth power supply wiring 132, a first data signal wiring 133, a second data signal wiring 134, a plurality of connecting wirings 135-138, a plurality of pads 181-187, 191-194, etc.

[0126] The third power supply wiring 131, the fourth power supply wiring 132, the first data signal wiring 133, and the second data signal wiring 134 are arranged along the first direction Y.

[0127] In the embodiment, the first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 may vertically overlap. The first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 may vertically overlap with the substrate 110 in between. The second power wiring 122 of the first layer 120 and the fourth power wiring 132 of the second layer 130 may vertically overlap. The third power wiring 131 of the first layer 120 and the fourth power wiring 132 of the second layer 130 may vertically overlap with the substrate 110 in between. As a result, the first power wiring 121 and the second power wiring 122 on the bottom surface of the substrate 110 vertically overlap with the third power wiring 131 and the fourth power wiring 132 on the top surface of the substrate 110, respectively, thereby increasing the transmission area and improving transparency.

[0128] In addition, in the embodiment, the substrate 110 may have a dielectric constant. In this case, a first capacitor is formed by the first power wiring 121, the third power wiring 131, and the substrate 110 between the first power wiring 121 and the third power wiring 131, and a second capacitor is formed by the second power wiring 122, the fourth power wiring 132, and the substrate between the second power wiring 122 and the fourth power wiring 132. As a result, the first capacitor and the second capacitor provide a noise reduction effect that makes the device insensitive to noise. Therefore, signal distortion due to noise does not occur, preventing poor image quality.

[0129] On the other hand, in the first embodiment (FIGS. 2 to 3B), the first power supply wiring 121 and the second power supply wiring 122 of the first layer 120 may be low-potential wiring, and the third power supply wiring 131 and the fourth power supply wiring 132 of the second layer 130 may be high-potential wiring. In the second embodiment (FIGS. 5 to 6B), the first power supply wiring 121 and the second power supply wiring 122 of the first layer 120 may be high-potential wiring, and the third power supply wiring 131 and the fourth power supply wiring 132 of the second layer 130 may be low-potential wiring.

[0130] On the other hand, in the fourth embodiment (FIGS. 11 to 12B), the first power supply wiring 121 and the fourth power supply wiring 132 may be low-potential wiring, and the second power supply wiring 122 and the third power supply wiring 131 may be high-potential wiring.

[0131] The first power supply wiring 121 arranged on the lower surface of the substrate 110 may be a low-potential wiring, and the second power supply wiring 122 arranged on the lower surface of the substrate 110 may be a high-potential wiring. The third power supply wiring 131 arranged on the upper surface of the substrate 110 and vertically overlapping the first power supply wiring 121 may be a high-potential wiring. The fourth power supply wiring 132 arranged on the upper surface of the substrate 110 and vertically overlapping the second power supply wiring 122 may be a low-potential wiring.

[0132] In this case, the first power supply wiring 121 is electrically connected to the fourth power supply wiring 132 , and the second power supply wiring 122 is electrically connected to the third power supply wiring 131 .

[0133] To this end, the first layer 120 may include a first connector 127, a second connector 128, etc. The first connector 127 and the second connector 128 are disposed between the first power wiring 121 and the second power wiring 122. The first connector 127 and the second connector 128 are disposed parallel to each other along the second direction X.

[0134] The first connector 127 may extend from the first power supply wiring 121 in the second positive (+) direction X across the first data signal wiring 133 and be spaced apart from the second power supply wiring 122. The second connector 128 may extend from the second power supply wiring 122 in the second negative (-) direction X across the second data signal wiring 134 and be spaced apart from the first power supply wiring 121.

[0135] The first connecting unit 127 is disposed across the first data signal wiring 133 of the second layer 130. The first connecting unit 127 may electrically connect the first power supply wiring 121 and the fourth power supply wiring 132 through a first via 117 on the substrate 110. The first via 117 may be located on a region of the first connecting unit 127. The second connecting unit 128 is disposed across the second data signal wiring 134 of the second layer 130. The second connecting unit 128 may electrically connect the second power supply wiring 122 and the third power supply wiring 131 through a second via 118 on the substrate 110. The second via 118 may be located on a region of the second connecting unit 128.

[0136] The respective arrangement structures of the first connecting portion 127 and the second connecting portion 128 and the respective arrangement positions of the first via 117 and the second via 118 described above prevent the first power supply wiring 121 and the fourth power supply wiring 132 from being electrically shorted to the first data signal wiring 133, and prevent the second power supply wiring 122 and the third power supply wiring 131 from being electrically shorted to the second data signal wiring 134.

[0137] Due to the above-described arrangement, a low potential voltage is supplied to the left of the driving IC 140 and the light-emitting element via the first power supply wiring 121 on the underside of the substrate 110, and a low potential voltage is supplied to the right of the driving IC 140 and the light-emitting element via the fourth power supply wiring 132 on the upper surface of the substrate 110. Furthermore, a high potential voltage is supplied to the left of the driving IC 140 and the light-emitting element via the third power supply wiring 131 on the upper surface of the substrate 110, and a high potential voltage is supplied to the right of the driving IC 140 and the light-emitting element via the second power supply wiring 122 on the lower surface of the substrate 110.

[0138] The first connector 127 may be a first equipotential power supply wiring because it makes the low potential voltage supplied to the first power supply wiring 121 and the low potential voltage supplied to the fourth power supply wiring 132 the same. The second connector 128 may be a second equipotential power supply wiring because it makes the high potential voltage supplied to the second power supply wiring 122 and the high potential voltage supplied to the third power supply wiring 131 the same.

[0139] Meanwhile, the third power supply wiring 131 is electrically connected to the driving IC 140 , and the fourth power supply wiring 132 is electrically connected to the driving IC 140 and the light emitting device chip 150 .

[0140] FIG. 13 is a cross-sectional view of a transparent display device according to the second embodiment.

[0141] The second embodiment is the same as the first embodiment (FIG. 1) except for the thermal diffusion layers 161 and 162. In the second embodiment, elements having the same shape, structure, and / or function as those in the first embodiment (FIG. 1) are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. The following omitted descriptions of the second embodiment can be easily understood from the description of the first embodiment (FIG. 1).

[0142] 13, the thermal diffusion layers 161 and 162 are disposed on the lower surface of the substrate 110. The thermal diffusion layers 161 and 162 may serve to quickly dissipate heat generated in the driving IC 140 and / or the light emitting device chip 150 to the outside. The thermal diffusion layers 161 and 162 may be made of a material with excellent heat dissipation properties. For example, the thermal diffusion layers 161 and 162 may be made of a metal such as aluminum with excellent heat dissipation properties. The thermal diffusion layers 161 and 162 may also be heat dissipation plates.

[0143] The thermal diffusion layer may include a first thermal diffusion layer 161 on the lower surface of the substrate 110 corresponding to the driving IC 140 and a second thermal diffusion layer 162 on the lower surface of the substrate 110 corresponding to the light emitting device chip 150. The first thermal diffusion layer 161 can quickly dissipate heat generated in the driving IC 140 to the outside, and the second thermal diffusion layer 162 can quickly dissipate heat generated in the light emitting device chip 150 to the outside.

[0144] Although not shown in the drawings, the thermal diffusion layers 161 and 162 may not be separated into the first thermal diffusion layer 161 and the second thermal diffusion layer 162, but may be arranged to extend from a first region on the lower surface of the substrate 110 corresponding to the driving IC 140 to a second region on the lower surface of the substrate 110 corresponding to the light emitting device chip 150. That is, the thermal diffusion layers 161 and 162 may be arranged not only in the first region and the second region but also in a third region between the first region and the second region.

[0145] Instead of the thermal diffusion layers 161 and 162, a light blocking layer, a light reflecting layer, a light absorbing layer, or the like may be disposed.

[0146] 14A and 14B are cross-sectional views illustrating an example of a transparent display device according to the third embodiment, and another example of a transparent display device according to the third embodiment.

[0147] FIG. 14A is a cross-sectional view illustrating the driving IC 140 and light-emitting element provided in one pixel, and FIG. 14B is a cross-sectional view illustrating the area of ​​one pixel where the driving IC 140 and light-emitting element are not arranged.

[0148] The third embodiment is similar to the first embodiment (FIG. 1) except for the first substrate 171 and the second substrate 172. In the third embodiment, components having the same shape, structure, and / or function as those in the first embodiment (FIG. 1) are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. The following omitted descriptions of the third embodiment can be easily understood from the description of the first embodiment (FIG. 1).

[0149] Referring to Figures 14A and 14B, the transparent display device according to the third embodiment may include a first substrate 171, a second substrate 172, a first layer 120, a second layer 130, a driving IC 140, a light-emitting element chip 150, etc.

[0150] The lower surface of the first substrate 171 and the upper surface of the second substrate 172 are arranged to face each other. In this case, the first layer 120 is arranged on the lower surface of the first substrate 171, and the second layer 130 is arranged on the upper surface of the second substrate 172.

[0151] The first layer 120 may include a first power supply wiring 121, a second power supply wiring 122, and the like, and the second layer 130 may include a third power supply wiring 131, a fourth power supply wiring 132, and the like.

[0152] The driving IC 140 and the light emitting device chip 150 are disposed on the upper surface of the second substrate 172. The driving IC 140 and the light emitting device chip 150 are disposed between the first substrate 171 and the second substrate 172. The upper side of the driving IC 140 and the upper side of the light emitting device chip 150 may be spaced apart from the lower surface of the first substrate 171, but this is not limitative.

[0153] Although not shown, a molding part is disposed between the first substrate 171 and the second substrate 172. The first substrate 171 and the second substrate 172 are joined together through the molding part, and the driving IC 140 and the light emitting device chip 150 are fixed thereto.

[0154] Meanwhile, a conductive spacer 175 is disposed between the first substrate 171 and the second substrate 172. The conductive spacer 175 can be used in place of the first via 111, the second via 112, and the via 113 shown in FIG. 2, the first via 114, the second via 115, and the via 116 shown in FIG. 5, and the first via 117 and the second via 118 shown in FIG.

[0155] For example, as shown in FIG. 14B, the first power wiring 121 and the fourth power wiring 132 are electrically connected via a conductive spacer 175. The conductive spacer 175 may be made of metal or a composite material such as a resin containing metal. A conductive ball or solder containing metal may be used instead of the conductive spacer 175. As shown in FIG. 11, the first power wiring 121 and the fourth power wiring 132, to which a low potential voltage is supplied, are electrically connected via the conductive spacer 175.

[0156] Although not shown, the second power supply line 122 and the third power supply line 131 to which a high potential voltage is supplied are electrically connected via another conductive spacer 175 .

[0157] The above detailed description should not be construed as limiting in all respects, but should be considered as illustrative. The scope of the embodiments should be determined by a reasonable analysis of the appended claims, and all modifications within the equivalent range of the embodiments are included in the scope of the embodiments.

Claims

1. a first layer including first and second power supply wirings along a first direction; a second layer disposed on the first layer and including a third power supply wiring, a fourth power supply wiring, a first data signal wiring, a second data signal wiring, and a plurality of connecting wirings along the first direction; a driving IC disposed between the third power supply wiring and the fourth power supply wiring; a light emitting element disposed between the third power supply wiring and the fourth power supply wiring, the driving IC is electrically connected to one of the first power supply wiring and the third power supply wiring, one of the second power supply wiring and the fourth power supply wiring, the first data signal wiring, the second data signal wiring, and the plurality of connecting wirings; the light emitting device is electrically connected to one of the second power supply wiring and the fourth power supply wiring and the plurality of connecting wirings; the first power supply wiring and the third power supply wiring vertically overlap each other, The second power wiring and the fourth power wiring are vertically overlapped.

2. The transparent display device of claim 1 further comprising a substrate having a bottom surface on which the first layer is disposed and a top surface on which the second layer is disposed.

3. the first power supply wiring and the second power supply wiring are low-potential wirings, The transparent display device according to claim 2 , wherein the third power supply wiring and the fourth power supply wiring are high-potential wirings.

4. The first layer is a connecting portion that crosses the second data signal wiring along a second direction and electrically connects the first power supply wiring and the second power supply wiring; 4. The transparent display device of claim 3, further comprising: a connection pattern that crosses the first data signal wiring along the second direction and electrically connects the third power wiring and the fourth power wiring through first vias and second vias on the substrate.

5. the second power wiring is electrically connected to the driving IC and the light emitting element through a via on the substrate; The transparent display device of claim 3 , wherein the third power wiring is electrically connected to the driving IC.

6. the first power supply wiring and the second power supply wiring are high-potential wirings, The transparent display device according to claim 2 , wherein the third power supply wiring and the fourth power supply wiring are low-potential wirings.

7. The first layer is a connecting portion that crosses the first data signal wiring along a second direction and electrically connects the first power supply wiring and the second power supply wiring; 7. The transparent display device of claim 6, further comprising: a connection pattern that crosses the second data signal wiring along the second direction and electrically connects the third power wiring and the fourth power wiring through first vias and second vias on the substrate.

8. the connecting portion is electrically connected to the driving IC through a via on the substrate; The transparent display device of claim 7 , wherein the fourth power wiring is electrically connected to the driving IC and the light emitting element.

9. the first power supply wiring and the fourth power supply wiring are low-potential wirings, The transparent display device according to claim 2 , wherein the second power supply wiring and the third power supply wiring are high-potential wirings.

10. The first layer is a first connection portion that crosses the first data signal wiring along a second direction and electrically connects the first power supply wiring and the fourth power supply wiring through a first via on the substrate; 10. The transparent display device of claim 9, further comprising: a second connection portion that crosses the second data signal wiring along the second direction and electrically connects the second power wiring and the third power wiring through a second via on the substrate.

11. the third power supply wiring is electrically connected to the driving IC; The transparent display device of claim 9 , wherein the fourth power wiring is electrically connected to the driving IC and the light emitting element.

12. a first substrate having a lower surface on which the first layer is disposed; a second substrate having an upper surface on which the second layer is disposed; The transparent display device according to claim 1 , wherein the driving IC and the light emitting element are disposed between the first substrate and the second substrate.

13. The transparent display device of claim 12 , further comprising a conductive spacer between the first substrate and the second substrate.

14. The transparent display device of claim 1 , wherein the light emitting element comprises a plurality of light emitting elements vertically stacked on one another and electrically connected to the plurality of interconnect lines.

15. The transparent display device of claim 1 , wherein the light emitting element comprises a plurality of light emitting elements arranged horizontally along the second direction and connected to the plurality of connecting wires.

Images