Multi-chip module package technology for advanced driver assistance system application

Abstract

To provide a multi-chip-module (MCM) and a thermal-mechanical testing vehicle (TMTV) that improve the overall cost, reliability and efficiency of a package.SOLUTION: An automotive grade MCM 100 includes an advanced driver assistance system (ADAS) system-on-chip and multiple dynamic random access memories (DRAMs) in one package. In addition, a thermal-mechanical testing vehicle (TMTV) is used to mimic ADAS chips on an ADAS system from thermal, mechanical or manufacturability perspective. There exists a system which includes multiple MCM components designed into a customized printed circuit board (PCB) 108 with a liquid cooling system.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Application No. 63 / 554,082, entitled "MULTI-CHIP-MODULE PACKAGE TECHNOLOGY FOR ADAS APPLICATION," filed February 15, 2024, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] A multi-chip module (MCM) is generally an electronic assembly (such as a package with several conductive terminals or "pins") in which multiple integrated circuits (ICs or "chips"), semiconductor dies, or other discrete components may be integrated, usually on a unified substrate, so that in use, the MCM can be treated as if it were a larger IC. MCM packaging may allow manufacturers to use multiple components for modularity or to improve yield over traditional monolithic IC approaches. In addition, a particular IC may have very similar or identical pinouts when used multiple times within a system. Carefully designed substrates may allow these dies to be stacked in a vertical configuration, making the resulting MCM have a smaller footprint, as area can be at a premium in miniature electronics designs.

[0003] Packaged and unpackaged integrated circuits may undergo environmental testing as an operation in the manufacturing process. In such testing, the integrated circuit device may be subjected to electrical testing, e.g., "test patterns," to confirm functionality while being subjected to environmental stress. For example, the integrated circuit may be heated or cooled to its specification limits while being electrically tested. In some cases, e.g., for qualification testing, the integrated circuit may be stressed beyond its specifications, e.g., to determine failure points or to establish guard bands on its environmental specifications.

[0004] Aspects of the subject technology can help improve the overall cost, reliability, and efficiency of circuits or other electronic components. Summary of the Invention

[0005] This description is generally directed to automotive-grade MCM technology that may include an advanced driver assistance system (ADAS) system-on-chip (SoC) and multiple dynamic random access memories (DRAMs) in one package. Additionally, a thermal-mechanical testing vehicle (TMTV) may be used to mimic the ADAS chip on the ADAS system from a thermal, mechanical, or manufacturability perspective. There may be systems that include multiple MCM components designed into a customized printed circuit board (PCB) with a liquid cooling system. [Brief explanation of the drawings]

[0006] Certain features of the subject technology are set forth in the appended claims. However, for purposes of explanation, several embodiments of the subject technology are set forth in the following figures. [Figure 1]FIG. 1 shows an example diagram of a multi-chip module (MCM) that may include an ADAS system-on-chip (SoC) and multiple co-packaged DRAMs. [Figure 2A] FIG. 2A shows an exemplary cross-sectional side view of a chip packaging technique on a substrate. [Figure 2B] FIG. 2B shows an exemplary cross-sectional side view of a chip packaging technique on a printed circuit board. [Figure 3] FIG. 3 shows an exemplary MCM and lid. [Figure 4A] FIG. 4A shows an exemplary MCM that takes TIM into account. [Figure 4B] FIG. 4B shows an exemplary MCM that takes the TIM into account. [Figure 5A] FIG. 5A illustrates an exemplary liquid cooling configuration associated with a TMTV. [Figure 5B] FIG. 5B shows an exemplary board associated with TMTV. [Figure 6] FIG. 6 shows an example TMTV design feature overview. [Figure 7] FIG. 7 shows an exemplary die crack sensor configuration. [Figure 8] FIG. 8 shows exemplary capacitor-related TMTV design features. [Figure 9] FIG. 9 shows an example corner bump and stacked via associated with the TMTV design feature. DETAILED DESCRIPTION OF THE INVENTION

[0007] The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology can be practiced. The accompanying drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject technology. However, the subject technology is not limited to the specific details set forth herein and may be practiced using one or more other implementation forms. In one or more embodiments, structures and components are shown in block diagram form to avoid obscuring the concepts of the subject technology.

[0008] As shown in FIG. 1 , a multi-chip module (MCM) 100 may include a processor 101 (e.g., an ADAS SoC) and multiple DRAMs (e.g., DRAM 104, DRAM 105, or DRAM 106) co-packaged with the processor 101, which may enable double data rate (DDR) bandwidth requirements and may enable cost reduction, increased power supply, or further optimization at the ADAS system level. While FIG. 1 shows three DRAMs, there may be any suitable number of DRAMs around the processor 101. The number of DRAMs implemented may be based on memory bandwidth requirements (e.g., the memory bandwidth (BW) requirements of the ADAS SoC given the available DRAM).

[0009] The disclosed MCM can enable significant enabled DDR bandwidth requirements for ADAS SoCs by ensuring data rates (e.g., LPDDR5 x 8.5 Gbps) with assured signal and power quality that may otherwise be difficult to achieve if DRAM is integrated at the board level. This, in turn, can help save DRAM-related system costs, which may include the assumption that the same total bandwidth is required regardless of the DRAM integration method (co-packaged or on-board) when an MCM such as that shown in FIG. 2 is implemented. FIGS. 2A and 2B show an exemplary comparison of an MCM with a flip-chip ball grid array (FCBGA). FIG. 2A shows an exemplary side cross-sectional view of a chip-on-substrate packaging technology. The MCM 100 can include a printed circuit board (PCB) 109, a substrate 108, a processor 101 (e.g., SoC 101), or memory 104 (e.g., DRAM 104). As shown in FIG. 2, the processor 101 and memory 104 may be on the same substrate 108 and may be connected through such substrate 108. FIG. 2B shows an exemplary cross-sectional side view of a chip packaging technique on a PCB. As shown in FIG. 2B, the MCM 110 may include a PCB 119, a substrate 118, a processor 111 (e.g., SoC 111), or a memory 114 (e.g., DRAM 104). As shown in FIG. 2, the processor 111 may be on the substrate 118, and the memory 114 may be on the PCB 119. The connection between the processor 111 and the memory 114 may be through at least the substrate 118 and the PCB 119.

[0010] The disclosed MCM 100 can help enable reduced cost and more efficient power delivery for ACM3 systems due to one or more of the following three considerations. The first consideration may be that high-density DRAM signal routing can be performed on the MCM 100 rather than on the PCB, thus allowing standard through-hole printed circuit boards (PCBs) to be applied instead of more costly microvia types to save cost. The second consideration may be that the DRAM 104 on package MCM architecture can enable smaller PCB area and smaller system cold plate form factors. The form factor reduction opportunity can be a significant percentage (e.g., about 70% or more) of combined footprint reduction (vs. SoC+DRAM on board). The board design can be simplified with the SoC / DRAM as the incoming known good unit, without DDR and system-level lift. A third consideration may be that there may be better power delivery (e.g., reduced power-related noise) due to a customized MCM ball grid array (ball pitch and ball map) to help optimize the PCB backcap placement, elimination of poor power delivery planes caused by DRAM routing on PCB 109, and power management integrated circuits (PMICs) much closer to SoC key IP load points to reduce IR drop. In one example, when considering other packaging technologies such as MCM 110, the overall power-related noise range reduction may be greater than 50%, the worst-case voltage drop reduction may be greater than 50%, DC resistance may be reduced by greater than 30%, or alternating current inductance (ACI) may be reduced by greater than 40%.

[0011] In addition to the SoC die, the package or PCB floorplan, among others, can be optimized for overall system-level performance. In one example, there can be core IP placement at the die edge beachfront to ensure direct access to die-side capacitors for fast di / dt transient response of the power delivery network, as well as close access to the PMIC located on the PCB.

[0012] The disclosed subject matter may be associated with automotive-grade MCM technology that may include an ADAS SoC 101 and multiple DRAMs 104 in one package. A multi-chip module (MCM) 100, as disclosed herein, may integrate the DRAMs 104 with the SoC 101 as one integrated ball grid array component for applications such as autonomous driving applications.

[0013] As disclosed, the DRAM 104 can be arranged around the SoC 101. The more symmetric the configuration, such as in a "butterfly" floorplan, the greater the likelihood of uniform warping if warping occurs. The design and signal / power performance of each SoC PHY to DRAM can be repeated across multiple instances to provide predictable system-level performance when multiple DRAMs operate under various user conditions. A nearly centralized SoC within the package floorplan can help save approximately 3-5°C in Tjunction max (Tjmax) on critical IP, such as machine learning engines, thereby improving performance or saving power. This structure can be mechanically balanced, which can result in uniform warpage distribution when assembled onto the PCB 109 to aid in a robust surface-mount technology (SMT) process.

[0014] FIG. 3 illustrates an exemplary thermal lid 130 that can be incorporated into the MCM 100. The thermal lid 130 can include a pedestal 131, a landing 133, or a cavity 135. The thermal lid 130 can be made of nickel-plated copper (Ni-plated Cu) with a pedestal design, as shown in FIG. 3 . The thermal lid 130 can also be manufactured from copper (Cu) electroplated with nickel (Ni). Copper can serve as the primary structural material due to its thermal conductivity (approximately 385 W / m·K at room temperature) and mechanical properties, while the nickel plating can provide surface protection against oxidation or corrosion. The nickel plating thickness can be adopted based on specific application requirements. Alternatively, the thermal lid 130 can be composed of other thermally conductive materials, such as aluminum (Al), copper-tungsten (Cu-W), copper-molybdenum (Cu-Mo), or other suitable metals or metal alloys with thermal or mechanical properties suitable for semiconductor packaging applications. Table 1 shows exemplary considerations associated with the thermal lid 130.

[0015] [Table 1]

[0016] The disclosed pedestal configuration of the thermal lid 130 can address inefficiencies based on differences in Z-height between the SoC silicon and the DRAM components. As shown, the pedestal 131 can be positioned over the SoC 101 or the DRAM 104, as needed, whichever is shortest (usually the SoC 101), or over multiple components (e.g., one or more of the DRAMs 104, 105, 106, and the SoC 101). In one example, if the SoC 101 has a significant cavity (e.g., cavity 135), it may be desirable to reduce the size of the cavity 135 between the thermal lid 130 and the SoC 101. Thus, the thermal lid 130 can be made with a pedestal 131 (e.g., a pedestal overhang or protrusion) associated with the thermal lid 130, which can improve performance.

[0017] 4A and 4B show cross-sectional views of example structures with and without DRAM thermal interface material (TIM) implementation, respectively. Referring to FIG. 4A, a first configuration shows MCM 100 implementing DRAM TIM 137, where SoC 101 may be surrounded by multiple DRAM components (e.g., DRAM 104, DRAM 105, DRAM 106) on substrate 108. When visualized, the thermal distribution map shows a substantially uniform temperature gradient across the package surface, as indicated by the coloring (e.g., green) suggesting effective heat dissipation.

[0018] 4B, a second configuration shows a semiconductor package arrangement similar to that of FIG. 4A, but without DRAM TIM 137. When tested, thermal map regions showed significantly elevated temperatures, such as around the DRAM areas (e.g., areas around DRAM 104, DRAM 105, and DRAM 106), indicated by coloring (e.g., red) suggesting less effective heat dissipation.

[0019] As disclosed, a thermal interface material (TIM) can be disposed on the DRAM 104 to provide a low thermal impedance path for the DRAM 104, which can enable a lower Tjmax for the DRAM 104 and, in turn, can help improve usable DRAM bandwidth by approximately 20% from reduced DRAM refresh cycles. Material selection and tolerance analysis to ensure sufficient, but not overflowing, TIM volume on the DRAM can be a key enabling factor. Using the DRAM TIM can result in a reduction of approximately 30 degrees or more in DRAM junction temperature during testing. Peak junction temperatures can reach reliability limits (e.g., 110 degrees Celsius) if no TIM is used.

[0020] Continuing with reference to the thermal lid 130, a thicker Cu lid (e.g., pedestal overhang) on ​​top of the SoC 101 can provide lower thermal impedance and a lower Tjmax for critical IP. The intentionally designed depth of the lid cavity 135 and overhang of the pedestal 131 can optimize thermal benefit by minimizing thermal interface material (TIM) bondline thickness or compensate for TIM delamination at the SoC die edge (a commonly observed degradation after reliability stress). The selection of a TIM for the SoC 101 can be modeled and characterized to balance thermal benefit with mechanical stress from chip-package interactions.

[0021] Referring to the TIM, a microfilm insulation such as Ajinomoto Build-up Film (ABF) based build-up substrate may be selected. The bill of material (BOM), stackup, or area may be selected based on, among other things, high speed serializer / deserializer (SerDes) signal loss requirements, DDR and high speed SerDes signal and power fan-out requirements and core IP power delivery requirements, or ball grid array requirements for ball count / pin map and ball pitch.

[0022] 5A shows a perspective view of an exemplary test board apparatus 140 (e.g., a liquid-cooled cold plate) that may be associated with an MCM Thermo-Mechanical Test Vehicle (TMTV). FIG. 5B shows a perspective view of the test board apparatus 140 in an open state. In some instances, to match MCM 100 to automotive-grade ADAS components, a combined thermal and mechanical daisy-chain test vehicle, i.e., Thermo-Mechanical Test Vehicle (TMTV), may be used to mimic the thermal, mechanical, and reliability aspects of a fully functional MCM on an ADAS system board with a complete thermal / mechanical enclosure, as further disclosed herein.

[0023] FIG. 5A is a perspective view of test substrate apparatus 140 showing a top surface of a substrate having mounting areas 141 and 142, connectors 144 (e.g., power or signal connectors) disposed along a first edge, thermal management features, and thermal monitoring elements integrated into the substrate surface. FIG. 5B is an exploded perspective view of test substrate apparatus 140 showing multiple integrated components. Mounting areas 141 and 142 are configured to receive semiconductor components. Connectors 144 may include multiple pins configured for power delivery. The thermal management features may include fluid channels 146 configured for coolant circulation. Thermal monitoring elements 147 may be positioned proximate mounting areas 141 or 142, and may be configured to measure temperature distribution across the mounting areas. Test substrate apparatus 140 may be configured to evaluate thermal performance parameters, which may include junction temperature, thermal resistance, or power delivery characteristics, of multi-chip semiconductor packages mounted thereon.

[0024] As disclosed herein, the thermal design and characteristics for the TMTV 140 may affect the die, package, PCB, liquid-cooled cold plate, external power supply, or data acquisition system. With reference to the die, heaters and sensors may be designed to be embedded in a two-layer metal daisy chain silicon. The placement of heaters and sensors may be based on the SoC IP power consumption and heat map.

[0025] Package substrate and PCB design features can be specified to provide a low thermal resistance path, while PCB edge power and sense pin connectors can be selected to meet the requirements.

[0026] A liquid cooling based cold plate can be designed for the TMTV 140 so that the SoC and DRAM thermals can be characterized in terms of liquid coolant flow rate and temperature as specified by automotive user conditions.

[0027] Other thermal characterization components can be designed and specified, such as cooling devices, flow meters, pressure transducers, etc. A thermal characterization plan can be developed to characterize the SoC junction temperature in different user conditions, such as full mission mode, process mode, or gear guard security mode, among other modes that may be for on-road or off-road operation.

[0028] MCM technology developments can leverage the mechanical daisy chain feature in the TMTV 140, among other features, to evaluate the connectivity and reliability from the die to the substrate to the PCB. The daisy chain design can mimic the functional path while enabling high-resolution test capability across multiple package interfaces, as shown in Figures 6-9.

[0029] Referring to Figure 6, Table 2 provides an example TMTV design feature summary matrix that maps various test structures throughout the package. This example may include bump daisy chains (60 balls total) distributed throughout the periphery and core regions, multiple stacked via configurations, monitoring points, die crack sensors, and dedicated DDR connection test structures. Figure 6 shows an example schematic of daisy chain connections at the ball grid array level. The example layout diagram shows test areas arranged in a grid pattern, with designated HSIO (high speed input / output) areas indicated.

[0030] [Table 2]

[0031] FIG. 7 illustrates an exemplary die crack sensor implementation, showing a daisy-chain configuration between metal layers Mr1 and Mr2. In one example, the sensor design incorporates precise dimensional control, including a minimum line width of approximately 0.45 μm, a via diameter of approximately 0.41 μm, and a seal ring spacing of approximately 0.225 μm. This configuration, combined with post-dicing optical inspection, can enable monitoring of potential die crack formation during reliability testing.

[0032] 8 shows an exemplary capacitor test structure layout and verification method. The design may include designated test areas with specific connectivity and inspection criteria, which may allow evaluation of capacitor function, shorts, or overall capacitance characteristics across the package.

[0033] Figure 9 shows an exemplary die corner stress sensor design via flip-chip bumps and bottom stacked vias in the flip-chip substrate. Figure 9 presents a corner bump and stacked via implementation strategy, featuring various configurations of stacked vias between different layer combinations (L1-L4, L1-L3, L2-L5, L2-L4) at each corner of the processor die. This design may enable monitoring of mechanical stress effects and electrical connectivity in what may be considered critical package locations.

[0034] Daisy chains were tested based on their resistance targets and acceptable resistance shift ranges during the MCM substrate fabrication and die assembly process to report time-zero yield loss, as well as component and board-level reliability stress dropouts categorized by daisy chain coverage. Failed or marginally passing daisy chain structures were then analyzed by electrical and physical failure analysis techniques to find root causes and solution fixes, and these learnings were applied to fully functional chip packaging design and BOM selection.

[0035] As shown in Figure 5B, multiple MCM footprints are designed into a product-mimicking ADAS board, and the board stackup and BOM are according to product requirements. In addition, two MCM components, edge connectors, and signal channels are arranged for daisy-chain resistance testing during in-situ and ex-situ stress application of system-level reliability. Stress conditions can be configured for specified system requirements, and this TMTV140 setup is capable of performing full-scale thermal characterization and reliability testing, including power temperature cycling, shock, vibration, temperature cycling, or temperature humidity, among others.

[0036] The system enclosure may include a liquid-cooled cold plate. The rigidity of the backside metal base may be designed to allow for a force-controlled cold plate fastening mechanism, which may be important to ensure a minimum TIM2 thickness (thermal interface between the cold plate and the MCM) and therefore a low thermal impedance path from a fully functional MCM to the external cooling system; otherwise, the SoC Tjmax penalty is estimated to be up to 10°C.

[0037] The methods, systems, or apparatuses disclosed herein may be incorporated into electric vehicles or other devices. A multi-chip module (MCM) and a thermomechanical test vehicle (TMTV) are disclosed herein. The MCM may include dynamic random access memory (DRAM) and a system-on-chip (SoC), where the DRAM and SoC are integrated into a single ball grid array component for various applications. The DRAM may be arranged symmetrically around the SoC, with some implementations resembling a butterfly floor plan. When the DRAM is arranged approximately symmetrically around the SoC (or radially distributed), it may create a butterfly floor plan or similar. The MCM may further include a thermal lid, which may be constructed of nickel and copper with a pedestal design. Applications for the MCM may include integration into vehicles (e.g., electric vehicles) or use in autonomous driving systems. The TMTV may include a thermal and mechanical daisy-chain test vehicle that simulates the thermal, mechanical, and reliability aspects of an MCM on an advanced driver assistance system (ADAS) board with a thermal or mechanical enclosure. Additionally, the TMTV may include a die, a package substrate, a liquid-cooled cold plate, or a data acquisition system. Other TMTV components may include a cooling device, a flow meter, or a pressure transducer.

[0038] A testing apparatus and associated features are disclosed herein. The testing apparatus may include a substrate having a first mounting area and a second mounting area configured to receive a semiconductor component, a plurality of connectors positioned along a first edge of the substrate, the connectors may include a plurality of pins configured for power or signal delivery, a plurality of fluid channels integrated into the substrate, the fluid channels may be configured for coolant circulation, a plurality of thermal monitoring elements disposed proximate the first and second mounting areas, the thermal monitoring elements may be configured to measure temperature distribution, or a plurality of alignment features configured to secure a thermal solution to the substrate while maintaining a predetermined contact pressure with the semiconductor component. The thermal monitoring elements may include a temperature sensor configured to measure a junction temperature of the semiconductor component and may be configured to measure thermal resistance between the semiconductor component and the thermal solution. The plurality of connectors may include a first connector configured for power delivery or a second connector configured for signal transmission. The plurality of fluid channels may include an inlet port configured to receive a coolant, an outlet port configured to exhaust the coolant, or a plurality of fluid passages connecting the inlet port to the outlet port. There may be a thermal interface layer disposed between the mounting area and the thermal solution, and the thermal interface layer may be configured to provide thermal coupling between the semiconductor component and the thermal solution. All combinations (including removal or addition of elements) in this and the paragraphs above are contemplated consistent with other portions of the detailed description.

[0039] Reference to an element in the singular is not intended to mean one and only one, but rather one or more, unless otherwise specified. For example, "a" module may refer to one or more modules. The use of an element preceded by "a," "an," "the," or "said" does not, without further constraints, exclude the presence of more identical elements.

[0040] Headings and sub-headings, if any, are used for convenience only and are not intended to limit the invention. The word exemplary is used to mean serving as an example or illustration. When terms such as include and have are used, such terms are intended to be inclusive in the same manner as the term "comprise" is interpreted when employed as a transitional term in the claims. Relative terms such as "first" and "second" may be used to distinguish one entity or act from another and do not necessarily require or imply any actual relationship or order between such entities or acts.

[0041] Phrases such as one aspect, aspect, another aspect, some aspects, one or more aspects, one embodiment, an embodiment, another embodiment, some embodiments, one or more embodiments, one embodiment, embodiment, another embodiment, some embodiments, one or more embodiments, one configuration, configuration, another configuration, some configurations, one or more configurations, the subject technology, the disclosure, the present disclosure, other variations thereof, and the like are used for convenience and do not imply that the disclosure associated with such phrases is essential to the subject technology or that such disclosure applies to all configurations of the subject technology. The disclosure associated with such phrases may apply to all configurations or to one or more configurations. The disclosure associated with such phrases may provide one or more examples. Phrases such as one aspect or some aspects may refer to one or more aspects, and vice versa, and this applies equally to the other aforementioned phrases.

[0042] The phrase "at least one of," preceding a list of items, together with the term "and" or "or" separating any of the items, modifies the list as a whole, not each member of the list. The phrase "at least one of," does not require the selection of at least one item; rather, the phrase allows for the inclusion of at least one of any one of the items, and / or at least one of any combination of the items, and / or at least one of each of the items. By way of example, each of "at least one of A, B, and C" or "at least one of A, B, or C" refers to A only, B only, or C only, any combination of A, B, and C, and / or at least one of each of A, B, and C.

[0043] It is understood that the specific order or hierarchy of steps, operations, or processes disclosed is an illustration of example approaches. Unless otherwise specified, it is understood that the specific order or hierarchy of steps, operations, or processes may be performed in different order. Some of the steps, operations, or processes may be performed simultaneously. The accompanying method claims present the various steps, operations, or process elements, if any, in an example order and are not meant to be limited to the specific order or hierarchy presented. They may be performed serially, linearly, in parallel, or in different orders. It is understood that the described instructions, operations, or systems may generally be integrated together in a single software / hardware product or packaged in multiple software / hardware products.

[0044] In one aspect, the term coupled or the like may refer to being directly coupled. In another aspect, the term coupled or the like may refer to being indirectly coupled.

[0045] Terms such as top, bottom, front, back, side, horizontal, vertical, etc. refer to an arbitrary coordinate system, rather than the usual gravitational coordinate system, and thus such terms may extend upward, downward, diagonally, or horizontally in the gravitational coordinate system.

[0046] This disclosure is provided to enable those skilled in the art to practice the various aspects described herein. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring the concepts of the subject technology. This disclosure provides various examples of the subject technology, and the subject technology is not limited to these examples. Various modifications to these aspects will be readily apparent to those skilled in the art, and the principles described herein may be applied to other aspects.

[0047] All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known, or that later become known, to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Furthermore, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is expressly recited in the claims. No element of a claim is to be construed under the provisions of 35 U.S.C. § 112(f) unless the element is expressly recited using the phrase "means for," or, in the case of a method claim, the element is recited using the phrase "step for."

[0048] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein can be implemented as hardware, electronic hardware, computer software, or a combination thereof. To illustrate this interchangeability of hardware and software, the various illustrative blocks, modules, elements, components, methods, and algorithms have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints on the overall system. Those skilled in the art may implement the described functionality in a variety of ways for each particular application. The various components and blocks may all be arranged differently (e.g., placed in a different order or divided differently) without departing from the scope of the subject technology.

[0049] The title, background art, brief description of the drawings, abstract, and drawings are incorporated into this disclosure and are provided as illustrative examples of the disclosure, not as a limiting description. They are submitted with the understanding that they will not be used to limit the scope or meaning of the claims. Additionally, it will be appreciated that the detailed description provides illustrative examples, and that in various embodiments, various features are grouped together for purposes of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed subject matter requires more features than are expressly recited in each claim. Rather, as the claims reflect, inventive subject matter lies in less than all features of a single disclosed structure or operation. The claims are incorporated into the detailed description, with each claim standing on its own as separately claimed subject matter.

[0050] The claims are not intended to be limited to the embodiments described herein, but are to be accorded the full scope consistent with the language of the claims and encompass all legal equivalents. Nevertheless, none of the claims are intended, and should not be interpreted, to encompass subject matter that lacks the requirements of applicable patent law.

Claims

1. A multi-chip module (MCM), comprising: Dynamic random access memory (DRAM); and a system on a chip (SoC), wherein the DRAM and the SoC are integrated as one unified ball grid array component for an application.

2. The MCM of claim 1 , wherein the DRAMs are arranged approximately symmetrically around the SoC.

3. 2. The MCM of claim 1, wherein said DRAMs are positioned to create a butterfly floorplan.

4. The MCM of claim 1 further comprising a thermal lid.

5. The MCM of claim 4 , wherein said thermal lid comprises nickel and copper, said thermal lid being of a pedestal design.

6. The MCM of claim 4 , wherein the thermal lid comprises nickel-plated copper.

7. The MCM of claim 4 , wherein the thermal lid further comprises a first material and a second material, the first material being used to provide a threshold thermal conductivity.

8. The MCM of claim 7 , wherein the second material is used to provide a threshold level of corrosion protection.

9. The MCM of claim 7 , wherein the first material comprises copper tungsten.

10. The MCM of claim 7 , wherein the first material comprises copper molybdenum.

11. The MCM of claim 4 further comprising a thermal interface material (TIM), said TIM disposed over one or more of said DRAMs.

12. The MCM of claim 11 , wherein the TIM comprises a specialty polymer film.

13. The MCM of claim 4 wherein the thermal lid includes a cavity.

14. The MCM of claim 4 , wherein the thermal lid comprises a pedestal above the SoC.

15. The MCM of claim 4 , wherein said thermal lid comprises a pedestal over one or more of said DRAMs.

16. The MCM of claim 1 , wherein the MCM is incorporated into an electric vehicle.

17. The MCM of claim 1 , wherein the application is an autonomous driving application.

18. A thermo-mechanical test vehicle (TMTV), comprising: Dai and A package substrate; and a liquid-cooled cold plate.

19. A cooling device; 20. The TMTV of claim 18, further comprising a flow meter.

20. 20. The TMTV of claim 19, further comprising a pressure transducer.

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