Semiconductor device

Abstract

To reduce the occurrence of a damage in an insulating circuit board.SOLUTION: A semiconductor device includes: an insulating circuit board including an insulating plate and a metal plate formed at a lower surface of the insulating plate, and having a rectangular shape in a plan view; and a heat release base 3 including an upper surface 31 having a rectangular shape in the plan view and including arrangement regions 31a and 31b where a pair of short sides (short side surfaces 30e, 30g) facing each other in the plan view and the insulating circuit board are disposed through a solder, and a plurality of protrusions formed in each of regions corresponding to four corners of the insulating circuit board in the arrangement regions 31a and 31b of the upper surface 31. The protrusion is an inner protrusion 32a that is close to a central line C parallel to the pair of short sides (short side surfaces 30e, 30g) on the upper surface 31 and far from the pair of short sides, or an outer protrusion 32b that is far from the central line C and close to the short sides (short side surfaces 30e, 30g) and is formed by a plurality of sub-protrusions.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] The semiconductor device includes a metal base plate (heat dissipation base) and a circuit board mounted on the metal base plate via solder. The underside of the circuit board is supported by protrusions formed on the metal base plate (see, for example, Patent Documents 1 and 2). In the semiconductor device, a spherical groove is formed in the metal base plate, and a joining component is joined to the metal base plate with brazing material (see, for example, Patent Document 3). In the semiconductor device, an irregular pattern is formed on the top surface of the metal base plate, and a substrate is mounted on the metal base plate via solder (see, for example, Patent Document 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 102253 [Patent Document 2] International Publication No. 2016 / 009741 [Patent Document 3] Japanese Patent Application Publication No. 5-166856 [Patent Document 4] US Patent Application Publication No. 2014 / 0138839 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above points, and has an object to provide a semiconductor device that can reduce the occurrence of damage to an insulating circuit board. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising: a heat dissipation base including: a plurality of insulated circuit boards each having a rectangular shape in a planar view, the heat dissipation base including an insulating plate and a metal plate formed on the underside of the insulating plate; an upper surface having a rectangular shape in a planar view, a pair of first sides opposing each other in a planar view, and a plurality of placement areas in which the plurality of insulated circuit boards are each placed via solder; and protrusions formed in areas of the plurality of placement areas on the upper surface corresponding to the four corners of the plurality of insulated circuit boards, wherein the protrusions are inner protrusions that are close to a center line on the upper surface that is parallel to the pair of first sides and far from the pair of first sides, or outer protrusions that are far from the center line and close to one of the first sides and are composed of a plurality of sub-protrusions.

[0006] According to another aspect of the present invention, there is provided a semiconductor device comprising: a plurality of insulated circuit boards, each having a rectangular shape in a plan view, including an insulating plate and a metal plate formed on a lower surface of the insulating plate; an upper surface, also having a rectangular shape in a plan view and a pair of long sides and a pair of short sides and a plurality of placement areas in which the plurality of insulated circuit boards are respectively placed via solder; and protrusions formed in areas of the plurality of placement areas on the upper surface corresponding to four corners of the plurality of insulated circuit boards, wherein the protrusions are inner protrusions that are close to a center line on the upper surface that is parallel to the pair of short sides and far from the pair of long sides, or outer protrusions that face one of the short sides, are far from the center line and close to a first side, and extend along the pair of long sides. [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to reduce the occurrence of damage to an insulating circuit board and prevent a decrease in reliability. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment; [Figure 2] 1 is a cross-sectional view (part 1) of a semiconductor device according to a first embodiment; [Figure 3] FIG. 2 is a cross-sectional view (part 2) of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment. [Figure 5] 2 is a plan view of a heat dissipation base included in the semiconductor device of the first embodiment. FIG. [Figure 6] 3 is an enlarged cross-sectional view of an outer protrusion of a heat dissipation base included in the semiconductor device of the first embodiment. FIG. [Figure 7] 3 is an enlarged plan view of an outer protrusion of a heat dissipation base included in the semiconductor device of the first embodiment. FIG. [Figure 8] 10 is an enlarged cross-sectional view of a protrusion of a heat dissipation base included in a semiconductor device of a reference example. [Figure 9] 10 is an enlarged plan view of a protrusion of a heat dissipation base included in the semiconductor device of the reference example. FIG. [Figure 10] 10 is a plan view of another heat dissipation base included in the semiconductor device of the first embodiment. FIG. [Figure 11] 10 is an enlarged plan view of a protrusion of a heat dissipation base included in the semiconductor device of the first embodiment (variation 1-1). FIG. [Figure 12] FIG. 10 is a plan view of a heat dissipation base included in the semiconductor device of the first embodiment (modification 1-2). [Figure 13] FIG. 10 is a plan view of a heat dissipation base included in the semiconductor device of the first embodiment (variation 1-3). [Figure 14] FIG. 10 is a plan view of a heat dissipation base included in the semiconductor device of the first embodiment (variation 1-4). [Figure 15] FIG. 10 is a plan view of another heat dissipation base included in the semiconductor device of the first embodiment (variation 1-4). [Figure 16] FIG. 10 is a plan view of a heat dissipation base included in a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 18] FIG. 10 is an enlarged cross-sectional view of a protrusion of a heat dissipation base included in the semiconductor device of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the XY plane facing upward (+Z direction) in the semiconductor device 1, 1a shown in the drawings. Similarly, "top" refers to the upward direction (+Z direction) in the semiconductor device 1, 1a shown in the drawings. The terms "back surface" and "bottom surface" refer to the XY plane facing downward (-Z direction) in the semiconductor device 1, 1a shown in the drawings. Similarly, "bottom" refers to the downward direction (-Z direction) in the semiconductor device 1 shown in the drawings. As necessary, the same directions as above will be used in all drawings. The terms "higher" and "upper" refer to the upper position (+Z direction) in the semiconductor device 1, 1a shown in the drawings. Similarly, the terms "lower" and "lower" refer to the lower position (-Z direction) in the semiconductor device 1 shown in the drawings. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. In the following explanation, "main component" refers to a component containing 80 vol% or more. "Almost the same" means that the difference is within a range of ±10%. "Perpendicular," "orthogonal," and "parallel" mean that the difference is within a range of ±10°.

[0010] [First embodiment] A semiconductor device according to a first embodiment will be described with reference to Fig. 1 to Fig. 5. Fig. 1 is a plan view of the semiconductor device according to the first embodiment, and Figs. 2 and 3 are cross-sectional views of the semiconductor device according to the first embodiment. Fig. 4 is a plan view of a semiconductor unit included in the semiconductor device according to the first embodiment, and Fig. 5 is a plan view of a heat dissipation base included in the semiconductor device according to the first embodiment.

[0011] Note that the sealing member of the semiconductor device is not shown in Figures 1 to 3. Figures 2 and 3 are cross-sectional views taken along dashed dotted lines X1-X1 and X2-X2 in Figure 1. Figures 4 and 5 show the semiconductor units 10a and 10b and the heat dissipation base 3 in plan view, respectively.

[0012] 1 to 3, the semiconductor device 1 includes semiconductor units 10a and 10b and a heat dissipation base 3 on which the semiconductor units 10a and 10b are arranged. The semiconductor device 1 further includes a case 2 that is arranged on the heat dissipation base 3 and that houses the semiconductor units 10a and 10b, and a sealing member (not shown) that seals the inside of the case 2.

[0013] The semiconductor units 10a and 10b include insulating circuit boards 11a and 11b and semiconductor chips 18a, 19a, 18b, and 19b. The insulating circuit boards 11a and 11b include insulating plates 12a and 12b, metal plates 13a and 13b, and conductive circuit patterns 14a, 15a, 16a, 14b, 15b, and 16b. The insulating plates 12a and 12b and the metal plates 13a and 13b are rectangular in plan view. The insulating plates 12a and 12b and the metal plates 13a and 13b may have rounded or C-chamfered corners. The size of the metal plates 13a and 13b is smaller than the size of the insulating plates 12a and 12b in plan view and is formed inside the insulating plates 12a and 12b.

[0014] The insulating plates 12a and 12b may be ceramic substrates. The ceramic substrate is made of ceramics with good thermal conductivity. Ceramics are made of materials mainly composed of, for example, aluminum oxide, aluminum nitride, or silicon nitride. The insulating circuit boards 11a and 11b including the insulating plates 12a and 12b having such a configuration may be, for example, DCB (Direct Copper Bonding) substrates or AMB (Active Metal Brazed) substrates. The thickness of such insulating plates 12a and 12b depends on the rated voltage of the semiconductor device 1. That is, the higher the rated voltage of the semiconductor device 1, the thicker the insulating plates 12a and 12b must be. On the other hand, the lower the rated voltage of the semiconductor device 1, the thinner the insulating plates 12a and 12b must be to reduce their thermal resistance.

[0015] The insulating plates 12a and 12b may be made of resin instead of a ceramic substrate. The resin may be a material with low thermal resistance and high insulation properties. Examples of such resins include thermosetting resins. The thermosetting resin may further contain a filler. The thermal resistance of the insulating plates 12a and 12b can be further reduced by controlling the material and content of the filler. Furthermore, depending on the filler, the linear expansion coefficient of the insulating plates 12a and 12b can be made approximately equal to the linear expansion coefficients of the metal plates 13a and 13b and the conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b (described later). By minimizing the difference in linear expansion coefficients, the insulating circuit boards 11a and 11b can reduce warping due to the difference in linear expansion coefficients even when thermal changes occur. In this case, the difference in linear expansion coefficients may be within an error range of 10% to 50%.

[0016] Examples of such thermosetting resins include at least one of epoxy resin, cyanate resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenol resin, melamine resin, silicone resin, maleimide resin, acrylic resin, and polyamide resin. The filler is composed of at least one of an oxide and a nitride. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, the filler may be hexagonal boron nitride.

[0017] The metal plates 13a and 13b are made of a metal with excellent thermal conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. In this example, copper is included. Furthermore, to improve corrosion resistance, the surfaces of the metal plates 13a and 13b may be plated. In this case, the plating material includes nickel. Examples of such plating materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0018] The metal plates 13a and 13b are rectangular in plan view. The corners may be rounded or chamfered. The metal plates 13a and 13b are smaller than the insulating plates 12a and 12b and are formed on the entire lower surfaces of the insulating plates 12a and 12b, excluding the edges. The metal plates 13a and 13b are primarily composed of a metal with excellent thermal conductivity. Examples of the metal include copper, aluminum, and alloys containing at least one of these. To improve the corrosion resistance of the metal plates 13a and 13b, the surfaces of the metal plates 13a and 13b may be plated. Examples of plating materials used in this process include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0019] The conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b for the insulating plates 12a and 12b are obtained by forming a metal plate on the upper surface of the insulating plates 12a and 12b and then etching or other processes on the metal plate. Alternatively, conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b that have been cut out from a metal plate in advance may be bonded to the upper surfaces of insulating plates 12a and 12b.

[0020] The conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b are formed on the entire upper surfaces of the insulating plates 12a and 12b, excluding the edges. Preferably, in a plan view, the ends of the conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b facing the outer periphery of the insulating plates 12a and 12b overlap the outer periphery of the metal plates 13a and 13b. This maintains a stress balance between the insulating circuit boards 11a and 11b and the metal plates 13a and 13b on the lower surfaces of the insulating plates 12a and 12b. This further suppresses damage to the insulating plates 12a and 12b, such as excessive warping and cracking.

[0021] The conductive circuit pattern 14a is connected to an internal terminal 25a, which is a positive terminal described below, and is formed in the center of the insulating plate 12a as shown in Fig. 4. Three semiconductor chips 18a and three semiconductor chips 19a are bonded to the conductive circuit pattern 14a via bonding members (not shown).

[0022] The conductive circuit pattern 15a is connected to an internal terminal 25b, which is a negative electrode terminal described later, and is U-shaped in a plan view. The conductive circuit pattern 15a is formed on the insulating plate 12a so as to surround the -Y direction side portion of the conductive circuit pattern 14a.

[0023] The conductive circuit pattern 16a is L-shaped in plan view and is formed on the insulating plate 12a at the corners of the conductive circuit pattern 14a in the +Y and -X directions. The conductive circuit pattern 16a is connected to the main electrodes on the upper surfaces of the semiconductor chips 18a and 19a by main current wires 52a, 52c, and 52e.

[0024] The conductive circuit pattern 17a is I-shaped in plan view and is formed on the insulating plate 12a on the +Y side of the conductive circuit pattern 16a and parallel to the ±X directions. The conductive circuit pattern 17a is electrically connected to control electrodes on the top surface of the semiconductor chip 18a by control wires 52g to 52i.

[0025] The conductive circuit pattern 14b is connected to an internal terminal 25c, which is an output terminal described later, and is formed over a range of two-thirds of the length from the edge of the insulating plate 12b in the +Y direction, as shown in Fig. 4. Three semiconductor chips 18b and three semiconductor chips 19b are bonded to the conductive circuit pattern 14b via bonding members (not shown). The end of the conductive circuit pattern 14b in the +X direction is connected to the conductive circuit pattern 16a by a main current wire 53a.

[0026] The conductive circuit pattern 15b has a crank shape in plan view and is formed on the insulating plate 12b along the -Y direction side of the conductive circuit pattern 14b. The conductive circuit pattern 15b is connected to the main electrodes on the upper surfaces of the semiconductor chips 18b and 19b by main current wires 54a, 54c, and 54e. The conductive circuit pattern 15b is also connected to the conductive circuit pattern 15a by a main current wire 53b.

[0027] The conductive circuit pattern 16b is I-shaped in plan view and is formed on the insulating plate 12b on the -Y direction side of the conductive circuit pattern 15b and parallel to the ±X directions. The conductive circuit pattern 16b is electrically connected to control electrodes on the upper surface of the semiconductor chip 18b by control wires 54g to 54i.

[0028] The conductive circuit patterns 14a, 15a, 16a, 17a, 14b, 15b, and 16b included in the semiconductor device 1 are merely examples. The number, shape, and size of the conductive circuit patterns may be selected appropriately as needed.

[0029] The semiconductor chips 18a, 18b, 19a, and 19b may be primarily made of silicon, or may be primarily made of a wide bandgap semiconductor, such as silicon carbide or gallium nitride.

[0030] The semiconductor chips 18a and 18b include switching elements. The switching elements are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). If the semiconductor chips 18a and 18b are IGBTs, they have a collector electrode on their bottom surfaces as a main electrode (input side), and a gate electrode and an emitter electrode on their top surfaces as a control electrode and a main electrode (output side). If the semiconductor chips 18a and 18b are power MOSFETs, they have a drain electrode on their bottom surfaces as a main electrode (input side), and a gate electrode and a source electrode on their top surfaces as a control electrode and a main electrode (output side), respectively.

[0031] The semiconductor chips 19a and 19b include diode elements. The diode elements may be, for example, SBD (Schottky Barrier Diode) or PiN (P-intrinsic-N) diodes used as FWD (Free Wheeling Diode). Each of the semiconductor chips 19a and 19b has a cathode electrode as a main electrode (output side) on the bottom surface and an anode electrode as a main electrode (input side) on the top surface.

[0032] In this embodiment, the main electrodes on the top surfaces of semiconductor chips 18a and 19a are electrically connected by main current wires 52b, 52d, and 52f. Similarly, the main electrodes on the top surfaces of semiconductor chips 18b and 19b are electrically connected by main current wires 54b, 54d, and 54f.

[0033] Furthermore, the semiconductor chips 18a and 18b may be RC (Reverse-Conducting)-IGBTs that combine the functions of an IGBT and an FWD, in which case the semiconductor chips 19a and 19b are omitted.

[0034] Alternatively, the switching elements of the semiconductor chips 18a and 18b may be power MOSFETs primarily made of silicon carbide. The body diode of a power MOSFET may function as an FWD. The semiconductor chips 18a and 18b each have, for example, a drain electrode on the bottom surface as a main electrode (input side), and a gate electrode and a source electrode on the top surface as a control electrode and a main electrode (output side). In this case, the semiconductor chips 19a and 19b are omitted.

[0035] The joining material for joining the semiconductor chips 18a, 19a, 18b, and 19b to the conductive circuit patterns 14a and 14b is, for example, solder. Lead-free solder is used. Lead-free solder mainly contains at least one of the following alloys: a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and a tin-silver-indium-bismuth alloy. The solder may also contain additives. Examples of additives include nickel, germanium, cobalt, antimony, and silicon. The addition of additives to the solder improves its wettability, gloss, and bonding strength, thereby improving reliability. Instead of solder, a metal sintered body may be used as the joining material. The material of the metal sintered body may be, for example, silver, copper, or an alloy containing at least one of these.

[0036] The heat dissipation base 3 includes a heat dissipation plate 30 and a plurality of protrusions 32 formed on the heat dissipation plate 30. As shown in FIG. 5 , the heat dissipation plate 30 includes a rectangular top surface 31 in a plan view and long side surfaces 30f, short side surfaces 30g, long side surfaces 30h, and short side surfaces 30e that surround the top surface 31 on all four sides. The long side surfaces 30f and 30h are parallel to each other. The short side surfaces 30g and 30e are parallel to each other. The long side surfaces 30f and 30h are perpendicular to the short side surfaces 30g and 30e. At the corner 30a, the long side surfaces 30h and the short side surfaces 30e are perpendicular to each other. At the corner 30b, the short side surfaces 30e and the long side surfaces 30f are perpendicular to each other. At the corner 30c, the long side surfaces 30f and the short side surfaces 30g are perpendicular to each other. At the corner 30d, the short side surfaces 30g and the long side surfaces 30h are perpendicular to each other. In plan view, the long side surfaces 30f, 30h and the short side surfaces 30g, 30e respectively correspond to a pair of long sides (second sides) and a pair of short sides (first sides) of the upper surface 31. Furthermore, the heat sink 30 has a center line C that is parallel to the pair of short sides (short side surfaces 30g, 30e) on the upper surface 31 and passes through the midpoints of the pair of long sides (long side surfaces 30f, 30h).

[0037] The upper surface 31 of the heat sink 30 includes arrangement regions 31a and 31b, respectively, in which the semiconductor units 10a and 10b are arranged with solder 40 (see FIG. 6) interposed therebetween. The arrangement region 31a includes corners 31a1 to 31a4. The arrangement region 31b includes corners 31b1 to 31b4. The arrangement regions 31a and 31b are included on the upper surface 31, with the center line C sandwiched between them. That is, the arrangement region 31a is included between the center line C and the short side (short side surface 30e) on the upper surface 31. The arrangement region 31b is included between the center line C and the short side (short side surface 30g) on ​​the upper surface 31. The solder 40 may be the same type as the solder used as the joining member described above.

[0038] Furthermore, fastening holes 34a to 34d are formed near the corners 30a to 30d (first corners) of the heat sink 30. The fastening holes 34a to 34d pass through the heat sink 30 near the corners 30a to 30d, respectively. The semiconductor device 1 can be placed at a predetermined installation location, and fastened to the predetermined installation location by screws inserted through the fastening holes 34a to 34d.

[0039] The heat sink 30 is mainly composed of a metal with excellent thermal conductivity. Examples of the metal include copper, aluminum, and an alloy containing at least one of these. To improve the corrosion resistance of the heat sink 30, the surface of the heat sink 30 may be plated. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.

[0040] The heat sink 30 may be warped downwardly convexly at the center line C. That is, the short sides 30e and 30g of the heat sink 30 may be positioned above (in the +Z direction) the center line C in a side view looking in the +Y direction (or the -Y direction).

[0041] The multiple protrusions 32 are formed in areas of the arrangement regions 31a, 31b on the upper surface 31 that correspond to the outer edges of the semiconductor units 10a, 10b (insulated circuit boards 11a, 11b). The arrangement regions 31a, 31b indicated by dashed lines in FIG. 5 correspond to the outlines of the insulating circuit boards 11a, 11b in a plan view. The multiple protrusions 32 are formed in the arrangement regions 31a, 31b on the upper surface 31 to correspond to the four corners of the semiconductor units 10a, 10b (insulated circuit boards 11a, 11b). Supporting the corners of the lower surfaces of the semiconductor units 10a, 10b by the multiple protrusions 32 maintains a gap between the lower surfaces of the semiconductor units 10a, 10b and the upper surface 31 of the heat sink 30, thereby maintaining a constant thickness of the bonding material therebetween.

[0042] The multiple protrusions 32 further include an inner protrusion 32a and an outer protrusion 32b. The inner protrusions 32a are the two of the multiple protrusions 32 that face the center line C, are close to the center line C, and are far from the pair of short sides (short side surfaces 30e, 30g). Such a pair of inner protrusions 32a may be a single protrusion having a columnar or frustum shape. The columnar shape may be a cylindrical or polygonal columnar shape. The frustum shape may be a polygonal frustum or a truncated cone shape. The longest width (or diameter in the case of a circle) of the upper surface of the inner protrusion 32a may be, for example, 1.2 mm or more and 1.7 mm or less. The upper surface of the inner protrusion 32a may be convex upward.

[0043] The outer protrusions 32b are two of the multiple protrusions 32 that face a pair of short sides (short side surfaces 30e, 30g) and are far from the center line C and close to the pair of short sides (short side surfaces 30e, 30g). Corners 31a1, 31a2, 31b3, and 31b4 (second corners) on the pair of short sides (short side surfaces 30e, 30g) of the arrangement regions 31a and 31b are located near the fastening holes 34a to 34d and face the fastening holes 34a to 34d, respectively. Accordingly, the outer protrusions 32b are also located near the fastening holes 34a to 34d and face the fastening holes 34a to 34d, respectively. Each pair of outer protrusions 32b is composed of multiple sub-protrusions. Note that FIG. 3 merely illustrates the outer protrusion 32b as a single protrusion so that it can be seen that the outer protrusion 32b is formed on the upper surface 31 of the heat sink 30. Details of the outer protrusions 32b will be described later.

[0044] The inner protrusion 32a and the outer protrusion 32b may be formed on the upper surface 31 of the heat sink 30 of the heat dissipation base 3, for example, by press working. For example, a groove 33 is formed around the outer protrusion 32b (plurality of sub-protrusions 32b1) described below by press working. The heights of the inner protrusion 32a and the outer protrusion 32b may be the same. Such inner protrusion 32a and outer protrusion 32b support the lower surfaces of the semiconductor units 10a, 10b (insulated circuit boards 11a, 11b) via solder 40. In addition, here, the outer protrusion 32b and the inner protrusion 32a have different configurations, as exemplified. The inner protrusion 32a may be formed of multiple sub-protrusions, similar to the outer protrusion 32b.

[0045] The case 2 includes a housing 20, external terminals 24a-24c, and internal terminals 25a-25c. The housing 20 integrally includes side walls 21a-21d and terminal placement sections 22a-22d that surround a storage area 23 on all four sides. The side walls 21a and 21c correspond to the short sides, and the side walls 21b and 21d correspond to the long sides. The storage area 23, which is surrounded by the side walls 21a-21d, has a rectangular shape in plan view. The lower surfaces of the side walls 21a-21d are bonded to the outer edge of the upper surface 31 of the heat dissipation base 3 (heat dissipation plate 30) with an adhesive (not shown).

[0046] Steps 22e and 22f are provided on the inner sides (storage area 23 side) of side walls 21a and 21c, respectively. Steps 22e and 22f are approximately parallel to the upper and lower surfaces of side walls 21a to 21d. Steps 22e and 22f are formed from side wall 21b to side wall 21d. Steps 22e and 22f may be located between the lower and upper surfaces of side walls 21a and 21c and protrude toward storage area 23.

[0047] Terminal placement sections 22a and 22b are integrally provided on the upper surface of side wall 21a and extend outward (in the +X direction) from side wall 21a. Terminal placement sections 22c and 22d are integrally provided on the upper surface of side wall 21c and extend outward (in the -X direction) from side wall 21c.

[0048] The external terminal 24a is a positive terminal and is exposed from the upper surface of the terminal placement portion 22a. The internal terminal 25a is a positive terminal that faces the conductive circuit pattern 14a in a plan view, is exposed from the upper surface of the step 22e, and is electrically connected to the conductive circuit pattern 14a by a main current wire 51a. The external terminal 24a and the internal terminal 25a are integrally connected within the side wall 21a.

[0049] The external terminal 24b is a negative terminal and is exposed from the upper surface of the terminal placement portion 22b. The internal terminal 25b is a negative terminal and faces the conductive circuit pattern 15a in a plan view. It is exposed from the upper surface of the step 22e and is electrically connected to the conductive circuit pattern 15a by a main current wire 51b. The external terminal 24b and the internal terminal 25b are integrally connected within the side wall 21a.

[0050] The external terminal 24c is an output terminal and is exposed from the upper surfaces of the terminal arrangement portions 22c and 22d. The internal terminal 25c is an output terminal that faces the conductive circuit pattern 14b in a plan view, is exposed from the upper surface of the step 22f, and is electrically connected to the conductive circuit pattern 14b by a main current wire 55. The external terminal 24c and the internal terminal 25c are integrally connected within the side wall 21c.

[0051] The case 2 is configured by integrally molding the housing 20 including the external terminals 24a-24c and the internal terminals 25a-25c. For example, the case 2 may be configured by injection molding using a thermoplastic resin. Examples of such resins include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, and acrylonitrile butadiene styrene (ABS) resin.

[0052] The storage area 23 of the case 2 may be sealed with a sealing member (not shown). The sealing member may be a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenol resin, maleimide resin, and polyester resin. Epoxy resin is preferable. Furthermore, a filler may be added to the sealing member. The filler may be an insulating ceramic having high thermal conductivity.

[0053] Next, the outer protrusions 32b of the multiple protrusions 32 will be described in detail with reference to FIGS. 6 and 7. FIG. 6 is an enlarged cross-sectional view of the outer protrusions of the heat dissipation base included in the semiconductor device of the first embodiment. FIG. 7 is an enlarged plan view of the outer protrusions of the heat dissipation base included in the semiconductor device of the first embodiment. Note that FIG. 6 is an enlarged view of the outer protrusions 32b and their surroundings included in the protrusions 32 surrounded by the dashed line in FIG. 3. FIG. 7 shows a plan view of the upper surface 31 of the heat dissipation base 3 (heat dissipation plate 30) including the outer protrusions 32b of FIG. 6.

[0054] The outer protrusion 32b is composed of a plurality of sub-protrusions 32b1. In the case of Figures 6 and 7, the outer protrusion 32b is composed of four sub-protrusions 32b1. The number of sub-protrusions 32b1 is not limited to four, and may be two, three, five or more. The sub-protrusions 32b1 may be columnar or frustum-shaped. The columnar shape may be a cylindrical or polygonal prism shape. The frustum shape may be a polygonal frustum shape or a circular cone shape.

[0055] The longest width (diameter in the case of Figures 6 and 7) of the upper surface of the sub-protrusion 32b1 may be, for example, 0.1 mm or more and 1.0 mm or less. The upper surface of the sub-protrusion 32b1 may also be convex upward. The spacing between the multiple sub-protrusions 32b1 in a planar view may be, for example, 0.3 mm or more and 1.1 mm or less. The multiple sub-protrusions 32b1 included in the outer protrusion 32b may have different sizes and shapes in a planar view.

[0056] As described above, the inner protrusion 32a and the outer protrusion 32b support the underside of the semiconductor units 10a, 10b (insulated circuit boards 11a, 11b) via the solder 40. Therefore, the outer protrusion 32b supports the underside of the semiconductor units 10a, 10b (insulated circuit boards 11a, 11b) with the multiple sub-protrusions 32b1. In this case, the thickness of the solder 40 on the outer protrusion 32b may be much thinner than the thickness of the solder 40 on the inner protrusion 32a. Alternatively, the thickness of the solder 40 on the outer protrusion 32b may be substantially zero, and the outer protrusion 32b may be in direct contact with the underside of the insulating circuit boards 11a, 11b. FIG. 6 shows the case where the solder 40 is in direct contact. The thickness of the solder 40 will be described later.

[0057] Here, the outer protrusions included in a semiconductor device of a reference example in comparison with the semiconductor device 1 will be described with reference to FIGS. 8 and 9. FIG. 8 is an enlarged cross-sectional view of the protrusions of the heat dissipation base included in the semiconductor device of the reference example. FIG. 9 is an enlarged plan view of the protrusions of the heat dissipation base included in the semiconductor device of the reference example. Note that FIGS. 8 and 9 correspond to FIGS. 6 and 7. Furthermore, the multiple sub-protrusions 32b1 in FIGS. 6 and 7 are indicated by dashed lines with respect to the outer protrusions 32b in FIGS. 8 and 9.

[0058] The semiconductor device of the reference example has the same configuration as the semiconductor device 1 except for the outer protrusion 32b. The outer protrusion 32b of the semiconductor device of the reference example has the same configuration as the inner protrusion 32a.

[0059] As described above, the protrusions 32 are provided at the corners of the arrangement areas 31a and 31b of the heat dissipation base 3. That is, the inner protrusions 32a are provided at the corners of the arrangement areas 31a and 31b on the side of the center line C, and the outer protrusions 32b are provided at the corners of the arrangement areas 31a and 31b on the side of a pair of short sides (short side surfaces 30e and 30g).

[0060] Furthermore, warpage occurs in the heat dissipation base 3 (heat dissipation plate 30) due to heating and cooling during the manufacturing process of the semiconductor device. Here, the heat dissipation base 3 may have an upward convex warp (negative warp) in which the center line C is located above (in the +Z direction) the pair of short sides (short side surfaces 30e, 30g). In particular, since the long sides of the heat dissipation base 3 are sufficiently longer than the short sides, the negative warp in the longitudinal direction is sufficiently larger than the negative warp in the lateral direction, and negative warp in the longitudinal direction may actually occur. In anticipation of such negative warp, the heat dissipation base 3 is given a downward convex warp (positive warp) in the longitudinal direction so that the center line C is located below the pair of short sides (short side surfaces 30e, 30g).

[0061] In manufacturing the semiconductor device of the reference example, first, insulating circuit boards 11a and 11b are placed, via solder plates, in placement areas 31a and 31b of warped heat dissipation base 3. Then, semiconductor chips 18a, 18b, 19a, and 19b are placed, via solder plates, on insulating circuit boards 11a and 11b, respectively.

[0062] When the solder plate is heated and melted, the molten solder flows along the upper surface 31 of the warped heat dissipation base 3 toward the center line C and accumulates near the center line C. Thereafter, when the molten solder is cooled and the semiconductor units 10a, 10b are joined to the heat dissipation base 3, the thickness of the solder 40 between the semiconductor units 10a, 10b and the heat dissipation base 3 becomes thicker on the side of the center line C than on the side of the pair of short sides (short side surfaces 30e, 30g).

[0063] In the semiconductor device of the reference example, the inner protrusion 32a on the center line C side supports the underside of the semiconductor units 10a and 10b (insulated circuit boards 11a and 11b) via solder 40. On the other hand, the outer protrusions 32b on the pair of short sides (short side surfaces 30e and 30g) directly support the underside of the semiconductor units 10a and 10b (insulated circuit boards 11a and 11b). If the undersides of the insulating circuit boards 11a and 11b of the semiconductor units 10a and 10b are in direct contact with the outer protrusion 32b, for example, stress may be generated in the semiconductor device of the reference example or the semiconductor device may be subjected to an external impact, which may damage the insulating plate 12a of the insulating circuit board 11a, starting from the outer protrusion 32b, as shown in FIG. 8. For example, when fastening holes 34a to 34d of the semiconductor device with screws, inward stress may be generated starting from the fastening holes 34a to 34d. In particular, the stress is greater near the fastening holes 34a to 34d. Therefore, stress is generated in the insulating circuit boards 11a and 11b starting from the outer protrusions 32b of the protrusions 32.

[0064] If insulating plate 12a is damaged in this way, the insulation and heat dissipation properties of insulating circuit board 11a will be reduced. Although insulating circuit board 11a is shown in Figure 8, insulating plate 12b of insulating circuit board 11b will also be damaged in the same way. This will reduce the reliability of the semiconductor device of the reference example that includes such insulating circuit boards 11a and 11b.

[0065] Meanwhile, the semiconductor device 1 includes insulating circuit boards 11a and 11b each having a rectangular shape in a plan view, each including insulating plates 12a and 12b and metal plates 13a and 13b formed on the lower surfaces of insulating plates 12a and 12b, a top surface 31 having a rectangular shape in a plan view and a pair of short sides (short side surfaces 30e and 30g) opposing each other in a plan view and arrangement regions 31a and 31b in which insulating circuit boards 11a and 11b are respectively arranged via solder 40, and a heat dissipation base 3 including protrusions 32 formed in areas of arrangement regions 31a and 31b on top surface 31 corresponding to the four corners of insulating circuit boards 11a and 11b. Protrusions 32 are inner protrusions 32a located near a center line C parallel to the pair of short sides on top surface 31 and far from the pair of short sides, or outer protrusions 32b formed by multiple sub-protrusions 32b1 located far from the center line C and near one of the short sides.

[0066] In this semiconductor device 1, outer protrusions 32b directly contact the undersides of insulating circuit boards 11a and 11b. Because outer protrusions 32b are composed of multiple sub-protrusions 32b1, stress on insulating circuit boards 11a and 11b from each of sub-protrusions 32b1 is alleviated. This reduces the occurrence of damage to insulating plates 12a and 12b of insulating circuit boards 11a and 11b. This prevents deterioration in the insulating properties and heat dissipation properties of insulating circuit boards 11a and 11b, preventing a decrease in the reliability of semiconductor device 1.

[0067] Furthermore, damage to the insulating circuit boards 11a, 11b can be reduced even if the fastening holes 34a-34d are provided near the corners 31a1, 31a2, 31b3, 31b4 that are farther from the center line C of the arrangement regions 31a, 31b in which the semiconductor units 10a, 10b are arranged on the heat dissipation base 3. This allows the area of ​​the heat dissipation base 3 in a plan view to be reduced, thereby enabling the semiconductor device 1 to be miniaturized.

[0068] Note that the description here has been given taking as an example a case where the insulating circuit boards 11a, 11b are the same size. That is, as shown in Fig. 5, arrangement areas 31a, 31b are provided on the upper surface 31 of the heat dissipation base 3, with the center line C sandwiched between the center line C and a pair of short sides (short side surfaces 30e, 30g). This is not limited to this case, and a description will be given of a heat dissipation base 3 in which insulating circuit boards 11a, 11b of different sizes are arranged, using Fig. 10.

[0069] Fig. 10 is a plan view of another heat dissipation base included in the semiconductor device of the first embodiment. Note that on the upper surface 31 of the heat dissipation base 3 in Fig. 10, placement areas 31a and 31b corresponding to the outlines of the insulating circuit boards 11a and 11b are indicated by dashed lines.

[0070] 10, the insulating circuit board 11a arranged on the heat dissipation base 3 has a pair of longer long sides than the insulating circuit board 11b. Accordingly, the arrangement region 31a on the upper surface 31 of the heat dissipation base 3 extends beyond the center line C toward the short side (short side surface 30g). The pair of long sides of the arrangement region 31b are shorter than the pair of long sides of the arrangement region 31a.

[0071] In this case, the four protrusions 32 further include an inner protrusion 32a and an outer protrusion 32b. Of the four protrusions 32, each pair of inner protrusions 32a provided in the arrangement regions 31a, 31b is closer to the center line C and farther from each pair of short sides (short side surfaces 30e, 30g). The shape and size of the inner protrusions 32a are as described above.

[0072] The pair of outer protrusions 32b provided in the placement areas 31a and 31b respectively face a pair of short sides (short side surfaces 30e and 30g) of the four protrusions 32, and are far from the center line C and close to the pair of short sides (short side surfaces 30e and 30g).

[0073] Even in such a case, as described above, deterioration in the insulating properties and heat dissipation properties of insulating circuit boards 11a and 11b is suppressed, thereby preventing deterioration in the reliability of semiconductor device 1. Note that although the following description of a modified example of semiconductor device 1 of the first embodiment will be given with reference to the case of FIG. 5, the same applies to the case of FIG. 10.

[0074] (Modification 1-1 of the first embodiment) Several modified examples of the semiconductor device 1 of the first embodiment will be described below. First, modified example 1-1 will be described with reference to FIG. 11. FIG. 11 is an enlarged plan view of a protrusion of a heat dissipation base included in the semiconductor device of the first embodiment (modified example 1-1). FIG. 11 corresponds to FIG. 7 of the first embodiment.

[0075] As described above, outer protrusion 32b is composed of multiple sub-protrusions 32b1. Furthermore, outer protrusion 32b preferably has a rectangular shape as a whole in a plan view. By having outer protrusion 32b have a rectangular shape as a whole in a plan view, it is possible to stably support the lower surfaces of insulating circuit boards 11a and 11b. In Figures 6 and 7, four outer protrusions 32b are arranged in two rows and two columns to form a rectangular shape.

[0076] In the case of modified example 1-1 shown in Figure 11, outer protrusion 32b is composed of nine sub-protrusions 32b1 arranged in three rows and three columns. Furthermore, outer protrusion 32b of modified example 1-1 has a greater number of sub-protrusions 32b1 than outer protrusion 32b of Figures 6 and 7. Therefore, outer protrusion 32b of modified example 1-1 reduces the stress caused by one sub-protrusion 32b1 compared to the cases of Figures 6 and 7, thereby reducing the impact on insulating circuit boards 11a and 11b.

[0077] Note that the first embodiment and its modified example 1-1 merely exemplify cases in which outer protrusion 32b is configured with sub-protrusions 32b1 arranged in two rows and two columns or three rows and three columns. Outer protrusion 32b may be configured with sub-protrusions 32b1 arranged in n rows and m columns (n ​​and m are integers). The number of n rows and m columns may be selected as appropriate depending on factors such as the area of ​​the lower surface of insulating circuit boards 11a and 11b.

[0078] (Modification 1-2 of the first embodiment) The heat dissipation base 3 of the semiconductor device 1 of Modification 1-2 will be described with reference to Fig. 12. Fig. 12 is a plan view of the heat dissipation base included in the semiconductor device of the first embodiment (Modification 1-2). Fig. 12 corresponds to Fig. 5 of the first embodiment.

[0079] As described above, the outer protrusions 32b are provided in the arrangement regions 31a and 31b facing a pair of short sides (short side surfaces 30e and 30g) of the multiple protrusions 32. In the first embodiment (FIG. 5), an example is described in which the outer protrusions 32b are provided at the corners 31a1 and 31a2 and the corners 31b3 and 31b4 on the pair of short sides (short side surfaces 30e and 30g) of the arrangement regions 31a and 31b.

[0080] In the modified example 1-2, an outer protrusion 32b is further provided between the corners 31a1, 31a2 and the corners 31b3, 31b4 of the arrangement areas 31a, 31b. In particular, Fig. 12 shows a case where one outer protrusion 32b is provided in the center between the corners 31a1, 31a2 and the corners 31b3, 31b4 of the arrangement areas 31a, 31b.

[0081] Even in this case, the thickness of the solder 40 on the outer protrusions 32b is thinner than the thickness of the solder 40 on the inner protrusions 32a, and the outer protrusions 32b may come into direct contact with the undersides of the insulating circuit boards 11a, 11b. Therefore, in Modification 1-2, by providing the outer protrusions 32b between the corners 31a1, 31a2 and the corners 31b3, 31b4 of the arrangement regions 31a, 31b, it is possible to more stably support the semiconductor units 10a, 10b while suppressing impacts on the insulating circuit boards 11a, 11b.

[0082] In addition, in Modification 1-2, a case where one outer protrusion 32b is provided between each of the corners 31a1, 31a2 and the corners 31b3, 31b4 of the arrangement regions 31a, 31b is described. The number of each is not limited to one, and multiple protrusions may be provided as needed. Furthermore, Modification 1-2 illustrates a case where one outer protrusion 32b is provided in the center between each of the corners 31a1, 31a2 and the corners 31b3, 31b4 of the arrangement regions 31a, 31b. The additional outer protrusion 32b is not limited to being provided in the center between each of the corners 31a1, 31a2 and the corners 31b3, 31b4 of the arrangement regions 31a, 31b, but may be provided closer to one of the corners 31a1, 31a2 and the corners 31b3, 31b4.

[0083] (Modification 1-3 of the first embodiment) The heat dissipation base 3 of the semiconductor device 1 of Modification 1-3 will be described with reference to Fig. 13. Fig. 13 is a plan view of the heat dissipation base included in the semiconductor device of the first embodiment (Modification 1-3). Note that Fig. 13 also corresponds to Fig. 5 of the first embodiment.

[0084] The multiple sub-protrusions 32b1 included in the outer protrusion 32b of variant example 1-3 are arranged in a row along a pair of short sides (short sides 30e, 30g) of the heat dissipation base 3, and multiple sub-protrusion groups 32b2 are provided along a pair of long sides (long sides 30f, 30h).

[0085] 13, the outer protrusions 32b have three rows of sub-protrusion groups 32b2 arranged along a pair of long sides (long side surfaces 30f, 30h) of the heat dissipation base 3. Each sub-protrusion group 32b2 has three sub-protrusions 32b1 arranged in a row along a pair of short sides (short side surfaces 30e, 30g) of the heat dissipation base 3. The gap between the sub-protrusion groups 32b2 may be wider than the gap between the sub-protrusions 32b1 within each sub-protrusion group 32b2.

[0086] Such outer protrusions 32b may come into direct contact with the undersides of insulating circuit boards 11a, 11b for each sub-protrusion group 32b2. Even in this case, as in the first embodiment, sub-protrusion group 32b2 of outer protrusion 32b is made up of multiple sub-protrusions 32b1, and therefore stress on insulating circuit boards 11a, 11b from each sub-protrusion 32b1 is alleviated.

[0087] As described above, the heat dissipation base 3 is warped downward (along the longitudinal direction) with the center line C facing downward. The insulating circuit boards 11a and 11b of the semiconductor units 10a and 10b joined to such a heat dissipation base 3 may also warp together with the heat dissipation base 3 due to heating and cooling.

[0088] The multiple rows of sub-projection groups 32b2 of outer projection 32b are provided along a pair of long sides (long side surfaces 30f, 30h) of heat dissipation base 3. Therefore, the multiple rows of sub-projection groups 32b2 of outer projection 32b can follow the warping of heat dissipation base 3 and insulating circuit boards 11a, 11b, respectively, and more stably support the lower surfaces of insulating circuit boards 11a, 11b.

[0089] The outer protrusions 32b in Modification 1-3 are provided along the pair of long sides (long side surfaces 30f, 30h) in the warping direction of the heat dissipation base 3. Therefore, depending on the warping direction of the heat dissipation base 3, the outer protrusions 32b in Modification 1-3 do not need to be provided along the pair of long sides (long side surfaces 30f, 30h).

[0090] Furthermore, the sub-projection group 32b2 of the outer projection 32b of Modification Example 1-3 may be arranged in one row or multiple rows along a pair of long sides (long side surfaces 30f, 30h). The multiple or multiple rows of the sub-projection group 32b2 may be aligned in a single row in the ±X direction or offset in the ±Y direction. The sub-projection group 32b2 is not limited to three sub-projections 32b1, and may include two, four, or more sub-projections 32b1 aligned in a single row. The number of sub-projections 32b1 included in each sub-projection group 32b2 may vary for each sub-projection group 32b2. Such outer projections 32b may be arranged in multiple rows between the corners 31a1, 31a2, and the corners 31b3, 31b4 of the arrangement region 31a, 31b on the upper surface 31 of the heat dissipation base 3, as in Modification Example 1-2.

[0091] (Modification 1-4 of the first embodiment) In a modification 1-4 of the first embodiment, the semiconductor device 1 of the first embodiment includes another pair of semiconductor units 10a, 10b, for a total of four semiconductor units. The heat dissipation base 3 in this case will be described with reference to FIGS. 14 and 15. FIG. 14 is a plan view of a heat dissipation base included in the semiconductor device of the first embodiment (modification 1-4), and FIG. 15 is a plan view of another heat dissipation base included in the semiconductor device of the first embodiment (modification 1-4). Note that FIGS. 14 and 15 correspond to FIGS. 5 and 10 of the first embodiment. Arrangement regions 31a to 31d indicated by dashed lines in FIGS. 14 and 15 correspond to the outline of the insulating circuit board in a plan view.

[0092] In addition to the arrangement areas 31a and 31b, arrangement areas 31c and 31d are further provided on the upper surface 31 of the heat dissipation base 3 of Modification 1-4. Therefore, the arrangement areas 31a to 31d are arranged in two rows and two columns on the upper surface 31 of the heat dissipation base 3.

[0093] With respect to the upper surface 31 of such a heat dissipation base 3, the outer protrusions 32b are provided on the side of a pair of short sides (short side surfaces 30e, 30g) of the arrangement areas 31a to 31d, at corners 31a1, 31b4, 31c2, and 31d3 of the arrangement areas 31a to 31d near (facing) the fastening holes 34a to 34d.

[0094] The heat dissipation base 3 of Modification 1-4 has a pair of long sides (long side surfaces 30f, 30h) shorter than the heat dissipation base 3 of the first embodiment, and is closer to the pair of short sides (short side surfaces 30e, 30g). When heated, this type of heat dissipation base 3 may warp not only in the longitudinal direction but also in the lateral direction. The heat dissipation base 3 of Modification 1-4 is pre-warped into a bowl shape with the center point O below. That is, the corners 30a to 30d of the heat dissipation base 3 are located above the center point O (in the +Z direction).

[0095] When semiconductor units are placed in the arrangement areas 31a to 31d of the warped heat dissipation base 3 via a solder plate and melted, the molten solder moves to the center point O of the upper surface 31 of the heat dissipation base 3 and accumulates in a circular or elliptical shape centered on the center point O in a plan view. If the semiconductor units are joined to the arrangement areas 31a to 31d of the heat dissipation base 3 in this state with solder 40, it is likely that almost no solder 40 will remain between the corners 31a1, 31b4, 31c2, and 31d3 of the arrangement areas 31a to 31d of the heat dissipation base 3 and the underside of the semiconductor units (insulated circuit board). Furthermore, as mentioned above, there is a risk of increased stress due to screw fastening near the fastening holes 34a to 34d.

[0096] For this reason, on the upper surface 31 of the heat dissipation base 3, four arrangement areas 31a to 31d are set in two rows and two columns, and outer protrusions 32b are provided at corners 31a1, 31b4, 31c2, and 31d3 of the arrangement areas 31a to 31d near the fastening holes 34a to 34d (facing the fastening holes 34a to 34d).

[0097] Therefore, in the semiconductor device 1 of Modification 1-4, as in the first embodiment, the outer protrusions 32b directly contact the underside of the insulating circuit board corresponding to the corners 31a1, 31b4, 31c2, and 31d3 of the arrangement regions 31a-31d. The outer protrusions 32b are composed of multiple sub-protrusions 32b1, and each of the sub-protrusions 32b1 relieves stress on the insulating circuit board. This reduces the occurrence of damage to the insulating plate of the insulating circuit board. This suppresses deterioration in the insulating properties and heat dissipation properties of the insulating circuit board, preventing a decrease in the reliability of the semiconductor device 1 of Modification 1-4.

[0098] Furthermore, even when the four arrangement regions 31a to 31d are arranged in two rows and two columns on the upper surface 31 of the heat dissipation base 3, the sizes may also be different. For example, the arrangement regions 31a to 31d on the upper surface 31 of the heat dissipation base 3 shown in Fig. 15 are sized according to the insulating circuit board. That is, the arrangement regions 31a and 31c extend beyond the center line C toward the short side (short side surface 30g). The pair of long sides of the arrangement regions 31b and 31d are shorter than the pair of long sides of the arrangement regions 31a and 31c.

[0099] Even in such a case, as in the case of Figure 14, the occurrence of damage to the insulating plate of the insulating circuit board can be reduced, and the deterioration of the insulating properties and heat dissipation properties of the insulating circuit board is suppressed, thereby preventing a decrease in the reliability of the semiconductor device 1.

[0100] [Second embodiment] The semiconductor device 1a of the second embodiment differs from the semiconductor device 1 of the first embodiment in that the outer protrusions 32b of the heat dissipation base 3 are different. The semiconductor device 1a has the same configuration as the semiconductor device 1 except for the outer protrusions 32b. Such a semiconductor device 1a will be described with reference to FIGS. 16 to 18. Note that although the case of the heat dissipation base 3 (excluding the outer protrusions 32b) shown in FIG. 5 will be described here, the same applies to the cases of FIGS. 10, 14, and 15.

[0101] FIG. 16 is a plan view of a heat dissipation base included in a semiconductor device of the second embodiment. FIG. 17 is a cross-sectional view of the semiconductor device of the second embodiment. FIG. 18 is an enlarged cross-sectional view of a protrusion of the heat dissipation base included in the semiconductor device of the second embodiment. Note that FIG. 16 corresponds to FIG. 5 of the first embodiment and shows the heat dissipation base 3 of the semiconductor device 1a in a plan view. FIG. 17 corresponds to FIG. 3 of the first embodiment and shows the semiconductor device 1a in a cross-sectional view taken along the dashed line X2-X2 in FIG. 1. FIG. 18 corresponds to FIG. 6 of the first embodiment and shows an enlarged view of the area enclosed by the dashed line in FIG. 17.

[0102] Similar to the first embodiment, the heat dissipation base 3 of the semiconductor device 1a also includes a heat dissipation plate 30 and a plurality of protrusions 32 formed on the heat dissipation plate 30. Fastening holes 34a to 34d penetrating the heat dissipation plate 30 are also formed near corners 30a to 30d of the heat dissipation plate 30. The corners 30a to 30d of the heat dissipation plate 30 face corners 31a1, 31a2, 31b3, and 31b4 of the arrangement regions 31a and 31b, respectively.

[0103] As in the first embodiment, the multiple protrusions 32 are formed in areas (corners 31a1, 31a2, 31b3, 31b4) of the arrangement areas 31a, 31b of the upper surface 31 corresponding to the outer edges (corners) of the semiconductor units 10a, 10b (insulated circuit boards 11a, 11b).

[0104] The plurality of protrusions 32 further includes an inner protrusion 32a and an outer protrusion 32b. The inner protrusion 32a faces the center line C of the plurality of protrusions 32, is close to the center line C, and is far from the pair of short sides (short side surfaces 30e, 30g). The outer protrusion 32b also faces the pair of short sides (short side surfaces 30e, 30g) of the plurality of protrusions 32, is far from the center line C, and is close to the pair of short sides (short side surfaces 30e, 30g).

[0105] However, as shown in Figures 16 and 17, the outer protrusion 32b of the second embodiment has a rectangular shape in plan view. Specifically, the pair of long sides of the outer protrusion 32b extend along the pair of long sides (long side surfaces 30f, 30h) and are longer than the pair of short sides. The pair of short sides of the outer protrusion 32b may be, for example, 0.1 mm or more and 1 mm or less, and the pair of long sides of the outer protrusion 32b may be, for example, 2.5 times or more and 5 times or less the pair of short sides. The thickness of the outer protrusion 32b may be the same as that of the outer protrusion 32b of the first embodiment.

[0106] When the semiconductor units 10a, 10b are joined to the placement areas 31a, 31b of the heat dissipation base 3 with solder 40, the lower surface of the insulating circuit board 11a is directly supported by the outer protrusions 32b, as shown in FIG. 18 . The outer protrusions 32b, which extend along the pair of long sides (long side surfaces 30f, 30h) of the heat dissipation base 3, support the insulating circuit boards 11a, 11b by following the downward warping of the heat dissipation base 3 about the center line C. The entire upper surface of the outer protrusions 32b supports the insulating circuit boards 11a, 11b, reducing stress on the insulating circuit boards 11a, 11b from the outer protrusions 32b. This reduces damage to the insulating plates 12a, 12b of the insulating circuit boards 11a, 11b. This prevents deterioration in the insulating properties and heat dissipation of the insulating circuit boards 11a, 11b, and prevents a decrease in the reliability of the semiconductor device 1a.

[0107] In the second embodiment, the outer protrusions 32b may also be provided between the corners 31a1, 31a2 and the corners 31b3, 31b4 of the arrangement areas 31a, 31b of the heat dissipation base 3, as in the modified example 1-2 of the first embodiment.

[0108] The outer protrusions 32b are not limited to a rectangular shape as long as they can follow the downward warping of the heat dissipation base 3 about the center line C. For example, they may be elliptical in shape with their semi-major axes extending along the pair of long sides (long side surfaces 30f, 30h) in a plan view. [Explanation of symbols]

[0109] 1,1a Semiconductor device 2 cases 3 Heat dissipation base 10a, 10b Semiconductor unit 11a, 11b Insulated circuit board 12a, 12b Insulating plate 13a,13b Metal plate 14a, 15a, 16a, 17a, 14b, 15b, 16b Conductive circuit patterns 18a, 18b, 19a, 19b Semiconductor chips 20 Case 21a,21b,21c,21d Side wall 22a, 22b, 22c, 22d Terminal arrangement section 22e, 22f steps 23 Storage area 24a,24b,24c external terminal 25a,25b,25c Internal terminal 30 Heat sink 30a,30b,30c,30d corner 30e,30g short side 30f,30h long side 31 Top side 31a,31b,31c,31d placement area 31a1,31a2,31a3,31a4,31b1,31b2,31b3,31b4,31c2,31d3 corner 32 Protrusion 32a Medial protrusion 32b Lateral process 32b1 Secondary process 32b2 Sub-process group 33 Groove 34a,34b,34c,34d Fastening hole 40 solder 51a, 51b, 52a-52f, 53a, 53b, 54a-54f, 55 Main current wire 52g~52i, 54g~54i Control wire

Claims

1. a plurality of insulating circuit boards each having a rectangular shape in plan view, each including an insulating plate and a metal plate formed on a lower surface of the insulating plate; a heat dissipation base including: an upper surface that is rectangular in plan view, the upper surface having a pair of first sides that face each other in plan view and a plurality of arrangement regions in which the plurality of insulating circuit boards are respectively arranged via solder; and protrusions that are formed in the plurality of arrangement regions on the upper surface in regions that correspond to four corners of the plurality of insulating circuit boards; Including, The protrusion is an inner protrusion located on the upper surface near a center line parallel to the pair of first sides and far from the pair of first sides, or an outer protrusion consisting of a plurality of sub-protrusions located far from the center line and near one of the first sides. Semiconductor device.

2. Each of the plurality of insulating circuit boards has a rectangular shape in a plan view, The protrusions correspond to the four corners of the insulating circuit boards, each of the pair of inner protrusions, and each of the pair of outer protrusions. The semiconductor device according to claim 1 .

3. The heat dissipation base has fastening holes formed at first corners thereof in a plan view, the fastening holes penetrating the heat dissipation base; the outer protrusions are formed on second corners of the plurality of placement areas that are closest to the first corners of the heat dissipation base, respectively; The semiconductor device according to claim 2 .

4. the plurality of arrangement regions are provided on the upper surface, one for each between the center line and the pair of first sides; The outer protrusion is further provided between the second corner portions of the plurality of placement regions. The semiconductor device according to claim 3 .

5. the heat dissipation base has a pair of second sides perpendicular to the pair of first sides, the plurality of arrangement regions are provided on the upper surface of the heat dissipation base along the center line; the outer protrusions are provided at the second corners closest to the first corners of the plurality of arrangement regions facing the pair of second sides, respectively; The semiconductor device according to claim 4 .

6. the pair of first sides are short sides of the heat dissipation base, The plurality of sub-protrusions included in the outer protrusion are arranged in a line along the pair of first sides. The semiconductor device according to claim 1 .

7. The plurality of sub-protrusions arranged in a row are further provided with gaps in a direction perpendicular to the pair of first sides. The semiconductor device according to claim 6.

8. a plurality of insulating circuit boards each having a rectangular shape in plan view, each including an insulating plate and a metal plate formed on a lower surface of the insulating plate; a heat dissipation base including: an upper surface that is rectangular in plan view and has a pair of long sides and a pair of short sides and a plurality of arrangement regions in which the plurality of insulating circuit boards are respectively arranged via solder; and protrusions formed in regions of the plurality of arrangement regions on the upper surface that correspond to four corners of the plurality of insulating circuit boards; Including, The protrusion is an inner protrusion that is close to a center line parallel to the pair of short sides on the upper surface and far from the pair of long sides, or an outer protrusion that is far from the center line and close to one first side, faces one of the short sides, and extends along the pair of long sides. Semiconductor device.

9. The heat dissipation base has fastening holes formed at first corners thereof in a plan view, the fastening holes penetrating the heat dissipation base; the outer protrusions are formed on second corners of the plurality of arrangement regions that are closest to the first corners of the heat dissipation base; The semiconductor device according to claim 8 .

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