Switching control circuit and semiconductor device

Abstract

To provide a switching control circuit and a semiconductor device that control safely a switching element even when a power source voltage has dropped.SOLUTION: In a power module 10, a switching control IC includes a signal output circuit that outputs a set signal for turning on a first switching element 30 when a logic level of an input signal Sin becomes a first logic level, and outputs a reset signal for turning off the first switching element when the logic level becomes a second logic level, a level shift circuit that shifts the level of each of the set signal and the reset signal, a driving circuit 45 that drives the first switching element on the basis of the level shift circuit, a power source circuit that generates a power source voltage Vreg to the signal output circuit on the basis of a power source voltage Vcc, and a detection circuit that, after the power source voltage Vcc becomes low from the first level, detects the rise to the second level.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a switching control circuit and a semiconductor device. [Background technology]

[0002] The switching control circuit controls a half-bridge circuit including a high-side switching element and a low-side switching element. The switching control circuit also includes a signal output circuit, a level shift circuit, and a drive circuit. The signal output circuit outputs pulses for switching the high-side switching element. The level shift circuit receives the pulses and outputs them as set signals and reset signals, thereby controlling the drive circuit that drives the high-side switching element (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-083072 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the power supply voltage drops, the signal output circuit may output pulses with a lower voltage level, which may prevent the level shift circuit from detecting the pulse signal correctly, and in such a case, the signal output circuit may no longer be able to safely control the switching of the switching element.

[0005] The present invention has been made in consideration of the above-mentioned conventional problems, and its object is to provide a switching control circuit that safely controls the switching of a switching element even when the power supply voltage drops. [Means for solving the problem]

[0006] a first drive circuit that drives the first switching element based on an output from the level shift circuit; a power supply circuit that generates a second power supply voltage for the signal output circuit based on a first power supply voltage; and a detection circuit that detects that the first power supply voltage has risen to a second level after dropping from a first level, wherein the signal output circuit outputs the reset signal when the first power supply voltage drops from the first level and returns to the second level when the logic level of the input signal is the second logic level, and the levels of the set signal and the reset signal change according to the level of the second power supply voltage, and the level shift circuit identifies the reset signal that is output when the first power supply voltage is at or above the second level.

[0007] A second aspect of the present invention is a semiconductor device comprising first and second switching elements and a switching control circuit that controls switching of the first and second switching elements, wherein the switching control circuit includes a signal output circuit that outputs a set signal for turning on the first switching element when a logic level of an input signal becomes a first logic level, and outputs a reset signal for turning off the first switching element when the logic level of the input signal becomes a second logic level; a level shift circuit that shifts the levels of the set signal and the reset signal; and a first drive circuit that drives the first switching element based on an output from the level shift circuit. a power supply circuit that generates a second power supply voltage for the signal output circuit based on a first power supply voltage; and a detection circuit that detects that the first power supply voltage has risen to a second level after dropping from a first level, wherein the signal output circuit outputs the reset signal when the first power supply voltage drops from the first level and then returns to the second level when the logic level of the input signal is at the second logic level, the levels of the set signal and the reset signal change according to the level of the first power supply voltage, and the level shift circuit identifies the reset signal that is output when the first power supply voltage is at or above the second level. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a switching control circuit that safely controls the switching of a switching element even when the power supply voltage drops. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of a power module 10. FIG. [Figure 2] FIG. 2 is a diagram illustrating an example of a power supply circuit 40. [Figure 3] FIG. 10 is a diagram showing an example of voltage changes when power supply voltages Vcc and Vreg are restored. [Figure 4] FIG. 4 is a diagram illustrating an example of a detection circuit 41. [Figure 5] 10 is a diagram illustrating an example of the operation of the detection circuit 41. FIG. [Figure 6] FIG. 2 is a diagram illustrating an example of a signal output circuit 42. [Figure 7] FIG. 10 is a diagram illustrating an example of an output circuit 83. [Figure 8] FIG. 2 is a diagram illustrating an example of a level shift circuit 43. [Figure 9] 10 is a diagram illustrating an example of the operation of the switching control IC 20. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] At least the following matters will become clear from the description of this specification and the accompanying drawings.

[0011] =====This embodiment===== 1 is a diagram showing the configuration of a power module 10 according to one embodiment of the present invention. The power module 10 is a semiconductor device for driving a load 11 based on instructions from a microcomputer (not shown), and is configured to include a switching control IC (Integrated Circuit) 20, a half-bridge circuit 21, and a capacitor 22.

[0012] The switching control IC 20 is a high voltage integrated circuit (HVIC) that controls the operation of the half bridge circuit 21 based on an input signal Sin from a microcomputer (not shown). The switching control IC 20 has terminals VCC, IN, GND, B, S, HO, and LO, which will be described in detail later.

[0013] The half-bridge circuit 21 is a circuit that drives, for example, a motor coil of an air conditioner, which is the load 11, and includes an IGBT (Insulated Gate Bipolar Transistor) 30 and an IGBT 31.

[0014] The IGBT 30 is a high-side switching element, and has a gate electrode connected to the terminal HO and an emitter electrode connected to the terminal S. A predetermined voltage Vdc (for example, 400 V) is applied to the collector electrode of the IGBT 30.

[0015] The IGBT 31 is a low-side switching element, and has a gate electrode connected to a terminal LO and a collector electrode connected to a terminal S. The emitter electrode of the IGBT 31 is grounded.

[0016] In this embodiment, IGBTs are used as the switching elements, but MOS transistors or bipolar transistors may also be used. IGBT 30 corresponds to the "first switching element on the high potential side," and IGBT 31 corresponds to the "second switching element on the ground side."

[0017] One end of the capacitor 22 is connected to the terminal B, and the other end is connected to the terminal S. The capacitor 22 is charged by applying a bootstrap voltage Vb from a charge pump circuit 44 (described later) to the terminal B. As a result, the bootstrap voltage Vb is generated across the capacitor 22. The bootstrap voltage Vb is a voltage used to turn on the high-side IGBT 30.

[0018] For example, when the voltage Vs of the terminal S is "0 V," the IGBT 30 turns on when the voltage of the gate electrode of the IGBT 30 becomes higher than the threshold voltage of the IGBT 30. However, when the IGBT 30 turns on, the voltage Vs of the terminal S approaches the voltage Vdc (for example, "400 V"), and therefore, in order to keep the IGBT 30 on, it is necessary to drive the IGBT 30 based on the voltage Vs of the terminal S to which the emitter electrode of the IGBT 30 is connected.

[0019] In this embodiment, a voltage higher than the voltage Vs at the terminal S by a bootstrap voltage Vb is generated at the terminal B. Therefore, as will be described in detail later, the switching control IC 20 can turn on the IGBT 30 by using the bootstrap voltage Vb.

[0020] <<<Configuration of the switching control IC20>>> The switching control IC 20 includes a power supply circuit 40, a detection circuit 41, a signal output circuit 42, a level shift circuit 43, a charge pump circuit 44, and drive circuits 45 and 46.

[0021] The power supply circuit 40 generates a power supply voltage Vreg used inside the switching control IC 20 based on a power supply voltage Vcc (e.g., 20 V) applied to the terminal VCC. The power supply circuit 40 of this embodiment is configured to be able to generate a stable power supply voltage Vreg even when the IGBT 31 is turned on. The power supply voltage Vcc corresponds to a "first power supply voltage," and the power supply voltage Vreg corresponds to a "second power supply voltage."

[0022] <<<An example of the power supply circuit 40>>> 2 is a diagram showing an example of a power supply circuit 40. The power supply circuit 40 is a circuit that generates a temperature-compensated power supply voltage Vreg (e.g., 5 V) based on a power supply voltage Vcc. The power supply circuit 40 includes a bias circuit 200 and an output circuit 201.

[0023] The bias circuit 200 is a circuit that generates a bias voltage V3 for operating Darlington-connected transistors (described later). The bias circuit 200 includes voltage generation circuits 210 and 211.

[0024] The voltage generating circuit 210 is a circuit that generates a voltage V1 at a predetermined level, and includes a resistor 220, five diodes D1 to D5, and a Zener diode 221.

[0025] The resistor 220, the diodes D1 to D5, and the Zener diode 221 are connected in series. Therefore, when a power supply Vcc is applied to one end of the resistor 220, the voltage V1 of the node to which the other end of the resistor 220 and the anode of the diode D1 are connected is expressed by the following equation (1).

[0026] V1 = Vz + 5 × Vf (1) Here, "Vz" is the breakdown voltage of the Zener diode 221, and "Vf" is the forward voltage of the diodes D1 to D5.

[0027] The voltage generating circuit 211 is a circuit that generates a bias voltage V3 based on the voltage V1, and includes an NPN transistor 230, resistors 231 and 232, and three diodes D6 to D8.

[0028] A voltage V1 is applied to the base electrode of NPN transistor 230, and diodes D6 to D8 are connected to the emitter electrode via resistors 231 and 232. Therefore, a voltage V2 expressed by the following equation (2) is output from the emitter electrode of NPN transistor 230.

[0029] V2=V1-Vbe=Vz+5×Vf-Vbe...(2) Here, "Vbe" is the base-emitter voltage of the NPN transistor 230. In the voltage generating circuit 211, the difference between the forward voltage "3×Vf" of the three diodes D6 to D8 and the voltage V2 is divided by a voltage dividing circuit formed by resistors 231 and 232. Therefore, the bias voltage V3 from the node to which the resistors 231 and 232 are connected is expressed by the following equation (3).

[0030] V3=3×Vf+(V2-3×Vf)×(R2 / (R1+R2)) =3×Vf+(Vz+2×Vf-Vbe)×(R2 / (R1+R2))...(3) Here, "R1" is the resistance value of the resistor 231, and "R2" is the resistance value of the resistor 232.

[0031] The output circuit 201 is a circuit that outputs a predetermined power supply voltage Vreg based on a bias voltage V3, and is configured to include a voltage-resistant circuit 240, NPN transistors 241 and 242, and a resistor 243.

[0032] The voltage-resistant circuit 240 is a circuit for protecting the NPN transistors 241 and 242 from overvoltage, and includes four diodes D9 to D12 connected in series.

[0033] The emitter electrode of the NPN transistor 241 is connected to the base electrode of the NPN transistor 242, and the collector electrode of the NPN transistor 241 is connected to the collector electrode of the NPN transistor 242. Therefore, the NPN transistors 241 and 242 of this embodiment are connected in a Darlington configuration, and can drive a larger load.

[0034] Furthermore, as described above, voltage V3 is applied to the base electrode of NPN transistor 241 in the first stage, and therefore power supply voltage Vreg shown in equation (4) below is output from the emitter electrode of NPN transistor 242.

[0035] Vreg=V3-2×Vbe =(3×Vf+(Vz+2×Vf-Vbe)×(R2 / (R1+R2))-2×Vbe...(4) The resistor 243 is an element for steadily generating the power supply voltage Vreg. Specifically, if the resistor 243 is not provided, when the load state of the power supply circuit 40 becomes no-load, the current flowing through the NPN transistors 241 and 242 becomes zero. As a result, the generation of the power supply voltage Vreg is stopped.

[0036] In such a case, when a current flows through the load of the power supply circuit 40, it takes time for the power supply circuit 40 to generate the power supply voltage Vreg.

[0037] In this embodiment, even if the load state of the power supply circuit 40 is no load, a current continues to flow through the resistor 243. Therefore, the power supply circuit 40 can steadily generate a predetermined power supply voltage Vreg regardless of the load state of the power supply circuit 40.

[0038] The temperature coefficient of the breakdown voltage "Vz" of the Zener diode 221 is positive, the temperature coefficient of the forward voltage "Vf" of the diodes D1 to D12 is negative, and the temperature coefficient of the base-emitter voltage "Vbe" is negative.

[0039] In this embodiment, resistors of the same type (for example, polysilicon) with the same temperature coefficient are used for the resistors 231 and 232. Therefore, the temperature coefficient of the term "R2 / (R1+R2)" in equation (4) can be almost ignored.

[0040] In this embodiment, for example, the number of diodes D1 to D12 is adjusted based on equation (4) so ​​that the power supply voltage Vreg is temperature compensated. As a result, the level of the power supply voltage Vreg becomes constant regardless of temperature. Also, in this embodiment, the power supply voltage Vreg can be set to a desired level by changing the resistance ratio of the resistors 231 and 232.

[0041] Thus, the power supply circuit 40 has a high output current capability because it includes Darlington-connected NPN transistors 241 and 242. Furthermore, the power supply circuit 40 can output a temperature-compensated power supply voltage Vreg (e.g., 5 V) at a predetermined level.

[0042] <<<Example of voltage changes in power supply voltages Vcc and Vreg>>> 3 is a diagram showing voltage changes in the power supply voltages Vcc and Vreg after the power supply voltage Vcc drops, where the dashed dotted line indicates the power supply voltage Vcc and the solid line indicates the power supply voltage Vreg.

[0043] At time t0, when the power supply voltage Vcc drops from the first level LV1, the power supply voltage Vreg also starts to drop from the third level LV3. When the power supply voltage Vcc drops to its lowest point at time t1 and starts to recover, the power supply voltage Vreg also starts to recover later.

[0044] At time t2, the power supply voltage Vcc returns to the second level LV2. At this time, the power supply voltage Vcc has risen to a level at which the power supply circuit 40 can generate the power supply voltage Vreg, but the power supply voltage Vcc has not yet returned to the level before it dropped.

[0045] At time t3, the power supply voltage Vcc returns to the level before the drop. In this way, before the power supply voltage Vcc returns to the level before the drop, the power supply circuit 40 of this embodiment starts outputting the power supply voltage Vreg of the fourth level LV4.

[0046] <<<An example of the detection circuit 41>>> 1 detects that the power supply voltage Vcc has risen to the second level LV2 after dropping. Specifically, the detection circuit 41 outputs a pulse signal S5 when the power supply voltage Vcc drops from the first level LV1 and then rises to the second level LV2.

[0047] As shown in Fig. 4, the detection circuit 41 includes a voltage detection circuit 50 and an additional pulse generation circuit 51. The voltage detection circuit 50 is a circuit that detects a drop in the power supply voltage Vcc, and when the power supply voltage Vcc recovers after the drop, it outputs a signal S7 corresponding to the power supply voltage Vcc. The additional pulse generation circuit 51 corresponds to the "pulse generation circuit."

[0048] The voltage detection circuit 50 includes resistors 60, 61, and 64, a capacitor 62, an NMOS transistor 63, and a level shift circuit 65.

[0049] Resistors 60 and 61 form a voltage divider circuit that divides the power supply voltage Vcc, generating a voltage Vcc_div at their connection point. Capacitor 62 is an element that stabilizes voltage Vcc_div and delays the time until NMOS transistor 63 turns on after the power supply voltage Vcc is restored.

[0050] The NMOS transistor 63 is an element that detects the level of the power supply voltage Vcc, and has a gate electrode to which a voltage Vcc_div is applied, a drain electrode to which the power supply voltage Vcc is applied via a resistor 64, and a source electrode that is grounded. When the voltage Vcc_div exceeds a threshold Vthnm and the NMOS transistor 63 is turned on, the NMOS transistor 63 generates a signal S6 at the ground voltage level, and when the voltage Vcc_div falls below the threshold Vthnm and the NMOS transistor 63 is turned off, the voltage level of the signal S6 becomes a level that corresponds to the power supply voltage Vcc.

[0051] The level shift circuit 65 is a circuit that shifts the level of the signal S6 at the power supply voltage Vcc level to a signal S7 at the power supply voltage Vreg level.

[0052] When the power supply voltage Vcc recovers, the additional pulse generating circuit 51 generates a pulse signal S5 that becomes the set signal S1 or the reset signal S2. Specifically, the additional pulse generating circuit 51 generates the pulse signal S5 when the power supply voltage Vcc recovers to the second level LV2 after dropping, based on the power supply voltage Vreg and the signal S7. The additional pulse generating circuit 51 includes an inverter circuit 70, an NMOS transistor 71, a resistor 72, a capacitor 73, and a NOR circuit 74.

[0053] When the voltage level of the signal S7 exceeds the threshold Vthiv, the inverter circuit 70 outputs a signal S7a at a level corresponding to the power supply voltage Vreg, and when the voltage level of the signal S7 falls below the threshold Vthiv, the inverter circuit 70 outputs a signal S7a at the ground voltage level.

[0054] The NMOS transistor 71 is an element that controls the charging and discharging of the capacitor 73. A signal S7a is input to the gate electrode, a power supply voltage Vreg is applied to the drain electrode via a resistor 72, and the source electrode is grounded. Specifically, when the NMOS transistor 71 is turned on, it discharges the capacitor 73, and when it is turned off, it charges the capacitor 73 with the power supply voltage Vreg via the resistor 72. The voltage generated across the capacitor 73 is referred to as a voltage Vreg_det.

[0055] The NOR circuit 74 outputs a pulse signal S5 based on the voltage Vreg_det and the signal S7a. Specifically, the NOR circuit 74 outputs a pulse signal S5 of “L” level when the voltage level of the voltage Vreg_det or the signal S7a exceeds a threshold Vthnor, and outputs a pulse signal S5 of “H” level when the voltage level of the voltage Vreg_det and the signal S7a falls below the threshold Vthnor.

[0056] <<<Example of operation of detection circuit 41>>> 5 is a diagram showing an example of the operation of the detection circuit 41. At time t10, the power supply voltage Vcc begins to decrease.

[0057] At time t11, when the voltage Vcc_div reaches a voltage that turns off the NMOS transistor 63, the signal S6 reaches a voltage corresponding to the voltage level of the power supply voltage Vcc. As a result, the voltage level of the signal S7 reaches a level corresponding to the signal S6, but does not reach the threshold value Vthiv of the inverter circuit 70.

[0058] The voltage level of the signal S7a corresponds to the voltage level of the power supply voltage Vreg, but is higher than the threshold Vthnor of the NOR circuit 74 and is not at a level that turns off the NMOS transistor 71, so the voltage level of the voltage Vreg_det becomes the ground voltage level. Therefore, the voltage level of the signal S5 becomes the ground voltage level.

[0059] At time t12, when the voltage level of signal S7a falls below threshold Vthnor, NMOS transistor 71 is turned off, capacitor 73 is charged by power supply voltage Vreg, and voltage Vreg_det becomes a level corresponding to the voltage level of power supply voltage Vreg. At this time, NOR circuit 74 outputs signal S5 whose level corresponds to the voltage level of power supply voltage Vreg.

[0060] At time t13, the power supply voltage Vreg starts to recover, and the capacitor 73 is charged by the power supply voltage Vreg.

[0061] At time t14, when the voltage Vreg_det exceeds the threshold Vthnor of the NOR circuit 74, the voltage level of the signal S7a is still lower than the threshold Vthnor, so the NOR circuit 74 outputs the signal S5 at the ground voltage level.

[0062] At time t15, when the power supply voltage Vreg rises and the voltage level of the signal S7a reaches a level that turns on the NMOS transistor 71, the capacitor 73 is discharged and the voltage Vreg_det reaches the ground voltage level. However, because the voltage level of the signal S7a is higher than the threshold Vthnor, the NOR circuit 74 outputs the signal S5 at the ground voltage level.

[0063] At time t16, when the power supply voltage Vcc returns to the second level LV2 and the voltage level of the signal S7 exceeds the threshold Vthiv, the voltage level of the signal S7a becomes the ground voltage level, which turns off the NMOS transistor 71 and starts charging the capacitor 73.

[0064] However, because the voltage levels of the voltage Vreg_det and the signal S7a are lower than the threshold Vthnor, the NOR circuit 74 outputs a signal S5 whose level corresponds to the voltage level of the power supply voltage Vreg. As a result, the detection circuit 41 outputs a pulse signal S5 when the power supply voltage Vcc drops from the first level LV1 and then returns to the second level LV2.

[0065] Furthermore, when the power supply voltage Vcc returns to the second level LV2, the voltage level of the power supply voltage Vreg becomes higher than the threshold Vthnm of the NMOS transistors 100, 103 (described later) of the level shift circuit 43 in Fig. 8. Accordingly, the voltage levels of the set pulse signal S1 and the reset pulse signal S2 output by the output circuit 83 (described later) in Fig. 7, which operates based on the power supply voltage Vreg, also become higher than the threshold Vthnm, and the level shift circuit 43 becomes able to distinguish between the set pulse signal S1 and the reset pulse signal S2.

[0066] At time t17, when the voltage level of voltage Vcc_div corresponding to power supply voltage Vcc exceeds threshold Vthnm of NMOS transistor 63, the voltage levels of signals S6 and S7 become ground voltage level, turning on NMOS transistor 71. Then, although voltage Vreg_det becomes ground voltage level, the voltage level of signal S7a is higher than threshold Vthnor, so NOR circuit 74 outputs pulse signal S5 at ground voltage level.

[0067] 1 outputs signals for controlling the switching of the IGBTs 30 and 31 based on an input signal Sin of a logic level input via a terminal IN. Specifically, based on the input signal Sin, the signal output circuit 42 outputs a set pulse signal S1 for turning on the high-side IGBT 30, a reset pulse signal S2 for turning off the IGBT 30, and a control signal S0 for controlling the switching of the low-side IGBT 31.

[0068] <<<An example of the signal output circuit 42>>> 6, the signal output circuit 42 includes an input detection circuit 80, a filter circuit 81, a pulse generation circuit 82, and an output circuit 83. The input detection circuit 80, the filter circuit 81, the pulse generation circuit 82, and the output circuit 83 operate based on the power supply voltage Vreg of the power supply circuit 40, with the ground voltage Vgnd as a reference. For this reason, the respective ground nodes of the input detection circuit 80, the filter circuit 81, the pulse generation circuit 82, and the output circuit 83 are connected to the ground terminal GND.

[0069] The input detection circuit 80 detects the level of the input signal Sin and outputs a signal Sa of the same logic level as the logic level of the input signal Sin. Specifically, when the input signal Sin becomes high level (hereinafter referred to as "H" level), the input detection circuit 80 outputs an "H" level signal Sa, and when the input signal Sin becomes low level (hereinafter referred to as "L" level), the input detection circuit 80 outputs an "L" level signal Sa. The input detection circuit 80 is configured to include, for example, a comparator (not shown). The "H" level corresponds to a "first logic level," and the "L" level corresponds to a "second logic level."

[0070] The filter circuit 81 is a low-pass filter that removes high-frequency noise from the signal Sa, and includes, for example, an operational amplifier (not shown), etc. The filter circuit 81 of this embodiment outputs the signal Sa from which noise has been removed as the control signal S0.

[0071] The pulse generating circuit 82 outputs a set pulse signal Sb and a reset pulse signal Sc based on the change point of the control signal S0. Specifically, when the control signal S0 changes from a low level to a high level, the pulse generating circuit 82 outputs a high-level set pulse signal Sb, and when the control signal S0 changes from a high level to a low level, the pulse generating circuit 82 outputs a high-level reset pulse signal Sc. In this embodiment, the set pulse signal Sb and the reset pulse signal Sc are each pulse signals whose amplitude levels change from 0 V to the level of the power supply voltage Vreg (for example, 5 V).

[0072] When the power supply voltage Vcc is at the first level LV1, the output circuit 83 outputs a set pulse signal S1 and a reset pulse signal S2 based on the set pulse Sb and the reset pulse Sc. On the other hand, when the power supply voltage Vcc drops and then returns to the second level, the output circuit 83 outputs the pulse signal S5 from the detection circuit 41 as the set pulse signal S1 or the reset pulse signal S2 based on the control signal S0. Specifically, when the set pulse signal Sb is input to the output circuit 83, the output circuit 83 outputs the set pulse signal S1, and when the reset pulse signal Sc is input to the output circuit 83, the output circuit 83 outputs the reset pulse signal S2.

[0073] As will be described in detail later, when the control signal S0 is at "H" level and the pulse signal S5 is input, the output circuit 83 outputs the pulse signal S5 as the set pulse signal S1. On the other hand, when the control signal S0 is at "L" level and the pulse signal S5 is input, the output circuit 83 outputs the pulse signal S5 as the reset pulse signal S2.

[0074] <<<An example of the output circuit 83>>> 7, the output circuit 83 includes OR circuits 90 and 91, AND circuits 92 and 94, and an inverter circuit 93. The OR circuit 90 is a circuit that outputs the set pulse signal S1, and outputs the pulse signal S5a or the set pulse signal Sb as the set pulse signal S1.

[0075] The OR circuit 91 is a circuit that outputs the reset pulse signal S2, and outputs the pulse signal S5b or the reset pulse signal Sc as the reset pulse signal S2.

[0076] The AND circuit 92 is a circuit that outputs a pulse signal S5a, and when the control signal S0 is at the "H" level, it outputs the pulse signal S5 from the detection circuit 41 as the pulse signal S5a.

[0077] The inverter circuit 93 is a circuit that inverts the logical level of the control signal S0 and outputs a control signal S0a. The AND circuit 94 is a circuit that outputs a pulse signal S5b and outputs the pulse signal S5 as the pulse signal S5b when the control signal S0a is at the "H" level (i.e., the control signal S0 is at the "L" level).

[0078] Since the OR circuits 90 and 91, the AND circuits 92 and 94, and the inverter circuit 93 operate based on the power supply voltage Vreg, the set pulse signal S1 and the reset pulse signal S2 in this embodiment are pulse signals whose amplitude levels change from 0 V to the level of the power supply voltage Vreg (e.g., 5 V).

[0079] 1 is a circuit that shifts the levels of the set pulse signal S1 and the reset pulse signal S2 to levels that can be distinguished by the drive circuit 45. Specifically, the level shift circuit 43 shifts the level of the set pulse signal S1 and outputs a set pulse signal S3 having an amplitude level of, for example, several tens of volts based on a voltage Vs that serves as a high-side reference potential. The level shift circuit 43 also shifts the level of the reset pulse signal S2 and outputs a reset pulse signal S4 having an amplitude level of, for example, several tens of volts based on the voltage Vs.

[0080] <<<An example of the level shift circuit 43>>> 8, the level shift circuit 43 includes NMOS transistors 100 and 103, resistors 101 and 104, and inverter circuits 102 and 105. The NMOS transistor 100 is an element that identifies the set pulse signal S1, and when turned on, it sets a voltage Vn0 at a connection point N0 with the resistor 101, one end of which has a voltage Vb applied, to the ground voltage level. On the other hand, when the NMOS transistor 100 is turned off, the voltage Vn0 becomes the level of the voltage Vb.

[0081] The inverter circuit 102 is an element that outputs a set pulse signal S3 based on voltage Vn0, and operates based on voltage Vb with voltage Vs as the reference. Therefore, when voltage Vn0 at the ground voltage level is input to the inverter circuit 102, the inverter circuit 102 outputs a set pulse signal S3 at the voltage Vb level. On the other hand, when voltage Vn0 at the voltage Vb level is input to the inverter circuit 102, the inverter circuit 102 outputs a set pulse signal S3 at the voltage Vs level.

[0082] The NMOS transistor 103 is an element that identifies the set pulse signal S2, and when turned on, it sets the voltage Vn1 at the connection point N1 with the resistor 104, one end of which has a voltage Vb applied, to the ground voltage level. On the other hand, when the NMOS transistor 103 is turned off, the voltage Vn1 becomes the level of the voltage Vb.

[0083] The inverter circuit 105 is an element that outputs a reset pulse signal S4 based on the voltage Vn1, and operates based on the voltage Vb with the voltage Vs as a reference. Therefore, when the voltage Vn1 at the ground voltage level is input to the inverter circuit 105, the inverter circuit 105 outputs a reset pulse signal S4 at the level of the voltage Vb. On the other hand, when the voltage Vn1 at the level of the voltage Vb is input to the inverter circuit 105, the inverter circuit 105 outputs a reset pulse signal S4 at the level of the voltage Vs. The NMOS transistor 100 corresponds to a "first transistor," and the NMOS transistor 103 corresponds to a "second transistor."

[0084] The charge pump circuit 44 in FIG. 1 generates a bootstrap voltage Vb for charging the capacitor 22 based on the power supply voltage Vcc (for example, 20 V) applied to the terminal VCC.

[0085] The drive circuit 45 is a circuit that turns on the high-side IGBT 30 based on the set pulse signal S3 and turns off the IGBT 30 based on the reset pulse signal S4. Specifically, the drive circuit 45 outputs a drive signal Vdr1 at the level of voltage Vb to the gate electrode of the IGBT 30 via the terminal HO based on the set pulse signal S3. As a result, the IGBT 30 turns on. On the other hand, the drive circuit 45 outputs a drive signal Vdr1 at the level of voltage Vs to the gate electrode of the IGBT 30 via the terminal HO based on the reset pulse signal S4. As a result, the IGBT 30 turns off.

[0086] The drive circuit 46 is a circuit that drives the low-side IGBT 31 based on the control signal S0. Specifically, the drive circuit 46 outputs a high-level drive signal Vdr2 to the gate electrode of the IGBT 31 via the terminal LO based on the low-level control signal S0. As a result, the IGBT 31 turns on. On the other hand, the drive circuit 46 outputs a low-level drive signal Vdr2 to the gate electrode of the IGBT 31 via the terminal LO based on the high-level control signal S0. As a result, the IGBT 31 turns off. The drive circuit 46 operates based on the power supply voltage Vcc. The drive circuit 45 corresponds to a "first drive circuit," and the drive circuit 46 corresponds to a "second drive circuit."

[0087] <<<Example of operation of the switching control IC20>>> 9 is a diagram showing an example of the operation of the switching control IC 20. At time t20, when a high-level input signal Sin is input, the pulse generating circuit 82 in FIG. 6 outputs a pulse signal Sb. Then, the output circuit 83 in FIG. 6 outputs a set pulse signal S1, and the level shift circuit 43 in FIG. 8 outputs a set pulse signal S3. As a result, the drive circuit 45 outputs a drive signal Vdr1 at the level of voltage Vb, turning on the IGBT 30. Meanwhile, the drive circuit 46 outputs a low-level drive signal Vdr2 based on the input signal Sin, turning off the IGBT 31.

[0088] At time t21, when an input signal Sin of "L" level is input, the pulse generating circuit 82 outputs a pulse signal Sc. Then, the output circuit 83 outputs a reset pulse signal S2, and the level shift circuit 43 outputs a reset pulse signal S4. As a result, the drive circuit 45 outputs a drive signal Vdr1 of the voltage Vs level, turning off the IGBT 30. Meanwhile, the drive circuit 46 outputs a drive signal Vdr2 of "H" level based on the input signal Sin, turning on the IGBT 31. Similar operations are repeated from time t22 until just before time t24.

[0089] At time t24, when the power supply voltage Vcc drops, the power supply voltage Vreg also starts to drop accordingly.

[0090] At time t25, when the input signal Sin of "L" level is input, if the power supply voltage Vreg is low, the pulse generating circuit 82 outputs a pulse signal Sc of a level corresponding to the power supply voltage Vreg.

[0091] Furthermore, because the power supply voltage Vreg is low, the output circuit 83 outputs a reset pulse signal S2 with a reduced voltage level. Therefore, the NMOS transistor 103 of the level shift circuit 43 is not turned on by the reset pulse signal S2, and the level shift circuit 43 cannot output the reset pulse signal S4. Therefore, the IGBT 30 is not turned off.

[0092] In this state, if the drive circuit 46 turns on the IGBT 31 based on the input signal Sin, a through current will flow through the half-bridge circuit 21, which may destroy the IGBTs 30 and 31. Therefore, when the power supply voltage Vcc returns to the second level LV2, the switching control IC 20 of this embodiment turns off the IGBT 30, cuts off the through current, and prevents the IGBTs 30 and 31 from being destroyed.

[0093] At time t26, when the power supply voltage Vcc returns to the second level LV2, the detection circuit 41 outputs the pulse signal S5, and the output circuit 83 outputs the pulse signal S5 as the reset pulse signal S2 because the pulse signal S5 was output when the signal S0 was at the "L" level. Then, the level shift circuit 43 outputs the reset pulse signal S4, and the IGBT 30 is turned off.

[0094] At time t27, when the input signal Sin goes high, the switching control IC 20 operates in the same manner as at time t20.

[0095] At time t28, when the power supply voltage Vcc drops, the power supply voltage Vreg also starts to drop accordingly.

[0096] At time t29, when an "H" level input signal Sin is input, if the power supply voltage Vreg is low, the pulse generating circuit 82 outputs a pulse signal Sb at a level corresponding to the power supply voltage Vreg. However, because the power supply voltage Vreg is low, the output circuit 83 outputs a set pulse signal S1 with a reduced voltage level. Therefore, the NMOS transistor 100 of the level shift circuit 43 is not turned on by the set pulse signal S1, and the level shift circuit 43 cannot output a set pulse signal S3. Therefore, the IGBT 30 is not turned on.

[0097] In this way, the switching control IC 20 receives the "H" level input signal Sin and is unable to turn on the IGBT 30 at the timing when it should turn on the IGBT 30. Therefore, if the power supply voltage Vcc drops at the timing when it should turn on the IGBT 30, the switching control IC 20 may malfunction. Therefore, the switching control IC 20 of this embodiment turns on the IGBT 30 when the power supply voltage Vcc returns to the second level LV2, thereby suppressing the malfunction.

[0098] At time t30, when the power supply voltage Vcc returns to the second level LV2, the detection circuit 41 outputs the pulse signal S5, and the output circuit 83 outputs the pulse signal S5 as the set pulse signal S1 because the pulse signal S5 was output when the signal S0 was at the "H" level. Then, the level shift circuit 43 outputs the set pulse signal S3, and the IGBT 30 is turned on.

[0099] At time t31, when the input signal Sin is at "L" level, the switching control IC 20 operates in the same manner as at time t21.

[0100] By operating the switching control IC 20 as described above, it is possible to suppress through current and malfunction, thereby providing a switching control circuit that safely controls the switching of the switching element even when the power supply voltage drops.

[0101] === Variations === In the above description, the drop of the power supply voltage Vcc from the first level LV1 and the rise to the second level Lv2 may be detected based on a change in a numerical value that increases or decreases in correlation with the power supply voltage Vcc. For example, as shown in Figures 3, 5, and 9, the level of the power supply voltage Vcc may be detected based on the power supply voltage Vreg dropping below the third level LV3 and then rising to the fourth level LV4.

[0102] ===Summary=== The power module 10 of this embodiment has been described above. The switching control IC 20 includes a power supply circuit 40, a detection circuit 41, a signal output circuit 42, a level shift circuit 43, and a drive circuit 45. The signal output circuit 42 outputs a reset pulse signal S1 when the power supply voltage Vcc returns to the second level LV2. This makes it possible to provide a switching control circuit that safely controls the switching of the switching elements even when the power supply voltage drops.

[0103] Furthermore, when the power supply voltage Vcc returns to the second level LV2, the signal output circuit 42 outputs a set pulse S2, thereby providing a switching control circuit that suppresses malfunctions even when the power supply voltage drops.

[0104] The detection circuit 41 includes a voltage detection circuit 50 and an additional pulse generation circuit 51, and the signal output circuit 42 outputs a pulse signal S5 as a set pulse signal S1 or a reset pulse signal S2 based on the input signal Sin. This makes it possible to suppress malfunctions, thereby enabling the power module 10 to be controlled more safely.

[0105] The level shift circuit 43 also includes NMOS transistors 100 and 103, whose threshold levels are lower than the second level LV2. This causes the detection circuit 41 to generate a pulse signal S5 when the voltage level of the power supply voltage Vcc becomes the second level LV2, thereby more reliably turning the IGBT 30 on and off.

[0106] The switching control IC 20 also includes a drive circuit 46. As a result, when the power supply voltage Vcc returns to the second level LV2, the IGBT 30 is turned off, the through current is cut off, and the IGBTs 30 and 31 are prevented from being destroyed.

[0107] Furthermore, the detection circuit 41 detects a change in the power supply voltage Vcc based on a change in a numerical value correlated with the power supply voltage Vcc, so that the detection circuit 41 can detect a change in the power supply voltage Vcc not only based on the power supply voltage Vcc but also based on a numerical value correlated with other power supply voltages Vcc.

[0108] The value correlated with the power supply voltage Vcc may be the power supply voltage Vreg, which makes it possible to suppress malfunctions by detecting the power supply voltage Vreg.

[0109] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0110] 10 Power Module 11 Load 20 Switching control IC 21 Half-bridge circuit 22,62,73 capacitors 40 Power circuit 41 Detection circuit 42 Signal output circuit 43,65 Level shift circuit 44 Charge pump circuit 45,46 Drive circuit 50 Voltage detection circuit 51 Additional pulse generation circuit 60, 61, 64, 72, 101, 104, 220, 231, 232, 243 Resistance 63,71,100,103 NMOS transistors 70,93,102,105 Inverter circuit 74 NOR circuit 80 Input detection circuit 81 Filter Circuit 82 Pulse Generator Circuit 83 Output circuit 90,91 OR circuit 92,94 AND circuit 200 Bias Circuit 201 Output circuit 210,211 Voltage generation circuit 221 Zener diode 230, 241, 242 NPN transistors 240 Voltage-resistant circuit

Claims

1. a signal output circuit that outputs a set signal for turning on a first switching element when the logic level of an input signal becomes a first logic level, and outputs a reset signal for turning off the first switching element when the logic level of the input signal becomes a second logic level; a level shift circuit that shifts the levels of the set signal and the reset signal; a first drive circuit that drives the first switching element based on an output from the level shift circuit; a power supply circuit that generates a second power supply voltage for the signal output circuit based on a first power supply voltage; a detection circuit that detects when the first power supply voltage drops from a first level and then rises to a second level; Equipped with The signal output circuit outputting the reset signal when the first power supply voltage drops from the first level and then returns to the second level when the logic level of the input signal is the second logic level; the levels of the set signal and the reset signal change according to the level of the second power supply voltage; The level shift circuit includes: identifying the reset signal that is output when the first power supply voltage is equal to or higher than the second level; Switching control circuit.

2. 2. The switching control circuit according to claim 1, The signal output circuit outputting the set signal when the first power supply voltage drops from the first level and then returns to the second level when the logic level of the input signal is the first logic level; The level shift circuit includes: identifying the set signal that is output when the first power supply voltage is equal to or higher than the second level; Switching control circuit.

3. 3. The switching control circuit according to claim 2, The detection circuit a voltage detection circuit that outputs a signal corresponding to the first power supply voltage when the first power supply voltage recovers after dropping; a pulse generating circuit that generates a pulse signal when the first power supply voltage returns to the second level after dropping, based on the second power supply voltage and the signal; Including, The signal output circuit outputting the pulse signal as the set signal or the reset signal based on the input signal; Switching control circuit.

4. 4. The switching control circuit according to claim 3, The level shift circuit includes: a first transistor to which the set signal is input; a second transistor to which the reset signal is input; Including, a threshold level of each of the first and second transistors is lower than the level of the second power supply voltage when the first power supply voltage is equal to or higher than the second level; Switching control circuit.

5. The switching control circuit according to any one of claims 1 to 4, a second drive circuit that drives a second switching element on the ground side connected to the first switching element on the high potential side based on the input signal; Switching control circuit.

6. The switching control circuit according to any one of claims 1 to 3, The detection circuit A change in the first power supply voltage is detected by a change in a value correlated to the first power supply voltage. Switching control circuit.

7. 7. A switching control circuit according to claim 6, The value correlated to the first power supply voltage is the second power supply voltage. Switching control circuit.

8. first and second switching elements; a switching control circuit that controls switching of the first and second switching elements; A semiconductor device comprising: The switching control circuit a signal output circuit that outputs a set signal for turning on the first switching element when the logic level of an input signal becomes a first logic level, and outputs a reset signal for turning off the first switching element when the logic level of the input signal becomes a second logic level; a level shift circuit that shifts the levels of the set signal and the reset signal; a first drive circuit that drives the first switching element based on an output from the level shift circuit; a power supply circuit that generates a second power supply voltage for the signal output circuit based on a first power supply voltage; a detection circuit that detects when the first power supply voltage drops from a first level and then rises to a second level; Equipped with The signal output circuit outputting the reset signal when the first power supply voltage drops from the first level and then returns to the second level when the logic level of the input signal is the second logic level; the levels of the set signal and the reset signal change according to the level of the second power supply voltage; The level shift circuit includes: identifying the reset signal that is output when the first power supply voltage is equal to or higher than the second level; Semiconductor device.

9. 9. The semiconductor device according to claim 8, The detection circuit A change in the first power supply voltage is detected by a change in a value correlated to the first power supply voltage. Semiconductor device.

10. 10. The semiconductor device according to claim 9, The value correlated to the first power supply voltage is the second power supply voltage. Semiconductor device.

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