Display device

Abstract

To provide a display device that can suppress a decrease in reliability.SOLUTION: A display device comprises: a substrate; a first inorganic insulating layer disposed over a display area in which a plurality of display elements are disposed and a peripheral area which surrounds the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer; a second inorganic insulating layer disposed on the organic insulating layer and overlapping a circumferential edge portion of the lower electrode; an organic layer disposed on the lower electrode and including a light emitting layer; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral area;l and a plurality of second metal layers electrically connected to the first metal layers. The second metal layer has pad portions. The second inorganic insulating layer is in contact with the first inorganic insulating layer in an area overlapping the pad portions.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer as well as functional layers such as a hole transport layer and an electron transport layer. Technology to prevent a decrease in reliability is needed for such display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, a display device includes a substrate, a first inorganic insulating layer disposed above the substrate across a display region where a plurality of display elements are disposed and a peripheral region around the display region, an organic insulating layer disposed on the first inorganic insulating layer, a lower electrode disposed on the organic insulating layer in the display region, a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral portion of the lower electrode, an organic layer including a light-emitting layer disposed on the lower electrode, an upper electrode disposed on the organic layer, a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral region and aligned along an edge of the substrate, and a plurality of second metal layers electrically connected to the first metal layers above the second inorganic insulating layer in the peripheral region. The second metal layers have pad portions extending further toward the edge of the substrate than the first metal layers. The second inorganic insulating layer is in contact with the first inorganic insulating layer in the region overlapping the pad portions. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a plan view showing an example of the configuration of an area including a plurality of pads of the display device shown in FIG. [Figure 5] FIG. 5 is a plan view showing an example of the configuration of an area including a plurality of pads of the display device shown in FIG. [Figure 6] FIG. 6 is a plan view showing the metal layer shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view of the display device taken along line VIII-VIII in FIG. [Figure 9]FIG. 9 is a plan view showing an example of the configuration of an area including a plurality of pads in a display device according to a comparative example. [Figure 10] FIG. 10 is a cross-sectional view of the display device taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view of the display device taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a plan view showing an example of the configuration of an area including a plurality of pads in the display device according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view of the display device taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view of the display device taken along line XIV-XIV in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those skilled in the art will readily conceive of appropriate modifications that maintain the gist of the invention and are therefore naturally within the scope of the present invention.

[0008] In addition, in order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0010] In the following explanation, "overlapping" refers not only to a case where another element overlaps a target element from the third direction Z, but also to a case where another element overlaps a target element from the direction opposite to the third direction Z. Furthermore, "overlapping" refers not only to a case where the target elements are in direct contact with each other, but also to a case where the target elements are spaced apart from each other, or a case where another element is located between the target elements.

[0011] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes a display panel PNL. The display panel PNL has an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0013] In this embodiment, the substrate 10 has a rectangular shape in plan view that is elongated in the second direction Y. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0014] The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA, on a substrate 10. The display area DA has a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y.

[0015] Each pixel PX includes multiple subpixels SP. In one example, the pixel PX includes a first color subpixel SP1, a second color subpixel SP2, and a third color subpixel SP3. The first color, second color, and third color are different from one another. Note that the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors. The display element 20 is an organic light emitting diode (OLED) as a light emitting element, and may be called an organic EL element.

[0019] The display device DSP has a plurality of pads PD in the peripheral area SA. The plurality of pads PD constitute, for example, pads for a touch panel. The plurality of pads PD are aligned in one direction along the panel edge PNLE. Here, the edge includes the edge and the area nearby. The panel edge PNLE includes the edge of the substrate 10. In this embodiment, the direction along the edge of the substrate 10 corresponds to the first direction X.

[0020] Each of the pads PD extends in the second direction Y, but is not limited to this. For example, some of the pads PD may extend in an oblique direction. The pads PD are formed, for example, by at least one metal layer described below. Such pads PD are electrically connected, for example, to a flexible printed circuit board FPC indicated by a dashed line.

[0021] Fig. 2 is a diagram showing an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP2 and SP3 are aligned in the second direction Y. Subpixels SP1 and SP2 are aligned in the first direction X, and subpixels SP1 and SP3 are aligned in the first direction X.

[0022] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0023] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example shown in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0024] An insulating layer 5 and partition walls 6 are arranged in the display area DA. In this embodiment, the partition walls 6 correspond to first partition walls. The insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0025] The partition walls 6 overlap the insulating layer 5 in a plan view. The partition walls 6 are formed in a lattice shape surrounding the openings AP1, AP2, and AP3. Similar to the insulating layer 5, the partition walls 6 can also be said to have openings in the subpixels SP1, SP2, and SP3.

[0026] The subpixels SP1, SP2, and SP3 each include display elements 201, 202, and 203 as the display element 20. The display element 201 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the aperture AP1. The peripheral portions of the lower electrode LE1, the organic layer OR1, and the upper electrode UE1 overlap the insulating layer 5 in a planar view. Here, the peripheral portions include the edges and the areas nearby.

[0027] The display element 202 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with the aperture AP2. The peripheral edges of the lower electrode LE2, the organic layer OR2, and the upper electrode UE2 overlap the insulating layer 5 in a plan view.

[0028] The display element 203 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with the aperture AP3. The peripheral edges of the lower electrode LE3, the organic layer OR3, and the upper electrode UE3 overlap the insulating layer 5 in a plan view.

[0029] 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect their exact shapes.

[0030] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode.

[0031] The lower electrode LE1 is connected to the pixel circuit 1 (shown in FIG. 1) of the subpixel SP1 through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0032] 2, the areas of the apertures AP1, AP2, and AP3 are different from one another: the area of ​​the aperture AP1 is larger than the area of ​​the aperture AP2, and the area of ​​the aperture AP2 is larger than the area of ​​the aperture AP3.

[0033] In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0034] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on a substrate 10. The circuit layer 11 includes various circuits such as the pixel circuits 1 shown in Fig. 1, and various wirings such as scanning lines GL, signal lines SL, and power supply lines PL.

[0035] The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 is disposed on the circuit layer 11. The insulating layer 12 has the function of flattening unevenness caused by the circuit layer 11. The insulating layer 12 is an organic insulating layer.

[0036] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and spaced apart from one another. The insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The insulating layer 5 is an inorganic insulating layer. In this embodiment, the insulating layer 5 corresponds to the second inorganic insulating layer.

[0037] The opening AP1 in the insulating layer 5 overlaps the lower electrode LE1, the opening AP2 overlaps the lower electrode LE2, and the opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the insulating layer 5.

[0038] The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Although the contact holes in the insulating layer 12 are omitted in FIG. 3, they correspond to the contact holes CH1, CH2, and CH3 in FIG. 2.

[0039] The partition walls 6 are disposed between adjacent display elements on the insulating layer 5. Specifically, the partition wall 6 shown on the right side of the figure is disposed between adjacent display elements 201 and 202, and the partition wall 6 shown on the left side of the figure is disposed between adjacent display elements 202 and 203.

[0040] The partition wall 6 includes a conductive lower portion 61 disposed on the insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The lower portion 61 of the partition wall 6 shown on the right side of the drawing is located between the openings AP1 and AP2. The lower portion 61 of the partition wall 6 shown on the left side of the drawing is located between the openings AP2 and AP3.

[0041] The lower portion 61 may be a single layer or a multi-layer body. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0042] 3, the lower portion 61 has a bottom layer 63 disposed on the insulating layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example shown in FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0043] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0044] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral edge located on the insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0045] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral edge located on the insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0046] 3, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 function as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0047] The cap layer CP1 is disposed on the upper electrode UE1, the cap layer CP2 is disposed on the upper electrode UE2, and the cap layer CP3 is disposed on the upper electrode UE3.

[0048] The encapsulating layer SE1 is disposed on the cap layer CP1, in contact with the partition wall 6, and continuously covers each element of the subpixel SP1. The encapsulating layer SE2 is disposed on the cap layer CP2, in contact with the partition wall 6, and continuously covers each element of the subpixel SP2. The encapsulating layer SE3 is disposed on the cap layer CP3, in contact with the partition wall 6, and continuously covers each element of the subpixel SP3.

[0049] 3, parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located on the partition wall 6 around the subpixel SP1. These parts are spaced apart from parts of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 that are located in the opening AP1 (parts that form the display element 201).

[0050] Similarly, parts of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located on the partition wall 6 around the subpixel SP2. These parts are spaced apart from parts of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 that are located in the opening AP2 (parts that form the display element 202).

[0051] Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located on the partition wall 6 surrounding the subpixel SP3, and these portions are spaced apart from the portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 that are located in the opening AP3 (the portions that constitute the display element 203).

[0052] Ends of the sealing layers SE1, SE2, and SE3 are located on the partition wall 6. In the example shown in Fig. 3, the ends of the sealing layers SE1 and SE2 located on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart, and the ends of the sealing layers SE2 and SE3 located on the partition wall 6 between the subpixels SP2 and SP3 are spaced apart.

[0053] The sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0054] The insulating layer 5, the sealing layers SE1, SE2, SE3 and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al2O3).

[0055] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material that can be used for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb).

[0056] The metal material of the shaft layer 64 may be, for example, aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi). The shaft layer 64 may also be made of an insulating material.

[0057] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer made of a metal material and an upper layer made of a conductive oxide. The metal material that forms the lower layer can be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy.

[0058] The conductive oxide forming the upper layer can be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). The upper portion 62 may have a single layer structure made of a metal material. Furthermore, the upper portion 62 may include a layer made of an insulating material.

[0059] The lower electrodes LE1, LE2, and LE3 are multilayer bodies including a transparent electrode made of an oxide conductive material such as ITO and a metal electrode made of a metal material such as silver.

[0060] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials.

[0061] In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength region, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength region, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength region. Each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0062] The upper electrodes UE1, UE2, and UE3 are made of a metal material such as an alloy of magnesium and silver (MgAg). The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. The multiple thin films are all transparent and have different refractive indices.

[0063] The circuit layer 11, the insulating layer 12, and the insulating layer 5 shown in FIG. 3 are disposed across the display area DA and the peripheral area SA.

[0064] Fig. 4 and Fig. 5 are plan views showing an example of the configuration of an area including a plurality of pads PD of the display device DSP shown in Fig. 1. Fig. 6 is a plan view showing the metal layers M1, M2, M3, and M4 shown in Fig. 5.

[0065] 4 and 5 show the vicinity of the panel edge PNLE in the peripheral area SA. In FIGS. 4 and 5, the display area DA is formed in the upper part of the figure. In FIGS. 4 and 5, the flexible printed circuit board FPC shown in FIG. 1 is indicated by a dashed line. In FIG. 5, the insulating layer 5 is omitted from the configuration example shown in FIG. 4.

[0066] 4 and 5, the pads PD are aligned in the first direction X and extend in the second direction Y. As described above, the insulating layer 5 and the insulating layer 12 are formed up to the region including the pads PD (peripheral region SA).

[0067] The insulating layer 5 is formed up to the panel edge PNLE as shown in Fig. 4. In contrast, the insulating layer 12 is not formed up to the panel edge PNLE as shown in Fig. 5.

[0068] The insulating layer 5 has an opening 51 as shown in Fig. 4. The insulating layer 12 has an opening 121 as shown in Fig. 5. In this embodiment, the opening 51 corresponds to the second opening, and the opening 121 corresponds to the first opening. The opening 51 of the insulating layer 5 overlaps with the opening 121 of the insulating layer 12.

[0069] The opening 51 in the insulating layer 5 and the opening 121 in the insulating layer 12 have, for example, a rectangular shape that is elongated in the second direction Y. The area of ​​the opening 121 in the insulating layer 12 is larger than the area of ​​the opening 51 in the insulating layer 5 in a plan view. The edge of the opening 121 is located outside the edge of the opening 51.

[0070] The display device DSP further includes a plurality of metal layers M1, M2, M3, and M4, as shown in Fig. 6. In this embodiment, the metal layer M1 corresponds to the fourth metal layer, the metal layer M2 corresponds to the third metal layer, the metal layer M3 corresponds to the first metal layer, and the metal layer M4 corresponds to the second metal layer.

[0071] Each of the metal layers M1, M2, M3, and M4 extends in the second direction Y. Adjacent metal layers M1, M2, M3, and M4 are arranged in the first direction X at intervals.

[0072] 5, the insulating layer 12 has a cover portion P12 that covers the multiple metal layers M3. The cover portion P12 has a shape that is elongated in the first direction X (for example, a rectangular shape).

[0073] 5, the insulating layer 12 has slits 123, 125, and 127 in the peripheral area SA. The cover portion P12 is separated from the insulating layer 12 formed around it by the slits 123, 125, and 127. In other words, the cover portion P12 is independent from the insulating layer 12 formed around it. Here, the insulating layer 12 formed around it includes the insulating layer 12 formed on the display area DA side.

[0074] The slit 123 is located between the display area DA (lower electrodes LE1, LE2, LE3) and the metal layer M4. The slit 123 is formed along the first direction X. The width of the slit 123 in the first direction X is greater than the distance between the metal layers M4 arranged at both ends in the first direction X.

[0075] The slits 125 and 127 are connected to both ends of the slit 123 in the first direction X. The slits 125 and 127 are formed in the second direction Y from the slit 123 toward the panel end PNLE. In addition, an area in which the insulating layer 12 is not formed is formed between the cover portion P12 and the end of the substrate 10 in the second direction Y.

[0076] 4 and 5, one metal layer M4 overlaps with the opening 51 and the opening 121. The metal layer M4 has a pad portion 70 as shown in FIG.

[0077] The pad portion 70 corresponds to, for example, a portion extending further in the second direction Y (panel end portion PNLE) than the metal layer M3. The pad portion 70 is located between the openings 51, 121 and the panel end portion PNLE in the second direction Y. The pad PD is mainly constituted by the pad portion 70 of the metal layer M4.

[0078] Fig. 7 is a cross-sectional view of the display device DSP taken along line VII-VII in Fig. 5. Fig. 8 is a cross-sectional view of the display device DSP taken along line VIII-VIII in Fig. 5. The circuit layer 11 has insulating layers 111, 112, and 113. The above-mentioned metal layers M1 and M2, together with the insulating layers 111, 112, and 113, form the circuit layer 11.

[0079] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The metal layer M1 is disposed on the insulating layer 111. The metal layer M1 is formed in the same layer as the scanning lines GL, for example.

[0080] The insulating layer 112 is an inorganic insulating layer, and is disposed on the insulating layer 111 and the metal layer M1. The insulating layer 112 has contact holes CH4 and CH5, as shown in FIG.

[0081] The metal layer M2 is disposed on the insulating layer 112. From another perspective, the metal layer M1 is disposed between the substrate 10 and the metal layer M2. The metal layer M2 is formed, for example, in the same layer as the signal line SL. Focusing on the slit 123, the metal layer M2 does not overlap the slit 123, as shown in FIG. 8.

[0082] The metal layer M2 is electrically connected to the metal layer M1 through contact holes CH4 and CH5. Specifically, the metal layer M2 has a first portion P1 connected to the metal layer M1 through contact hole CH4 and a second portion P2 connected to the metal layer M1 through contact hole CH5.

[0083] The second portion P2 extends toward the display area DA. The first portion P1 is aligned with and spaced apart from the second portion P2 in the second direction Y. In other words, a gap G1 is formed between the first portion P1 and the second portion P2.

[0084] 8, the length of the slit 123 in the second direction Y is smaller than the length of the gap G1 in the second direction Y. A portion of the metal layer M1 overlaps the slit 123 with the gap G1 therebetween.

[0085] The insulating layer 113 is an inorganic insulating layer and is disposed on the insulating layer 112 and the metal layer M2. From another perspective, the metal layer M2 is disposed between the substrate 10 and the insulating layer 113. In this embodiment, the insulating layer 113 corresponds to the first inorganic insulating layer. The insulating layer 113 has a contact hole CH6.

[0086] The metal layer M3 is disposed on the insulating layer 113. The metal layer M3 is electrically connected to the metal layer M2. Specifically, the metal layer M3 is in contact with the first portion P1 of the metal layer M2 through the contact hole CH6.

[0087] The insulating layer 12 is disposed on the insulating layer 113 and the metal layer M3. As shown in FIG. 8, the cover portion P12 of the insulating layer 12 covers the metal layer M3. Specifically, the cover portion P12 covers the peripheral edge portion M3E of the metal layer M3. As a result, the peripheral edge portion M3E of the metal layer M3 is not exposed from the cover portion P12. The opening 121 overlaps the metal layer M3 in the cover portion P12.

[0088] The insulating layer 5 is disposed on the insulating layers 12 and 113 and the cover portion P12. The insulating layer 113 is exposed from the insulating layer 12 at the slit 123, as shown in FIG.

[0089] Insulating layer 113 is covered with insulating layer 5 at slit 123. In other words, insulating layer 5 contacts insulating layer 113 at slit 123. Although not shown in FIGS. 7 and 8 , insulating layer 5 also contacts insulating layer 113 at slits 125 and 127.

[0090] The metal layer M4 is located above the insulating layer 5. Specifically, the metal layer M4 is disposed on the insulating layer 5. The metal layer M4 is in contact with the metal layer M3 exposed from the opening 51 of the insulating layer 5. In other words, the metal layer M4 is electrically connected to the metal layer M3 through the openings 51 and 121.

[0091] Focusing on the pad portion 70, the insulating layer 5 is disposed between the pad portion 70 and the insulating layer 113. Specifically, the insulating layer 5 is in contact with the insulating layer 113 in a region that overlaps with the pad portion 70 in the third direction Z. Furthermore, in this embodiment, the insulating layer 5 is in contact with the pad portion 70 in this region.

[0092] 7, the insulating layer 5 is in contact with the insulating layer 113 between adjacent pad portions 70. In other words, the insulating layer 12 is not formed between adjacent pad portions 70.

[0093] As shown in FIG. 8, the metal layer M1 extends further toward the panel edge portion PNLE than the metal layer M3. The pad portion 70 overlaps the metal layer M1 in the third direction Z. As shown in FIG. 8, the insulating layer 5 covers the peripheral portion 121E of the opening 121 of the insulating layer 12. The insulating layer 12 is not exposed from the insulating layer 5. Therefore, the metal layer M4 is not in contact with the insulating layer 12.

[0094] The insulating layers 111, 112, and 113 are made of silicon oxide, silicon nitride, or silicon oxynitride. The metal layers M2, M3, and M4 are made of, for example, a plurality of layers.

[0095] In one example, at least one of the metal layers M2, M3, and M4 has two titanium layers made of a titanium-based material and an aluminum layer made of an aluminum-based material located between the two titanium layers. Note that at least one of the metal layers M2, M3, and M4 may be formed by disposing an aluminum layer between layers made of a molybdenum-based material.

[0096] Fig. 9 is a plan view showing an example of the configuration of a region including a plurality of pads PD of a display device DSP10 according to a comparative example. Fig. 10 is a cross-sectional view of the display device DSP10 taken along line XX in Fig. 9. Fig. 11 is a cross-sectional view of the display device DSP10 taken along line XI-XI in Fig. 9. Fig. 9 shows only the opening 51 of the insulating layer 5. The opening 51 and the opening 121 have a rectangular shape that is elongated in the second direction Y.

[0097] In the display device DSP10 according to the comparative example, the pad PD is formed by the metal layer M3 and the metal layer M4. As shown in Fig. 11, the insulating layer 5 is not in contact with the insulating layer 113 in the region overlapping the pad PD.

[0098] In the display device DSP10 according to the comparative example, the insulating layer 12 is formed continuously up to the periphery of the pads PD. As shown in Fig. 10, the insulating layer 12 is located between adjacent pads PD.

[0099] Therefore, the insulating layer 5 is in contact with the insulating layer 12 between adjacent pads PD. In other words, the insulating layer 5 is not in contact with the insulating layer 113 between adjacent pads PD. Furthermore, as shown in FIG. 11 , the insulating layer 5 is in contact with the insulating layer 12 also in the region where the slit 123 is formed in this embodiment.

[0100] The adhesive strength between insulating layer 5, which is an inorganic insulating layer, and insulating layer 12, which is an organic insulating layer, is weaker than the adhesive strength between inorganic insulating layers. Therefore, in display device DSP10, insulating layer 5 is likely to peel off from insulating layer 12. Such peeling reduces the reliability of the display device.

[0101] In contrast, in this embodiment, the insulating layer 5 is in contact with the insulating layer 113, which is an inorganic insulating layer, in the region overlapping the pad portion 70. With this configuration, the adhesion between the insulating layer 5 and its underlying layer is improved, and peeling of the insulating layer 5 can be suppressed.

[0102] Furthermore, in this embodiment, the insulating layer 5 contacts the insulating layer 113 between adjacent pad portions 70 and in the slits 123, 125, and 127. This makes it possible to prevent the insulating layer 5 from peeling off between adjacent pad portions 70 and in the slits 123, 125, and 127.

[0103] As a result, in the peripheral region SA, it is possible to reduce the area of ​​the portion (interface between the insulating layer 5 and the insulating layer 12) that can become the starting point of peeling, and to suppress peeling of the insulating layer 5. In this way, with this embodiment, it is possible to suppress a decrease in the reliability of the display device DSP.

[0104] 9 and 11, in the display device DSP10 according to the comparative example, the pad PD is connected to the insulating layer 12 formed around it. Therefore, moisture easily penetrates into the pad PD from the periphery through the insulating layer 12.

[0105] The moisture is, for example, moisture in the atmosphere (outside air). In Figure 9, the path of moisture penetration is indicated by arrow W. The penetrated moisture may corrode the metal layer M4 that constitutes the pad PD. Such corrosion may cause peeling of the insulating layer 5 and the metal layer M4.

[0106] In this embodiment, the cover portion P12 is spaced apart from the insulating layer 12 formed around it. This makes it difficult for moisture to penetrate into the pad portion 70 from the outside, as shown by the arrow W in FIG. 5. As a result, corrosion that could cause peeling is less likely to occur in the metal layer M4. From this perspective, this embodiment can also suppress a decrease in the reliability of the display device DSP.

[0107] 8, the insulating layer 12 covers the entire periphery M3E of the metal layer M3. In other words, the peripheral edge M3E of the metal layer M3 is not exposed. This prevents undesired erosion of the aluminum layer by the etching solution used in the process of forming the lower electrode on the insulating layer 12.

[0108] 8, the metal layer M2 does not overlap the slit 123. This makes it possible to prevent undesired erosion of the metal layer M2 in the region overlapping the slit 123 by the etching solution (disconnection of the metal layer M2) in the step of forming the slit 123 in the manufacturing process.

[0109] In this embodiment, insulating layer 5 covers peripheral portion 121E of opening 121 in insulating layer 12. This makes it possible to suppress undesired erosion (disappearance) of insulating layer 12 in the step of forming opening 51 in insulating layer 5 in the manufacturing process.

[0110] As described above, the configuration of this embodiment can provide a display device DSP that can suppress a decrease in reliability. In addition, various other advantageous effects can be obtained from this embodiment.

[0111] Next, other embodiments will be described. In the configurations of the following embodiments, the same configurations as those of the first embodiment can be applied to parts that are not specifically mentioned.

[0112] [Second embodiment] Fig. 12 is a plan view showing an example of the configuration of a region including a plurality of pads PD of the display device DSP according to this embodiment. Fig. 13 is a cross-sectional view of the display device DSP taken along line XIII-XIII in Fig. 12. Fig. 14 is a cross-sectional view of the display device DSP taken along line XIV-XIV in Fig. 12. This embodiment differs from the first embodiment in that the display device DSP further includes a partition wall 8 formed in the peripheral region SA.

[0113] In this embodiment, the partition wall 8 corresponds to the second partition wall. The partition wall 8, together with the pad portion 70 of the metal layer M4, constitutes the pad PD. The partition wall 8 is disposed between the insulating layer 5 and the metal layer M4. As shown in FIGS. 13 and 14, the partition wall 8 is in contact with the insulating layer 5 and the metal layer M4, respectively.

[0114] The partition wall 8 has a lower portion 61 and an upper portion 62 configured in the same manner as the partition wall 6. In the partition wall 8, the upper portion 62 also protrudes from the side surface of the lower portion 61. The lower portion 61 is in contact with the insulating layer 5.

[0115] Furthermore, the lower portion 61 is in contact with the metal layer M3 via the openings 51 and 121. In other words, the lower portion 61 and the upper portion 62 are electrically connected to the metal layer M3. The upper portion 62 is in contact with the metal layer M4 (pad portion 70). That is, the metal layer M4 is electrically connected to the metal layer M3 via the partition wall 8.

[0116] 13 and 14, the metal layer M4 is disposed on the upper portion 62, but the metal layer M4 may be disposed so as to cover at least a portion of the lower portion 61. In the region overlapping the pad portion 70, the insulating layer 113, the insulating layer 5, the lower portion 61, the upper portion 62, and the pad portion 70 are stacked in this order in the third direction Z.

[0117] The configuration of this embodiment can also provide the same effects as those of the first embodiment. In this embodiment, the display device DSP further includes a partition wall 8. Therefore, the thickness of the pad PD is greater than that of the first embodiment.

[0118] When mounting a flexible printed circuit board FPC on multiple pads PD, an anisotropic conductive film may be disposed as an adhesive, for example. The anisotropic conductive film contains conductive particles. With the configuration of this embodiment, when mounting the flexible printed circuit board FPC, the partition wall 8 is recessed, allowing the conductive particles to bite into the pad portion 70, improving the compression bonding strength. This makes it easier to mount the flexible printed circuit board FPC on multiple pads PD. As a result, the reliability of the display device DSP can be improved.

[0119] All display devices that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices described above as embodiments of the present invention are within the scope of the present invention as long as they incorporate the gist of the present invention. Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and these modifications are also considered to be within the scope of the present invention. For example, displays in which a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits processes or modifies conditions, to the above-described embodiments are also within the scope of the present invention as long as they incorporate the gist of the present invention.

[0120] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0121] 5...insulating layer, 6, 8...partition wall, 10...substrate, 12...insulating layer, 20...display element, 51...opening, 61...lower part, 62...upper part, 70...pad part, 113...insulating layer, 121...opening, 123...slit, DA...display area, DSP...display device, M1, M2, M3, M4...metal layer, P1...first part, P2...second part, P12...cover part, PNL...display panel, SA...peripheral area.

Claims

1. A substrate; a first inorganic insulating layer disposed above the substrate across a display area in which a plurality of display elements are disposed and a peripheral area around the display area; an organic insulating layer disposed on the first inorganic insulating layer; a lower electrode disposed on the organic insulating layer in the display area; a second inorganic insulating layer disposed on the organic insulating layer and overlapping a peripheral portion of the lower electrode; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode disposed on the organic layer; a plurality of first metal layers disposed on the first inorganic insulating layer in the peripheral region and aligned along an edge of the substrate; a plurality of second metal layers electrically connected to the first metal layer above the second inorganic insulating layer in the peripheral region; the second metal layer has a pad portion extending toward an edge of the substrate further than the first metal layer; the second inorganic insulating layer is in contact with the first inorganic insulating layer in a region overlapping the pad portion; Display device.

2. the second inorganic insulating layer is in contact with the pad portion in the region; The display device according to claim 1 .

3. a first partition disposed between adjacent display elements; a second partition wall disposed between the second inorganic insulating layer and the pad portion, the first partition wall and the second partition wall each have a conductive lower portion and an upper portion protruding from a side surface of the lower portion; The display device according to claim 1 .

4. the lower portion of the second partition wall is in contact with the second inorganic insulating layer in the region; the upper portion of the second partition is in contact with the pad portion in the region; The display device according to claim 3 .

5. the lower portion of the second partition is electrically connected to the first metal layer. The display device according to claim 4 .

6. the second inorganic insulating layer is in contact with the first inorganic insulating layer between the adjacent pad portions; The display device according to claim 1 .

7. the organic insulating layer has a first opening overlapping the first metal layer; the second inorganic insulating layer has a second opening that overlaps the first opening and through which the first metal layer and the second metal layer are in contact; The display device according to claim 1 .

8. the second inorganic insulating layer covers a peripheral portion of the first opening; The display device according to claim 7 .

9. the organic insulating layer has a cover portion covering the plurality of first metal layers in the peripheral region; The display device according to claim 1 .

10. the cover portion covers a peripheral edge of the first metal layer. The display device according to claim 9 .

11. the cover portion is spaced apart from the organic insulating layer formed in the display area; The display device according to claim 9 .

12. the organic insulating layer is located between the lower electrode and the second metal layer and further has a slit formed along an edge of the substrate; The display device according to claim 11.

13. the second inorganic insulating layer is in contact with the first inorganic insulating layer at the slit; The display device according to claim 12.

14. a third metal layer disposed between the first inorganic insulating layer and the substrate and electrically connected to the first metal layer; The display device according to claim 12.

15. the third metal layer does not overlap the slit; The display device according to claim 14.

16. a fourth metal layer disposed between the third metal layer and the substrate and electrically connected to the third metal layer; The display device according to claim 14.

17. the third metal layer has a first portion connected to the first metal layer and the fourth metal layer, and a second portion connected to the fourth metal layer. The display device according to claim 16.

18. A gap is formed between the first portion and the second portion. The display device according to claim 17.

19. the fourth metal layer overlaps the slit with the gap therebetween; 19. The display device according to claim 18.

20. the fourth metal layer extends toward an edge of the substrate and overlaps the pad portion; The display device according to claim 16.

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