Nitride semiconductor device

Abstract

To perform surge protection while reducing parasitic inductance.SOLUTION: A nitride semiconductor device 100 includes a first connection member 121 which connects a source pad 103 and a first lead frame 131, a second connection member 122 which connects a drain pad 104 and a second lead frame 132, and a third connection member 123 which connects a gate pad 102 and a third lead frame 133. A surge protection diode chip 111 is mounted in the third lead frame 133. The nitride semiconductor device 100 further includes a fourth connection member 124 which connects the first lead frame 131 and the source pad 103 at a position closer to the third lead frame 133 than the first connection member 121, and a fifth connection member 125 which connects the first lead frame 131 and the surge protection diode chip 111 at a position closer to the third lead frame 133 than the first connection member 121.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices using HEMTs are recognized as devices that have lower on-resistance and are capable of high-speed, high-frequency operation compared to typical silicon (Si) power devices.

[0003] In order to take advantage of the high-speed switching characteristics of a HEMT, it is necessary to minimize switching loss. One of the factors that affect the switching operation of a HEMT is electromotive noise caused by parasitic inductance coupled to the source terminal of the HEMT. To eliminate the effects of electromotive noise caused by such parasitic inductance, a Kelvin source terminal (also called a driver source terminal) is used in addition to the source terminal. For example, Patent Document 1 discloses a semiconductor device equipped with a driver source lead. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-202310

[0005] [overview] In nitride semiconductor devices using a Kelvin source terminal, a parasitic inductance coupled to the Kelvin source terminal exists in the charge / discharge path that controls the gate-source voltage. This parasitic inductance coupled to the Kelvin source terminal can also cause switching loss. In addition, unexpected surges due to static electricity or the like can be applied between the gate and source, and these surges can cause breakdown of the insulation between the gate and source.

[0006] A nitride semiconductor device according to one embodiment of the present disclosure includes a transistor chip. The transistor chip includes a transistor made of a nitride semiconductor and a gate pad, a source pad, and a drain pad electrically connected to the transistor. The nitride semiconductor device further includes a first connection member electrically connected to the source pad, a first lead frame electrically connected to the first connection member, a second connection member electrically connected to the drain pad, a second lead frame electrically connected to the second connection member, a third connection member electrically connected to the gate pad, a third lead frame electrically connected to the third connection member, a fourth lead frame on which the transistor chip is mounted, a surge protection diode chip mounted on the third lead frame, a fourth connection member electrically connected to the first lead frame and the source pad at a position closer to the third lead frame than the first connection member, and a fifth connection member electrically connected to the first lead frame and the surge protection diode chip at a position closer to the third lead frame than the first connection member. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view of the transistor chip shown in FIG. [Figure 3] FIG. 3 is a schematic plan view of an exemplary transistor structure. [Figure 4] FIG. 4 is a cross-sectional view taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a diagram schematically showing a circuit for controlling the gate-source voltage of a transistor in the nitride semiconductor device of FIG. [Figure 6] FIG. 6 is a diagram schematically showing a drain-source current path and a gate-Kelvin source current path in the nitride semiconductor device of FIG. [Figure 7] FIG. 7 is a schematic plan view of an exemplary nitride semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a diagram schematically showing a drain-source current path in the nitride semiconductor device of FIG.

[0008] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0009] Terms such as "first," "second," and "third" used in this disclosure are used merely to distinguish between objects and do not rank the objects. Additionally, the expression "at least one" used in this disclosure means one or more of a desired number of options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [First embodiment] A nitride semiconductor device 100 according to a first embodiment will be described with reference to FIGS. 1 to 6. In the present disclosure, components will be described based on mutually orthogonal X, Y, and Z axes shown in the drawings. The term "plan view" used in the present disclosure refers to viewing the nitride semiconductor device 100 in the Z-axis direction, unless explicitly stated otherwise. In the following description, for convenience, the +Z direction of the nitride semiconductor device 100 shown in FIG. 1 may be referred to as up, the -Z direction as down, the +X direction as right, and the -X direction as left. However, the up, down, left, and right directions of the nitride semiconductor device 100 are not limited to these orientations.

[0012] [1-1. Schematic structure of nitride semiconductor device] Fig. 1 is a schematic plan view of a nitride semiconductor device 100 having a surface-mount package structure. The nitride semiconductor device 100 includes a transistor chip 101. Fig. 2 is a plan view of the transistor chip 101 shown in Fig. 1. Fig. 3 is a schematic plan view of a transistor structure in the transistor chip 101, and Fig. 4 is a cross-sectional view taken along line F4-F4 shown in Fig. 3.

[0013] The transistor chip 101 includes a transistor 10 (see FIGS. 3 and 4) made of a nitride semiconductor. The transistor chip 101 also includes a plurality of electrode pads. As shown in FIG. 2, in the first embodiment, the transistor chip 101 includes a gate pad 102, a plurality of source pads 103, and a plurality of drain pads 104. The gate pad 102, the source pad 103, and the drain pad 104 are electrically connected to the transistor 10. Note that while FIG. 3 shows only two transistors 10, in reality, a large number of transistors 10 are arranged in a matrix (for example, in the X-axis direction and the Y-axis direction).

[0014] 1, the nitride semiconductor device 100 further includes a surge protection diode chip 111. The surge protection diode chip 111 includes a surge protection diode 112 (see FIG. 5) for protecting the transistor 10 from unexpected surges caused by, for example, static electricity. An example of the surge protection diode 112 is a TVS (Transient Voltage Suppressor) diode.

[0015] The nitride semiconductor device 100 includes a plurality of connecting members. In the first embodiment, the nitride semiconductor device 100 includes a plurality of first connecting members 121 each electrically connected to one of the plurality of source pads 103, a plurality of second connecting members 122 each electrically connected to one of the plurality of drain pads 104, and a third connecting member 123 electrically connected to the gate pad 102. The nitride semiconductor device 100 also includes a fourth connecting member 124 and a fifth connecting member 125.

[0016] The nitride semiconductor device 100 includes a plurality of lead frames. In the first embodiment, the nitride semiconductor device 100 includes a first lead frame 131 electrically connected to the first connection member 121, a second lead frame 132 electrically connected to the second connection member 122, and a third lead frame 133 electrically connected to the third connection member 123. The nitride semiconductor device 100 also includes a fourth lead frame 134 as a die pad. The transistor chip 101 is mounted on the fourth lead frame 134. The surge protection diode chip 111 is mounted on the third lead frame 133.

[0017] The fourth connection member 124 is electrically connected to the first lead frame 131 and one of the plurality of source pads 103. The fifth connection member 125 is electrically connected to the first lead frame 131 and the surge protection diode chip 111. The first to fifth connection members 121 to 125 and the first to fourth lead frames 131 to 134 will be described in detail later.

[0018] The nitride semiconductor device 100 includes a sealing resin 105 that seals the transistor chip 101 and the surge protection diode chip 111. For ease of understanding, only the outline of the sealing resin 105 is shown in FIG.

[0019] [1-2. Structure and layout of electrode pads] The gate pad 102, source pad 103, and drain pad 104 provided as electrode pads of the transistor chip 101 are formed of at least one conductive material selected from the group including, for example, titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), an AlCu alloy, nickel (Ni), and gold (Au). For example, the electrode pads may have a laminated structure including a metal layer and a plating layer covering the metal layer. In this case, the metal layer may have a four-layer structure including, for example, a Ti layer, a TiN layer, an AlCu layer, and a TiN layer, in that order from the top surface. The plating layer may have a structure in which, for example, a Cu layer, a Ni layer, and an Au layer are laminated in that order on the metal layer.

[0020] As shown in FIG. 2, the gate pad 102 may have a rectangular shape (e.g., a square shape) in a plan view. The gate pad 102 is located, for example, near one corner of a transistor chip 101 that has a rectangular shape in a plan view. A plurality of source pads 103 and a plurality of drain pads 104 are spaced apart from one another and arranged alternately in one direction (the X-axis direction in FIG. 2). Hereinafter, for convenience of explanation, the direction in which the source pads 103 and the drain pads 104 are arranged alternately in a plan view (the X-axis direction) will be referred to as a first direction X, and the direction perpendicular to the first direction X in a plan view (the Y-axis direction) will be referred to as a second direction Y. Note that, although two source pads 103 and two drain pads 104 are arranged in the example of FIG. 2, three or more source pads 103 and three or more drain pads 104 may be arranged.

[0021] The multiple source pads 103 may have the same or different shapes and sizes in a plan view. In the first embodiment, the multiple source pads 103 include a first source pad 103A located close to the gate pad 102 and one or more (one in the example of FIG. 2) second source pads 103B located farther from the gate pad 102 than the first source pad 103A. The first source pad 103A has a different shape from the second source pad 103B.

[0022] For example, the first source pad 103A includes a main region 103A1 and an extension region 103A2 extending from the main region 103A1 toward the gate pad 102. In the first source pad 103A, the main region 103A1 has a rectangular shape elongated in the second direction Y. The extension region 103A2 protrudes from one end of the main region 103A1 in the longitudinal direction (second direction Y) and extends in the first direction X. The first source pad 103A has an overall L-shape. The extension region 103A2 is adjacent to and spaced apart from the gate pad 102 in the first direction X. The second source pad 103B has, for example, a rectangular shape elongated in the second direction Y, i.e., a shape similar to the main region 103A1 of the first source pad 103A.

[0023] The multiple drain pads 104 may have the same or different shapes and sizes in a plan view. In the first embodiment, the multiple drain pads 104 include a first drain pad 104A located close to the gate pad 102 and one or more (one in the example of FIG. 2) second drain pads 104B located farther from the gate pad 102 than the first drain pad 104A. The first drain pad 104A has the same shape as the second drain pad 104B but is smaller in size than the second drain pad 104B.

[0024] For example, the first drain pad 104A has a rectangular shape that is elongated in the second direction Y. Similarly, the second drain pad 104B has a rectangular shape that is elongated in the second direction Y. The first drain pad 104A has a dimension that is shorter in the second direction Y than the second drain pad 104B. Furthermore, the first drain pad 104A has a dimension that is shorter in the second direction Y than each source pad 103 (first and second source pads 103A, 103B). One end of the first drain pad 104A in the longitudinal direction (second direction Y) is adjacent to but spaced apart from the gate pad 102 and the extension region 103A2 of the first source pad 103A in the second direction Y.

[0025] [1-3. Lead frame] The first to fourth lead frames 131 to 134 are formed of, for example, Cu or an alloy containing Cu. An example of the structure and layout of the first to fourth lead frames 131 to 134 will be described below with reference to FIG.

[0026] In the first embodiment, the first lead frame 131 includes a first region 131A and a second region 131B that are separated from each other and to which the same potential is applied. For example, a ground voltage is applied to the first region 131A and the second region 131B. The first region 131A includes multiple (two in the example of FIG. 1 ) lead ends 131E1 and 131E2 that are extended as source terminals outside the package (outside the nitride semiconductor device 100). The second region 131B includes a lead end 131E3 that is extended as a Kelvin source terminal outside the package. In one example, the back surfaces (rear side of the page) of the lead ends 131E1 and 131E2 are exposed from the sealing resin 105 as source terminals, and similarly, the back surface of the lead end 131E3 is exposed from the sealing resin 105 as a Kelvin source terminal.

[0027] The first region 131A and the second region 131B are adjacent to each other in the first direction X in which the first source pad 103A and the second source pad 103B are aligned. The first region 131A is disposed in a position facing all of the source pads 103 (i.e., the first and second source pads 103A and 103B) in the second direction Y. However, although the first region 131A faces the main region 103A1 (see FIG. 2) of the first source pad 103A in the second direction Y, it does not face the extension region 103A2 (see FIG. 2) of the first source pad 103A in the second direction Y.

[0028] The first region 131A is electrically connected to the source pad 103 by a first connection member 121. In the example of FIG. 1, the first and second source pads 103A, 103B are each connected to the first region 131A by one first connection member 121. Therefore, a ground voltage is applied to the first and second source pads 103A, 103B via the first region 131A and each first connection member 121.

[0029] The second region 131B faces the extension region 103A2 (see FIG. 2) of the first source pad 103A in the second direction Y. The second region 131B may face a part of the main region 103A1 (see FIG. 2) of the first source pad 103A in the second direction Y. The second region 131B is electrically connected to the extension region 103A2 of the first source pad 103A by the fourth connection member 124. Therefore, a ground voltage is applied to the first source pad 103A via the second region 131B and the fourth connection member 124.

[0030] A given power supply voltage is applied to the second lead frame 132. The second lead frame 132 includes multiple (four in the example of FIG. 1) lead ends 132E1, 132E2, 132E3, and 132E4 that are drawn out of the package as drain terminals. In one example, the back surfaces of the lead ends 132E1 to 132E4 are exposed from the sealing resin 105 as drain terminals. The second lead frame 132 is electrically connected to the drain pad 104 by a second connection member 122. In the example of FIG. 1, the first and second drain pads 104A and 104B are each connected to the second lead frame 132 by one second connection member 122. Therefore, a power supply voltage is applied to the first and second drain pads 104A and 104B via the second lead frame 132 and each second connection member 122.

[0031] A given gate control voltage is applied to the third lead frame 133. The third lead frame 133 includes a lead end 133E that is drawn out of the package as a gate terminal. In one example, the back surface of the lead end 133E is exposed from the sealing resin 105 as the gate terminal. The third lead frame 133 is electrically connected to the gate pad 102 by a third connection member 123. Therefore, a gate control voltage is applied to the gate pad 102 via the third lead frame 133 and the third connection member 123.

[0032] The third lead frame 133 further includes a diode mounting region 133A for mounting the surge protection diode chip 111. The diode mounting region 133A has, for example, a rectangular shape that is elongated in the first direction X, and a lead end 133E extends in the second direction Y from one end (the right end in FIG. 1) of the diode mounting region 133A in the longitudinal direction. The third lead frame 133 has an L-shape as a whole.

[0033] The third lead frame 133 is provided adjacent to but spaced apart from the second region 131B of the first lead frame 131 in the first direction X. In the example of FIG. 1, the diode mounting region 133A is adjacent to but spaced apart from the second region 131B in the first direction X. For example, the surge protection diode chip 111 is mounted in the elongated rectangular diode mounting region 133A at a position closer to the second region 131B (on the left side in FIG. 1). The third connecting member 123 is connected to the diode mounting region 133A at a position farther from the second region 131B in the first direction X than the surge protection diode chip 111 (on the right side in FIG. 1).

[0034] The surge protection diode chip 111 includes a front surface electrode 111A provided as an anode electrode and a back surface electrode (not shown) provided as a cathode electrode. The surge protection diode chip 111 is mounted on a diode mounting region 133A of the third lead frame 133 by a conductive bonding material (not shown) such as solder or conductive paste (e.g., Ag paste) bonded to the back surface electrode. The front surface electrode 111A of the surge protection diode chip 111 is electrically connected to the second region 131B of the first lead frame 131 by a fifth connecting member 125.

[0035] As described above, the fourth lead frame 134 is provided as a die pad for the transistor chip 101. The fourth lead frame 134 also functions as a heat dissipation member for dissipating heat generated in the transistor chip 101 to the outside. The fourth lead frame 134 has a rectangular shape in a plan view, and has, for example, a size equal to or larger than that of the transistor chip 101. The transistor chip 101 is mounted on the fourth lead frame 134 with a conductive bonding material (not shown) such as solder or a conductive paste (for example, Ag paste).

[0036] [1-4. Connecting parts] The first to fifth connection members 121 to 125 are formed of any conductive member (conductive material). In the first embodiment, the first and second connection members 121, 122 are each formed of a bridge-shaped conductive member. A bridge-shaped conductive member may be called a conductive clip or simply a clip. An example of a clip material is Cu, and a clip made of Cu may be called a Cu clip. Meanwhile, the third to fifth connection members 123 to 125 are each conductive wires (bonding wires) formed by a wire bonding device, and are formed of a conductor such as Au, Al, or Cu.

[0037] Compared to wires, clips have advantages such as large current capacity, low resistance, low inductance, and high heat dissipation. Because the first and second connecting members 121 and 122 are located on the current path between the drain and the source, by using clips for the first and second connecting members 121 and 122, it is possible to take advantage of the above advantages and create a structure suitable for power transistor applications.

[0038] On the other hand, wires have advantages over clips, such as ease of mounting and high design freedom. By using wires for the third to fifth connecting members 123 to 125, it is possible to easily mount the third to fifth connecting members 123 to 125 while flexibly responding to changes in the size of the transistor chip 101 and changes in the positions (relative positional relationships) among the gate pad 102, source pad 103 (particularly, the extension region 103A2 of the first source pad 103A), first lead frame 131 (particularly, the second region 131B), and third lead frame 133 (particularly, the diode mounting region 133A).

[0039] With respect to the lengths of the third to fifth connection members 123 to 125 (wire lengths in the first embodiment), the fourth connection member 124 may have a length shorter than the third connection member 123. The fourth connection member 124 may also have a length shorter than the fifth connection member 125. The fourth connection member 124 forms a current path between the extension region 103A2 of the first source pad 103A and the second region 131B of the first lead frame 131, which includes the Kelvin source terminal (lead end 131E3). That is, the fourth connection member 124 is located on the current path between the Kelvin source terminal and the source electrode of the transistor 10. Therefore, by shortening the length of the fourth connection member 124 as much as possible, the parasitic inductance coupled to the Kelvin source terminal can be reduced. From this perspective, in the first embodiment, the fourth connection member 124 is configured to have a length shorter than the third connection member 123 and also shorter than the fifth connection member 125.

[0040] As an example, as described above, the second region 131B of the first lead frame 131 is disposed at a position facing the extension region 103A2 of the first source pad 103A in the second direction Y. This makes it possible to minimize the angle formed by the fourth connection member 124 and a line segment extending in the second direction Y and to connect the second region 131B and the extension region 103A2 over the shortest distance, thereby minimizing the length of the fourth connection member 124.

[0041] 1, the surge protection diode chip 111 connected to the second region 131B by the fifth connecting member 125 is mounted in the diode mounting region 133A of the third lead frame 133 at a position closer to the second region 131B (on the left side in FIG. 1). This arrangement allows the length of the fifth connecting member 125 to be shortened, and by making the length of the fourth connecting member 124 shorter than the length of the fifth connecting member 125 set in this manner, the length of the fourth connecting member 124 can be further minimized.

[0042] 1, the third connection member 123 is connected to the diode mounting region 133A at a position farther from the second region 131B in the first direction X than the surge protection diode chip 111 (to the right in FIG. 1). Furthermore, the third lead frame 133 does not face the gate pad 102 in the second direction Y. In this arrangement, the angle between the fourth connection member 124 and a line segment extending in the second direction Y may be smaller than the angle between the third connection member 123 and a line segment extending in the second direction Y. This allows the length of the fourth connection member 124 to be shorter than the length of the third connection member 123.

[0043] [1-5. Nitride Semiconductor Transistors] Next, a structural example of the transistor 10 formed on the transistor chip 101 will be described with reference to Figures 3 and 4. Below, the cross-sectional structure of the transistor 10 will first be described with reference to Figure 4, and then the planar layout of the transistor 10 will be described with reference to Figure 3.

[0044] 4 is a schematic cross-sectional view showing the structure of a HEMT using GaN as an example of transistor 10. Note that Fig. 4 does not show the sealing resin 105, electrode pads (gate pad 102, source pad 103, drain pad 104), interlayer insulating layers located below the electrode pads, and internal wiring structures (gate wiring, source wiring, drain wiring, etc.).

[0045] The transistor 10 includes a semiconductor substrate 12 and a buffer layer 14 located on the semiconductor substrate 12. The transistor 10 further includes an electron transit layer 16 and an electron supply layer 18 located on the electron transit layer 16.

[0046] The semiconductor substrate 12 may be formed of Si, silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the semiconductor substrate 12 is a Si substrate. The semiconductor substrate 12 may have a thickness of, for example, 100 μm or more and 1500 μm or less. In one example, the thickness of the semiconductor substrate 12 is 250 μm.

[0047] The buffer layer 14 includes one or more nitride semiconductor layers. The electron transport layer 16 is located on the buffer layer 14. The buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transport layer 16.

[0048] For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different Al compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. To suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0049] The electron transit layer 16 may be, for example, a GaN layer. The electron transit layer 16 may have a thickness of, for example, 0.5 μm or more and 2 μm or less. To suppress leakage current in the electron transit layer 16, impurities may be introduced into a portion of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the impurity concentration in the electron transit layer 16 may be, for example, 4×10 16 cm -3 It can be more than that.

[0050] The electron supply layer 18 has a larger band gap than the electron transit layer 16. The electron supply layer 18 may be, for example, an AlGaN layer. Since the band gap increases as the Al composition increases, the electron supply layer 18, which is an AlGaN layer, has a larger band gap than the electron transit layer 16, which is a GaN layer. For example, the electron supply layer 18 is an Al GaN layer with an Al composition ratio X. X Ga (1-X)It is composed of N. The Al composition ratio X may be 0.1 < X < 0.4, and preferably 0.1 < X < 0.3. The electron supply layer 18 may have a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the thickness of the electron supply layer 18 is 8 nm or more.

[0051] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, 2DEG20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0052] The transistor 10 further includes a gate layer 22 located on the electron supply layer 18 and a gate electrode 24 located on the gate layer 22. The gate layer 22 is partially provided on the electron supply layer 18.

[0053] The gate layer 22 is composed of a nitride semiconductor containing acceptor-type impurities. For example, the gate layer 22 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. In one example, the gate layer 22 is GaN containing at least one of Mg and Zn as an impurity.

[0054] The gate electrode 24 includes one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. In another example, the gate electrode 24 includes a first metal layer made of Ti and a second metal layer formed of TiN and located on the first metal layer. The gate electrode 24 forms a Schottky junction with the gate layer 22. The gate electrode 24 is partially disposed on the gate layer 22. The gate electrode 24 may have a thickness of, for example, 50 nm to 200 nm.

[0055] The transistor 10 further includes a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 is formed of at least one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON), for example. In one example, the passivation layer 26 is formed of a material containing SiN. The passivation layer 26 may have a thickness of, for example, 80 nm to 150 nm.

[0056] The passivation layer 26 includes a source opening 26A and a drain opening 26B spaced apart from each other in the first direction X. The gate layer 22 is located between the source opening 26A and the drain opening 26B. The gate layer 22 is located closer to the source opening 26A than to the drain opening 26B.

[0057] The transistor 10 includes a source electrode 28 in contact with the electron supply layer 18 through a source opening 26A, and a drain electrode 30 in contact with the electron supply layer 18 through a drain opening 26B. The source electrode 28 and the drain electrode 30 may include one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be formed by combining two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, an AlCu layer, and the like. In one example, the source electrode 28 and the drain electrode 30 have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including, from the top surface side, a Ti layer, an AlCu layer, a Ti layer, and a TiN layer.

[0058] The source electrode 28 includes a source contact portion 28A filled in the source opening 26A and an extension portion 28B formed integrally with the source contact portion 28A and positioned on the passivation layer 26. The source contact portion 28A is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 via the source opening 26A. The extension portion 28B functions as a source field plate electrode.

[0059] 4, extension 28B (source field plate electrode) covers the entire gate electrode 24 and gate layer 22. Extension 28B includes end 28BE facing drain electrode 30 as a source field plate electrode end. Extension 28B (source field plate electrode) plays a role in alleviating electric field concentration near the end of gate layer 22 when a high voltage is applied between the source and drain in an off state in which 2DEG 20 in the region of electron transit layer 16 directly below gate layer 22 has disappeared.

[0060] The drain electrode 30 includes a drain contact portion 30A filled in the drain opening 26B. The drain contact portion 30A is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 via the drain opening 26B.

[0061] In the transistor 10 configured as described above, the gate layer 22 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. As a result, in the region immediately below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. As a result, when a gate control voltage that turns off the transistor 10 is applied to the gate electrode 24 (for example, when the gate-source voltage is 0 V or lower), a 2DEG 20 is not formed in the region of the electron transit layer 16 immediately below the gate layer 22. On the other hand, a 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the gate layer 22.

[0062] In this way, the presence of the gate layer 22 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region of the electron transit layer 16 directly below the gate layer 22, thereby achieving normally-off operation of the transistor. When an appropriate gate control voltage (on voltage) is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the region of the electron transit layer 16 directly below the gate layer 22, establishing electrical conduction between the source and drain.

[0063] Although not shown, the gate electrode 24 is electrically connected to the gate pad 102 by a through conductor (via) that penetrates the interlayer insulating layer and a gate wiring. The source electrode 28 is electrically connected to the source pad 103 by a through conductor (via) that penetrates the interlayer insulating layer and a source wiring. The drain electrode 30 is electrically connected to the drain pad 104 by a through conductor (via) that penetrates the interlayer insulating layer and a drain wiring.

[0064] Next, the planar layout of transistor 10 in the active region will be described with reference to Figure 3. Note that Figure 3 does not show sealing resin 105, electrode pads (gate pad 102, source pad 103, drain pad 104), interlayer insulating layers located below the electrode pads, or internal wiring structures (gate wiring, source wiring, drain wiring, etc.). Furthermore, passivation layer 26 is also not shown. For ease of understanding, Figure 3 shows end 28BE of extension 28B (source field plate electrode) shown in Figure 4 with a dashed line.

[0065] As shown in FIG. 3, in the active region of the transistor 10, the source contact portion 28A, the gate electrode 24 (gate layer 22), and the drain contact portion 30A are arranged side by side in the first direction X. A combination of the source contact portion 28A, the gate electrode 24 (gate layer 22), and the drain contact portion 30A arranged side by side in the first direction X constitutes one HEMT cell 10HC. Note that although the example of FIG. 3 shows two HEMT cells 10HC arranged side by side in the first direction X, in reality, more HEMT cells 10HC may be arranged. The number of HEMT cells 10HC is not particularly limited, and the transistor 10 may include one or more HEMT cells 10HC.

[0066] [1-6. Functions of nitride semiconductor devices] Next, the operation of the nitride semiconductor device 100 will be described with reference to FIGS. Fig. 5 is a diagram schematically showing a circuit for controlling the gate-source voltage of the transistor 10. Fig. 6 is a diagram schematically showing a drain-source current path Pd and a gate-Kelvin source charge / discharge path Pg in the nitride semiconductor device 100 of Fig. 1.

[0067] As shown in FIG. 5, a parasitic inductance Ls resulting from, for example, the source-side wiring of the package (first connection member 121, first region 131A of first lead frame 131, etc.) is coupled to the source terminal Ts (lead ends 131E1, 131E1, 131E3) of transistor 10. This parasitic inductance Ls generates electromotive noise due to changes in the drain current flowing through the drain-source current path Pd (see FIG. 6) when transistor 10 is turned on based on the application of voltage Vg1. This electromotive noise increases the switching loss of transistor 10.

[0068] In the first embodiment, the Kelvin source terminal Tks (lead terminal 131E3) is connected to the first source pad 103A. The same potential as that of the source terminal Ts is applied to this Kelvin source terminal Tks. In the first embodiment, in the first lead frame 131, the second region 131B including the Kelvin source terminal Tks (lead terminal 131E3) is separated from the first region 131A including the source terminal Ts (lead terminals 131E1, 131E1, 131E3).

[0069] Therefore, the gate-Kelvin source charge / discharge path Pg (see FIG. 6), which controls the gate-source voltage of the transistor 10 using the Kelvin source terminal Tks, is separated from the drain-source current path Pd. Therefore, the gate-source voltage, which is controlled based on the gate control voltage Vg2 applied by a gate drive circuit (not shown) connected to the gate terminal Tg (lead terminal 133E) and the Kelvin source terminal Tks (lead terminal 131E3), is not affected by the electromotive noise. This makes it possible to suppress switching losses caused by electromotive noise and achieve high-speed switching operations. Furthermore, because the gate-Kelvin source charge / discharge path Pg is not affected by electromotive noise, malfunctions such as self-turn-on can also be suppressed.

[0070] 5, the gate-Kelvin source charge / discharge path Pg includes a parasitic inductance Lg coupled to the gate terminal Tg and a parasitic inductance Lks coupled to the Kelvin source terminal Tks. For example, the parasitic inductance Lg is caused by the gate-side wiring of the package (the third connection member 123, the third lead frame 133, etc.), and the parasitic inductance Lks is caused by the Kelvin source-side wiring of the package (the fourth connection member 124, the second region 131B of the first lead frame 131, etc.). These parasitic inductances Lg and Lks also fluctuate the gate-source voltage of the transistor 10, causing switching loss.

[0071] In the first embodiment, the fourth connection member 124 connected to the Kelvin source terminal Tks is disposed closer to the third lead frame 133 than the first connection member 121. The fourth connection member 124 is electrically connected to the second region 131B of the first lead frame 131 and the extension region 103A2 of the first source pad 103A. This minimizes the length of the fourth connection member 124, thereby minimizing the parasitic inductance Lks included in the gate-Kelvin source charge / discharge path Pg. This makes it possible to suppress fluctuations in the gate-source voltage caused by the parasitic inductance Lks.

[0072] In the first embodiment, a surge protection diode 112 is connected to the gate-Kelvin source charge / discharge path Pg. The surge protection diode 112 prevents an unexpected surge caused by static electricity or the like from being applied to the gate electrode 24 of the transistor 10.

[0073] The surge protection diode 112 (surge protection diode chip 111) is mounted on the third lead frame 133 and is electrically connected to the second region 131B of the first lead frame 131 by a fifth connection member 125. That is, like the fourth connection member 124 described above, the fifth connection member 125 connected to the surge protection diode chip 111 is disposed at a position closer to the third lead frame 133 than the first connection member 121. This arrangement makes it possible to connect the surge protection diode 112 between the gate and source of the transistor 10 using the minimum wiring path. This makes it possible to suppress the effects of noise applied to the surge protection diode 112 while suitably protecting the transistor 10 from surges.

[0074] [1-7. Advantages of nitride semiconductor devices] The nitride semiconductor device 100 of the first embodiment has the following advantages. (1-1) The nitride semiconductor device 100 includes a first connection member 121 connected between the source pad 103 and a first lead frame 131, a second connection member 122 connected between the drain pad 104 and a second lead frame 132, and a third connection member 123 connected between the gate pad 102 and a third lead frame 133. The nitride semiconductor device 100 further includes a fourth connection member 124 connected between the source pad 103 and the first lead frame 131 at a position closer to the third lead frame 133 than the first connection member 121. The first lead frame 131 includes a first region 131A to which the first connection member 121 is connected and a second region 131B to which the fourth connection member 124 is connected.

[0075] In this configuration, the source terminal Ts (lead terminals 131E1 and 131E2) can be assigned to the first region 131A, and the Kelvin source terminal Tks (lead terminal 131E3) can be assigned to the second region 131B, to which the same potential as that of the first region 131A is applied. Furthermore, by providing the fourth connection member 124 closer to the third lead frame 133 than the first connection member 121, the gate-Kelvin source charge / discharge path Pg for controlling the gate-source voltage can be electrically isolated from the drain-source current path Pd. This prevents the drain current flowing through the drain-source current path Pd from flowing into the gate-Kelvin source charge / discharge path Pg, making it possible to control the gate-source voltage without being affected by electromotive noise due to the parasitic inductance Ls. As a result, switching loss and malfunctions such as self-turn-on caused by electromotive noise can be suppressed.

[0076] (1-2) The nitride semiconductor device 100 further includes a surge protection diode chip 111 mounted on a third lead frame 133, and a fifth connection member 125 connected to the first lead frame 131 and the surge protection diode chip 111 at a position closer to the third lead frame 133 than the first connection member 121. This configuration makes it possible to connect the surge protection diode 112 between the gate and source of the transistor 10 in the gate-Kelvin source charge / discharge path Pg using the minimum wiring path. This makes it possible to suppress the effects of noise applied to the surge protection diode 112 and to suitably protect the transistor 10 from surges.

[0077] (1-3) The fourth connecting member 124 has a length shorter than that of the third connecting member 123. In this configuration, the parasitic inductance Lks coupled to the Kelvin source terminal Tks (lead end 131E3) can be reduced, thereby suppressing fluctuations in the gate-source voltage caused by the parasitic inductance Lks.

[0078] (1-4) The fourth connecting member 124 also has a length shorter than that of the fifth connecting member 125. In this configuration, the parasitic inductance Lks coupled to the Kelvin source terminal Tks (lead end 131E3) can be further reduced, thereby further suppressing fluctuations in the gate-source voltage caused by the parasitic inductance Lks.

[0079] (1-5) The second region 131B is physically separated from the first region 131A in the first lead frame 131. This prevents the drain current flowing through the drain-source current path Pd from flowing from the first region 131A into the second region 131B (gate-Kelvin-source charge / discharge path Pg), thereby effectively eliminating the influence of electromotive noise due to the parasitic inductance Ls.

[0080] (1-6) The multiple source pads 103 include a first source pad 103A and a second source pad 103B. The first source pad 103A includes a main region 103A1 to which a first connection member 121 is connected and an extension region 103A2 extending from the main region 103A1 toward the gate pad 102, and a fourth connection member 124 is connected to the extension region 103A2. By providing such an extension region 103A2, the gate-Kelvin source charge / discharge path Pg can be electrically separated from the drain-source current path Pd. Furthermore, in this configuration, one of the multiple source pads 103 can be connected to the Kelvin source terminal Tks without providing an additional source pad.

[0081] (1-7) The first and second connecting members 121, 122 are formed by conductive clips having a bridge shape. Clips have advantages such as large current capacity, low resistance, low inductance, and high heat dissipation. Since the first and second connecting members 121, 122 are located on the drain-source current path Pd, employing clips for the first and second connecting members 121, 122 makes it possible to take advantage of the above advantages and achieve a structure suitable for power transistor applications.

[0082] (1-8) The third to fifth connection members 123 to 125 are formed of conductive wires. Wires have advantages such as ease of mounting and high design flexibility. The position of the gate-Kelvin-source charge / discharge path Pg can change depending on the size of the transistor chip 101 and the positions (relative positional relationships) among the gate pad 102, the source pad 103 (particularly, the extension region 103A2 of the first source pad 103A), the first lead frame 131 (particularly, the second region 131B), and the third lead frame 133 (particularly, the diode mounting region 133A). By using wires for the third to fifth connection members 123 to 125, it is possible to flexibly accommodate changes in the position of the gate-Kelvin-source charge / discharge path Pg, while easily mounting the third to fifth connection members 123 to 125.

[0083] (1-9) The transistor 10 is configured as a HEMT using GaN. This allows the nitride semiconductor device 100 having the advantages of (1-1) to (1-8) above to be used as a power device using a GaN-HEMT.

[0084] [Second embodiment] Next, a nitride semiconductor device 200 according to a second embodiment will be described with reference to FIGS. 7 and 8. The second embodiment differs from the first embodiment in that the structure of the first lead frame 131 is changed. The other configurations are the same as those of the first embodiment. Below, a description of the same components as those of the first embodiment will be omitted, and only components different from those of the first embodiment will be described.

[0085] 7 is a schematic plan view of a nitride semiconductor device 200 according to the second embodiment. As shown in FIG. 7, the first lead frame 131 according to the second embodiment is configured as a single lead frame and is not separated into two regions (a first region 131A and a second region 131B; see FIG. 1). Even with this configuration, the lead ends 131E1 and 131E2 of the first lead frame 131 can be used as a source terminal Ts (see FIG. 5), while the lead end 131E3 of the first lead frame 131 can be used as a Kelvin source terminal Tks (see FIG. 5).

[0086] Fig. 8 is a diagram schematically illustrating a drain-source current path Pd in ​​a nitride semiconductor device 200. Note that the drain-side current path of the drain-source current path Pd is the same as that in the first embodiment (see Fig. 6), and is therefore not shown in Fig. 8. Furthermore, the gate-Kelvin source charge / discharge path Pg is also the same as that in the first embodiment (see Fig. 6), and is therefore not shown.

[0087] 8, in the second embodiment, the drain current branches along the drain-source current path Pd from the first connection member 121 to the lead ends 131E1, 131E2, and 131E3 of the first lead frame 131. That is, the drain current flowing from the second source pad 103B to the first lead frame 131 via the first connection member 121 branches to the lead ends 131E1 and 131E2, and the drain current flowing from the first source pad 103A to the first lead frame 131 via the first connection member 121 branches to the lead ends 131E2 and 131E3.

[0088] 8, approximately ¾ of the total drain current flowing through the two first connection members 121 flows through the lead terminals 131E1 and 131E2, and approximately ¼ of the total drain current flows through the lead terminal 131E3. Therefore, although the influence of electromotive noise due to the parasitic inductance Ls is not zero compared to the first embodiment, by using the lead terminal 131E3 as the Kelvin source terminal Tks (see FIG. 5), the influence of the above-mentioned electromotive noise on the gate-source voltage can be significantly reduced.

[0089] As a result, even when the first lead frame 131 of the second embodiment is used, the same advantages as those (1-1) to (1-4) and (1-6) to (1-9) described in the first embodiment can be obtained.

[0090] [Example of change] The above-described embodiments can be modified, for example, as follows: The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above-described embodiments will be assigned the same reference numerals as in the above-described embodiments, and their description will be omitted.

[0091] The gate pad 102 is not limited to being located near a corner of the transistor chip 101. For example, the gate pad 102 may be located near the center of one of the sides of the transistor chip 101.

[0092] The plurality of source pads 103 may all have the same shape. Furthermore, the plurality of drain pads 104 may all have the same shape. Of the multiple source pads 103, the source pad 103 closest to the gate pad 102 may be connected to only the fourth connection member 124 without connecting the first connection member 121.

[0093] The first source pad 103A does not have to include the extension region 103A2. For example, the width (dimension in the first direction X) of the first source pad 103A may be made larger overall than the width of the second source pad 103B, and the fourth connection member 124 may be connected to the first source pad 103A.

[0094] In the first embodiment, the second region 131B of the first lead frame 131 does not necessarily have to face the extending region 103A2 of the first source pad 103A in the second direction Y.

[0095] The third lead frame 133 may face a part or the whole of the gate pad 102 in the second direction Y. The transistor chip 101 may be the same size as the fourth lead frame 134.

[0096] The transistor 10 is not limited to a HEMT using GaN, but may be any other nitride semiconductor transistor. The transistor 10 is not limited to the structure shown in Figures 3 and 4. For example, the gate layer 22 is not limited to the rectangular cross-sectional shape shown in Figure 4. For example, the gate layer 22 may be formed to have a convex cross-sectional shape including a main body portion (e.g., a ridge-shaped main body portion) in which the gate electrode 24 is located and two extension portions extending from the main body portion toward the source contact portion 28A and the drain contact portion 30A.

[0097] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0098] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X axis direction may be the vertical direction, or the Y axis direction may be the vertical direction.

[0099] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. [Note] The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0100] [Appendix A1] A transistor chip (101) including a transistor (10) made of a nitride semiconductor, and a gate pad (102), a source pad (103), and a drain pad (104) electrically connected to the transistor (10); a first connection member (121) electrically connected to the source pad (103); a first lead frame (131) electrically connected to the first connection member (121); a second connection member (122) electrically connected to the drain pad (104); a second lead frame (132) electrically connected to the second connection member (122); a third connection member (123) electrically connected to the gate pad (102); a third lead frame (133) electrically connected to the third connection member (123); a fourth lead frame (134) on which the transistor chip (101) is mounted; a surge protection diode chip (111) mounted on the third lead frame (133); a fourth connection member (124) electrically connected to the first lead frame (131) and the source pad (103) at a position closer to the third lead frame (133) than the first connection member (121); a fifth connection member (125) electrically connected to the first lead frame (131) and the surge protection diode chip (111) at a position closer to the third lead frame (133) than the first connection member (121); A nitride semiconductor device (100; 200) comprising:

[0101] [Appendix A2] The nitride semiconductor device (100; 200) according to Appendix A1, wherein the fourth connection member (124) has a length shorter than that of the third connection member (123).

[0102] [Appendix A3] The nitride semiconductor device (100; 200) according to appendix A1 or A2, wherein the fourth connecting member (124) has a length shorter than that of the fifth connecting member (125).

[0103] [Appendix A4] The first lead frame (131) includes a first region (131A) and a second region (131B) that are separated from each other and configured to have the same potential applied thereto; the second region (131B) is provided closer to the third lead frame (133) than the first region (131A); the first connecting member (121) is connected to the first region (131A); The nitride semiconductor device (100) according to any one of Appendices A1 to A3, wherein the fourth connection member (124) is connected to the second region (131B).

[0104] [Appendix A5] The source pad (103A) includes a main region (103A1) and an extension region (103A2) extending from the main region (103A1) toward the gate pad (102), The nitride semiconductor device (100; 200) according to any one of Appendices A1 to A4, wherein the fourth connection member (124) is connected to the extension region (103A2).

[0105] [Appendix A6] the first lead frame (131) includes a first region (131A) and a second region (131B) that are separated from each other and configured to have the same potential applied thereto, and that are arranged side by side in a first direction (X) in a plan view; the second region (131B) is provided closer to the third lead frame (133) than the first region (131A) in the first direction (X); The source pad (103) includes a main region (103A1) extending in a second direction (Y) perpendicular to the first direction (X) in a plan view, and an extension region (103A2) extending in the first direction (X) from the main region (103A1) toward the gate pad (102), the extension region (103A2) faces the second region (131B) in the second direction (Y); the first connecting member (121) is connected to the first region (131A) and the main region (103A1); The nitride semiconductor device (100) according to any one of Appendices A1 to A3, wherein the fourth connection member (124) is connected to the second region (131B) and the extension region (103A2).

[0106] [Appendix A7] The nitride semiconductor device (100; 200) according to any one of Appendices A1 to A6, wherein the first connecting member (121) and the second connecting member (122) are conductive clips having a bridge shape.

[0107] [Appendix A8] The nitride semiconductor device (100; 200) according to any one of Appendices A1 to A7, wherein the third connecting member (123), the fourth connecting member (124), and the fifth connecting member (125) are conductive wires.

[0108] [Appendix A9] The source pad (103) is one of a plurality of source pads (103A, 103B) provided on the transistor chip (101), The drain pad (104) is one of a plurality of drain pads (104A, 104B) provided on the transistor chip (101), the plurality of source pads (103A, 103B) and the plurality of drain pads (104A, 104B) are arranged alternately one by one in one direction in a plan view, the first connection member (121) is one of a plurality of first connection members (121) each connected to one of the plurality of source pads (103A, 103B); The nitride semiconductor device (100; 200) according to any one of Appendices A1 to A8, wherein the second connection member (122) is one of a plurality of second connection members (122) each connected to one of the plurality of drain pads (104A, 104B).

[0109] [Appendix A10] One of the plurality of source pads (103A, 103B) includes a main region (103A1) and an extension region (103A2) extending from the main region (103A1) toward the gate pad (102), The nitride semiconductor device (100; 200) according to Appendix A9, wherein the fourth connection member (124) is connected to the extension region (103A1).

[0110] [Appendix A11] The transistor (10) an electron transit layer (16); an electron supply layer (18) located on the electron transit layer (16) and having a band gap larger than that of the electron transit layer (16); a gate layer (22) located on the electron supply layer (18) and containing acceptor-type impurities; a gate electrode (24) located on the gate layer (22); a source electrode (28) and a drain electrode (30) located in contact with the electron supply layer (18); The nitride semiconductor device (100; 200) according to any one of Appendices A1 to A10, comprising:

[0111] [Appendix B1] A transistor chip (101) including a transistor (10) made of a nitride semiconductor, and a gate pad (102), a source pad (103), and a drain pad (104) electrically connected to the transistor (10); a first connection member (121) electrically connected to the source pad (103); a first lead frame (131A) electrically connected to the first connection member (121); a second connection member (122) electrically connected to the drain pad (104); a second lead frame (132) electrically connected to the second connection member (122); a third connection member (123) electrically connected to the gate pad (102); a third lead frame (133) electrically connected to the third connection member (123); a fourth lead frame (134) on which the transistor chip (101) is mounted; a surge protection diode chip (111) mounted on the third lead frame (133); a fifth lead frame (131B) provided closer to the third lead frame (133) than the first lead frame (131A); a fourth connection member (124) electrically connected to the fifth lead frame (131B) and the source pad (103A); a fifth connection member (125) electrically connected to the surge protection diode chip (111) and the fifth lead frame (131B); A nitride semiconductor device (100) comprising: [Explanation of symbols]

[0112] 10...Transistor 12...Semiconductor substrate 14...Buffer layer 16...Electron transit layer 18...electron supply layer 20...Two-dimensional electron gas 22...Gate layer 24...Gate electrode 26...passivation layer 28...Source electrode 28A...Source contact part 30...Drain electrode 30A...Drain contact 100, 200...Nitride semiconductor device 101...Transistor chip 102...Gate pad 103...Sauce Pad 103A...First source pad 103A1…Main area 103A2…extension area 103B...Second source pad 104...Drain pad 104A...First drain pad 104B...Second drain pad 105...Sealing resin 111...Surge protection diode chip 112...Surge protection diode 121...first connecting member 122...second connecting member 123...Third connecting member 124...Fourth connecting member 125...fifth connecting member 131...First lead frame 131A...First Area 131B...Second Area 131E1, 131E2...Lead end (source terminal Ts) 131E3...Lead end (Kelvin source terminal Ts) 132...Second lead frame 132E1, 132E2, 132E32, 132E4...Lead end (drain terminal Td) 133...Third lead frame 133A...Diode mounting area 133E...Lead end (gate terminal Td) 134...4th lead frame X…first direction Y...Second direction

Claims

1. a transistor chip including a transistor made of a nitride semiconductor and a gate pad, a source pad, and a drain pad electrically connected to the transistor; a first connection member electrically connected to the source pad; a first lead frame electrically connected to the first connection member; a second connection member electrically connected to the drain pad; a second lead frame electrically connected to the second connection member; a third connection member electrically connected to the gate pad; a third lead frame electrically connected to the third connection member; a fourth lead frame on which the transistor chip is mounted; a surge protection diode chip mounted on the third lead frame; a fourth connection member electrically connected to the first lead frame and the source pad at a position closer to the third lead frame than the first connection member; a fifth connection member electrically connected to the first lead frame and the surge protection diode chip at a position closer to the third lead frame than the first connection member; A nitride semiconductor device comprising:

2. The nitride semiconductor device according to claim 1 , wherein said fourth connecting member has a length shorter than that of said third connecting member.

3. The nitride semiconductor device according to claim 1 , wherein said fourth connecting member has a length shorter than that of said fifth connecting member.

4. the first lead frame includes a first region and a second region that are separated from each other and configured to have the same potential applied thereto; the second region is provided closer to the third lead frame than the first region, the first connection member is connected to the first region; The nitride semiconductor device according to claim 1 , wherein said fourth connection member is connected to said second region.

5. The nitride semiconductor device according to claim 4 , wherein said fourth connecting member has a length shorter than that of said third connecting member.

6. The nitride semiconductor device according to claim 4 , wherein said fourth connecting member has a length shorter than that of said fifth connecting member.

7. the source pad includes a main region and an extension region extending from the main region toward the gate pad; The nitride semiconductor device according to claim 1 , wherein said fourth connection member is connected to said extension region.

8. the first lead frame includes a first region and a second region that are separated from each other and configured to have the same potential applied thereto, and that are arranged side by side in a first direction in a plan view; the second region is provided closer to the third lead frame than the first region in the first direction; the source pad includes a main region extending in a second direction perpendicular to the first direction in a plan view, and an extension region extending in the first direction from the main region toward the gate pad; the extension region faces the second region in the second direction, the first connecting member is connected to the first region and the main region, The nitride semiconductor device according to claim 1 , wherein said fourth connection member is connected to said second region and said extension region.

9. The nitride semiconductor device according to claim 1 , wherein said first connecting member and said second connecting member are conductive clips having a bridge shape.

10. The nitride semiconductor device according to claim 1 , wherein said third connecting member, said fourth connecting member, and said fifth connecting member are conductive wires.

11. the source pad is one of a plurality of source pads provided on the transistor chip, the drain pad is one of a plurality of drain pads provided on the transistor chip, the plurality of source pads and the plurality of drain pads are arranged alternately one by one in one direction in a plan view, the first connection member is one of a plurality of first connection members each connected to one of the plurality of source pads; 2. The nitride semiconductor device according to claim 1, wherein said second connection member is one of a plurality of second connection members each connected to one of said plurality of drain pads.

12. one of the plurality of source pads includes a main region and an extension region extending from the main region toward the gate pad; The nitride semiconductor device according to claim 11 , wherein said fourth connection member is connected to said extension region.

13. The transistor is an electron transit layer; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing an acceptor-type impurity; a gate electrode located on the gate layer; a source electrode and a drain electrode located in contact with the electron supply layer; 13. The nitride semiconductor device according to claim 1, comprising:

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