Semiconductor device

Abstract

To suppress consumption power during a waiting period for the generation of a processing request.SOLUTION: A PLL circuit outputs an output signal when the frequency of the output signal converges to a locked state after startup. A CPU determines whether a processing request is necessary at a fixed period, outputs a startup command when it receives a processing request from an external device for generating the processing request if required, and transfers to a low consumption power state in accordance with a program. A timer repeats an operation of executing counting until a count value reaches a first set value corresponding to the above period, and outputs a control signal over a fixed period of time during which the count value shows a prescribed value. A control circuit starts up the PLL circuit when the startup command or the control signal is outputted, and stops the PLL circuit when the startup command is not outputted within the prescribed period in the case the PLL circuit is started up based on the control signal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The disclosed technology relates to a semiconductor device. [Background technology]

[0002] The following techniques are known as techniques for reducing power consumption in microcomputers. For example, Patent Document 1 describes a microcomputer that includes a CPU that receives a CPU clock to execute instructions, an input / output circuit that receives CPU processing requests from an external circuit, and a monitoring control circuit that accesses the input / output circuit during a sleep period of the CPU and performs a monitoring operation to detect CPU processing requests. The CPU stops executing instructions during the sleep period, and the monitoring control circuit operates during the sleep period and cancels the sleep period when it detects a CPU processing request.

[0003] Patent Document 2 describes a semiconductor integrated circuit that includes a PLL circuit that receives a reference clock signal as input and outputs a multiplied clock signal obtained by multiplying the frequency of the reference clock signal by a predetermined multiple, a control circuit that stops or suspends operation of the PLL circuit in response to an external request, a selection circuit that selects and outputs the reference clock signal or the multiplied clock signal, and a functional circuit that operates using the reference clock signal or the multiplied clock signal selected by the selection circuit, in which, when a processing request for the functional circuit is input while the control circuit has stopped or suspended operation of the PLL circuit, the control circuit determines whether or not to resume operation of the PLL circuit based on the processing request for the functional circuit, and if it determines not to resume operation of the PLL circuit, it controls the selection circuit to select the reference clock signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-116719 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-131014 Summary of the Invention [Problem to be solved by the invention]

[0005] A microcomputer executes processing related to a processing request from an external device in response to the request. While waiting for a processing request from the external device, the microcomputer reduces power consumption by entering a low-power consumption state (sleep state). In the low-power consumption state, the operation of some of the circuits that make up the microcomputer is stopped, so it takes a certain amount of time to return to the normal state.

[0006] When an external device periodically determines whether a processing request is necessary and issues a processing request when necessary, the following methods can be considered as a method for shortening the time from when a processing request is issued to when the processing is completed. For example, one method is to return each circuit in a low power consumption state to a normal state before the processing request is actually issued, in accordance with the period for determining whether a processing request is necessary in the external device. While this can shorten the time from when a processing request is issued to when the processing is completed, it is desirable to reduce the power consumption during the standby period while waiting for the processing request to be issued.

[0007] The disclosed technology has been made in consideration of the above points, and aims to reduce power consumption during a standby period in which a processing request is awaited. [Means for solving the problem]

[0008] The semiconductor device according to the disclosed technology includes a PLL circuit that outputs an output signal when, after startup, the frequency of the output signal reaches a locked state where the frequency of the output signal converges; a CPU that determines whether a processing request is required at a fixed period and generates the processing request when necessary, outputs a startup command when receiving the processing request from an external device, and transitions to a low power consumption state according to a program; a timer that repeats counting until a count value reaches a first set value corresponding to the period and outputs a control signal for a fixed period during which the count value indicates a predetermined value; and a control circuit that starts the PLL circuit when the startup command or the control signal is output, and stops the PLL circuit when the PLL circuit is started based on the control signal and the startup command is not output within the fixed period. [Effects of the Invention]

[0009] According to the semiconductor device according to the disclosed technique, it is possible to reduce power consumption during a standby period in which a processing request is awaited. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating an example of a configuration of a system including a semiconductor device according to an embodiment of the disclosed technique and an external device. [Figure 2] FIG. 10 is a diagram illustrating an example of a manner in which a processing request is generated by an external device. [Figure 3] 1 is a circuit block diagram showing an example of a configuration of a semiconductor device according to an embodiment of the disclosed technique; [Figure 4] 10 is a timing chart showing an example of an operation of a semiconductor device according to an embodiment of the disclosed technique. [Figure 5] 10 is a timing chart showing an example of an operation of a semiconductor device according to an embodiment of the disclosed technique. [Figure 6] 10 is a timing chart showing an example of an operation of a semiconductor device according to an embodiment of the disclosed technique. [Figure 7] FIG. 1 is a circuit block diagram showing an example of a configuration of a semiconductor device according to a comparative example. [Figure 8]10 is a timing chart showing an example of an operation of a semiconductor device according to a comparative example. [Figure 9] 10 is a timing chart showing an example of an operation of a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0012] 1 is a diagram showing an example of the configuration of a system 1 including a semiconductor device 10 according to an embodiment of the disclosed technique and an external device 20. The semiconductor device 10 constitutes a microcomputer, and is configured to include electronic components such as resistor elements, capacitors, and transistors integrated on a semiconductor substrate.

[0013] The external device 20 determines at regular intervals whether a processing request is necessary, and if necessary, generates a processing request and transmits it to the semiconductor device 10. FIG. 2 is a diagram showing an example of how a processing request is generated by the external device 20. The external device 20 determines at regular intervals T whether to generate a processing request. If the external device 20 determines that it is necessary to generate a processing request, it generates the processing request and transmits it to the semiconductor device 10. When the semiconductor device 10 receives a processing request, it executes the processing by interrupt processing.

[0014] 3 is a circuit block diagram showing an example of the configuration of the semiconductor device 10. The semiconductor device 10 includes a CPU (Central Processing Unit) 11, a timer 12, a control circuit 13, a PLL (Phase Locked Loop) circuit 14, and an arithmetic circuit 15.

[0015] The CPU 11 transmits various commands S5, including a start command and a stop command, to the control circuit 13. For example, when the CPU 11 receives a processing request S4 transmitted from the external device 20, it outputs the start command S5 to restore the PLL circuit 14, which is in a stopped state, to an operating state. The CPU 11 also transitions to a low power consumption state in accordance with a program. When the CPU 11 receives a processing request S4 from the external device 20 while in the low power consumption state, it returns to the normal state. The low power consumption state is a state in which power consumption is lower than in the normal state by stopping some or all of its functions. The low power consumption state is also called a sleep state.

[0016] The timer 12 repeats the counting operation until it reaches the first timer set value C1. In this embodiment, the first timer set value C1 is set to 0. X FFFF is set and timer 12 is 0 X 0000 to 0 X The timer 12 repeats counting up to FFFF. The first timer set value C1 corresponds to the period T at which the external device 20 determines whether to issue a processing request S4. That is, the count value of the timer 12 is set to the initial value 0. X 0000 to 0, which is the first timer setting value C1 X The time required to reach FFFF corresponds to the period T.

[0017] The timer 12 outputs the control signal S1 for a certain period during which the count value indicates a predetermined value. More specifically, the timer 12 outputs the control signal S1 for a period from when the count value reaches a second timer set value C2 to when the count value reaches a first set value C1. In this embodiment, the second timer set value C2 is set to 0. X F000 is set. Therefore, the count value of timer 12 is 0 X F000 to 0 XThe control signal S1 is output over a period until the timer reaches FFFF. Any value can be set as the second timer set value C2. The first timer set value C1 and the second timer set value C2 are stored in a register (not shown) provided in the timer 12. The first timer set value C1 and the second timer set value C2 can be set by the CPU 11.

[0018] The control circuit 13 controls the activation and deactivation of the PLL circuit 14. More specifically, when a start command S5 is output from the CPU 11 or a control signal S1 is output from the timer 12, the control circuit 13 activates the PLL circuit 14 by outputting a high-level control signal S2. In other words, even if a start command S5 is not output from the CPU 11, the control circuit 13 activates the PLL circuit 14 when a control signal S1 is output from the timer 12.

[0019] When the control circuit 13 activates the PLL circuit 14 based on the control signal S1, if a start command S5 is not output within a predetermined period, the control circuit 13 transitions the control signal S2 to a low level to stop the PLL circuit 14. The predetermined period may be, for example, the period during which the control signal S1 is output. The control circuit 13 also transitions the control signal S2 to a low level to stop the PLL circuit 14 when a stop command S5 is output from the CPU 11.

[0020] The PLL circuit 14 is a circuit that outputs a clock signal S3 of a constant frequency. The PLL circuit 14 is activated when the control signal S2 transitions to high level. It takes a certain amount of time for the frequency of the clock signal S3 to converge after the PLL circuit 14 is activated. This time is called the "lock-up time." After activation, the PLL circuit 14 outputs the clock signal S3 when it enters a locked state. The PLL circuit 14 stops when the control signal S2 transitions to low level. When the PLL circuit 14 enters the stopped state, the output of the clock signal S3 is stopped. The power consumption of the PLL circuit 14 is relatively low in the stopped state and relatively high in the operating state.

[0021] The arithmetic circuit 15 performs predetermined arithmetic processing in response to a processing request S4 from the external device 20. The arithmetic circuit 15 performs the arithmetic processing in synchronization with a clock signal S3 output from the PLL circuit 14. The power consumption of the arithmetic circuit 15 is relatively high when the clock signal S3 is supplied, and is relatively low when the clock signal S3 is not supplied.

[0022] 4 is a timing chart showing an example of the operation of the semiconductor device 10 when a processing request S4 is generated from the external device 20. It is assumed that, at the initial point in time, the CPU 11 is in a low power consumption state and the PLL circuit 14 is in a stopped state.

[0023] The timer 12 starts counting down from 0 to 1000 based on the first timer setting value C1 stored in the register. X 0000 to 0 X The timer 12 repeats the counting operation until the count reaches FFFF. The first timer set value C1 corresponds to the period T at which the external device 20 determines whether to issue a processing request S4. The timer 12 counts up to the second timer set value C2, 0. X After reaching F000, the first timer setting value C1 is 0 X The control signal S1 is output for a period until it reaches FFFF.

[0024] In response to the output of the control signal S1, the control circuit 13 changes the control signal S2 to a high level, causing the PLL circuit 14 to transition from a stopped state to an operating state. After startup, the PLL circuit 14 outputs the clock signal S3 when it reaches a locked state in which the frequency of the clock signal S3 converges.

[0025] Thereafter, the external device 20 issues a processing request S4. Upon receiving the processing request S4, the CPU 11 transitions from the low power consumption state to the normal state and outputs a startup command S5 for starting up the PLL circuit 14. Based on the startup command S5, the control circuit 13 maintains the state in which the control signal S2 is at a high level. Because the PLL circuit 14 is started up before the startup command S5 is output (before the processing request S4 is issued), the arithmetic circuit 15 can immediately perform arithmetic processing related to the processing request S4 without waiting for the lockup time of the PLL circuit 14.

[0026] 5 is a timing chart showing an example of the operation of the semiconductor device 10 when no processing request S4 is issued from the external device 20. It is assumed that, at the initial point in time, the CPU 11 is in a low power consumption state and the PLL circuit 14 is in a stopped state.

[0027] The timer 12 starts counting down from 0 to 1000 based on the first timer setting value C1 stored in the register. X 0000 to 0 X The timer 12 repeats the counting operation until the count reaches FFFF. The first timer set value C1 corresponds to the period T at which the external device 20 determines whether to issue a processing request S4. The timer 12 counts up to the second timer set value C2, 0. X After reaching F000, the first timer setting, 0 X The control signal S1 is output for a period until it reaches FFFF.

[0028] In response to the output of the control signal S1, the control circuit 13 changes the control signal S2 to a high level, causing the PLL circuit 14 to transition from a stopped state to an operating state. After startup, the PLL circuit 14 outputs the clock signal S3 when it reaches a locked state in which the frequency of the clock signal S3 converges.

[0029] Since no processing request S4 is generated and therefore no startup command S5 is output from the CPU 11, the control circuit 13 transitions the control signal S2 to a low level in response to the end of output of the control signal S1. This transition causes the PLL circuit 14 to transition from an operating state to a stopped state, and the output of the clock signal S3 is stopped. The CPU 11 remains in the low power consumption state.

[0030] 6 is a timing chart showing an example of the operation of the semiconductor device 10 when the PLL circuit 14 is stopped by an instruction from the CPU 11. Initially, the CPU 11 is in a normal state, and the PLL circuit 14 is in an operating state. When the processing related to the processing request S4 from the external device 20 is completed, the CPU 11 outputs a stop instruction S5 to stop the PLL circuit 14. Based on the stop instruction S5, the control circuit 13 transitions the control signal S2 to a low level. This transition causes the PLL circuit 14 to transition from an operating state to a stopped state, thereby stopping the output of the clock signal S3.

[0031] 7 is a circuit block diagram showing an example of the configuration of a semiconductor device 10X according to a comparative example. The semiconductor device 10X according to the comparative example differs from the semiconductor device 10 according to the embodiment of the disclosed technique in that the control signal S1 is supplied to the CPU 11 instead of the control circuit 13.

[0032] 8 is a timing chart showing an example of the operation of the semiconductor device 10X according to the comparative example when a processing request S4 is generated from the external device 20. At the initial point in time, the CPU 11 is in a low power consumption state, and the PLL circuit 14 is in a stopped state.

[0033] The timer 12 starts counting down from 0 to 1000 based on the first timer setting value C1 stored in the register. X 0000 to 0 X The timer 12 repeats the counting operation until the count reaches FFFF. The first timer set value C1 corresponds to the period T at which the external device 20 determines whether to issue a processing request S4. The timer 12 counts up to the second timer set value C2, 0. XWhen it reaches F000, it outputs a control signal S1.

[0034] In response to the output of the control signal S1, the CPU 11 transitions from the low power consumption state to the normal state and outputs a startup command S5 to start the PLL circuit 14. Based on the startup command S5, the control circuit 13 transitions the control signal S2 to a high level, causing the PLL circuit 14 to transition from a stopped state to an operating state. After startup, the PLL circuit 14 outputs the clock signal S3 when it reaches a locked state in which the frequency of the clock signal S3 converges.

[0035] Thereafter, the external device 20 generates a processing request S4. Since the PLL circuit 14 has been activated before the processing request S4 is generated, the arithmetic circuit 15 can immediately perform the arithmetic processing related to the processing request S4 without waiting for the lock-up time of the PLL circuit 14.

[0036] 9 is a timing chart showing an example of the operation of the semiconductor device 10X according to the comparative example when no processing request S4 is issued from the external device 20. It is assumed that, at an initial point in time, the CPU 11 is in a low power consumption state and the PLL circuit 14 is in a stopped state.

[0037] The timer 12 counts up to the second timer set value C2, 0 X When it reaches F000, it outputs a control signal S1.

[0038] In response to the output of the control signal S1, the CPU 11 transitions from the low power consumption state to the normal state and outputs a startup command S5 to start the PLL circuit 14. Based on the startup command S5, the control circuit 13 transitions the control signal S2 to a high level, causing the PLL circuit 14 to transition from a stopped state to an operating state. After startup, the PLL circuit 14 outputs the clock signal S3 when it reaches a locked state in which the frequency of the clock signal S3 converges.

[0039] After the control signal S1 is output, the CPU 11 determines whether the count value of the timer 12 reaches the first timer setting of 0. XIf no processing request S4 occurs within the period until FFFF is reached, a stop command S5 for stopping the PLL circuit 14 is output, and then the state shifts to a low power consumption state.

[0040] The control circuit 13 transitions the control signal S2 to a low level based on the stop command S5, causing the PLL circuit 14 to transition from an operating state to a stopped state and stop outputting the clock signal S3.

[0041] In the semiconductor device 10X according to the comparative example, the PLL circuit 14 is activated only based on the activation command S5 from the CPU 11. Therefore, in preparation for the occurrence of a processing request S4, the CPU 11 sets the count value of the timer 12 to 0, which is the second timer set value C2. X When the count value reaches F000, the CPU 11 always transitions to the normal state and outputs the start command S5. When a processing request S4 occurs, the CPU 11 starts counting the count value until it reaches the second timer set value C2, 0. X During the period from when the count value reaches F000 until the processing request S4 is generated (hereinafter referred to as the first waiting period), the normal state is established, and if the processing request S4 is not generated, the count value becomes 0, which is the second timer setting value C2. X After reaching F000, the first timer setting value C1 is 0 X The CPU 11 is in the normal state during the period until the power consumption reaches FFFF (referred to as the second standby period). In this way, according to the semiconductor device 10X of the comparative example, the CPU 11 is in the normal state in which power consumption is relatively high during the first standby period and the second standby period.

[0042] On the other hand, according to the semiconductor device 10 according to the embodiment of the disclosed technique, the PLL circuit 14 is activated not only based on the activation command S5 from the CPU 11 but also based on the control signal S1 from the timer 12. Therefore, the CPU 11 does not need to output the activation command S5 based on the control signal S1, and the count value of the timer 12 is 0, which is the second timer set value C2. XIt is not necessary to transition to the normal state when the value reaches F000. Therefore, the CPU 11 can maintain the low power consumption state during the first standby period when a processing request S4 is generated and during the second standby period when a processing request S4 is not generated. Therefore, according to the semiconductor device 10 according to the embodiment of the disclosed technique, it is possible to suppress power consumption during the standby period in which the semiconductor device 10 waits for the generation of a processing request S4 from the external device 20.

[0043] Furthermore, according to the semiconductor device 10 according to the embodiment of the disclosed technique, the PLL circuit 14 can be put into an operating state before the processing request S4 is generated, so that when the processing request S4 actually occurs, the arithmetic circuit 15 can immediately perform the arithmetic processing related to the processing request S4 without waiting for the lockup time of the PLL circuit 14. As a result, by keeping the PLL circuit 14 in a stopped state during the waiting period for the generation of the processing request S4, it is possible to shorten the time from the generation of the processing request S4 to the completion of the processing in a configuration that suppresses power consumption.

[0044] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) a PLL circuit that outputs an output signal when a locked state is reached in which the frequency of the output signal converges after startup; a CPU that determines at regular intervals whether a processing request is required, and generates the processing request when required, and outputs a start-up command when the processing request is received from an external device, and transitions to a low power consumption state according to a program; a timer that repeats counting until a count value reaches a first set value corresponding to the period, and outputs a control signal for a certain period during which the count value indicates a predetermined value; a control circuit that starts the PLL circuit when the start-up command or the control signal is output, and stops the PLL circuit when the start-up command is not output within a predetermined period after the PLL circuit is started based on the control signal; A semiconductor device having:

[0045] (Appendix 2) The timer outputs the control signal for a period from when the count value reaches a second set value until when the count value reaches the first set value. 2. The semiconductor device according to claim 1.

[0046] (Appendix 3) When the control circuit activates the PLL circuit based on the control signal, if the activation command is not output within a period in which the control signal is being output, the control circuit stops the PLL circuit. 10. The semiconductor device according to claim 1 or 2.

[0047] (Appendix 4) If the CPU does not receive the processing request in the low power consumption state, the CPU maintains the low power consumption state. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer. [Explanation of symbols]

[0048] 1 System 10, 10X Semiconductor Equipment 11 CPU 12 Timers 13 Control circuit 14 PLL circuit 15 Arithmetic circuit 20 External device

Claims

1. a PLL circuit that outputs an output signal when a locked state is reached in which the frequency of the output signal converges after startup; a CPU that determines whether a processing request is necessary at a fixed interval and generates the processing request when necessary, outputs a start-up command when the processing request is received from an external device, and transitions to a low power consumption state according to a program; a timer that repeats counting until a count value reaches a first set value corresponding to the period, and outputs a control signal for a certain period during which the count value indicates a predetermined value; a control circuit that starts the PLL circuit when the start command or the control signal is output, and stops the PLL circuit when the start command is not output within a predetermined period after the PLL circuit is started based on the control signal; A semiconductor device having:

2. The timer outputs the control signal for a period from when the count value reaches a second set value until when the count value reaches the first set value. The semiconductor device according to claim 1 .

3. When the control circuit activates the PLL circuit based on the control signal, if the activation command is not output within a period in which the control signal is being output, the control circuit stops the PLL circuit. The semiconductor device according to claim 1 .

4. If the CPU does not receive the processing request in the low power consumption state, the CPU maintains the low power consumption state. The semiconductor device according to claim 1 .

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