Current sensor and semiconductor current sensor

Abstract

To provide a current sensor in which the linearity of an output value to an input value is satisfactory.SOLUTION: The current sensor comprises: a bus bar; two magneto-resistance effect element (MR element) arranged on each of symmetric bent parts of the bus bar; and an application part applying bias magnetic field to the MR element. When a bridge circuit includes four MR elements, magnetization directions of respective fixed layers of the two MR elements arranged on a first bent part are reversed to each other in a direction orthogonal to the centerline of the bus bar, and magnetization directions of respective fixed layers of the two MR elements arranged on a second bent part are reversed to each other in a direction orthogonal to the centerline. When the bus bars are turned on and the application part applies bias magnetic field, magnetization directions of free layers of the two MR elements of the four MR elements are oriented in the same direction in parallel to the centerline while magnetization directions of free layers of the remaining two MR elements are reversed to each other.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a current sensor and a semiconductor-type current sensor. [Background technology]

[0002] A current sensor is known that is inserted in a current path to detect the current flowing through the current path and detects the current value of the current. The current sensor has a current path that is bent, for example, into a U-shape, and detects the induced magnetic field generated by the current flowing through the current path using a magnetoresistive element (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5853316 Summary of the Invention [Problem to be solved by the invention]

[0004] Previous current sensors had the problem that the linearity of the detected resistance value as the output value relative to the current value flowing through the current path as the input value was poor due to the properties of the magnetic resistance element and the arrangement of the magnetic resistance element relative to the current path.

[0005] The present invention has been made to solve such problems, and provides a current sensor or the like that has good linearity of output values ​​relative to input values. [Means for solving the problem]

[0006] A current sensor according to a first aspect of the present invention includes a bus bar having a first straight portion and a second straight portion that are parallel to each other across a center line, and a first bent portion and a second bent portion that are continuous with one end of the first straight portion and the second straight portion and are symmetrical to each other about the center line, and includes magnetoresistive effect elements each having a fixed layer and a free layer, wherein a first detection element and a second detection element are arranged in the first bent portion, and a third detection element and a fourth detection element are arranged in the second bent portion, and an application unit that applies a bias magnetic field to the free layer of each of the first to fourth detection elements, and when a bridge circuit is formed with the first to fourth detection elements, The magnetization directions of the fixed layers of the first detection element and the second detection element are perpendicular to the center line and opposite to each other, and the magnetization directions of the fixed layers of the third detection element and the fourth detection element are perpendicular to the center line and opposite to each other.When the bus bar is not energized and a bias magnetic field is applied by the application unit, the magnetization directions of the free layers of two detection elements forming a first set of the first to fourth detection elements are parallel to the center line and in the same direction as each other, and the magnetization directions of the free layers of the remaining two detection elements forming a second set are parallel to the center line and in the same direction as each other and opposite to the magnetization directions of the two detection elements forming the first set.

[0007] In a second aspect of the present invention, the semiconductor current sensor includes the above current sensor housed in a single semiconductor package. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a current sensor or the like having good linearity of the output value relative to the input value. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is an exploded perspective view of the current sensor according to the embodiment. [Figure 2] 10A and 10B are diagrams illustrating an induced magnetic field generated in a bus bar and an arrangement of detection elements. [Figure 3] FIG. 2 is a diagram showing the configuration of a bridge circuit and the relationship between two semiconductor chips. [Figure 4] FIG. 10 is a diagram showing the relationship between the arrangement of each detection element and linearity error. [Figure 5] FIG. 2 is a diagram illustrating the relationship between two semiconductor chips. [Figure 6] FIG. 10 is a diagram illustrating variations in the combination of detection elements. [Figure 7] FIG. 10 is a diagram showing the configuration of a full-bridge circuit and another relationship between two semiconductor chips. [Figure 8] FIG. 10 is a diagram illustrating another mutual relationship between two semiconductor chips. [Figure 9] FIG. 10 is a diagram illustrating variations in the combination of detection elements. [Figure 10] FIG. 10 is a diagram showing the configuration of a semiconductor current sensor according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiments of the present invention will be described with reference to the accompanying drawings. In each drawing, elements with the same reference numerals have the same or similar configurations. Furthermore, when multiple elements with the same or similar configurations exist in each drawing, some elements may be referenced with the same reference numerals and others may not be referenced with the same reference numerals to avoid complication. Note that the invention according to the claims is not limited to the following embodiments. Furthermore, not all of the configurations described in the embodiments are necessarily essential as means for solving the problem.

[0011] 1 is an exploded perspective view of a current sensor 100 according to this embodiment. The current sensor 100 according to this embodiment includes a bus bar 110, a substrate 120, a first chip 130, a second chip 140, a support plate 150, a first shield case 161, and a second shield case 162. The bus bar 110 is a current path and is made of a good conductor such as copper (Cu). The specific shape of the bus bar 110 will be described later, but the bus bar 110 is a generally U-shaped flat plate overall, and connection holes 111 are provided at two ends for connecting conductors that are the current path to be measured.

[0012] First chip 130 and second chip 140, which are semiconductor chips each including two magnetoresistive effect elements, are mounted on substrate 120. First chip 130 and second chip 140 may be mounted on substrate 120 as a magnetic sensor package packaged with synthetic resin. Substrate 120 has input / output terminals (not shown) for receiving power from an external power source and outputting an output signal of a bridge circuit formed by combining the magnetoresistive effect elements of first chip 130 and second chip 140.

[0013] Support plate 150 is a plate-like member that supports bus bar 110 and substrate 120. Accommodating portion 151 is a recess provided in the center of support plate 150 to match the shape of bus bar 110, and side edge portions 152 are receiving portions for substrate 120 provided on both sides of support plate 150. When bus bar 110 is accommodated in accommodating portion 151 and substrate 120 is fixed to side edge portions 152, first chip 130 and second chip 140 are arranged in predetermined positions with respect to bus bar 110, as will be described later.

[0014] First shield case 161 and second shield case 162 sandwich bus bar 110, substrate 120, and support plate 150, which are assembled together, and enclose most of bus bar 110 except for the protruding ends. First shield case 161 and second shield case 162 are formed using a synthetic resin such as ABS with magnetic powder dispersed therein. First shield case 161 and second shield case 162 prevent the intrusion of disturbance magnetic fields, allowing each magnetoresistance effect element to accurately detect the induced magnetic field that is generated when current is applied to bus bar 110.

[0015] In this embodiment, as shown by the coordinate axes in the drawing, the stacking direction of substrate 120 relative to busbar 110 is defined as the Z-axis direction, and two axes perpendicular to the Z-axis direction are defined as the X-axis direction and the Y-axis direction. In the subsequent drawings, similar coordinate axes based on the state in which current sensor 100 is arranged as in FIG. 1 are also shown to indicate the orientation of elements depicted in each drawing.

[0016] 2 is a diagram illustrating the induced magnetic field generated in busbar 110 and the arrangement of each detection element. Specifically, the diagram is of busbar 110, first chip 130, and second chip 140 of current sensor 100 observed from the Z-axis direction, and conductor 200, which is the current path to be detected, is indicated by a dotted line.

[0017] Conductor 200 is connected in series with busbar 110 by connecting each of the two separated ends to both ends of busbar 110 via connection holes 111. A current to be measured Sc flows in the direction of the hatched arrow (or in the opposite direction) through busbar 110 connected in series with conductor 200 in this way. When current to be measured Sc flows through busbar 110 in the direction of the hatched arrow, an induced magnetic field Sf is generated in the direction of the outline arrow.

[0018] As described above, busbar 110 is a generally U-shaped flat plate, but when viewed from the Z-axis direction, it has a shape that is bilaterally symmetrical across centerline SL. More specifically, busbar 110 has first and second straight portions 113 and 114 that are parallel to each other across centerline SL, and first and second bent portions 115 and 116 that are continuous with one end of each of first and second straight portions 113 and 114 (the ends opposite the open ends where connection holes 111 are provided) and are symmetrical to each other with respect to centerline SL. First and second straight portions 113 and 114 only need to allow current to flow parallel to the centerline, and may have wide portions near the open ends as shown in the figure, or portions with varying thickness. First and second bent portions 115 and 116 only need to allow current to flow continuously in orthogonal directions, and may have L-shaped or J-shaped bends as shown in the figure. In the figure, the boundary between first straight portion 113 and first bent portion 115, and the boundary between second bent portion 116 and second straight portion 114 are shown as boundary lines HL, but these boundaries do not have to have visible shapes and can be considered as positions where the direction of the induced magnetic field Sf essentially begins to change. In addition, a straight or other shaped current path may be interposed between first bent portion 115 and second bent portion 116.

[0019] The direction of the induced magnetic field Sf changes depending on the position of the current flowing through the busbar 110. In particular, in the first bent portion 115 and the second bent portion 116, as shown in the figure, the direction continuously changes over 180° from the positive direction of the X-axis, through the negative direction of the Y-axis, and then to the negative direction of the X-axis. In this embodiment, when observed from the Z-axis direction, the first chip 130 is arranged to overlap the first bent portion 115, and the second chip 140 is arranged to overlap the second bent portion 116. That is, the mounting positions of the first chip 130 and the second chip 140 relative to the substrate 120 and the fixing position of the substrate 120 relative to the support plate 150 are adjusted so that the first chip 130 and the second chip 140 are arranged in this manner. Because the first chip 130 and the second chip 140 are formed on a single substrate 120, the relative positions of these chips and the busbar 110 can be easily adjusted.

[0020] The first chip 130 includes two magnetoresistive effect elements (first detection element 131 and second detection element 132). Similarly, the second chip 140 includes two magnetoresistive effect elements (third detection element 143 and fourth detection element 144).

[0021] The magnetoresistive element used in this embodiment is a spin-valve MR element. The MR element has a configuration in which an antiferromagnetic layer extending in the XY direction, a magnetization pinned layer with a fixed magnetization direction, a gap layer, and a free layer with a magnetization whose direction changes depending on the direction of the target magnetic field are stacked in this order in the positive direction of the Z axis. The antiferromagnetic layer is made of an antiferromagnetic material and generates exchange coupling with the magnetization pinned layer to fix the magnetization direction of the magnetization pinned layer. The magnetization pinned layer may be a so-called self-pinned type pinned layer (SFP layer: Synthetic Ferri Pinned Layer). The self-pinned type pinned layer has a laminated ferrimagnetic structure in which a ferromagnetic layer, a nonmagnetic intermediate layer, and a ferromagnetic layer are stacked, and the two ferromagnetic layers are antiferromagnetically coupled. If the magnetization pinned layer is a self-pinned type pinned layer, the antiferromagnetic layer may be omitted.

[0022] The free layer generally has shape anisotropy in which the easy axis of magnetization is perpendicular to the magnetization direction of the fixed magnetization layer, and the MR element of this embodiment has a shape elongated in the Y-axis direction. In an MR element with such a configuration, the resistance value changes depending on the angle between the magnetization direction of the free layer and the magnetization direction of the fixed magnetization layer, with the resistance value being minimum when this angle is 0° and maximum when this angle is 180°. The stacking direction of each layer in the MR element may be opposite to the above. The MR element may also be a TMR (tunneling magnetoresistance) element or a GMR (giant magnetoresistance) element. In a TMR element, the gap layer is a tunnel barrier layer. In a GMR element, the gap layer is a nonmagnetic conductive layer.

[0023] When the first chip 130 is disposed on the first bent portion 115, the first detection element 131 is located at the first arrangement Ta, and the second detection element 132 is located at the second arrangement Tb. Similarly, when the second chip 140 is disposed on the second bent portion 116, the third detection element 143 is located at the third arrangement Tc, and the fourth detection element 144 is located at the fourth arrangement Td. Here, for the sake of clarity, the first arrangement Ta and the second arrangement Tb, and the third arrangement Tc and the fourth arrangement Td, which are adjacent along the X-axis direction, are used. However, the arrangement of the two detection elements may be adjacent along the Y-axis direction or along another direction. However, it is preferable that the arrangement of the first detection element 131 and the second detection element 132 be symmetrical with the arrangement of the third detection element 143 and the fourth detection element 144 across the center line SL.

[0024] 3 is a diagram showing the configuration of a full-bridge circuit composed of four detection elements and the relationship between two semiconductor chips. In the figure, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are each magnetoresistive effect elements according to this embodiment. Here, the first resistor R1 is the second detection element 132 included in the first chip 130, the second resistor R2 is the fourth detection element 144 included in the second chip 140, the third resistor R3 is the third detection element 143 included in the second chip 140, and the fourth resistor R4 is the first detection element 131 included in the first chip 130.

[0025] In the figure, the PIN direction Dp indicated by the hatched arrow represents the magnetization direction of the pinned layer, and the FREE direction Df indicated by the dotted arrow represents the magnetization direction of the free layer when a bias magnetic field is applied by the hard bias layer HM. A hard bias layer (Hard Magnet) is formed in each magnetoresistive element, and the magnetization direction of the free layer can be determined for each magnetoresistive element. Note that in the following figures, for simplicity, the hard bias layer HM is omitted from each element unless otherwise specified.

[0026] The first resistor R1 (second detection element 132) and the second resistor R2 (fourth detection element 144) are connected in series between a DC power supply and ground to form a half-bridge circuit (second half-bridge circuit), and a first output voltage V is generated at the midpoint between the first resistor R1 and the second resistor R2 according to the strength of the magnetic field applied to the first resistor R1 and the second resistor R2. out1 The fourth resistor R4 (first detection element 131) and the third resistor R3 (third detection element 143) are also connected in series between the DC power supply and the ground to form a half-bridge circuit (first half-bridge circuit), and at the midpoint between the fourth resistor R4 and the third resistor R3, a second output voltage V out2 The DC power supply outputs a constant supply voltage V SUP The first resistor R1 to the fourth resistor R4 together form a full bridge circuit.

[0027] When the first chip 130 is placed over the first bent portion 115, the pin direction Dp of the first resistor R1 coincides with the positive direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the first resistor R1 coincides with the positive direction of the Y-axis parallel to the center line SL. When the current to be measured Sc flows through the first bent portion 115, the induced magnetic field Sf generated by this has a component in the positive direction of the X-axis (see FIG. 2). Therefore, the resistance value of the first resistor R1 decreases according to the strength of the induced magnetic field Sf. When the second chip 140 is placed over the second bent portion 116, the pin direction Dp of the second resistor R2 coincides with the positive direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the second resistor R2 coincides with the negative direction of the Y-axis parallel to the center line SL. When the measurement current Sc flows through the second bent portion 116, the induced magnetic field Sf generated by this has a component in the negative direction of the X-axis (see FIG. 2), and therefore the resistance value of the second resistor R2 increases according to the strength of the induced magnetic field Sf. out1 The supply voltage V varies depending on the resistance of the first resistor R1 and the resistance of the second resistor R2. SUP is the divided output.

[0028] When the first chip 130 is placed over the first bent portion 115, the pin direction Dp of the fourth resistor R4 coincides with the negative direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the fourth resistor R4 coincides with the positive direction of the Y-axis parallel to the center line SL. When the current to be measured Sc flows through the first bent portion 115, the induced magnetic field Sf generated by this current has a component in the positive direction of the X-axis (see FIG. 2). Therefore, the resistance value of the fourth resistor R4 increases according to the strength of the induced magnetic field Sf. When the second chip 140 is placed over the second bent portion 116, the pin direction Dp of the third resistor R3 coincides with the negative direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the third resistor R3 coincides with the negative direction of the Y-axis parallel to the center line SL. When the measurement current Sc flows through the second bent portion 116, the induced magnetic field Sf generated by this has a component in the negative direction of the X-axis (see FIG. 2), and the resistance value of the third resistor R3 decreases according to the strength of the induced magnetic field Sf. out2The supply voltage V varies depending on the resistance of the fourth resistor R4 and the resistance of the third resistor R3. SUP is the divided output.

[0029] Therefore, when a large current to be measured Sc flows through the first bending portion 115 and the second bending portion 116, the first output voltage V out1 becomes larger, and the second output voltage V out2 In other words, the first output voltage V out1 and the second output voltage V out2 fluctuate complementarily, the full bridge circuit as a whole is suitable as a measurement circuit for measuring the magnitude of the current Sc to be measured with high precision.

[0030] 4A and 4B are diagrams showing the relationship between the arrangement of each detection element and linearity error. In particular, Fig. 4A shows the arrangement of the pair of first chip 130 and second chip 140 relative to first bent portion 115 and second bent portion, and Fig. 4B shows the relationship between the current applied to bus bar 110 and linearity error in the arrangement of Fig. 4A.

[0031] 4A shows a state in which first chip 130a is arranged at a position where the angle between the direction of induced magnetic field Sf and center line SL is 40° at first bending portion 115. Also, second chip 140a is arranged in a pair with first chip 130a, and shows a state in which second chip 140 is arranged at a position where the angle between the direction of induced magnetic field Sf and center line SL is 40° at second bending portion 116. As described with reference to FIG. 2, first chip 130a and second chip 140a include first detector element 131 and second detector element 132, and third detector element 143 and fourth detector element 144, respectively. The position of first chip 130a may be determined based on the midpoint between first detector element 131 and second detector element 132, and the position of second chip 140a may be determined based on the midpoint between third detector element 143 and fourth detector element 144. As described with reference to FIG. 3, the PIN direction Dp and the FREE direction Df of each detecting element are oriented in the directions shown in the drawing.

[0032] 4A shows first chip 130b arranged at a position where the angle between the direction of induced magnetic field Sf and center line SL is 90° near the boundary between first bent portion 115 and first straight portion 113. Second chip 140b is arranged in pairs with first chip 130b, and shows second chip 140 arranged at a position where the angle between the direction of induced magnetic field Sf and center line SL is 90° near the boundary between second bent portion 116 and second straight portion 114. As with first chip 130a and second chip 140a, the position of first chip 130b may be determined based on the midpoint between first detection element 131 and second detection element 132, and the position of second chip 140b may be determined based on the midpoint between third detection element 143 and fourth detection element 144. The PIN direction Dp and the FREE direction Df of each detecting element are oriented in the directions shown in the figure.

[0033] In FIG. 4B, the horizontal axis represents the current value (mA) of the measurement current Sc flowing through the bus bar 110, and the vertical axis represents the linearity error (%). The linearity error is a function of the output signal (the first output voltage V described with reference to FIG. 3) that should be output in proportion to the measurement current Sc actually applied. out1 and the second output voltage V out2 It indicates the percentage by which the difference signal between the two (the difference signal between the two) deviates from an ideal straight line.

[0034] The dotted line shows the simulation results for a pair of first chip 130a and second chip 140a positioned so that the angle between the direction of induced magnetic field Sf and center line SL is 40°, while the solid line shows the simulation results for a pair of first chip 130b and second chip 140b positioned so that the angle between the direction of induced magnetic field Sf and center line SL is 90°. As is clear from the figure, the dotted line shows that the linearity error is generally smaller with respect to changes in the measured current Sc than the solid line. The inventors conducted repeated simulations and found that when first detection element 131 and second detection element 132 are arranged at first bent portion 115 and third detection element 143 and fourth detection element 144 are arranged at second bent portion 116 in positions where the angle formed between the center line SL and the direction of the induced magnetic field Sf generated when the current to be measured Sc is applied to bus bar 110 is less than 90°, linearity errors can generally be kept small relative to changes in the current to be measured Sc. In particular, it was found that linearity errors can be kept small more effectively when the angle formed is 25° or more and less than 90°, and further 30° or more and less than 60°.

[0035] Next, the relationship between the arrangement of first detection element 131 and second detection element 132 in first chip 130 and the arrangement of third detection element 143 and fourth detection element 144 in second chip 140 will be described. Fig. 5 is a diagram illustrating the relationship between two semiconductor chips (first chip 130 and second chip 140). In particular, the left side shows first chip 130 arranged in first bent portion 115, and the right side shows second chip 140 arranged in second bent portion 116.

[0036] The first chip 130 shown on the left has a detection element MR1, which is a magnetoresistive effect element, located on the right side of the center of the chip, and a similar detection element MR2 located on the left side of the center, and further has terminals t1 to t6 that may or may not be wired to these detection elements as shown. When the first chip 130 is placed in the first bent portion 115, the detection element MR2 located on the left corresponds to the first arrangement Ta, and the detection element MR1 located on the right corresponds to the second arrangement Tb (see FIG. 2). Note that terminal t1 is connected to a supply voltage VSUP The terminal t2 is the power supply terminal that supplies the second output voltage V out2 As an output terminal that outputs the first output voltage V out1 The terminals t4 to t6 function as output terminals that output the signal t1, t2, t3, t4, t5, t6, and t7, and terminals t4 to t6 can be used as connection pads.

[0037] The detector MR1 has a fixed layer whose pin direction Dp coincides with the positive direction of the X-axis when placed in the first bent portion 115, and a free layer whose free direction Df coincides with the positive direction of the Y-axis when a bias magnetic field is applied. The detector MR1, which has such a fixed layer and free layer, corresponds to the first resistor R1 in the full-bridge circuit (see FIG. 3). The detector MR2 has a fixed layer whose pin direction Dp coincides with the negative direction of the X-axis when placed in the first bent portion 115, and a free layer whose free direction Df coincides with the positive direction of the Y-axis when a bias magnetic field is applied. The detector MR2, which has such a fixed layer and free layer, corresponds to the fourth resistor R4 in the full-bridge circuit (see FIG. 3).

[0038] In this embodiment, if a semiconductor chip CH1 identical to such first chip 130 is rotated 180 degrees around the Z axis, it can be used as second chip 140 to be placed in second bent portion 116. In other words, the semiconductor chip CH1 having the same structure can be used as both first chip 130 and second chip 140.

[0039] Specifically, when the semiconductor chip CH1 is rotated 180° around the Z axis, it becomes the second chip 140 shown on the right, with the detection element MR1 located on the left side of the center and the detection element MR2 located on the right side of the center. When such a second chip 140 is arranged in the second bent portion 116, the detection element MR1 located on the left side corresponds to the third arrangement Tc, and the detection element MR2 located on the right side corresponds to the fourth arrangement Td (see FIG. 2). Here, the terminal t5 of the first chip 130 and the terminal t4 of the second chip 140 are connected by a connecting wire WR, and similarly, the terminal t4 of the first chip 130 and the terminal t5 of the second chip 140 are connected by a connecting wire WR. When connected in this manner, the terminal t1 of the second chip 140 serves as a ground terminal, and the terminal t2 serves as a second output voltage V out2 As an output terminal that outputs the first output voltage V out1 It functions as an output terminal that outputs the first output voltage V out1 Either the terminal t3 of the first chip 130 or the terminal t3 of the second chip 140 may be used as the output terminal for outputting the second output voltage V out2 Either the terminal t2 of the first chip 130 or the terminal t2 of the second chip 140 may be used as the output terminal for outputting the signal.

[0040] When the detector element MR1 is disposed in the second bent portion 116, it has a fixed layer whose PIN direction Dp is aligned with the negative X-axis direction and a free layer whose FREE direction Df is aligned with the negative Y-axis direction when a bias magnetic field is applied. The detector element MR1, which has such a fixed layer and free layer, corresponds to the third resistor R3 in a full-bridge circuit (see FIG. 3). When the detector element MR2 is disposed in the second bent portion 116, it has a fixed layer whose PIN direction Dp is aligned with the positive X-axis direction and a free layer whose FREE direction Df is aligned with the negative Y-axis direction when a bias magnetic field is applied. The detector element MR2, which has such a fixed layer and free layer, corresponds to the second resistor R2 in a full-bridge circuit (see FIG. 3). In this way, the first chip 130 disposed in the first bent portion 115 and the second chip 140 disposed in the second bent portion 116 can use the same semiconductor chip CH1, which contributes to reducing the number of components and manufacturing costs.

[0041] Next, a description will be given of variations in the combination of four detection elements that can effectively suppress linearity errors as shown in Fig. 4. Fig. 6 is a diagram illustrating variations in the combination of detection elements.

[0042] In this embodiment, there are various variations in the combination of detector elements that can effectively suppress linearity errors. In the example described with reference to FIG. 3, the PIN direction Dp of the first resistor R1 (second detector element 132) included in the first chip 130 was the positive direction of the X axis, and the FREE direction Df when a bias magnetic field was applied was the positive direction of the Y axis. The PIN direction Dp of the second resistor R2 (fourth detector element 144) included in the second chip 140 was the positive direction of the X axis, and the FREE direction Df when a bias magnetic field was applied was the negative direction of the Y axis. The PIN direction Dp of the third resistor R3 (third detector element 143) included in the second chip 140 was the negative direction of the X axis, and the FREE direction Df when a bias magnetic field was applied was the negative direction of the Y axis. The PIN direction Dp of the fourth resistor R4 (first detector element 131) included in the first chip 130 was the negative direction of the X axis, and the FREE direction Df when a bias magnetic field was applied was the positive direction of the Y axis.

[0043] As a result of repeated simulations by the inventors, it was found that possible combinations of the PIN direction Dp and the FREE direction Df in each of the detection elements in this embodiment satisfy the following condition (1) regarding the magnetization direction (PIN direction Dp) of the pinned layer and the following condition (2) regarding the magnetization direction (FREE direction Df) of the free layer: (1) the PIN directions Dp of the first detection element 131 (fourth resistor R4) and the second detection element 132 (first resistor R1) included in the first chip 130 are opposite to each other in a direction perpendicular to the center line SL of the bus bar 110 (X-axis direction), and the PIN directions Dp of the third detection element 143 (third resistor R3) and the fourth detection element 144 (second resistor R2) included in the second chip 140 are opposite to each other in a direction perpendicular to the center line SL of the bus bar 110 (X-axis direction), and (2) when the bus bar 110 is not energized, the bias magnetic field When a voltage is applied, the FREE directions Df of two detection elements (the combination of the first detection element 131 and the second detection element 132 in the example of FIG. 3) forming a first set among the first detection element 131 to the fourth detection element 144 are parallel to the center line SL of the bus bar 110 (the Y-axis direction) and are oriented in the same direction as each other, and the FREE directions Df of the remaining two detection elements (the combination of the third detection element 143 and the fourth detection element 144 in the example of FIG. 3) forming a second set are also parallel to the center line SL and are oriented in the same direction as each other, but are opposite to the FREE directions Df of the two detection elements forming the first set.

[0044] As examples of combinations of detection elements that satisfy these two conditions, variations 1 to 6 shown in FIG. 6 can be given. Any of these variations can effectively suppress linearity errors. However, depending on the variation that can be selected, it may not be possible to realize the first chip 130 and the second chip 140 on the same semiconductor chip by utilizing rotational symmetry, as explained using FIG. 5. In such cases, it is sufficient to realize the first chip 130 and the second chip 140 on separate semiconductor chips.

[0045] In the above-described embodiment, the hard bias layer provided in each detection element is used as an example of the application unit that applies a bias magnetic field to the free layer. However, the configuration of the application unit is not limited to this. Depending on the configuration, the application unit can also be configured with a laminate (hereinafter referred to as a laminate) including a ferromagnetic portion and an antiferromagnetic portion that is in contact with the ferromagnetic portion and exchange-couples with the ferromagnetic portion, or an application coil. A laminate generally does not reverse its magnetization direction due to a strong external magnetic field. Furthermore, an application coil allows control of the bias magnetic field by controlling the current amount. Furthermore, compared to an application unit configured with a hard bias layer or a laminate, the element dimensions have a higher degree of freedom. The application unit to be used can be determined based on the specifications required for the current sensor 100.

[0046] Another example of this embodiment will now be described. In the embodiment described so far, the first detection element 131 and the second detection element 132 included in the first chip 130 arranged in the first bent portion 115 are incorporated into the bridge circuit as the fourth resistor R4 and the first resistor R1, respectively, and the third detection element 143 and the fourth detection element 144 included in the second chip 140 arranged in the second bent portion 116 are incorporated into the bridge circuit as the third resistor R3 and the second resistor R2, respectively. However, the configuration of the bridge circuit and the relationship between the two semiconductor chips are not limited to this. FIG. 7 is a diagram showing another relationship between the configuration of the bridge circuit and the two semiconductor chips. In the example shown in Figure 7, the first detection element 131 and the second detection element 132 included in the first chip 130 arranged in the first bent portion 115 are incorporated into the bridge circuit as the first resistor R1 and the second resistor R2, respectively, and the third detection element 143 and the fourth detection element 144 included in the second chip 140 arranged in the second bent portion 116 are incorporated into the bridge circuit as the fourth resistor R4 and the third resistor R3, respectively.

[0047] The first resistor R1 (first detection element 131) and the second resistor R2 (second detection element 132) are connected in series between a DC power supply and ground to form a half-bridge circuit (first half-bridge circuit), and a first output voltage V is generated at the midpoint between the first resistor R1 and the second resistor R2 according to the strength of the magnetic field applied to the first resistor R1 and the second resistor R2.out1 The fourth resistor R4 (third detection element 143) and the third resistor R3 (fourth detection element 144) are also connected in series between the DC power supply and the ground to form a half-bridge circuit (second half-bridge circuit), and at the midpoint between the fourth resistor R4 and the third resistor R3, a second output voltage V out2 The DC power supply outputs a constant supply voltage V SUP The first resistor R1 to the fourth resistor R4 together form a full bridge circuit.

[0048] When the first chip 130 is placed over the first bent portion 115, the pin direction Dp of the first resistor R1 coincides with the negative direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the first resistor R1 coincides with the positive direction of the Y-axis parallel to the center line SL. When the current to be measured Sc flows through the first bent portion 115, the induced magnetic field Sf generated by this has a component in the positive direction of the X-axis (see FIG. 2). Therefore, the resistance value of the first resistor R1 increases according to the strength of the induced magnetic field Sf. When the first chip 130 is placed over the first bent portion 115, the pin direction Dp of the second resistor R2 coincides with the positive direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the second resistor R2 coincides with the negative direction of the Y-axis parallel to the center line SL. When the measurement current Sc flows through the first bent portion 115, the induced magnetic field Sf generated by the measurement current Sc has a component in the positive direction of the X-axis (see FIG. 2), and the resistance value of the second resistor R2 decreases according to the strength of the induced magnetic field Sf. out1 The supply voltage V varies depending on the resistance of the first resistor R1 and the resistance of the second resistor R2. SUP is the divided output.

[0049] When the second chip 140 is placed over the second bent portion 116, the pin direction Dp of the fourth resistor R4 coincides with the negative direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the fourth resistor R4 coincides with the positive direction of the Y-axis parallel to the center line SL. When the current to be measured Sc flows through the second bent portion 116, the induced magnetic field Sf generated by this has a component in the negative direction of the X-axis (see FIG. 2). Therefore, the resistance value of the fourth resistor R4 decreases according to the strength of the induced magnetic field Sf. When the second chip 140 is placed over the second bent portion 116, the pin direction Dp of the third resistor R3 coincides with the positive direction of the X-axis perpendicular to the center line SL. At this time, the free direction Df of the third resistor R3 coincides with the negative direction of the Y-axis parallel to the center line SL. When the measurement current Sc flows through the second bent portion 116, the induced magnetic field Sf generated by this has a component in the negative direction of the X-axis (see FIG. 2), and therefore the resistance value of the third resistor R3 increases in accordance with the strength of the induced magnetic field Sf. out2 The supply voltage V varies depending on the resistance of the fourth resistor R4 and the resistance of the third resistor R3. SUP is the divided output.

[0050] Therefore, when a large current to be measured Sc flows through the first bending portion 115 and the second bending portion 116, the first output voltage V out1 becomes smaller, and the second output voltage V out2 In other words, the first output voltage V out1 and the second output voltage V out2 Since the two currents fluctuate in a complementary manner, the full-bridge circuit as a whole is suitable as a measurement circuit for accurately measuring the magnitude of the target current Sc. Even with this configuration, linearity errors can be effectively suppressed, as explained with reference to FIG.

[0051] Even when the first chip 130 and the second chip 140 are configured in this manner, semiconductor chips of the same structure can be used. Figure 8 is a diagram illustrating another mutual relationship between the two semiconductor chips (first chip 130 and second chip 140). In particular, the left side shows the first chip 130 disposed in the first bent portion 115, and the right side shows the second chip 140 disposed in the second bent portion 116.

[0052] As shown in the figure, the first chip 130 and the second chip 140 can each use a semiconductor chip CH2 with the same structure. The semiconductor chip CH2 has a detection element MR1, which is a magnetoresistive effect element, located on the right side of the center, and a similar detection element MR2 located on the left side of the center, and further has terminals t1 to t6 that may or may not be wired to these detection elements as shown. When the semiconductor chip CH2 is placed in the first bent portion 115, it functions as the first chip 130, with the detection element MR2 located on the left corresponding to the first arrangement Ta and the detection element MR1 located on the right corresponding to the second arrangement Tb (see FIG. 2). Note that terminal t1 functions as a power supply terminal that supplies a supply voltage VSUP, terminal t2 as an output terminal that outputs a first output voltage Vout1, and terminal t3 as a ground terminal.

[0053] The detection element MR1 has a fixed layer whose PIN direction Dp coincides with the positive direction of the X-axis when placed in the first bent portion 115, and a free layer whose FREE direction Df coincides with the negative direction of the Y-axis when a bias magnetic field is applied. The detection element MR1 having such a fixed layer and free layer corresponds to the second resistor R2 in the full-bridge circuit (see FIG. 7). The detection element MR2 has a fixed layer whose PIN direction Dp coincides with the negative direction of the X-axis when placed in the first bent portion 115, and a free layer whose FREE direction Df coincides with the positive direction of the Y-axis when a bias magnetic field is applied. The detection element MR2 having such a fixed layer and free layer corresponds to the first resistor R1 in the full-bridge circuit (see FIG. 7).

[0054] When the semiconductor chip CH2 is placed in the second bent portion 116, it functions as the second chip 140, with the detection element MR2 located on the left side corresponding to the third arrangement Tc and the detection element MR1 located on the right side corresponding to the fourth arrangement Td (see FIG. 2). Note that the terminal t1 functions as a power supply terminal that supplies the supply voltage VSUP, the terminal t2 as an output terminal that outputs the second output voltage Vout2, and the terminal t3 as a ground terminal.

[0055] The detector MR1 has a fixed layer whose pin direction Dp coincides with the positive direction of the X-axis when disposed in the second bent portion 116, and a free layer whose free direction Df coincides with the negative direction of the Y-axis when a bias magnetic field is applied. The detector MR1 having such a fixed layer and free layer corresponds to the third resistor R3 in the full-bridge circuit (see FIG. 7). The detector MR2 has a fixed layer whose pin direction Dp coincides with the negative direction of the X-axis when disposed in the second bent portion 116, and a free layer whose free direction Df coincides with the positive direction of the Y-axis when a bias magnetic field is applied. The detector MR2 having such a fixed layer and free layer corresponds to the fourth resistor R4 in the full-bridge circuit (see FIG. 7). In this way, the first chip 130 disposed in the first bent portion 115 and the second chip 140 disposed in the second bent portion 116 can use the same semiconductor chip CH2, which contributes to reducing the number of components and manufacturing costs.

[0056] Even when the first chip 130 and the second chip 140 are configured in this manner, there are various variations in the combination of the four detection elements that can effectively suppress linearity errors as shown in Fig. 4. Fig. 9 is a diagram illustrating variations in the combination of detection elements.

[0057] The conditions for configuring the first chip 130 and the second chip 140 as shown in FIG. 7 are: (1) the pin directions Dp of the first detection element 131 (first resistor R1) and the second detection element 132 (second resistor R2) included in the first chip 130 are opposite to each other in a direction perpendicular to the center line SL of the bus bar 110 (the X-axis direction); and the pin directions Dp of the third detection element 143 (fourth resistor R4) and the fourth detection element 144 (third resistor R3) included in the second chip 140 are opposite to each other in a direction perpendicular to the center line SL of the bus bar 110 (the X-axis direction); When no current is flowing at 0 and a bias magnetic field is applied, the FREE directions Df of the two detection elements (in the example of Figure 7, the combination of the first detection element 131 and the third detection element 143) that make up the first set of the first to fourth detection elements 131 to 144 are parallel to the center line SL of the bus bar 110 (Y-axis direction) and are oriented in the same direction as each other, and the FREE directions Df of the remaining two detection elements (in the example of Figure 7, the combination of the second detection element 132 and the fourth detection element 144) that make up the second set are also parallel to the center line SL and are oriented in the same direction as each other, but are opposite to the FREE directions Df of the two detection elements that make up the first set.

[0058] As examples of combinations of detection elements that satisfy these two conditions, variations 1 to 6 shown in FIG. 9 can be given. Any of these variations can effectively suppress linearity errors. However, depending on the variation that can be selected, it may not be possible to realize the first chip 130 and the second chip 140 on the same semiconductor chip, as explained using FIG. 8. In such cases, the first chip 130 and the second chip 140 may be realized on separate semiconductor chips. Also, as in the example shown in FIG. 6, the application unit may be configured with a laminate or an application coil depending on the configuration of the variation and the specifications required for the current sensor 100.

[0059] In the present embodiment described above, the current sensor 100 is constructed through a process of assembling multiple elements as shown in Fig. 1, but it is also possible to construct a semiconductor-type current sensor by miniaturizing each of the elements described above and housing them in a single semiconductor package. Fig. 10 is a diagram showing the configuration of the semiconductor-type current sensor 101. Specifically, this shows an example in which the current sensor is incorporated into a DIP (Dual In-line Package).

[0060] The semiconductor current sensor 101 has four terminals (terminals T1 to T8) on each side surface. Of the terminals T1 to T4 arranged on one side surface, at least one of T1 and T2 is connected to one end of a current path to be detected, and at least one of T3 and T4 is connected to the other end of the current path. The bus bar 110' is embedded in the semiconductor package, and one of its open ends is connected to the terminals T1 and T2, and the other is connected to the terminals T3 and T4. Like the bus bar 110, the bus bar 110' has a straight portion and a bent portion. Like the first chip 130 and the second chip 140, the first chip 130' and the second chip 140' are respectively arranged at the bent portions of the bus bar. The first chip 130' has a first detection element 131' and a second detection element 132', and the second chip 140' has a third detection element 143' and a fourth detection element 144'. These configurations are similar to those of the first chip 130 and the second chip 140.

[0061] Terminal T8 is connected to the supply voltage V SUP Terminal T7 is the power supply terminal that supplies the first output voltage V out1 The terminal T6 is the output terminal that outputs the second output voltage V out2 Terminal T5 functions as an output terminal that outputs a signal, and terminal T6 functions as a ground terminal. Each terminal is connected to a corresponding terminal of first chip 130' or second chip 140' by, for example, a bonding wire BW. Each element that constitutes the current sensor is sealed with resin.

[0062] In this embodiment, each current sensor is configured as one full-bridge circuit, but in order to detect the current value of the detection target more accurately, two or more full-bridge circuits may be configured by increasing the number of detection elements. [Explanation of symbols]

[0063] 100...current sensor, 101...semiconductor-type current sensor, 110, 110'...bus bar, 111...connection hole, 113...first straight portion, 114...second straight portion, 115...first bent portion, 116...second bent portion, 120...substrate, 130, 130a, 130b, 130'...first chip, 131, 131'...first detection element, 132, 132'...second detection element, 140, 140a, 140b, 140'...second chip, 143, 143 '...third detection element, 144, 144'...fourth detection element, 150...support plate, 151...accommodation portion, 152...side edge portion, 161...first shielding case, 162...second shielding case, 200...conductor, SL...center line, HL...boundary line, Sc...current to be measured, Sf...induced magnetic field, Ta...first arrangement, Tb...second arrangement, Tc...third arrangement, Td...fourth arrangement, R1...first resistor, R2...second resistor, R3...third resistor, R4...fourth resistor, V SUP …supply voltage, V out1 …first output voltage, V out2 ...second output voltage, HM...hard bias layer, Dp...PIN direction, Df...FREE direction, CH1, CH2...semiconductor chip, MR1, MR2...detection element, t1 to t6, T1 to T8...terminal, WR...connecting wire, BW...bonding wire

Claims

1. a bus bar including a first straight portion and a second straight portion that are parallel to each other across a center line, and a first bent portion and a second bent portion that are continuous with one end of the first straight portion and one end of the second straight portion and are symmetrical to each other with respect to the center line; a first detection element and a second detection element, each of which has a fixed layer and a free layer, disposed in the first bent portion, and a third detection element and a fourth detection element, disposed in the second bent portion; an application unit that applies a bias magnetic field to the free layer of each of the first detection element to the fourth detection element; Equipped with When a bridge circuit is formed from the first detection element to the fourth detection element, the magnetization directions of the pinned layers of the first detection element and the second detection element are opposite to each other in a direction perpendicular to the center line, and the magnetization directions of the pinned layers of the third detection element and the fourth detection element are opposite to each other in a direction perpendicular to the center line, When the bus bar is not energized and the bias magnetic field is applied by the application unit, the magnetization directions of the free layers of two detection elements forming a first set of the first to fourth detection elements are parallel to the center line and in the same direction as each other, and the magnetization directions of the free layers of the remaining two detection elements forming a second set are parallel to the center line and in the same direction as each other, opposite to the magnetization directions of the two detection elements forming the first set.

2. 2. The current sensor according to claim 1, wherein the first and second detection elements are arranged in the first bent portion, and the third and fourth detection elements are arranged in the second bent portion, such that an angle formed by the center line and a direction of an induced magnetic field generated when a current is applied to the bus bar is less than 90°.

3. The current sensor according to claim 1 , wherein the first to fourth detection elements are formed on a single substrate.

4. The current sensor according to claim 1 , wherein the application section is configured by a hard bias layer formed in each of the first to fourth detection elements.

5. 2. The current sensor according to claim 1, wherein the applying section is formed of a laminate including a ferromagnetic section and an antiferromagnetic section in contact with the ferromagnetic section and exchange-coupled with the ferromagnetic section.

6. The current sensor according to claim 1 , wherein the applying section is configured by an applying coil.

7. 2. The current sensor according to claim 1, wherein a first half-bridge circuit formed by the first detection element and the third detection element, and a second half-bridge circuit formed by the second detection element and the fourth detection element, together form a full-bridge circuit.

8. The current sensor according to claim 7, wherein the first detection element and the fourth detection element are both formed on a first chip, the second detection element and the third detection element are both formed on a second chip, and the first chip and the second chip have the same structure.

9. 8. The current sensor according to claim 7, wherein the two detection elements of the first set are assigned to the first half-bridge circuit and the second half-bridge circuit, respectively, and the two detection elements of the second set are assigned to the first half-bridge circuit and the second half-bridge circuit, respectively.

10. 2. The current sensor according to claim 1, wherein a first half-bridge circuit formed by the first detection element and the second detection element, and a second half-bridge circuit formed by the third detection element and the fourth detection element, together form a full-bridge circuit.

11. The current sensor of claim 10, wherein the first detection element and the second detection element are both formed on a first chip, the third detection element and the fourth detection element are both formed on a second chip, and the first chip and the second chip have the same structure.

12. 11. The current sensor according to claim 10, wherein the two detection elements of the first set are assigned to the first half-bridge circuit and the second half-bridge circuit, respectively, and the two detection elements of the second set are assigned to the first half-bridge circuit and the second half-bridge circuit, respectively.

13. A semiconductor current sensor comprising the current sensor according to any one of claims 1 to 12 housed in a single semiconductor package.

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