Mother board for display devices and display device manufacturing method

Abstract

To enable inspection of display devices during manufacturing to be carried out efficiently or with high accuracy.SOLUTION: A mother board for display devices according to an embodiment comprises: a plurality of panel units, each including a display region and a periphery region surrounding the display region; a margin region in the surrounding of the plurality of panel units; a lower electrode located in the display region; a rib layer having a pixel opening that overlaps the lower electrode; a first barrier located in the display region and enclosing the pixel opening; and a second barrier located in at least one of the peripheral region and the margin region. The first barrier includes a lower part and an upper part having an edge protruding from a side face of the lower part. The second barrier is provided with a first section that includes the lower part and does not include the upper part.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a mother substrate for a display device and a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. When manufacturing such display devices, inspections are performed to confirm whether elements on the substrate are formed as designed. There is a demand for technology to perform such inspections efficiently and with high accuracy. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a mother substrate for a display device and a method for manufacturing a display device, which enable efficient and highly accurate inspection during the manufacturing of the display device. [Means for solving the problem]

[0005] Generally, according to an embodiment, a mother substrate for a display device includes a plurality of panel sections each including a display area and a peripheral area around the display area, a margin area around the plurality of panel sections, a lower electrode disposed in the display area, a rib layer having pixel openings overlapping the lower electrode, a first partition wall disposed in the display area and surrounding the pixel opening, and a second partition wall disposed in at least one of the peripheral area and the margin area. The first partition wall includes a lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. The second partition wall includes a first portion that includes the lower portion but does not include the upper portion.

[0006] Furthermore, according to an embodiment, a method for manufacturing a display device includes preparing a substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion; forming a lower electrode in the display area; forming a rib layer covering the panel portion and the margin area; forming a first partition in the display area including a lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; forming a second partition in at least one of the margin area and the peripheral area, and performing an etching process to remove the upper portion of a first portion of the second partition. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display panel taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the motherboard according to the first embodiment. [Figure 5] FIG. 5 is a schematic plan view of a part of the motherboard according to the first embodiment. [Figure 6]FIG. 6 is a schematic plan view showing an example of a configuration applicable to the test pattern according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of the motherboard taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a flowchart showing an example of a method for manufacturing the display device according to the first embodiment. [Figure 9A] FIG. 9A is a schematic cross-sectional view showing a step of forming a panel section on the motherboard according to the first embodiment. [Figure 9B] FIG. 9B is a schematic cross-sectional view showing a step subsequent to FIG. 9A. [Figure 9C] FIG. 9C is a schematic cross-sectional view showing a step subsequent to FIG. 9B. [Figure 9D] FIG. 9D is a schematic cross-sectional view showing a step subsequent to FIG. 9C. [Figure 9E] FIG. 9E is a schematic cross-sectional view showing a step subsequent to FIG. 9D. [Figure 9F] FIG. 9F is a schematic cross-sectional view showing a step subsequent to FIG. 9E. [Figure 9G] FIG. 9G is a schematic cross-sectional view showing a step subsequent to FIG. 9F. [Figure 9H] FIG. 9H is a schematic cross-sectional view showing a step subsequent to FIG. 9G. [Figure 9I] FIG. 9I is a schematic cross-sectional view showing a step subsequent to FIG. 9H. [Figure 9J] FIG. 9J is a schematic cross-sectional view showing a step subsequent to FIG. 9I. [Figure 10A] FIG. 10A is a schematic cross-sectional view showing a step of removing the rib layer in the terminal portion. [Figure 10B] FIG. 10B is a schematic cross-sectional view showing a step subsequent to FIG. 10A. [Figure 11A] FIG. 11A is a schematic cross-sectional view showing an example of a step of removing the upper part from the partition walls of the test pattern according to the first embodiment. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing a step subsequent to FIG. 11A. [Figure 11C]FIG. 11C is a schematic cross-sectional view showing a step subsequent to FIG. 11B. [Figure 12] FIG. 12 is a schematic cross-sectional view showing an example of a measurement step according to the first embodiment. [Figure 13] FIG. 13 is a schematic plan view showing an example of a measurement step according to the first embodiment. [Figure 14A] FIG. 14A is a schematic cross-sectional view showing a part of the manufacturing process of the display device according to the second embodiment. [Figure 14B] FIG. 14B is a schematic cross-sectional view showing a step subsequent to FIG. 14A. [Figure 14C] FIG. 14C is a schematic cross-sectional view showing a step subsequent to FIG. 14B. [Figure 14D] FIG. 14D is a schematic cross-sectional view showing a step subsequent to FIG. 14C. [Figure 15] FIG. 15 is a schematic plan view of a test pattern according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may also include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] The display device DSP further includes a terminal unit T arranged in the peripheral area SA. For example, a flexible circuit board is connected to the terminal unit T. Signals and voltages for driving the pixel circuits 1 are input to the display device DSP via the flexible circuit board and the terminal unit T.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] Conductive partition walls 6A (first partition walls) are disposed above the rib layer 5. The partition walls 6A function as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition walls 6A entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5.

[0025] Specifically, the partition wall 6A has a partition wall opening 601A in the subpixel SP1, a partition wall opening 602A in the subpixel SP2, and a partition wall opening 603A in the subpixel SP3. The partition wall openings 601A, 602A, and 603A are larger than the pixel openings AP1, AP2, and AP3, respectively. The partition wall openings 601A, 602A, and 603A overlap the entire display elements DE1, DE2, and DE3, respectively. That is, the partition wall 6A surrounds the display elements DE1, DE2, and DE3.

[0026] 3 is a schematic cross-sectional view of the display panel PNL taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0027] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0028] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. This shape of the partition wall 6A is called an overhanging shape.

[0029] In the example of FIG. 3, the lower part 61 includes a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0030] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6A.

[0032] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0033] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0034] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the stacked film FL1 and the partition wall 6A around the subpixel SP1. The sealing layer SE12 continuously covers the stacked film FL2 and the partition wall 6A around the subpixel SP2. The sealing layer SE13 continuously covers the stacked film FL3 and the partition wall 6A around the subpixel SP3.

[0035] 3, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6A. Furthermore, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6A. As another example, the end of the sealing layer SE11 and the end of the sealing layer SE12 may overlap on the partition wall 6A. Similarly, the end of the sealing layer SE11 and the end of the sealing layer SE13 may overlap on the partition wall 6A.

[0036] 3, portions of the stacked films FL1, FL2, and FL3 are located on the partition wall 6A. Portions of these stacked films FL1, FL2, and FL3 are covered by sealing layers SE11, SE12, and SE13, respectively. As another example, at least one of the stacked films FL1, FL2, and FL3 does not need to be disposed on the partition wall 6A.

[0037] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0042] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0043] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The bottom layer 63 and the shaft layer 64 of the lower portion 64 of the partition wall 6A are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material. Alternatively, the lower portion 64 may be formed of a single layer.

[0045] The first top layer 65 of the partition wall 6A is formed of, for example, a metal material. The second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0046] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] When manufacturing the display device DSP, a large motherboard is fabricated on which a plurality of regions (panel portions) each corresponding to a display panel PNL are formed. A configuration applicable to this motherboard will be described below.

[0050] 4 is a schematic plan view of the mother substrate MB (mother substrate for a display device) according to this embodiment. The mother substrate MB has a rectangular shape as shown in the figure, but may have other shapes such as a circle.

[0051] The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA around the panel portions PP. In the example of Fig. 4, the panel portions PP are lined up in the X and Y directions with blank areas BA between them. However, at least two of the plurality of panel portions PP on the mother substrate MB may be adjacent to each other without a blank area BA between them.

[0052] The motherboard MB further includes at least one test pattern TG. In the example of Fig. 4, multiple test patterns TG are arranged in the blank area BA. The positions and number of these test patterns TG are not particularly limited, but as an example, it is preferable that the test patterns TG are distributed in various places, such as near the edges and in the center of the motherboard MB.

[0053] 5 is a schematic plan view of a portion of the mother substrate MB. This drawing focuses on one panel portion PP. The outer shape of the panel portion PP corresponds to a cutting line CL1 along which the panel portion PP is cut out from the mother substrate MB.

[0054] Each panel unit PP has the above-mentioned display area DA and peripheral area SA. The peripheral area SA further includes an inspection area TA. In the inspection area TA, test pads and the like for inspecting the operation of the display panel PNL are arranged.

[0055] A cut line CL2 is formed on each panel portion PP, which divides the panel portion PP into a portion including a display area DA and a portion including an inspection area TA.

[0056] When manufacturing the display device DSP, first, the panel portion PP is cut out from the mother substrate MB along the cut line CL1. Then, the cut-out panel portion PP is inspected using the inspection pads. After this inspection, the inspection area TA is cut out from the panel portion PP along the cut line CL2.

[0057] The test pattern TG shown in Figure 4 may be placed not only in the margin area BA but also in the peripheral area SA. For example, the test pattern TG can be placed in the inspection area TA. In this case, the test pattern TG will not remain in the panel portion PP after the inspection area TA is separated along the cut line CL2. Even when the test pattern TG is placed in the margin area BA as shown in Figure 4, the test pattern TG will not remain in the panel portion PP after the inspection area TA is separated along the cut line CL2.

[0058] As another example, the test pattern TG may be arranged in a portion of the peripheral area SA excluding the inspection area TA. In this case, the test pattern TG remains in the panel unit PP after the inspection area TA is cut off along the cut line CL2.

[0059] Fig. 6 is a schematic plan view showing an example of a configuration applicable to the test pattern TG. Fig. 7 is a schematic cross-sectional view of the motherboard MB taken along line VII-VII in Fig. 6. Elements below the organic insulating layer 12 are omitted in Fig. 7.

[0060] As shown in Fig. 6, the test pattern TG is formed by the partition walls 6B (second partition walls). In the example of Fig. 6, the partition walls 6B have partition wall openings 601B, 602B, and 603B.

[0061] For example, the shapes and layout of the partition wall openings 601B, 602B, and 603B are similar to those of the partition wall openings 601A, 602A, and 603A shown in Fig. 2. However, the partition wall 6B may have one or more openings with shapes different from those of the partition wall openings 601A, 602A, and 603A. Alternatively, the partition wall 6B may not have any openings.

[0062] The partition wall 6B has a first portion P1 (a portion with a diagonal line pattern) and a second portion P2 (a portion with a dot pattern). In the example of FIG. 6, the first portion P1 is located between the partition wall openings 601B and 602B. The portion of the partition wall 6B excluding the first portion P1 corresponds to the second portion P2. Note that the position where the first portion P1 is provided is not limited to this example.

[0063] 6 and 7, the first portion P1 includes the lower portion 61 (the bottom layer 63 and the axial layer 64) similar to the partition wall 6A, but does not include the upper portion 62 (the first top layer 65 and the second top layer 66).

[0064] On the other hand, as shown in FIG. 7, the second portion P2 includes a lower portion 61 (a bottom layer 63 and an axial layer 64) and an upper portion 62 (a first top layer 65 and a second top layer 66).

[0065] Similar to the partition wall 6A, in each of the first portion P1 and the second portion P2, both end portions of the bottom layer 63 protrude from the side surfaces of the stem layer 64. In addition, in the second portion P2, both end portions of the upper portion 62 protrude from the side surfaces of the stem layer 64.

[0066] The lower portion 61 of the partition wall 6B is formed of the same material as the lower portion 61 of the partition wall 6A. Specifically, the bottom layer 63 and the shaft layer 64 of the first portion P1 and the second portion P2 are formed of the same material as the bottom layer 63 and the shaft layer 64 of the partition wall 6A, respectively. The thickness of the bottom layer 63 of the first portion P1 and the second portion P2 is equal to the thickness of the bottom layer 63 of the partition wall 6A. Furthermore, the thickness of the shaft layer 64 of the first portion P1 and the second portion P2 is equal to the thickness of the shaft layer 64 of the partition wall 6A.

[0067] The upper portion 62 of the second portion P2 is formed of the same material as the upper portion 62 of the partition wall 6A. Specifically, the first top layer 65 and the second top layer 66 of the second portion P2 are formed of the same material as the first top layer 65 and the second top layer 66 of the partition wall 6A, respectively. The thickness of the first top layer 65 of the second portion P2 is equal to the thickness of the first top layer 65 of the partition wall 6A. Furthermore, the thickness of the second top layer 66 of the second portion P2 is equal to the thickness of the second top layer 66 of the partition wall 6A.

[0068] 6, the outline of the lower portion 61 of the second portion P2 is indicated by a broken line. For example, the lower portion 61 of the second portion P2 is connected to the lower portion 61 of the first portion P1.

[0069] As shown in Fig. 7, lower portions 61 of the first portion P1 and the second portion P2 are disposed on the rib layer 5. In the examples of Figs. 6 and 7, the rib layer 5 has a pair of openings 50 located around the first portion P1. The first portion P1 is located between these openings 50 in a plan view. Instead of the openings 50, recesses having the same shape as the openings 50 may be formed in the rib layer 5.

[0070] Next, an example of a manufacturing method of the display device DSP will be described. Fig. 8 is a flowchart showing an example of the manufacturing method of the display device DSP. Figs. 9A to 9J are schematic cross-sectional views showing the process of forming a panel section PP on a mother substrate MB. Figs. 9A to 9J mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0071] In forming the panel portion PP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10 of a mother substrate MB (step PR1 in FIG. 8). Next, as shown in FIG. 9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in FIG. 8).

[0072] Next, as shown in Fig. 9B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB (step PR3 in Fig. 8). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0073] After the rib layer 5 is formed, steps for forming the partition walls 6A are performed (steps PR4 and PR5 in FIG. 8). In step PR4, as shown in FIG. 9C, a first layer L1 to be processed into the bottom layer 63, a second layer L2 to be processed into the shaft layer 64, a third layer L3 to be processed into the first top layer 65, and a fourth layer L4 to be processed into the second top layer 66 are sequentially formed over the entire mother substrate MB. Furthermore, a resist R1 is disposed on the fourth layer L4. The resist R1 is patterned into the shape of the partition walls 6A. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be formed by, for example, sputtering.

[0074] In the subsequent step PR5, the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, step PR5 may include wet etching to remove portions of the fourth layer L4 that are not covered by the resist R1, dry etching to remove portions of the first layer L1, the second layer L2, and the third layer L3 that are not covered by the resist R1, and wet etching to reduce the width of the second layer L2. The etching performed in step PR5 is appropriately selected depending on the structure and material of the partition wall 6A.

[0075] After step PR5, as shown in FIG. 9D, the partition walls 6A are formed in the display area DA. After the partition walls 6A are formed, the resist R1 is removed (peeled off). In the wet etching that reduces the width of the second layer L2 described above, the second top layer 66 (fourth layer L4) may also be slightly eroded. If this erosion occurs, the width of the second top layer 66 will be smaller than the width of the first top layer 65.

[0076] Next, a step for providing pixel openings AP1, AP2, and AP3 is performed (step PR6 in FIG. 8). In this step PR6, a resist R2 is formed to cover the partition wall 6A, as shown in FIG. 9E. Furthermore, using the resist R2 as a mask, dry etching is performed on the rib layer 5. As a result, pixel openings AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed in the rib layer 5, as shown in FIG. 9F. After the dry etching, the resist R2 is removed (peeled off).

[0077] After step PR6, a step for removing the rib layer 5 in the terminal portion T shown in FIG. 1 is carried out (step PR7 in FIG. 8).

[0078] 10A and 10B are schematic cross-sectional views of the terminal portion T for explaining step PR7. As shown in these figures, the terminal portion T includes a conductive pad PD. The pad PD is disposed on an insulating layer 110 made of, for example, an inorganic insulating material. The pad PD and the insulating layer 110 are included in, for example, the circuit layer 11 shown in FIG. 3. For example, the periphery of the pad PD is covered with an organic insulating layer 12.

[0079] Upon completion of step PR6, the pads PD are covered with the rib layer 5 as shown in FIG. 10A. In step PR7, a resist R3 having an opening above the pads PD is placed on the rib layer 5. Then, using the resist R3 as a mask, the rib layer 5 is dry-etched. As a result, a terminal opening APt that exposes the pads PD is formed in the rib layer 5 as shown in FIG. 10B. After the dry etching, the resist R3 is removed (peeled off).

[0080] After step PR7, a step for forming display element DE1 is performed (step PR8 in FIG. 8). To form display element DE1, first, as shown in FIG. 9G, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0081] The laminated film FL1 and sealing layer SE11 are formed over the entire mother substrate MB, including the display area DA of each panel unit PP, the peripheral area SA, and the margin area BA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6A. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6A.

[0082] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R4 is disposed on the sealing layer SE11, as shown in FIG. 9G. The resist R4 covers the subpixel SP1 and part of the partition wall 6A around it.

[0083] Then, an etching process is performed using the resist R4 as a mask. As a result, as shown in FIG. 9H, the portions of the stacked film FL1 and the sealing layer SE11 exposed by the resist R4 are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, in the peripheral region SA and the marginal region BA, the stacked film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R4 is removed (peeled off).

[0084] After step PR8, a step for forming display element DE2 is performed (step PR9 in FIG. 8). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0085] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. The stacked film FL2 is divided into multiple parts by overhanging partition walls 6A. The sealing layer SE12 continuously covers each divided part of the stacked film FL2 and the partition walls 6A. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 9I. For example, in the peripheral region SA and the marginal region BA, the stacked film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0086] After step PR9, a step for forming display element DE3 is performed (step PR10 in FIG. 8). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0087] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. The stacked film FL3 is divided into multiple parts by overhanging partition walls 6A. The sealing layer SE13 continuously covers each divided part of the stacked film FL3 and the partition walls 6A. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 9J. For example, in the peripheral region SA and the marginal region BA, the stacked film FL3 and the sealing layer SE13 are removed by etching during the patterning process.

[0088] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0089] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Figure 3 are formed in this order (step PR11 in Figure 8). Furthermore, each panel portion PP is cut out from the mother substrate MB along the cutting line CL1 (step PR12 in Figure 8).

[0090] Thereafter, an inspection is carried out on each panel portion PP (step PR13 in FIG. 8). This inspection includes an inspection of the lighting of each display element DE1, DE2, DE3 using inspection pads arranged in the inspection area TA. After the inspection, the inspection area TA is cut along the cut line CL2 (step PR14 in FIG. 8). This completes the display panel PNL.

[0091] The partition wall 6B is formed by steps PR4 and PR5, similar to the partition wall 6A. However, immediately after step PR5, the partition wall 6B has an upper portion 62 as a whole. That is, the upper portion 62 is also disposed in the first portion P1 shown in FIGS. 6 and 7.

[0092] 11A to 11C are schematic cross-sectional views showing an example of a process for removing the upper portion 62 from the first portion P1. These cross-sectional views show the same portion as in FIG. 7, and elements below the organic insulating layer 12 are omitted.

[0093] To remove the upper portion 62 from the first portion P1, a resist R is formed to cover the partition wall 6B, as shown in FIG. 11A. Furthermore, as indicated by the arrows, the resist R is exposed using a mask MK. The mask MK has an opening above the first portion P1. The resist R is, for example, a positive type. Therefore, as shown in FIG. 11B, the exposed portion of the resist R is removed in a development process. In FIG. 11B, the second portion P2 is entirely covered with the resist R. Furthermore, the upper portion 62 of the first portion P1 is exposed from the resist R.

[0094] For example, if the first top layer 65 is made of a metal material, the first top layer 65 has light-shielding properties. In this case, the resist R located below the first top layer 65 is not exposed. Therefore, in FIG. 11B, the resist R remains below the upper portion 62 of the first portion P1.

[0095] Next, an etching step is performed with the resist R in place. As a result, as shown in Fig. 11C, the upper portion 62 of the first portion P1 is removed, exposing the upper surface of the shaft layer 64. The upper portion 62 of the second portion P2 is not removed by the etching step because it is covered with the resist R.

[0096] The etching step may be a single type of etching (e.g., dry etching) that simultaneously removes the first top layer 65 and the second top layer 66. As another example, the etching step may include etching to remove the second top layer 66 and etching to remove the first top layer 65. For example, if the first top layer 61 is formed of titanium and the second top layer 66 is formed of ITO, the etching step may include wet etching to remove the second top layer 66 and dry etching to remove the first top layer 65.

[0097] If the etching step includes dry etching, the rib layer 5 exposed from the resist R may also be removed. As a result, an opening 50 is formed in the rib layer 5 around the first portion P1. After the etching step, the resist R is removed (peeled off).

[0098] During the etching process, the resist R entirely covers the partition walls 6A in the display area DA, so the partition walls 6A are not eroded during the etching process.

[0099] 8. As the process shown in FIGS. 11A to 11C, process PR6 for forming pixel openings AP1, AP2, and AP3 in the rib layer 5 may be used. In this case, the resist R corresponds to the resist R2 shown in FIG. 9E. In addition, the etching process for removing the upper portion 62 of the first portion P1 includes dry etching for forming the pixel openings AP1, AP2, and AP3 in the rib layer 5.

[0100] 11A to 11C, a step PR7 for forming a terminal opening APt in the rib layer 5 may be used. In this case, the resist R corresponds to the resist R3 shown in FIGS. 10A and 10B. The etching step for removing the upper portion 62 of the first portion P1 includes dry etching for forming the terminal opening APt in the rib layer 5.

[0101] After removing the upper portion 62 of the first portion P1, a measurement step is performed on the partition 6B of the test pattern TG. The timing of performing this measurement step is not particularly limited. In one example, the measurement step is performed before forming the display elements DE1, DE2, and DE3 (steps PR8, PR9, and PR10).

[0102] Fig. 12 is a schematic cross-sectional view showing an example of the measurement step. Fig. 13 is a schematic plan view showing an example of the measurement step. In the measurement step, as shown in Fig. 12, the height H of the lower part 61 of the first portion P1 is measured. The height H corresponds to the distance in the Z direction from the upper surface of the rib layer 5 to the upper surface of the shaft layer 64. The height H can be measured using, for example, an atomic force microscope (AFM) or a white light interference microscope.

[0103] 12 and 13, the length L1 of the bottom layer 63 protruding from the side surface of the shaft layer 64 is measured. The length L1 corresponds to the distance between the side surface of the shaft layer 64 and the end of the bottom layer 63 in the X direction. The length L1 can be measured, for example, by analyzing an image of the first portion P1 taken in a planar view.

[0104] Furthermore, in the measuring step, a length L2 of the upper portion 62 protruding from the side surface of the shaft layer 64 is measured based on the first portion P1 and the second portion P2, as shown in Fig. 13. In the example of Fig. 13, the length L2 corresponds to the distance between the side surface of the shaft layer 64 and the end portion of the first top layer 65 in the X direction. The length L2 can be measured, for example, by analyzing an image obtained by photographing the first portion P1 and the second portion P2 in a planar view.

[0105] The first portion P1 and the second portion P2 shown in FIG. 13 are both located between the partition openings 601B and 602B and extend in the Y direction. The lower portions 61 of the first portion P1 and the second portion P2 each have a width W1. The width W1 corresponds to the width of the bottom layer 63 in the X direction. The width W1 is the sum of the width W11 of the shaft layer 64 in the X direction and twice the length L1. The width W11 and length L1 of the lower portion 61 of the first portion P1 are the same as those of the lower portion 61 of the second portion P2 adjacent to the first portion P1.

[0106] In such a case, the length L2 can be calculated by, for example, multiplying the difference between the width W2 of the upper portion 62 of the second portion P2 and the width W11 of the stem layer 64 of the first portion P1 by 1 / 2. In the example of FIG. 13 , the width W2 corresponds to the width of the first top layer 65 in the X direction. The length L2 may be calculated by measuring the length of the first top layer 65 of the second portion P2 that protrudes from the side surface of the stem layer 64 of the first portion P1 at the boundary between the first portion P1 and the second portion P2.

[0107] The height H, length L1, and length L2 obtained in the measurement process are used to inspect whether the partition 6A is formed normally. That is, because the partitions 6A and 6B are formed in the same process (PR4 and PR5 in FIG. 8), the height H, length L1, and length L2 measured for the partition 6B can be considered to be the height H, length L1, and length L2 of the partition 6A, respectively. If at least one of the height H, length L1, and length L2 is outside a predetermined tolerance range, the manufacturing process after the measurement process may be stopped.

[0108] The measurement process may be performed for each of the multiple test patterns TG distributed on the mother substrate MB as shown in Fig. 4. In this case, it is possible to suppress variations in measurement depending on the position on the mother substrate MB. As another example, the measurement process may be performed for some of the multiple test patterns TG.

[0109] As described above, in this embodiment, the measurement step is performed using the first portion P1 that does not include the upper portion 62. If the entire partition wall 6B includes the upper portion 62, it is necessary to measure the height H, length L1, and length L2 through destructive testing to observe the cross section of the partition wall 6B. Destructive testing is difficult to perform during the manufacturing process of the display device DSP, and the testing requires time and effort.

[0110] In contrast, if the test pattern TG is provided with the first portion P1 that does not include the upper portion 62 as in the present embodiment, it is possible to measure the height H, length L1, and length L2 by observing the mother substrate MB from above without requiring destructive testing. Such measurements can be easily performed during the manufacturing of the display device DSP, and if an inspection using the measurement results indicates a defect, the manufacturing can be stopped without performing any subsequent processes.

[0111] Furthermore, as described above, when the process PR6 for forming pixel openings AP1, AP2, and AP3 in the rib layer 5 is used as the process for removing the upper portion 62 from the partition wall 6B, an increase in the number of steps can be suppressed. The same applies when the process PR7 for forming terminal openings APt in the rib layer 5 is used.

[0112] Furthermore, as shown in FIG. 6, when the partition 6B of the test pattern TG has a shape similar to that of the partition 6A, it is expected that the measurement results of the height H, length L1, and length L2 of the partition 6B will be more consistent with the actual height H, length L1, and length L2 of the partition 6A.

[0113] As described above, according to this embodiment, it is possible to efficiently and highly accurately inspect the display device DSP during manufacturing. In addition to the effects described above, various other advantageous effects can be obtained from this embodiment.

[0114] [Second embodiment] A second embodiment will now be described. Elements similar to those in the first embodiment will be given the same reference numerals and redundant explanations will be omitted.

[0115] 14A to 14D are schematic cross-sectional views showing a part of the manufacturing process of the display device DSP according to this embodiment. Specifically, these figures, like FIGS. 11A to 11C, show an example of the process of removing the upper portion 62 from the first portion P1.

[0116] 11A, a positive resist R is formed to cover the partition wall 6B. Furthermore, as indicated by the arrows, the resist R is exposed using a mask MK. The mask MK has an opening above the first portion P1. The opening width of the mask MK is equal to the width of the upper portion 62 (the width of the first top layer 65 in FIG. 14A).

[0117] A development process following such exposure removes the exposed portions of the resist R, as shown in FIG. 14B. In FIG. 11B, the second portion P2 is entirely covered with the resist R. Furthermore, an upper portion 62 of the first portion P1 is exposed from the resist R. Because the opening width of the mask MK is equal to the width of the upper portion 62, the resist R around the first portion P1 is not removed. As a result, the rib layer 5 around the first portion P1 is not exposed from the resist R.

[0118] Next, an etching step is performed with the resist R in place. As a result, the upper portion 62 of the first portion P1 is removed, as shown in FIG. 14C. The shape of the first portion P1 thus formed is the same as the example in FIG. 11C. However, in FIG. 14C, the opening 50 in the rib layer 5 is not formed.

[0119] After the etching step, the resist R is removed (peeled off) as shown in Fig. 14D. Using the first portion P1 and the second portion P2 thus formed, a measurement step similar to that in the first embodiment is carried out. Even in this case, the same effects as in the first embodiment can be obtained.

[0120] [Third embodiment] A third embodiment will now be described. Elements similar to those in the first embodiment will be assigned the same reference numerals and overlapping descriptions will be omitted.

[0121] 15 is a schematic plan view of a test pattern TG according to the third embodiment. In the example of this figure, two first portions P1 (P1x, P1y) are provided in one test pattern TG.

[0122] 6, and is located between the partition wall openings 601B and 602B. On the other hand, the first portion P1x is located between the partition wall openings 602B and 603B.

[0123] From another perspective, the first portion P1y is provided in a portion of the partition wall 6B extending in the Y direction, while the first portion P1x is provided in a portion of the partition wall 6B extending in the X direction.

[0124] 15, a plurality of openings 50 adjacent to the first portions P1x and P1y are provided in the rib layer 5. However, similar to the second embodiment, the rib layer 5 does not necessarily have to have the openings 50.

[0125] For example, the above-described measurement process is performed on both of the first portions P1x and P1y. If the values ​​of the height H, length L1, and length L2 may vary depending on the extending direction of the partition walls 6A and 6B, more accurate measurements can be achieved by applying the configuration of this embodiment.

[0126] The number of first portions P1 provided in one test pattern TG may be 3 or more. In addition, although the examples in which the area of ​​the first portion P1 is smaller than the area of ​​the second portion P2 are shown in both Figures 6 and 15, the area of ​​the first portion P1 may be larger than the area of ​​the second portion P2.

[0127] All display devices, motherboards, and manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices, motherboards, and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0128] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0129] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0130] MB...motherboard, DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, TG...test pattern, 5...rib layer, 6A, 6B...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a plurality of panel units each including a display area and a peripheral area around the display area; marginal areas around the plurality of panel portions; a lower electrode disposed in the display area; a rib layer having pixel openings overlapping the lower electrode; a first partition wall disposed in the display region and surrounding the pixel opening; a second partition wall disposed in at least one of the peripheral region and the margin region; Equipped with the first partition wall includes a lower portion and an upper portion having an end portion protruding from a side surface of the lower portion, the second partition wall has a first portion that includes the lower portion and does not include the upper portion. Motherboard for display devices.

2. the lower portion of each of the first partition wall and the second partition wall is disposed on the rib layer; The mother substrate for a display device according to claim 1 .

3. In each of the first partition wall and the second partition wall, the lower portion includes a bottom layer and an axial layer disposed on the bottom layer. The mother substrate for a display device according to claim 1 .

4. The end of the bottom layer protrudes from the side surface of the shaft layer. The mother substrate for a display device according to claim 3 .

5. the bottom layer of the first partition wall and the bottom layer of the second partition wall are formed of the same material; The mother substrate for a display device according to claim 3 .

6. the shaft layer of the first partition wall and the shaft layer of the second partition wall are formed of the same material; The mother substrate for a display device according to claim 3 .

7. The rib layer has an opening located around the periphery of the first portion. The mother substrate for a display device according to claim 1 .

8. the second partition wall further comprises a second portion including the lower portion and the upper portion.

8. The mother substrate for a display device according to claim 1.

9. the upper portion of the first partition wall and the upper portion of the second portion are formed of the same material. The mother substrate for a display device according to claim 8 .

10. a width of the lower portion of the first portion and a width of the lower portion of at least a part of the second portion are equal to each other; The mother substrate for a display device according to claim 8 .

11. The lower portion of the first portion and the lower portion of the second portion are connected to each other. The mother substrate for a display device according to claim 8 .

12. A substrate is prepared, the substrate including a panel portion including a display area and a peripheral area around the display area, and a margin area around the panel portion; forming a lower electrode in the display area; forming a rib layer covering the panel portion and the marginal area; forming a first partition wall in the display area, the first partition wall including a lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; forming a second partition wall including the lower portion and the upper portion in at least one of the marginal region and the peripheral region; performing an etching process to remove the upper portion of the first portion of the second partition wall; A method for manufacturing a display device, comprising:

13. measuring the height of the lower portion of the first portion from which the upper portion has been removed; The method for manufacturing a display device according to claim 12 , further comprising:

14. In each of the first partition wall and the second partition wall, the lower portion includes a bottom layer and a shaft layer disposed on the bottom layer, The end of the bottom layer protrudes from the side surface of the shaft layer. The method for manufacturing a display device according to claim 12 .

15. Measure the length of the bottom layer protruding from the side of the shaft layer at the lower part of the first portion from which the upper part has been removed. The method for manufacturing a display device according to claim 14 , further comprising:

16. before the etching step, a resist is disposed to cover the first partition wall and expose the first portion of the second partition wall; performing the etching step with the resist in place to remove the upper portion of the first portion; The method for manufacturing a display device according to claim 12 .

17. the resist covers a second portion of the second partition wall; the second portion after the etching step has the lower portion and the upper portion; The method for manufacturing a display device according to claim 16.

18. measuring a length of the upper portion protruding from the side surface of the lower portion based on the first portion and the second portion; The method for manufacturing a display device according to claim 17, further comprising:

19. forming a pixel opening in the rib layer by the etching step, the pixel opening exposing the lower electrode; The method for manufacturing a display device according to claim 14 , further comprising:

20. The etching step forms terminal openings in the rib layer that expose conductive pads located below the rib layer. The method for manufacturing a display device according to claim 14 , further comprising:

Images