Method of manufacturing electro-optical device

Abstract

To provide a method of manufacturing an electro-optical device capable of simplifying a manufacturing process.SOLUTION: A method of manufacturing an electro-optical device includes steps of: forming a capacitive element; forming a first insulating layer; forming a scanning line; forming a second insulating layer; forming a semiconductor layer; forming a gate insulating layer; etching the second insulating layer to form a first contact hole exposing the scanning line; etching the second insulating layer and the first insulating layer to form a second contact hole exposing a first capacitance electrode; and forming a gate electrode on the gate insulating layer, forming a first conductive portion in the first contact hole, forming a first electrode on the semiconductor layer, and forming a second conductive portion in the second contact hole. The steps of forming the first contact hole and forming the second contact hole are performed simultaneously.SELECTED DRAWING: Figure 19

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing an electro-optical device. [Background technology]

[0002] 2. Description of the Related Art One known electro-optical device is an active drive type liquid crystal device, in which each pixel has a transistor that controls switching of a pixel electrode.

[0003] For example, Patent Document 1 describes an electro-optical device including scanning lines, data lines, TFTs, pixel electrodes, and capacitive elements. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-144370 Summary of the Invention [Problem to be solved by the invention]

[0005] In the electro-optical device described above, it is desired to simplify the manufacturing process. [Means for solving the problem]

[0006] One aspect of the method for manufacturing an electro-optical device according to the present invention is to forming a capacitance element on a substrate, the capacitance element having a first capacitance electrode, a second capacitance electrode, and a dielectric layer provided between the first capacitance electrode and the second capacitance electrode; forming a first insulating layer covering the capacitive element; forming a scan line on the first insulating layer; forming a second insulating layer covering the scan lines; forming a semiconductor layer on the second insulating layer; forming a gate insulating layer on the semiconductor layer; Etching the second insulating layer to form a first contact hole exposing the scan line; etching the second insulating layer and the first insulating layer to form a second contact hole exposing the first capacitor electrode; forming a gate electrode on the gate insulating layer, forming a first conductive portion in the first contact hole that electrically connects the gate electrode and the scanning line, forming a first electrode on the semiconductor layer, and forming a second conductive portion in the second contact hole that electrically connects the first electrode and the first capacitor electrode; and The step of forming the first contact hole and the step of forming the second contact hole are carried out simultaneously. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 2] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the electro-optical device according to the embodiment. [Figure 4] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 5] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 6] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 7] FIG. 1 is a cross-sectional view schematically showing an electro-optical device according to an embodiment. [Figure 8] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 9] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 10] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 11] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 12]FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 13] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 14] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 15] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 16] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 17] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 18] FIG. 1 is a plan view schematically showing an electro-optical device according to an embodiment. [Figure 19] 4 is a flowchart illustrating a method for manufacturing an electro-optical device according to the embodiment. [Figure 20] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 21] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 22] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 23] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 24] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 25] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 26] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 27] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 28] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 29] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 30]5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 31] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 32] 5A to 5C are cross-sectional views schematically illustrating the manufacturing process of the electro-optical device according to the embodiment. [Figure 33] 1A and 1B are diagrams for explaining an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Electro-optical devices 1.1. Overall structure First, a liquid crystal device 100 as an electro-optical device according to this embodiment will be described with reference to the drawings. Fig. 1 is a plan view schematically showing the liquid crystal device 100 according to this embodiment. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1, schematically showing the liquid crystal device 100 according to this embodiment. Note that Figs. 1 and 2 illustrate an X-axis, a Y-axis, and a Z-axis as three mutually orthogonal axes.

[0010] The liquid crystal device 100 is an active-drive liquid crystal device having a thin film transistor (TFT) as a transistor for each pixel. As shown in Figures 1 and 2, the liquid crystal device 100 includes, for example, an element substrate 10, a sealant 20, a liquid crystal layer 30, and an opposing substrate 40.

[0011] As shown in FIG. 1, the element substrate 10 is larger than the counter substrate 40 in a plan view. The planar shape of the element substrate 10 is, for example, a rectangle. In the illustrated example, "planar view" refers to the view from the Z-axis direction. Note that "up" refers to the direction perpendicular to the substrate surface of the element substrate 10, from the substrate surface of the element substrate 10 toward the liquid crystal layer 30, etc., i.e., the Z-axis direction.

[0012] The sealant 20 bonds the element substrate 10 and the counter substrate 40 together. The sealant 20 is provided along the outer edge of the counter substrate 40. The sealant 20 is, for example, an adhesive such as a thermosetting, photosetting, or electron beam curing epoxy resin. A display region E including a plurality of pixels P arranged in a matrix is ​​provided inside the sealant 20. The display region E is surrounded by a peripheral region F. In the peripheral region F, a parting portion 42 is provided between the sealant 20 and the display region E, surrounding the display region E. The parting portion 42 is made of, for example, a light-shielding metal or metal oxide.

[0013] The element substrate 10 includes, for example, an external connection terminal 101, a data line driving circuit 102, an inspection circuit 103, a scanning line driving circuit 104, first wiring 105, and second wiring 106.

[0014] A plurality of external connection terminals 101 are provided. In the illustrated example, the plurality of external connection terminals 101 are arranged in the X-axis direction. The data line driving circuit 102 is provided between a first side along the plurality of external connection terminals 101 and the sealing material 20. The inspection circuit 103 is provided between the display area E and the sealing material 20 along a second side opposite to the first side. The scanning line driving circuit 104 is provided between the display area E and the sealing material 20 along third and fourth sides perpendicular to the first side and opposite to each other. Although not illustrated, the inspection circuit 103 may also be provided between the display area E and the sealing material 20 along the data line driving circuit 102.

[0015] The first wiring 105 is provided between the sealant 20 along the second side and the inspection circuit 103. The first wiring 105 is connected to two scanning line driving circuits 104. A plurality of first wirings 105 are provided. The second wiring 106 is connected to the data line driving circuit 102 and the scanning line driving circuit 104. The second wiring 106 is electrically connected to a plurality of external connection terminals 101. A plurality of second wirings 106 are provided.

[0016] As shown in FIG. 2, the element substrate 10 includes, for example, a first substrate 11, pixel electrodes 12, TFTs 50, and a first alignment layer 13.

[0017] The first substrate 11 is, for example, a glass substrate or a quartz substrate.

[0018] The pixel electrodes 12 and the TFTs 50 are provided on the liquid crystal layer 30 side of the first substrate 11. A pixel electrode 12 and a TFT 50 are provided for each pixel P. A plurality of pixel electrodes 12 and TFTs 50 are provided corresponding to a plurality of pixels P. The pixel electrodes 12 and the TFTs 50 constitute a pixel P. The pixel electrodes 12 are transparent electrodes made of, for example, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The TFTs 50 are switching elements.

[0019] The first alignment layer 13 is provided on the liquid crystal layer 30 side of the first substrate 11. The first alignment layer 13 covers the first substrate 11, the pixel electrodes 12, the TFTs 50, and the first wiring 105. The first alignment layer 13 is, for example, an inorganic alignment layer such as a silicon oxide layer, or an organic alignment layer such as a polyimide layer.

[0020] The liquid crystal layer 30 is provided between the element substrate 10 and the counter substrate 40. The liquid crystal layer 30 is formed by sealing liquid crystal having positive or negative dielectric anisotropy in the gap between the element substrate 10 and the counter substrate 40.

[0021] The counter substrate 40 is provided on the opposite side of the liquid crystal layer 30 from the element substrate 10 side. Light L is incident on the counter substrate 40. The light L is incident on the liquid crystal device 100 from the counter substrate 40 side. The light L is emitted, for example, from a laser light source (not shown). The light L may also be incident from the element substrate 10 side. Although not shown, the liquid crystal device 100 may also have a focusing means such as a microlens that focuses the incident light L for each pixel P.

[0022] The counter substrate 40 includes, for example, a second substrate 41, a parting portion 42, an insulating layer 43, a counter electrode 44, and a second alignment layer 45.

[0023] The second substrate 41 is disposed opposite the first substrate 11. The second substrate 41 is, for example, a glass substrate or a quartz substrate. The second substrate 41 transmits light L. In a plan view, the area of ​​the second substrate 41 is, for example, smaller than the area of ​​the first substrate 11.

[0024] The parting portion 42 is provided on the liquid crystal layer 30 side of the second substrate 41. As shown in FIG. 1, the parting portion 42 overlaps with the inspection circuit 103 and the scanning line driving circuit 104 in a plan view. The parting portion 42 blocks light L incident from the counter substrate 40 side from entering peripheral circuits such as the inspection circuit 103 and the scanning line driving circuit 104. This makes it possible to suppress malfunction of the peripheral circuits. Furthermore, the parting portion 42 reduces the incidence of unnecessary stray light into the display region E. This makes it possible to suppress a decrease in the contrast of the liquid crystal device 100.

[0025] As shown in FIG. 2, the insulating layer 43 is provided on the liquid crystal layer 30 side of the second substrate 41. The insulating layer 43 covers the parting portion 42. The insulating layer 43 is provided between the liquid crystal layer 30 and the second substrate 41. The surface of the insulating layer 43 facing the liquid crystal layer 30 is, for example, a flat surface. The insulating layer 43 transmits light L. The insulating layer 43 is, for example, a silicon oxide layer.

[0026] The counter electrode 44 is provided on the liquid crystal layer 30 side of the insulating layer 43. The counter electrode 44 is provided between the liquid crystal layer 30 and the insulating layer 43. The counter electrode 44 is electrically connected to conductive portions 46 shown in FIG. 1 provided at the four corners of the counter substrate 40. The conductive portions 46 are electrically connected to common wiring 16, which will be described later. The counter electrode 44 is a transparent electrode made of, for example, ITO or IZO. The conductive portions 46 are made of a metal, such as copper or aluminum.

[0027] 2, the second alignment layer 45 is provided on the liquid crystal layer 30 side of the counter electrode 44. The liquid crystal layer 30 is provided between the first alignment layer 13 and the second alignment layer 45. The second alignment layer 45 is, for example, an inorganic alignment layer such as a silicon oxide layer, or an organic alignment layer such as a polyimide layer.

[0028] The liquid crystal device 100 employs optical designs for a normally white mode or a normally black mode. In the normally white mode, the transmittance of the pixel P when no voltage is applied is greater than the transmittance when a voltage is applied. In the normally black mode, the transmittance of the pixel P when no voltage is applied is less than the transmittance when a voltage is applied. Although not shown, polarizing elements may be arranged on the incident side and the exit side of the light L in the liquid crystal device 100 according to the optical design.

[0029] In the following, an example will be described in which inorganic alignment layers are used as the alignment layers 13 and 45, and a liquid crystal layer 30 made of liquid crystal having negative dielectric anisotropy is used, and an optical design of a normally black mode is adopted.

[0030] 1.2. Equivalent Circuit FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device 100. As shown in FIG.

[0031] 3, the element substrate 10 of the liquid crystal device 100 has, for example, scanning lines 14, data lines 15, and common wiring 16. The scanning lines 14, the data lines 15, and the common wiring 16 are provided above a first substrate 11 of the element substrate 10.

[0032] The scanning lines 14 extend in the X-axis direction. The data lines 15 and the common wiring 16 extend in the Y-axis direction. Although not shown, the common wiring 16 does not have to extend in the Y-axis direction. A pixel P is an area defined by the scanning lines 14 and the data lines 15. The pixel P includes a pixel electrode 12, a TFT 50, and a capacitance element 60. The capacitance element 60 is provided corresponding to the pixel electrode 12.

[0033] The scanning lines 14 are electrically connected to the gates of the TFTs 50. The data lines 15 are electrically connected to the sources of the TFTs 50. The scanning lines 14 simultaneously control the on / off of the TFTs 50 arranged in the X-axis direction. The pixel electrodes 12 are electrically connected to the drains of the TFTs 50.

[0034] The data lines 15 are electrically connected to the data line driving circuit 102. The data lines 15 supply image signals D1, D2, ..., Dn supplied from the data line driving circuit 102 to the pixels P. The scanning lines 14 are electrically connected to the scanning line driving circuit 104. The scanning lines 14 supply scanning signals SC1, SC2, ..., SCm supplied from the scanning line driving circuit 104 to the pixels P.

[0035] The image signals D1, D2, ..., Dn supplied from the data line driving circuit 102 to the data lines 15 may be supplied line-sequentially in this order, or may be supplied in groups to adjacent data lines 15. The scanning line driving circuit 104 may supply scanning signals SC1, SC2, ..., SCm to the scanning lines 14 in pulsed line-sequential manner at predetermined timing.

[0036] When a scanning signal SC1 is input to the TFT 50, the TFT 50 is turned on for a certain period of time. As a result, an image signal D1 supplied from the data line 15 is written to the pixel electrode 12 at a predetermined timing. The image signal D1 of a predetermined level written to the liquid crystal layer 30 via the pixel electrode 12 is then held for a certain period of time between the pixel electrode 12 and the counter electrode 44 disposed opposite the pixel electrode 12 with the liquid crystal layer 30 interposed therebetween.

[0037] One end of the capacitance element 60 is electrically connected to the drain of the TFT 50 and the pixel electrode 12. The other end of the capacitance element 60 is electrically connected to the common line 16 to which a constant potential is applied. The capacitance element 60 prevents the stored image signal D1 from leaking.

[0038] Although not shown, an inspection circuit 103 is connected to the data lines 15. This makes it possible to detect the image signals D1, D2, ..., Dn during the manufacturing process of the liquid crystal device 100 and check for operational malfunctions of the liquid crystal device 100. Furthermore, two capacitive elements 60 may be provided in parallel in one pixel P.

[0039] 1.3. Element substrate configuration FIG. 4 is a plan view schematically showing the element substrate 10 of the liquid crystal device 100. FIG. 5 is a cross-sectional view taken along line AA in FIG. 4, schematically showing the element substrate 10. FIG. 6 is a cross-sectional view taken along line BB in FIG. 4, schematically showing the element substrate 10. FIG. 7 is a cross-sectional view taken along line CC in FIG. 4, schematically showing the element substrate 10. FIGS. 8 to 18 are plan views schematically showing the element substrate 10. For convenience, FIGS. 8 to 18 only show some of the components of the element substrate 10 around one pixel P.

[0040] 4 to 18, the element substrate 10 of the liquid crystal device 100 includes, for example, a capacitive element 60, interlayer insulating layers 71, 72, 73, 74, 75, and 76, relay electrodes 80, 81, 82, 83, 84, and 85, and a spacer 90. For convenience, components other than the scanning line 14, the semiconductor layer 52 of the TFT, the relay electrodes 81 and 82, and the spacer 90 are not shown in FIG.

[0041] As shown in FIGS. 5 and 6, the capacitive element 60 is provided on the first substrate 11. The capacitive element 60 is provided between the first substrate 11 and the scanning line 14. In the example shown in the figures, a recess 11a is formed in the first substrate 11. The capacitive element 60 is provided in the recess 11a. In the example shown in FIG. 8, the planar shape of the recess 11a is a rectangle with its longitudinal direction in the Y-axis direction.

[0042] As shown in FIGS. 5 and 6, the capacitive element 60 includes a first capacitive electrode 62, a dielectric layer 64, and a second capacitive electrode 66.

[0043] The first capacitor electrode 62 is provided on the first substrate 11. As shown in FIG. 9, the first capacitor electrode 62 covers the recess 11a. The first capacitor electrode 62 is made of, for example, conductive polysilicon. As shown in FIGS. 6 and 10, a spacer 90 is provided on the first capacitor electrode 62. A contact hole 132 that exposes the first capacitor electrode 62 is formed in the spacer 90. The spacer 90 is made of, for example, silicon oxide or silicon nitride.

[0044] 5 and 6, the dielectric layer 64 is provided on the capacitance electrode 62. The dielectric layer 64 is provided between the first capacitance electrode 62 and the second capacitance electrode 66. Furthermore, the dielectric layer 64 is provided on the first substrate 11 and the spacer 90. The material of the dielectric layer 64 is, for example, silicon nitride, silicon oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

[0045] The second capacitance electrode 66 is provided on the dielectric layer 64. The second capacitance electrode 66 is not provided on the spacer 90. As shown in FIG. 11 , the first capacitance electrode 62 has an area that does not overlap with the second capacitance electrode 66 in a plan view. The material of the second capacitance electrode 66 is, for example, the same as that of the first capacitance electrode 62.

[0046] 5 to 7, the first interlayer insulating layer 71 is provided on the first substrate 11. The first interlayer insulating layer 71 is provided between the first substrate 11 and the second interlayer insulating layer 72. The first interlayer insulating layer 71 covers the capacitive element 60 and the spacer 90. The material of the first interlayer insulating layer 71 and interlayer insulating layers 72 to 76 described later is, for example, silicon oxide or silicon nitride.

[0047] As shown in FIGS. 5 and 6, the scanning lines 14 are provided on the first interlayer insulating layer 71. The scanning lines 14 are provided between the capacitive elements 60 and the TFTs 50. In a plan view, the TFTs 50 overlap with the scanning lines 14. As shown in FIG. 12, in a plan view, the scanning lines 14 have regions that do not overlap with the second capacitive electrodes 66. Furthermore, the scanning lines 14 do not overlap with the contact holes 132. The scanning lines 14 are made of, for example, tungsten silicide or aluminum. The scanning lines 14 block light that enters the semiconductor layer 52 of the TFTs 50 from the first substrate 11 side.

[0048] 5 to 7, the second interlayer insulating layer 72 is provided on the first interlayer insulating layer 71. The second interlayer insulating layer 72 is provided between the first interlayer insulating layer 71 and the third interlayer insulating layer 73. The second interlayer insulating layer 72 covers the scanning lines 14.

[0049] The TFT 50 is provided on the second interlayer insulating layer 72. The TFT 50 is provided, for example, between the first substrate 11 and the common wiring 16. The TFT 50 has a semiconductor layer 52, a gate insulating layer 54, and a gate electrode 56. The TFT 50 has, for example, an LDD (Lightly Doped Drain) structure.

[0050] The semiconductor layer 52 is provided on the second interlayer insulating layer 72. In the example shown in Fig. 13, the semiconductor layer 52 extends in the Y-axis direction. The semiconductor layer 52 constitutes the source, drain, and channel of the TFT 50. The material of the semiconductor layer 52 is, for example, conductive polysilicon.

[0051] 5 and 6, the gate insulating layer 54 is provided on the semiconductor layer 52. The gate insulating layer 54 is provided between the semiconductor layer 52 and the gate electrode 56. Furthermore, the gate insulating layer 54 is provided on the second interlayer insulating layer 72. The gate insulating layer 54 is made of, for example, silicon oxide.

[0052] The gate electrode 56 is provided on the gate insulating layer 54. The gate electrode 56 is made of, for example, conductive polysilicon. The gate electrode 56 controls the current flowing through the channel of the semiconductor layer 52.

[0053] As shown in FIG. 5 , the gate electrode 56 is electrically connected to the scanning line 14 via conductive portions 110 and 111. Contact holes 130 and 131 are formed in the second interlayer insulating layer 72. The contact holes 130 and 131 overlap the scanning line 14 in a plan view. The contact holes 130 and 131 expose the scanning line 14. The contact holes 130 and 131 are spaced apart from each other. The contact holes 130 and 131 have, for example, the same depth. The conductive portion 110 is provided in the contact hole 130. The conductive portion 111 is provided in the contact hole 131. The conductive portions 110 and 111 electrically connect the gate electrode 56 and the scanning line 14. In a plan view, the semiconductor layer 52 is located between the conductive portion 110 and the conductive portion 111.

[0054] 6, the relay electrode 80 is provided on the semiconductor layer 52. The relay electrode 80 is electrically connected to the semiconductor layer 52. Furthermore, the relay electrode 80 is provided on the gate insulating layer 54. The relay electrode 80 is separated from the gate electrode 56, as shown in FIG.

[0055] As shown in FIG. 6 , the relay electrode 80 is electrically connected to the first capacitor electrode 62 via a conductive portion 112. A contact hole 132 is formed in the interlayer insulating layers 71, 72 and the spacer 90. The contact hole 132 overlaps with the first capacitor electrode 62 in a plan view. The contact hole 132 exposes the first capacitor electrode 62. The conductive portion 112 is provided in the contact hole 132. The conductive portion 112 electrically connects the semiconductor layer 52 and the first capacitor electrode 62. Specifically, the conductive portion 112 electrically connects the drain of the semiconductor layer 52 and the first capacitor electrode 62.

[0056] 7, the relay electrode 81 is provided on the second interlayer insulating layer 72. In the illustrated example, the relay electrode 81 is provided on the second interlayer insulating layer 72 via the gate insulating layer 54. The relay electrode 81 is separated from the gate electrode 56 and the relay electrode 80, as shown in FIG.

[0057] As shown in FIG. 7 , the relay electrode 81 is electrically connected to the second capacitor electrode 66 via a conductive portion 113. A contact hole 133 is formed in the interlayer insulating layers 71 and 72. The contact hole 133 overlaps with the second capacitor electrode 66 in a plan view. The contact hole 133 exposes the second capacitor electrode 66. The conductive portion 113 is provided in the contact hole 133. The conductive portion 113 electrically connects the relay electrode 81 and the second capacitor electrode 66. The material of the relay electrodes 80 and 81 and the conductive portions 110, 111, 112, and 113 is the same as that of the gate electrode 56, for example. The contact holes 132 and 133 are deeper than the contact holes 130 and 131. The contact hole 132 is deeper than the contact hole 133, for example.

[0058] 5 to 7, the third interlayer insulating layer 73 is provided on the gate insulating layer 54. The third interlayer insulating layer 73 is provided between the second interlayer insulating layer 72 and the fourth interlayer insulating layer 74. The third interlayer insulating layer 73 covers the TFT 50, the relay electrodes 80 and 81, and the conductive portions 110, 111, 112, and 113.

[0059] 5 and 6, the relay electrode 82 is provided on the third interlayer insulating layer 73. The TFT 50 is provided between the scanning line 14 and the relay electrode 82. The relay electrode 82 is made of a material such as tungsten silicide, aluminum, or titanium. The relay electrode 82 blocks light incident on the semiconductor layer 52 of the TFT 50 from above.

[0060] As shown in FIG. 6 , the relay electrode 82 is electrically connected to the relay electrode 80 via a conductive portion 114. A contact hole 134 is formed in the third interlayer insulating layer 73. The contact hole 134 overlaps with the relay electrode 80 in a plan view. The contact hole 134 exposes the relay electrode 80. The conductive portion 114 is provided in the contact hole 134. The conductive portion 114 electrically connects the relay electrode 80 and the relay electrode 82. The material of the conductive portion 114 is, for example, the same as that of the relay electrode 82.

[0061] The fourth interlayer insulating layer 74 is provided on the third interlayer insulating layer 73. The fourth interlayer insulating layer 74 is provided between the third interlayer insulating layer 73 and the fifth interlayer insulating layer 75. The fourth interlayer insulating layer 74 covers the relay electrodes 82.

[0062] The data line 15 is provided on the fourth interlayer insulating layer 74. The data line 15 is provided between the TFT 50 and the common wiring 16. In the example shown in the figure, the data line 15 is provided between the capacitive element 60 and the common wiring 16. The data line 15 is made of a material such as tungsten silicide, aluminum, or titanium.

[0063] As shown in FIG. 6 , the data line 15 is electrically connected to the semiconductor layer 52 via a conductive portion 115. A contact hole 135 is formed in the interlayer insulating layers 73 and 74 and the gate insulating layer 54. The contact hole 135 overlaps with the semiconductor layer 52 in a plan view. The contact hole 135 exposes the semiconductor layer 52. The conductive portion 115 is provided in the contact hole 135. The conductive portion 115 electrically connects the semiconductor layer 52 and the data line 15. Specifically, the conductive portion 115 electrically connects the source of the semiconductor layer 52 and the data line 15.

[0064] As shown in FIG. 5, the relay electrode 83 is provided on the fourth interlayer insulating layer 74. As shown in FIG. 16, the relay electrode 83 is separated from the data line 15. As shown in FIG. 5, the relay electrode 83 is electrically connected to the relay electrode 81 via a conductive portion 116. A contact hole 136 is formed in the interlayer insulating layers 73 and 74. The contact hole 136 overlaps with the relay electrode 81 in a plan view. The contact hole 136 exposes the relay electrode 81. The conductive portion 116 is provided in the contact hole 136. The conductive portion 116 electrically connects the relay electrode 81 and the relay electrode 83.

[0065] The relay electrode 84 is provided on the fourth interlayer insulating layer 74. As shown in FIG. 16 , the relay electrode 84 is separated from the data line 15 and the relay electrode 83. The data line 15 is located between the relay electrodes 83 and 84. As shown in FIG. 5 , the relay electrode 84 is electrically connected to the relay electrode 82 via a conductive portion 117. A contact hole 137 is formed in the fourth interlayer insulating layer 74. The contact hole 137 overlaps with the relay electrode 82 in a plan view. The contact hole 137 exposes the relay electrode 82. The conductive portion 117 is provided in the contact hole 136. The conductive portion 117 electrically connects the relay electrode 82 and the relay electrode 84. The material of the relay electrodes 83 and 84 and the conductive portions 115, 116, and 117 is, for example, the same as that of the data line 15. The contact holes 135 and 136 are deeper than the contact hole 137. The contact hole 135 is, for example, deeper than the contact hole 136 .

[0066] The fifth interlayer insulating layer 75 is provided on the fourth interlayer insulating layer 74. The fifth interlayer insulating layer 75 is provided between the fourth interlayer insulating layer 74 and the sixth interlayer insulating layer 76. The fifth interlayer insulating layer 75 covers the data line 15, the relay electrodes 83 and 84, and the conductive portions 115, 116, and 117.

[0067] The common wiring 16 is provided on the fifth interlayer insulating layer 75. The common wiring 16 overlaps the TFT 50 in plan view. The common wiring 16 is formed by laminating, for example, a titanium layer, a titanium nitride layer, an aluminum layer, etc. The common wiring 16 blocks light incident on the semiconductor layer 52 of the TFT 50 from above.

[0068] As shown in FIG. 5 , the common wiring 16 is electrically connected to the relay electrode 83 via a conductive portion 118. A contact hole 138 is formed in the fifth interlayer insulating layer 75. The contact hole 138 overlaps with the relay electrode 83 in a plan view. The contact hole 138 exposes the relay electrode 83. The conductive portion 118 is provided in the contact hole 138. The conductive portion 118 electrically connects the relay electrode 81 and the common wiring 16.

[0069] The common wiring 16 is electrically connected to the second capacitance electrode 66 via the conductive portion 118, the relay electrode 83, the conductive portion 116, the relay electrode 81, and the conductive portion 113. The common wiring 16 is electrically connected to, for example, the counter electrode 44. Therefore, a constant potential is applied to the common wiring 16, the second capacitance electrode 66, the relay electrodes 81 and 83, and the conductive portions 113, 116, and 118.

[0070] The relay electrode 85 is provided on the fifth interlayer insulating layer 75. As shown in FIG. 17 , the relay electrode 85 is separated from the common wiring 16. As shown in FIG. 5 , the relay electrode 85 is electrically connected to the relay electrode 84 via the conductive portion 119. A contact hole 139 is formed in the fifth interlayer insulating layer 75. The contact hole 139 overlaps the relay electrode 84 in a plan view. The contact hole 139 exposes the relay electrode 84. The conductive portion 119 is provided in the contact hole 139. The conductive portion 119 electrically connects the relay electrode 84 and the relay electrode 85. The material of the relay electrode 85 and the conductive portions 118 and 119 is, for example, the same as that of the common wiring 16. The depths of the contact holes 138 and 139 are, for example, the same as each other.

[0071] The sixth interlayer insulating layer 76 is provided on the fifth interlayer insulating layer 75. The sixth interlayer insulating layer 76 covers the common line 16, the relay electrode 85, and the conductive portions 118 and 119. The interlayer insulating layers 73, 74, 75, and 76 form a laminated insulating layer 77.

[0072] As shown in FIG. 7, the pixel electrode 12 is provided on the sixth interlayer insulating layer 76. As shown in FIG. 18, the planar shape of the pixel electrode 12 is approximately rectangular. As shown in FIG. 7, the pixel electrode 12 is electrically connected to the relay electrode 85 via the conductive portion 120. A contact hole 140 is formed in the sixth interlayer insulating layer 76. The contact hole 140 overlaps the relay electrode 85 in a planar view. The contact hole 140 exposes the relay electrode 85. The conductive portion 120 is provided in the contact hole 140. The conductive portion 120 electrically connects the relay electrode 85 and the pixel electrode 12. The material of the conductive portion 120 is, for example, the same as that of the pixel electrode 12.

[0073] The pixel electrode 12 is electrically connected to the drain of the semiconductor layer 52 and the first capacitance electrode 62 via the conductive portion 120, the relay electrode 85, the conductive portion 119, the relay electrode 84, the conductive portion 117, the relay electrode 82, the conductive portion 114, the relay electrode 80, and the conductive portion 112.

[0074] 2. Manufacturing method of electro-optical device Next, a method for manufacturing the liquid crystal device 100 as an electro-optical device according to this embodiment will be described with reference to the drawings. Fig. 19 is a flowchart illustrating the method for manufacturing the liquid crystal device 100 according to this embodiment. Figs. 20 to 32 are cross-sectional views schematically showing the manufacturing process for the liquid crystal device 100 according to this embodiment.

[0075] 21, 24, 28, 30, and 32 correspond to the AA cross section in Fig. 4. Figures 20, 22, 25, 27, 29, and 31 correspond to the BB cross section in Fig. 4. Figures 23 and 26 correspond to the CC cross section in Fig. 4.

[0076] 19 and 20, a capacitance element 60 having a first capacitance electrode 62, a second capacitance electrode 66, and a dielectric layer 64 provided between the first capacitance electrode 62 and the second capacitance electrode 66 is formed on a first substrate 11 (step S1). Specifically, the first capacitance electrode 62 is formed on the first substrate 11. Next, a spacer 90 is formed on the first capacitance electrode 62. Next, the dielectric layer 64 is formed on the first capacitance electrode 62 and the spacer 90. Next, the second capacitance electrode 66 is formed on the dielectric layer 64.

[0077] Next, a first interlayer insulating layer 71 is formed on the first substrate 11 to cover the capacitive elements 60 and the spacers 90 (step S2). Next, the scanning lines 14 are formed on the first interlayer insulating layer 71 (step S3). Next, a second interlayer insulating layer 72 is formed on the first interlayer insulating layer 71 to cover the scanning lines 14 (step S4). Next, a semiconductor layer 52 is formed on the second interlayer insulating layer 72 (step S5). Next, a gate insulating layer 54 is formed on the semiconductor layer 52 (step S6).

[0078] As shown in FIG. 21, the gate insulating layer 54 and the second interlayer insulating layer 72 are etched to form contact holes 130 and 131 that expose the scanning line 14. Furthermore, as shown in FIG. 22, the gate insulating layer 54, the interlayer insulating layers 71 and 72, and the spacer 90 are etched to form a contact hole 132 that exposes the first capacitor electrode 62. Furthermore, as shown in FIG. 23, the gate insulating layer 54 and the interlayer insulating layers 71 and 72 are etched to form a contact hole 133 that exposes the second capacitor electrode 66. As described above, the contact holes 130, 131, 132, and 133 are formed (step S7). In this process, the steps of forming the contact holes 130, 131, 132, and 133 are performed simultaneously. That is, the etching for forming the contact holes 130, 131, 132, and 133 starts and ends simultaneously.

[0079] Next, a conductive layer (not shown) is formed to cover the entire surface. The conductive layer is then patterned to form a gate electrode 56 on the gate insulating layer 54, as shown in FIGS. 24 and 25. Furthermore, as shown in FIG. 24, a conductive portion 110 electrically connecting the gate electrode 56 and the scanning line 14 is formed in the contact hole 130. Furthermore, a conductive portion 111 electrically connecting the gate electrode 56 and the scanning line 14 is formed in the contact hole 131. Furthermore, as shown in FIG. 25, a relay electrode 80 is formed on the gate insulating layer 54. Furthermore, a conductive portion 112 electrically connecting the relay electrode 80 and the first capacitor electrode 62 is formed in the contact hole 132. Furthermore, as shown in FIG. 26, a relay electrode 81 is formed on the gate insulating layer 54. Furthermore, a conductive portion 113 electrically connecting the relay electrode 81 and the second capacitor electrode 66 is formed in the contact hole 133. In this manner, the gate electrode 56, the relay electrodes 80 and 81, and the conductive portions 110, 111, 112, and 113 are formed (step S8).

[0080] 27, a third interlayer insulating layer 73 is formed to cover the gate electrode 56 and the relay electrodes 80, 81 (step S9). Next, the third interlayer insulating layer 73 is etched to form a contact hole 134 that exposes the relay electrode 80 (step S10). Next, a relay electrode 82 is formed on the third interlayer insulating layer 73, and a conductive portion 114 that electrically connects the relay electrodes 80, 82 to the contact hole 134 is formed (step S11). Next, a fourth interlayer insulating layer 74 is formed on the third interlayer insulating layer 73 to cover the relay electrode 82 (step S12).

[0081] As shown in FIG. 28, the interlayer insulating layers 73 and 74 are etched to form a contact hole 136 that exposes the relay electrode 81. Furthermore, the fourth interlayer insulating layer 74 is etched to form a contact hole 137. Furthermore, as shown in FIG. 29, the interlayer insulating layers 73 and 74 and the gate insulating layer 54 are etched to form a contact hole 135. In this manner, the contact holes 135, 136, and 137 are formed (step S13). In this process, the processes of forming the contact holes 135, 136, and 137 are performed simultaneously.

[0082] Next, a conductive layer (not shown) is formed to cover the entire surface. The conductive layer is then patterned to form the data line 15 and relay electrodes 83 and 84 on the fourth interlayer insulating layer 74, as shown in FIGS. 30 and 31 . Furthermore, as shown in FIG. 30 , a conductive section 116 that electrically connects the relay electrodes 81 and 83 is formed in the contact hole 136. Furthermore, a conductive section 117 that electrically connects the relay electrodes 82 and 84 is formed in the contact hole 137. Furthermore, as shown in FIG. 31 , a conductive section 115 that electrically connects the semiconductor layer 52 and the data line 15 is formed in the contact hole 135. In this manner, the data line 15, the relay electrodes 83 and 84, and the conductive sections 115, 116, and 117 are formed (step S14).

[0083] 32, a fifth interlayer insulating layer 75 that covers the data line 15 and the relay electrodes 83 and 84 is formed on the fourth interlayer insulating layer 74 (step S15). Next, the fifth interlayer insulating layer 75 is etched to form a contact hole 138 that exposes the relay electrode 83 and a contact hole 139 that exposes the relay electrode 84 (step S16). In this step, the steps of forming the contact holes 138 and 139 are performed simultaneously.

[0084] Next, a conductive layer (not shown) is formed to cover the entire surface. The conductive layer is then patterned to form the common wiring 16 and the relay electrode 85 on the fifth interlayer insulating layer 75. Furthermore, a conductive portion 118 that electrically connects the relay electrode 83 and the common wiring 16 is formed in the contact hole 138. Furthermore, a conductive portion 119 that electrically connects the relay electrodes 84 and 85 is formed in the contact hole 139. In this manner, the common wiring 16, the relay electrode 85, and the conductive portions 118 and 119 are formed (step S17).

[0085] 5 to 7, a sixth interlayer insulating layer 76 that covers the common wiring 16 and the relay electrode 85 is formed on the fifth interlayer insulating layer 75 (step S18). Next, as shown in FIG. 7, a contact hole 140 that exposes the common wiring 16 is formed in the sixth interlayer insulating layer 76 (step S19). Next, a pixel electrode 12 is formed on the sixth interlayer insulating layer 76, and a conductive portion 120 that electrically connects the relay electrode 85 and the pixel electrode 12 is formed in the contact hole 140 (step S20).

[0086] The interlayer insulating layers 71 to 76 are formed by, for example, a chemical vapor deposition (CVD) method. After the interlayer insulating layers 71 to 76 are formed, each of the interlayer insulating layers 71 to 76 may be subjected to chemical mechanical planarization (CMP) processing. The pixel electrodes 12, scanning lines 14, data lines 15, common wiring 16, gate electrodes 56, capacitor electrodes 62 and 66, relay electrodes 80 to 85, and conductive portions 110 to 120 are formed by, for example, a CVD method, a sputtering method, or a vacuum deposition method. The semiconductor layer 52, gate insulating layer 54, dielectric layer 64, and spacer 90 are formed by, for example, a CVD method or a sputtering method. The contact holes 130 to 140 are formed by, for example, patterning using photolithography and dry etching.

[0087] As shown in FIG. 2, a liquid crystal layer 30 is formed on an element substrate 10 , and the element substrate 10 and an opposing substrate 40 are joined together with a sealant 20 .

[0088] Through the above steps, the liquid crystal device 100 can be manufactured.

[0089] The method for manufacturing the liquid crystal device 100 has the following advantages, for example.

[0090] The method for manufacturing the liquid crystal device 100 includes the steps of forming, on the first substrate 11, a capacitance element 60 having a first capacitance electrode 62, a second capacitance electrode 66, and a dielectric layer 64 provided between the first capacitance electrode 62 and the second capacitance electrode 66; forming a first interlayer insulating layer 71 as a first insulating layer covering the capacitance element 60; forming a scanning line 14 on the first interlayer insulating layer 71; forming a second interlayer insulating layer 72 as a second insulating layer covering the scanning line 14; forming a semiconductor layer 52 on the second interlayer insulating layer 72; forming a gate insulating layer 54 on the semiconductor layer 52; and etching the second interlayer insulating layer 72 to form a contact hole 130 as a first contact hole exposing the scanning line 14. the step of etching the second interlayer insulating layer 72 and the first interlayer insulating layer 71 to form a contact hole 132 as a second contact hole that exposes the first capacitor electrode 62; the step of forming a gate electrode 56 on the gate insulating layer 54, forming a conductive portion 110 in the contact hole 130 as a first conductive portion that electrically connects the gate electrode 56 and the scanning line 14, forming a relay electrode 80 as a first electrode on the semiconductor layer 52, and forming a conductive portion 112 in the contact hole 132 as a second conductive portion that electrically connects the relay electrode 80 and the first capacitor electrode 62; and the step of forming the contact hole 130 and the step of forming the contact hole 132 are performed simultaneously.

[0091] Therefore, the method for manufacturing the liquid crystal device 100 can reduce the number of manufacturing steps compared to when the first contact hole and the second contact hole are formed in separate steps, which simplifies the manufacturing process and improves productivity.

[0092] In the method for manufacturing the liquid crystal device 100, the step of forming the capacitive element 60 includes the steps of forming a first capacitive electrode 62 on the first substrate 11, forming a dielectric layer 64 on the first capacitive electrode 62, and forming a second capacitive electrode 66 on the dielectric layer 64. Therefore, in the method for manufacturing the liquid crystal device 100, the first capacitive electrode 62 can be formed on the first substrate 11 side, and the second capacitive electrode 66 can be formed on the opposite side from the first substrate 11.

[0093] The method for manufacturing the liquid crystal device 100 includes a step of etching the second interlayer insulating layer 72 and the first interlayer insulating layer 71 to form a contact hole 133 as a third contact hole that exposes the second capacitor electrode 66, and the steps of forming the contact hole 130, the contact hole 132, and the contact hole 133 are performed simultaneously, and in the step of forming the gate electrode 56, the relay electrode 80, and the conductive portions 110 and 112, the relay electrode 81 as a second electrode is formed on the second interlayer insulating layer 72, and the conductive portion 113 as a third conductive portion that electrically connects the relay electrode 81 and the second capacitor electrode 66 is formed in the contact hole 133. Therefore, the method for manufacturing the liquid crystal device 100 can simplify the manufacturing process compared to when the first contact hole, the second contact hole, and the third contact hole are formed in separate steps.

[0094] The method for manufacturing the liquid crystal device 100 includes a step of etching the second interlayer insulating layer 72 to form contact hole 131 as a fourth contact hole that exposes the scanning line 14, and in the step of forming gate electrode 56, relay electrode 80, and conductive portions 110 and 112, conductive portion 111 is formed in contact hole 131 as a fourth conductive portion that electrically connects gate electrode 56 and scanning line 14, and semiconductor layer 52 is located between conductive portion 110 and conductive portion 111 in plan view. Therefore, in the method for manufacturing the liquid crystal device 100, conductive portions 110 and 111 can reduce light incident on semiconductor layer 52.

[0095] The method for manufacturing the liquid crystal device 100 includes the steps of forming a laminated insulating layer 77 as a third insulating layer that covers the gate electrode 56 and the relay electrode 80, and forming the pixel electrode 12 on the laminated insulating layer 77, and the conductive portion 112 is electrically connected to the pixel electrode 12, and a constant potential is applied to the conductive portion 113. Therefore, the method for manufacturing the liquid crystal device 100 can electrically connect the semiconductor layer 52 and the pixel electrode 12 via the conductive portion 112.

[0096] 3. Electronic equipment Next, a projector 200 as an electronic device according to this embodiment will be described with reference to the drawings. Fig. 33 is a diagram for explaining the projector 200 as an electronic device according to this embodiment.

[0097] The projector 200 includes, for example, a liquid crystal device 100. The projector 200 is a liquid crystal projector.

[0098] As shown in FIG. 33, the projector 200 includes, for example, a polarized lighting device 210 arranged along the system optical axis LS, two dichroic mirrors 220 and 222 as light separation elements, three reflecting mirrors 230, 232 and 234, five relay lenses 240, 242, 244, 246 and 248, three transmissive liquid crystal light valves 250, 252 and 254 as light modulation elements, a cross dichroic prism 260 as a light combining element, and a projection lens 270.

[0099] The polarized illumination device 210 has a lamp unit 212 as a light source, which is configured from a white light source such as an extra-high pressure mercury lamp or a halogen lamp, an integrator lens 214 , and a polarization conversion element 216 .

[0100] Dichroic mirror 220 reflects red light (R) and transmits green light (G) and blue light (B) out of the polarized light beam emitted from polarized illumination device 210. Dichroic mirror 222 reflects green light (G) that has transmitted through dichroic mirror 220 and transmits blue light (B).

[0101] Red light (R) reflected by dichroic mirror 220 is reflected by reflecting mirror 230 and then passes through relay lens 248 before entering liquid crystal light valve 250. Green light (G) reflected by dichroic mirror 222 passes through relay lens 246 and enters liquid crystal light valve 252. Blue light (B) transmitted through dichroic mirror 222 passes through a light guide system made up of three relay lenses 240, 242, and 244 and two reflecting mirrors 232 and 234 and enters liquid crystal light valve 254.

[0102] The liquid crystal light valves 250, 252, and 254 are disposed opposite the respective color light incident surfaces of the cross dichroic prism 260. The color light incident on the liquid crystal light valves 250, 252, and 254 is modulated based on video information (video signals) and emitted toward the cross dichroic prism 260.

[0103] Cross dichroic prism 260 is made by bonding four right-angle prisms together, and on their inner surfaces, a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are arranged in a cross shape. These dielectric multilayer films combine the three colored lights to generate light that represents a color image. The combined light is projected onto screen 280 by projection lens 270, which is a projection optical system, and the image is enlarged and displayed.

[0104] For example, the above-described liquid crystal device 100 is applied to the liquid crystal light valve 250. The same applies to the liquid crystal light valves 252 and 254.

[0105] In addition to the projector 200, the liquid crystal device 100 may be installed in various electronic devices such as an EVF (Electrical View Finder), a mobile mini projector, a head-up display, a smartphone, a mobile phone, a mobile computer, a digital camera, a digital video camera, a display, an in-vehicle device, an audio device, an exposure device, and a lighting device.

[0106] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0107] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0108] The following can be derived from the above-described embodiment and modifications.

[0109] One aspect of the method for manufacturing an electro-optical device includes: forming a capacitance element on a substrate, the capacitance element having a first capacitance electrode, a second capacitance electrode, and a dielectric layer provided between the first capacitance electrode and the second capacitance electrode; forming a first insulating layer covering the capacitive element; forming a scan line on the first insulating layer; forming a second insulating layer covering the scan lines; forming a semiconductor layer on the second insulating layer; forming a gate insulating layer on the semiconductor layer; Etching the second insulating layer to form a first contact hole exposing the scan line; etching the second insulating layer and the first insulating layer to form a second contact hole exposing the first capacitor electrode; forming a gate electrode on the gate insulating layer, forming a first conductive portion in the first contact hole that electrically connects the gate electrode and the scanning line, forming a first electrode on the semiconductor layer, and forming a second conductive portion in the second contact hole that electrically connects the first electrode and the first capacitor electrode; and The step of forming the first contact hole and the step of forming the second contact hole are carried out simultaneously.

[0110] According to this method for manufacturing an electro-optical device, the manufacturing process can be simplified.

[0111] In one aspect of the method for manufacturing an electro-optical device, The step of forming the capacitance element includes: forming the first capacitance electrode on the substrate; forming the dielectric layer on the first capacitor electrode; forming the second capacitance electrode on the dielectric layer; may have

[0112] According to this method for manufacturing an electro-optical device, the first capacitance electrode can be formed on the substrate side, and the second capacitance electrode can be formed on the opposite side to the substrate.

[0113] In one aspect of the method for manufacturing an electro-optical device, a step of etching the second insulating layer and the first insulating layer to form a third contact hole exposing the second capacitor electrode; the step of forming the first contact hole, the step of forming the second contact hole, and the step of forming the third contact hole are performed simultaneously; In the process of forming the gate electrode, the first conductive portion, the first electrode, and the second conductive portion, a second electrode may be formed on the second insulating layer, and a third conductive portion may be formed in the third contact hole to electrically connect the second electrode and the second capacitance electrode.

[0114] According to this method for manufacturing an electro-optical device, the manufacturing process can be simplified.

[0115] In one aspect of the method for manufacturing an electro-optical device, etching the second insulating layer to form a fourth contact hole exposing the scan line; In the step of forming the gate electrode, the first conductive portion, the first electrode, and the second conductive portion, a fourth conductive portion is formed in the fourth contact hole to electrically connect the gate electrode and the scanning line; The semiconductor layer may be located between the first conductive portion and the fourth conductive portion in a plan view.

[0116] According to this method for manufacturing an electro-optical device, the first conductive section and the fourth conductive section can reduce the amount of light incident on the semiconductor layer.

[0117] In one aspect of the method for manufacturing an electro-optical device, forming a third insulating layer covering the gate electrode and the first electrode; forming a pixel electrode on the third insulating layer; and the second conductive portion is electrically connected to the pixel electrode; A constant potential may be applied to the third conductive portion.

[0118] According to this method for manufacturing an electro-optical device, the semiconductor layer and the pixel electrode can be electrically connected via the second conductive portion. [Explanation of symbols]

[0119] 10...element substrate, 11...first substrate, 12...pixel electrode, 13...first alignment layer, 14...scanning line, 15...data line, 16...common wiring, 20...sealing material, 30...liquid crystal layer, 40...counter substrate, 41...second substrate, 42...partition portion, 43...insulating layer, 44...counter electrode, 45...second alignment layer, 50...TFT, 52...semiconductor layer, 54...gate insulating layer, 56...gate electrode, 60...capacitor element, 62...first capacitor electrode, 64...dielectric layer, 66...second capacitor electrode, 71...first interlayer insulating layer, 72...second interlayer insulating layer, 73...third interlayer insulating layer, 74...fourth interlayer insulating layer, 75...fifth interlayer insulating layer, 76...sixth interlayer insulating layer, 80, 81, 82, 83, 84, 85...relay electrodes, 90spacer, 100...liquid crystal device, 101...external connection terminal, 102...data line driving circuit, 103 ...inspection circuit, 104...scanning line driving circuit, 105...first wiring, 106...second wiring, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120...conductive portion, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140...contact hole, 200...projector, 210...polarized lighting device, 2 12... Lamp unit, 214... Integrator lens, 216... Polarization conversion element, 220, 222... Dichroic mirror, 230, 232, 234... Reflection mirror, 240, 242, 244, 246, 248... Relay lens, 250, 252, 254... Liquid crystal light valve, 260... Cross dichroic prism, 270... Projection lens, 280... Screen

Claims

1. forming a capacitance element on a substrate, the capacitance element having a first capacitance electrode, a second capacitance electrode, and a dielectric layer provided between the first capacitance electrode and the second capacitance electrode; forming a first insulating layer covering the capacitive element; forming a scan line on the first insulating layer; forming a second insulating layer covering the scan lines; forming a semiconductor layer on the second insulating layer; forming a gate insulating layer on the semiconductor layer; Etching the second insulating layer to form a first contact hole exposing the scan line; etching the second insulating layer and the first insulating layer to form a second contact hole exposing the first capacitor electrode; forming a gate electrode on the gate insulating layer, forming a first conductive portion in the first contact hole that electrically connects the gate electrode and the scanning line, forming a first electrode on the semiconductor layer, and forming a second conductive portion in the second contact hole that electrically connects the first electrode and the first capacitor electrode; and A method for manufacturing an electro-optical device, wherein the step of forming the first contact hole and the step of forming the second contact hole are carried out simultaneously.

2. In claim 1, The step of forming the capacitance element includes: forming the first capacitance electrode on the substrate; forming the dielectric layer on the first capacitance electrode; forming the second capacitance electrode on the dielectric layer; A method for manufacturing an electro-optical device comprising:

3. In claim 2, a step of etching the second insulating layer and the first insulating layer to form a third contact hole exposing the second capacitor electrode; the step of forming the first contact hole, the step of forming the second contact hole, and the step of forming the third contact hole are performed simultaneously; A method for manufacturing an electro-optical device, wherein in the process of forming the gate electrode, the first conductive portion, the first electrode, and the second conductive portion, a second electrode is formed on the second insulating layer, and a third conductive portion that electrically connects the second electrode and the second capacitive electrode is formed in the third contact hole.

4. In claim 1 or 2, etching the second insulating layer to form a fourth contact hole exposing the scan line; In the step of forming the gate electrode, the first conductive portion, the first electrode, and the second conductive portion, a fourth conductive portion is formed in the fourth contact hole to electrically connect the gate electrode and the scanning line; A method for manufacturing an electro-optical device, wherein the semiconductor layer is located between the first conductive portion and the fourth conductive portion in a plan view.

5. In claim 3, forming a third insulating layer covering the gate electrode and the first electrode; forming a pixel electrode on the third insulating layer; and the second conductive portion is electrically connected to the pixel electrode; A method for manufacturing an electro-optical device, wherein a constant potential is applied to the third conductive portion.

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