Successive approximation analog-to-digital converter

Abstract

To suppress increase of the size of a circuit configuration and increase the speed.SOLUTION: An successive approximation ADC includes: a CDAC having a main capacitor bank composed of a plurality of first capacitors; and an auxiliary capacitor bank composed of a plurality of second capacitors for supplying a correction capacitance value to the first capacitors; a comparator for outputting a bit signal on the basis of a charge redistribution signal output by the CDAC through charge redistribution in response to an analog input signal; a logic circuit for outputting a digital output signal based on the bit signal; and a correction capacitance value instruction circuit for outputting a correction instruction value indicating a correction capacitance value to be supplied to the first capacitors. The correction capacitance value instruction circuit stores two correction instruction values one bit ahead as pre-correction instruction values, selects one of the pre-correction instruction values according to the bit signal from the comparator, and calculates latest two correction instruction values on the basis thereof.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a successive approximation type analog-to-digital converter. [Background technology]

[0002] A circuit that uses a successive approximation register (SAR) to convert an input analog signal into a digital signal and output the digital signal is called a successive approximation register (hereinafter referred to as a "successive approximation register ADC" or "SAR ADC"). Also, a successive approximation register ADC that includes a capacitive digital-to-analog converter (CDAC) that uses a capacitor bank for analog signal input is known as a capacitive or capacitance redistribution type successive approximation register ADC. For example, Patent Document 1 listed below discloses such a capacitance redistribution type successive approximation register ADC.

[0003] In a capacitance redistribution type successive approximation ADC, correction (calibration) is performed to remove the influence of manufacturing variations in each capacitor of the CDAC. For example, Non-Patent Document 1 below discloses a calibration technique for a CDAC. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-074706 [Non-patent literature]

[0005] [Non-Patent Document 1] Mojitaba Bagheri et al., “A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization”, IEEE, TRANSACTIONS ON CIRCUITS AND SYSTEM-I: REGULAR PAPERS, Vol. 67, No. 9, pp. 2883-2896, September 2020 Summary of the Invention [Problem to be solved by the invention]

[0006] The CDAC in a conventional successive approximation ADC is configured to include a main capacitor bank, an auxiliary capacitor bank for correction, and a circuit to control it. As a result of the correction, a correction value (capacitance value) from the auxiliary capacitor bank is added to each bit indicated by the main capacitor bank, so as the number of supported bits increases, the circuit configuration becomes complex and large, and the operating speed decreases.

[0007] Therefore, an object of the present invention is to provide a new correction architecture for the CDAC of a successive approximation register ADC.

[0008] More specifically, an object of the present invention is to provide a successive approximation type ADC that can suppress an increase in the size of the circuit configuration and achieve high-speed operation even when the number of supported bits increases.

[0009] Another object of the present invention is to provide a technique for improving the accuracy of correction for a CDAC.

[0010] Another object of the present invention is to provide a technique that does not deteriorate the dynamic range of a successive approximation ADC due to correction of the CDAC. [Means for solving the problem]

[0011] The present invention, which aims to solve the above problems, comprises the following invention-specific matters and technical features.

[0012] According to one aspect, the present invention provides a capacitance redistribution-based successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter includes an ADC control circuit and an ADC main circuit that converts an input analog input signal into a digital output signal under the control of the ADC control circuit and outputs the digital output signal. The ADC main circuit includes a CDAC including a main capacitor bank composed of a plurality of first capacitors connected in parallel and an auxiliary capacitor bank composed of a plurality of second capacitors connected in parallel and connected to be able to supply a correction capacitance value to any of the plurality of first capacitors in the main capacitor bank, a comparator that outputs a bit signal based on a capacitance redistribution signal output in response to the analog input signal in accordance with capacitance redistribution by the CDAC, a logic circuit that outputs the digital output signal in a predetermined format based on the bit signal output from the comparator, and a correction capacitance value indication circuit that outputs a correction indication value for indicating a correction capacitance value to be supplied to the first capacitor in the main capacitor bank. The correction capacitance value indication circuit stores in advance at least two sets of correction indication values ​​at a timing at least one bit earlier as pre-correction indication values, selects one of the pre-correction indication values ​​according to the bit signal fed back from the comparator, and calculates the two latest sets of correction indication values ​​based on one of the selected pre-correction indication values.

[0013] The CDAC can control the correction capacitance value to be supplied to the first capacitor based on one of the two correction instruction values.

[0014] The ADC main circuit may include a multiplexer that selects one of the two correction indication values ​​in accordance with the bit signal fed back from the comparator. The multiplexer may be configured as a part of the CDAC.

[0015] Furthermore, the CDAC can control the connection configuration of the second capacitor so that the correction capacitance value is supplied to the first capacitor based on one of the two correction instruction values.

[0016] The successive approximation type analog-to-digital converter may further include an offset correction control circuit that controls the execution of offset correction for the comparator, and an offset correction circuit that supplies an offset correction value to the comparator under the control of the offset correction control circuit.

[0017] The offset correction control circuit may control the offset correction circuit to increase or decrease an output current value for the comparator, and may specify, as the offset correction value, the output current value when the bit signal output from the comparator changes due to an increase or decrease in the output current value.

[0018] The comparator may also include an analog comparator that outputs a comparison result signal based on the capacitance redistribution signal, and a latch circuit that outputs the bit signal based on the comparison result signal output from the analog comparator.

[0019] The offset correction circuit may provide the offset correction value for the comparison result signal.

[0020] The ADC control circuit may control the ADC main circuit to operate in either a correction mode or a normal mode. In the correction mode, the ADC control circuit may specify the correction capacitance value to be supplied from the auxiliary capacitor bank to the first capacitor to be corrected based on the bit signal output from the comparator by performing linearity correction on the CDAC so that a target digital output signal is output based on a first capacitor to be corrected corresponding to a predetermined bit. In the normal mode, the ADC control circuit may supply the specified correction capacitance value from some of the second capacitors to the first capacitor to be corrected in accordance with the correction instruction value based on the bit signal output from the comparator.

[0021] In addition, the ADC control circuit can increase or decrease the capacitance value supplied from the auxiliary capacitor bank by changing the correction instruction value in stages or gradually, and identify the capacitance value when the bit signal output from the comparator changes as the correction capacitance value for the first capacitor to be corrected.

[0022] Furthermore, the CDAC may supply the capacitance value based on some of the plurality of second capacitors to the first capacitor to be corrected in accordance with the correction instruction value.

[0023] Furthermore, the ADC control circuit may connect the first capacitor to be corrected to a first reference voltage and connect first capacitors other than the first capacitor to be corrected to a second reference voltage. In this state, the ADC control circuit may control the CDAC to supply the first capacitor to be corrected with a capacitance value based on some of the plurality of second capacitors connected to the first reference voltage.

[0024] In addition, the ADC control circuit may control the connection configuration of the second capacitor so that the capacitance value of the second capacitor that was not used to supply the identified correction capacitance value to the first capacitor to be corrected is distributed to each of the first reference voltage and the second reference voltage in the normal mode.

[0025] Furthermore, in the correction mode, the ADC control circuit can perform the linearity correction after performing offset correction on the comparator.

[0026] The auxiliary capacitor bank may also include a split capacitor for dividing the plurality of second capacitors into predetermined most significant bits and predetermined least significant bits.

[0027] In addition, the correction capacitance value indication circuit is configured to hold p^2 correction indication values ​​p bits (where p is a positive number greater than or equal to 2) before as pre-correction indication values, and based on the bit signal, one of the two pre-correction indication values ​​one bit before can be selected as the latest correction indication value.

[0028] Another aspect of the present invention is a method for operating a successive approximation register analog-to-digital converter that converts an input analog input signal into a digital output signal and outputs the digital output signal. The method includes: outputting a capacitance redistribution signal in response to the analog input signal according to capacitance redistribution by a CDAC; outputting a bit signal by a comparator in response to the capacitance redistribution signal; and outputting the digital output signal in a predetermined format based on the bit signal. Here, outputting the capacitance redistribution signal includes outputting a correction instruction value that specifies a correction capacitance value to be supplied to a plurality of first capacitors connected in parallel in a main capacitor bank of the CDAC; and controlling a plurality of second capacitors connected in parallel in an auxiliary capacitor bank of the CDAC to supply the correction capacitance value specified by the correction instruction value to any of the plurality of first capacitors. Outputting the correction indication value includes pre-storing at least two of the correction indication values ​​at a timing at least one bit earlier as pre-correction indication values, selecting one of the pre-correction indication values ​​according to the bit signal fed back from the comparator, and calculating the two latest correction indication values ​​based on one of the selected pre-correction indication values.

[0029] The operating method may further include performing linearity correction to identify the correction capacitance value to be supplied from the auxiliary capacitor bank to the first capacitor to be corrected based on the bit signal output from the comparator, so that a target digital output signal is output based on the first capacitor to be corrected corresponding to a predetermined bit.

[0030] In addition, performing the linearity correction may include increasing or decreasing the capacitance value supplied from the auxiliary capacitor bank by changing the correction instruction value stepwise or gradually, and identifying the capacitance value when the bit signal output from the comparator changes in response to the increase or decrease in the capacitance value as the correction capacitance value for the first capacitor to be corrected.

[0031] In this specification, the term "means" does not simply mean physical means, but also includes cases where the functions of the means are realized by software. The functions of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means. Furthermore, the term "system" refers to a logical collection of multiple devices (or functional modules that realize specific functions), regardless of whether each device or functional module is contained within a single housing. [Effects of the Invention]

[0032] The present invention provides a new correction architecture for the CDAC of a successive approximation register ADC. In particular, the present invention provides a successive approximation register ADC that can suppress an increase in the size of its circuit configuration and achieve high-speed operation even when the number of supported bits increases.

[0033] Furthermore, according to the present invention, it is possible to improve the accuracy of correction for the CDAC.

[0034] Furthermore, according to the present invention, it becomes possible to suppress deterioration of the dynamic range of the successive approximation ADC by correcting the CDAC.

[0035] Other technical features, objects, and operational effects or advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings. The effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present. [Brief explanation of the drawings]

[0036] [Figure 1] FIG. 1 is a diagram showing an example of a functional model of a successive approximation type ADC according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing an example of a circuit configuration of a CDAC core in a successive approximation register ADC according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a diagram for explaining the basic concept of correction for the CDAC in the successive approximation type ADC according to the first embodiment of the present invention. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of a correction capacitance value indicating circuit in the successive approximation type ADC according to the first embodiment of the present invention. [Figure 5A] FIG. 5A is a flowchart showing an example of correction processing for a CDAC in a successive approximation type ADC according to the first embodiment of the present invention. [Figure 5B] FIG. 5B is a flowchart showing an example of correction processing for the CDAC in the successive approximation type ADC according to the first embodiment of the present invention. [Figure 6] FIG. 6 is a sequence diagram for explaining offset correction for the analog comparator in the successive approximation type ADC according to the first embodiment of the present invention. [Figure 7] FIG. 7 is a schematic sequence diagram for explaining an example of linearity correction for the CDAC of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 8] FIG. 8 is a detailed sequence diagram for explaining an example of linearity correction for the CDAC of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 9] FIG. 9 is a diagram showing an example of a capacitor connection configuration when performing linearity correction on the CDAC of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing an example of a capacitor connection configuration when performing linearity correction on the CDAC of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing an example of a capacitor connection configuration when performing linearity correction on the CDAC of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 12] FIG. 12 is a diagram showing an example of a capacitor connection configuration in the CDAC in the normal mode of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 13] FIG. 13 is a diagram showing an example of a capacitor connection configuration in the CDAC in the normal mode of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 14] FIG. 14 is a diagram showing an example of a capacitor connection configuration in the CDAC in the normal mode of the successive approximation register ADC according to the first embodiment of the present invention. [Figure 15] FIG. 15 is a diagram showing an example of a capacitor connection configuration in the CDAC in the normal mode of the successive approximation type ADC according to the first embodiment of the present invention. [Figure 16] FIG. 16 is a diagram showing an example of the configuration of a correction capacitance value indicating circuit in a successive approximation type ADC according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0037] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and are not intended to exclude various modifications or applications of techniques not explicitly described below. The present invention can be implemented in various modifications (e.g., combinations of the embodiments) without departing from the spirit of the present invention. Furthermore, in the following description of the drawings, identical or similar parts are denoted by identical or similar reference numerals. The drawings are schematic and do not necessarily correspond to actual dimensions, ratios, etc. Parts in the drawings may have different dimensional relationships or ratios.

[0038] [First embodiment] This embodiment is characterized in that, in a successive approximation type ADC, when a digital output signal for an analog input signal is output based on a comparison result obtained by redistributing the capacitance of a capacitor corresponding to a digital code, two correction instruction values ​​for the capacitor obtained at the timing one bit earlier are stored, and one of the two correction instruction values ​​is selected based on the comparison result to generate the two latest correction instruction values, which are then supplied to the capacitor, thereby correcting the capacitance value of the capacitor.

[0039] (Overall configuration example) 1 is a diagram showing an example of a functional model of a successive approximation register ADC according to a first embodiment of the present invention. As shown in the diagram, the successive approximation register ADC 1 of this embodiment includes, for example, an ADC main circuit 10 and an ADC control circuit 20. The successive approximation register ADC 1 is controlled by, for example, a system control circuit 30. The ADC main circuit 10 can operate at a power supply voltage higher than the power supply voltages of the ADC control circuit 20 and the system control circuit 30, and therefore, can typically be configured in a block separate from the blocks of the ADC control circuit 20 and the system control circuit 30, but is not limited to this.

[0040] The ADC main circuit 10 is a circuit that converts an input analog signal into a digital signal using a capacitive successive approximation register (i.e., a capacitor bank) and outputs the digital signal. In this example, the ADC main circuit 10 is configured to output a digital output signal D_MAIN based on differential analog input signals Vin_P and Vin_N. The digital output signal D_MAIN may be in a serial format or a parallel format, but in this disclosure it is assumed to be in a parallel format.

[0041] More specifically, the ADC main circuit 10 includes, for example, a capacitive digital-to-analog converter (hereinafter referred to as "CDAC") 110, an analog comparator 120, a latch circuit 130, and a logic circuit 140. In the present disclosure, the ADC main circuit 10 further includes an offset correction circuit 150.

[0042] The CDAC 110 is a capacitive digital-to-analog converter using a capacitor bank. The CDAC 110 includes, for example, a CDAC core 111 composed of a capacitor bank and a multiplexer 112 for selecting an appropriate correction instruction value to be output to the capacitor bank of the CDAC core 111. The multiplexer 112 may be configured separately from the CDAC 110. The CDAC core 111 compares the differential voltage of differential analog input signals Vin_P and Vin_N with a voltage (capacitance value) resulting from capacitance redistribution of the capacitor bank corresponding to a digital code, and outputs analog differential capacitance redistribution signals VC_P and VC_N according to the comparison result. The CDAC core 111 also includes an auxiliary capacitor bank (see FIG. 2) used to correct manufacturing variations in the capacitor bank. In this disclosure, the former may be referred to as the main capacitor bank, and the latter may be referred to as the auxiliary capacitor bank. The specific configuration of the CDAC core 111 and its correction method will be described later. During the execution of linearity correction, which will be described later, the switch SW_VCM is controlled so that the differential capacitance redistribution signals VC_P and VC_N are forcibly set to the common voltage VCM.

[0043] The analog comparator 120 is a circuit that compares the voltages of the differential capacitance redistribution signals VC_P and VC_N output from the CDAC 110 with a predetermined comparison reference voltage (not shown) and outputs differential comparison result signals COMPout_P and COMPout_N according to the comparison result. The analog comparator 120 is preferably set to have a low gain so that kickback noise caused by device operation, etc., does not propagate to the input side. In the present disclosure, the analog comparator 120 undergoes offset correction using an offset correction circuit 150 in order to improve the accuracy of linearity correction for the CDAC 110.

[0044] The latch circuit 130 is a circuit that outputs a bit signal corresponding to the state (value) of an input signal. The latch circuit 130 functions as a comparator in conjunction with the analog comparator 120. Specifically, the latch circuit 130 sequentially outputs comparison result signals COMP indicating logical values ​​corresponding to the differential comparison result signals COMPout_P and COMPout_N in accordance with a predetermined clock signal CLK. For example, the latch circuit 130 outputs a logical value "1" if the differential voltage between the differential comparison result signals COMPout_P and COMPout_N is greater than a predetermined reference voltage VREF, and outputs a logical value "0" if the differential voltage is smaller than the predetermined reference voltage VREF. In contrast to the analog comparator 120, the latch circuit 130 is preferably set to have a high gain.

[0045] The logic circuit 140 outputs a predetermined digital signal based on the bit signal input from the latch circuit 130. Specifically, the logic circuit 140 performs serial-to-parallel conversion by sequentially associating one bit of the serial comparison result signal COMP output from the latch circuit 130 with a parallel code bit, and can output this as a digital signal D_MAIN of an N-bit parallel digital code at a predetermined timing. Furthermore, the logic circuit 140 can control the CDAC 110 and the ADC control circuit 20 based on the input comparison result signal COMP. That is, the CDAC 110 and the ADC control circuit 20 are each controlled in accordance with the digital signal D_MAIN.

[0046] The offset correction circuit 150 is a circuit for performing offset correction on the analog comparator 120. Here, offset correction refers to correcting the offset of the output of the comparator including the latch circuit 130 by changing the current value superimposed on the comparison result signal COMP stepwise or gradually until the state of the comparison result signal COMP is inverted when the potential difference between the differential comparison input signals (i.e., the differential capacitance redistribution signals VC_P and VC_N) of the analog comparator 120 is set to "0." In other words, because the output voltage of the analog comparator 120 determines the output logic of the latch circuit 130, the offset correction circuit 150 offset-corrects the output voltage of the analog comparator 120 so that the threshold value of the output logic of the latch circuit 130 is set with high accuracy.

[0047] The offset correction circuit 150 includes, for example, a current output DA converter (IDAC) formed of a sink-type current source. Under the control of an offset correction control circuit 240 (described later), the offset correction circuit 150 variably adjusts the output current values ​​of the IDACs so that the difference between the differential comparison result signals COMPout_P and COMPout_N output from the analog comparator 120 approaches "0" when the difference between the signals is set to "0." The offset correction circuit 150 stores the output current value when the difference becomes "0" or approximately "0" as an offset correction value. Offset correction for the analog comparator 120 is performed prior to correction (calibration) for the CDAC 110. Note that, in the present disclosure, the offset correction circuit 150 is configured as part of the ADC main circuit 10, but may also be configured as part of the ADC control circuit 20. Details of offset correction by the offset correction circuit 150 will be described later.

[0048] The ADC control circuit 20 is a circuit that controls the operation of the ADC main circuit 10. The ADC control circuit 20 may be configured as a programmable device in part or in whole. Under the control of the system control circuit 30, the ADC main circuit 10 performs linearity correction (calibration) in the calibration mode to eliminate the effects of manufacturing variations in the capacitor bank of the CDAC 110. Meanwhile, in the normal mode, the ADC control circuit 20 outputs a calibration instruction value obtained in the calibration mode to the ADC main circuit 10. Two calibration instruction values ​​are prepared, and one of them is selected according to the value of the comparison result signal COMP. Typically, the ADC control circuit 20 performs offset correction of the analog comparator 120 before performing linearity correction of the CDAC 110.

[0049] Note that, when the offset correction of the analog comparator 120 has already been performed, the ADC control circuit 20 may immediately perform control to perform linearity correction of the CDAC 110. The ADC control circuit 20 is configured to include, for example, a selector 210, a correction capacitance value specifying circuit 220, a state machine 230, and an offset correction control circuit 240.

[0050] The selector 210 is a circuit for selectively controlling the operation of the correction capacitance value specifying circuit 220 in accordance with the output from the logic circuit 140. Specifically, the selector 210 outputs a selector signal to a multiplexer 222 (see FIG. 4) in the correction capacitance value specifying circuit 220 for selecting an appropriate correction specifying value in accordance with the digital output signal D_MAIN output from the logic circuit 140.

[0051] The correction capacitance value instruction circuit 220 is a circuit for outputting a correction instruction value obtained by executing linearity correction to the CDAC 110. The CDAC 110 supplies a correction value (correction capacitance value) for the capacitor Cm of the main capacitor bank 111a by the capacitor Ca of the auxiliary capacitor bank 111b in accordance with the given correction instruction value. The configuration of the correction capacitance value instruction circuit 220 will be described in detail later.

[0052] The state machine 230 is a circuit for controlling the operating state of the ADC main circuit 10. Specifically, under the control of the system control circuit 30, the state machine 230 controls whether the CDAC 110 operates in a correction mode for performing correction (calibration) or in a normal mode for actual operation. In the correction mode, the state machine 230 also controls the offset correction circuit 150 to perform offset correction prior to linearity correction. Note that if offset correction has already been performed in the past, this step may be omitted.

[0053] The offset correction control circuit 240 controls the offset correction of the output voltage of the analog comparator 120 by controlling the output current value of the IDAC of the offset correction circuit 150 to change stepwise or gradually. That is, the offset correction control circuit 240 gradually adjusts the value of the output current of the IDAC in response to the value of the digital output signal D_MAIN output from the latch circuit 130 to correct the offset including the latch when the difference between the differential capacitance redistribution signals VC_P and VC_N output from the analog comparator 120 is set to 0. The offset correction control circuit 240 sets the output current value when the value of the comparison result signal COMP output from the latch circuit 130 is inverted as the minimum offset value and stores this correction value. As a result, the output voltage of the analog comparator 120 is offset-corrected, and the threshold value of the output logic of the latch circuit 130 is set with high accuracy.

[0054] The system control circuit 30 is a higher-level circuit for comprehensively controlling the operation of the successive approximation register ADC 1. For example, the system control circuit 30 controls the successive approximation register ADC 1 to operate in a correction mode or a normal mode. Specifically, in the correction mode, the system control circuit 30 outputs a correction enable signal CAL_EN and controls the ADC control circuit 20 to perform a correction process on the CDAC 110. In response to this, in the correction process, the ADC control circuit 20 performs offset correction on the analog comparator 120 prior to performing linearity correction, and then performs linearity correction on the CDAC core 111. Furthermore, in the normal mode, the system control circuit 30 controls the ADC control circuit 20 to correct the capacitor Ca of the CDAC 110 with a correction value determined by the linearity correction.

[0055] In the following description, when the above-mentioned various differential signals (e.g., "differential analog input signals Vin_P and Vin_N") can be treated as the same except for their polarity, they may be referred to as, for example, "differential analog input signal Vin" for simplicity.

[0056] (Example of CDAC circuit configuration) 2 is a diagram showing an example of the circuit configuration of a CDAC core in a successive approximation register ADC according to the first embodiment of the present invention. As shown in the figure, the CDAC core 111 includes a main capacitor bank 111a and an auxiliary capacitor bank 111b. Note that the figure shows one of the capacitor banks in the CDAC core 111 that correspond to different polarities.

[0057] The main capacitor bank 111a is composed of a plurality of first capacitors (hereinafter referred to as "capacitors Cm") connected in parallel in an array, and the auxiliary capacitor bank 111b is composed of a plurality of second capacitors (hereinafter referred to as "capacitors Ca") connected in parallel in an array. In this example, the main capacitor bank 111a is composed of n-1 capacitors Cm (i.e., capacitors Cm <n-1>~Cm <0> This is called "Cm <n-1:0>It is sometimes written as ". ) and a capacitor Cm_unit. Here, the capacitor Cm <n-1>corresponds to the MSB, and the capacitor Cm <0> corresponds to the LSB of the digital code. The capacitor Cm_unit is a capacitor for ensuring a minimum base capacitance value. The capacitance value of the capacitor Cm_unit is set to, for example, 2^0×C.

[0058] Each capacitor Cm <x>The capacitance value of the capacitor Cm is ideally binary weighted (where C is a constant that indicates an arbitrary capacitance value). <n-1>The capacitance value of the capacitor Cm is the maximum. In the present disclosure, the capacitance value of each of the capacitors Cm is set to a negative value obtained by subtracting a predetermined capacitance value from such an ideal value (nominal value). As will be described later, in linearity correction, the shortfall obtained by subtracting the predetermined capacitance value from the ideal value is compensated for by the capacitance value of the auxiliary capacitor bank 111b. <x>The predetermined capacitance value to be subtracted from the ideal value in the main capacitor bank 111a can be appropriately determined in relation to the capacitance value of the entire auxiliary capacitor bank 111b, taking into consideration the range of correctable capacitance values. <n-1>The capacitance value of this capacitor should normally be the nominal value 2^(n-1) x C, but in this case a predetermined capacitance value a(n-1) is subtracted to enable correction to the negative side, e.g., 2^(n-1) x Ca(n-1).

[0059] A switch SWm is connected in series to each capacitor Cm so that a specific voltage can be selectively applied to it depending on the operating state of the CDAC 110. Each switch SWm is independently controlled. For example, by controlling the opening and closing of each switch SWm, some of the capacitors Cm can be connected to either a first reference voltage (e.g., a reference voltage VREF_P) or a second reference voltage (e.g., a reference voltage VREF_N) having a polarity different from that of the first reference voltage, and the remaining capacitors Cm can be connected to the second reference voltage or the first reference voltage in a complementary manner. In addition, the switch SW_VCM is a switch for forcibly setting the capacitance reallocation signal VC (see FIG. 2) to the common voltage VCM.

[0060] The auxiliary capacitor bank 111b supplies a capacitance value for each capacitor Cm of the main capacitor bank 111a to make it ideal or approach the ideal value. a bits (n a is any positive number) <0> ~Ca <n a In this example, the capacitance of the capacitor Ca is <3> is 2^(n a -1)×C. The auxiliary capacitor bank 111b is configured to include a split capacitor Ca_split inserted at an arbitrary position of the parallel-connected capacitors Ca. <0> ~Ca <n a -1> is the upper a bits and the lower b bits (a+b=n a ) In this way, by inserting the split capacitor Ca_split between the upper a bits and the lower b bits, it is possible to express a relatively small capacitance value while improving the efficiency of the circuit area and power, and to increase the bit resolution in linearity correction. In this example, the capacitance value of the split capacitor Ca_split is 2^(1) × C. Therefore, in the configuration shown in the figure, the capacitance value of the capacitor Ca <3> For the capacitance value of the capacitor Ca <0> The capacitance value can be expressed up to 1 / 8.

[0061] A switch SWa is connected to each capacitor Ca so that a specific voltage can be selectively applied to it depending on the operating state of the CDAC 110. Each switch SWa is independently controlled. For example, by controlling the opening and closing of each switch SWa, some of the capacitors Ca can be connected to either a first reference voltage or a second reference voltage, and the remaining capacitors Ca can be connected to either the second reference voltage or the first reference voltage in a complementary manner.

[0062] (Basic concept of linearity correction) 3 is a diagram for explaining the basic concept of linearity correction for a CDAC in a successive approximation ADC according to the first embodiment of the present invention. Here, the CDAC 110 (i.e., the CDAC core 111) has a capacitor Cm <0> ~Cm <n-1>) is assumed to be an n-bit configuration.

[0063] Referring to the figure, the linearity correction is performed by using the capacitor Cm corresponding to the MSB of the main capacitor bank 111a. <n-1>Sequence sq(1) for correcting the capacitor Cm <n-2>Sequence sq(2) for correcting the capacitor Cm <n-3>The sequence sq(3), ..., LSB of the capacitor Cm <0> In each sequence sq, the capacitance value of the capacitor Cm corresponding to the upper bits including the predetermined bit to be corrected is equal to the total capacitance value of the capacitors Cm and Cm_unit corresponding to the lower bits, i.e., Cm <n-1>=ΣCm <n-2:0>+Cm_unit The correction is performed so that

[0064] For example, if the CDAC has a 3-bit configuration (n=3), sq(1):Cm <2> =Cm <1> +Cm <0> +Cm_unit sq(2):Cm <1> =Cm <0> +Cm_unit sq(3):Cm <0> =Cm_unit This becomes:

[0065] In this way, the capacitor Cm corresponding to the MSB of the main capacitor bank 111a <n-1>to the capacitor Cm corresponding to the LSB <0> In the process of sequentially determining the correction capacitance value (capacitance value supplied by the auxiliary capacitor Ca) for each bit, the capacitance value of the capacitor Cm for the lower bit depends on the capacitance values ​​of the capacitors Cm for all bits above it.

[0066] (Example of circuit configuration for correction capacitance value indication circuit) 4 is a diagram showing an example of the configuration of a correction capacitance value instruction circuit in the successive approximation type ADC according to the first embodiment of the present invention. As described above, the correction capacitance value instruction circuit 220 is a circuit for outputting, to the CDAC 110, a correction instruction value that instructs the CDAC 110 on the correction capacitance value to be supplied to each capacitor Cm of the main capacitor bank 111a obtained by linearity correction. As shown in the diagram, the correction capacitance value instruction circuit 220 is configured to include, for example, a flip-flop 221, multiplexers 222 to 224, and an adder 225.

[0067] The flip-flop 221 is a D flip-flop circuit for holding the value of the correction instruction signal D_AUX (correction instruction value D_AUX) supplied to the CDAC 110 at the timing of one bit earlier. In other words, the flip-flop 221 is configured so that the correction instruction signal D_AUX supplied to the CDAC 110 is directly fed back while the successive approximation type ADC 1 is in operation. In the present disclosure, the value of the supplied correction instruction signal D_AUX is a logical value of either a first value (e.g., "0") or a second value (e.g., "1"), and therefore two flip-flops 221a and 221b are provided to respectively hold values ​​of the pre-correction instruction signals PreD_AUX0 / 1 (hereinafter referred to as "pre-correction instruction values" and sometimes "pre-correction instruction values ​​PreD_AUX0 / 1") at the timing of one bit earlier. Which of the correction instruction signals PreD_AUX of the flip-flops 221a and 221b (i.e., the correction instruction value at the timing of one bit before the feedback) is used is determined based on the comparison result signal COMP output from the latch circuit 130. Note that the capacitor Cm corresponding to the MSB of the CDAC 110 (i.e., the CDAC core 111) <n-1>For bit 1, since there is no correction instruction value at the timing one bit before, the flip-flops 221a and 221b are set to, for example, an initial value "0".

[0068] The multiplexer 222 is a circuit for selectively outputting the correction instruction values ​​output from the flip-flops 221a and 221b under the control of the selector 210. That is, while the successive approximation type ADC 1 is operating in the normal mode, the selector 210 controls the multiplexer 222 based on the comparison result signal COMP output from the latch circuit 130 so that the pre-correction instruction signal PreD_AUX is output from either the flip-flops 221a or 221b, and in response to this, the multiplexer 222 selectively outputs either the pre-correction instruction signal PreD_AUX output from the flip-flops 221a or 221b.

[0069] The multiplexer 223, under the control of the selector 210, selects the capacitor Cm <n-2:0>In this example, the multiplexer 223 is provided with multiplexers 223a and 223b. Each of the multiplexers 223a and 223b is connected to a capacitor Cm <n-2:0>The multiplexers 223a and 223b selectively output the correction instruction value of any one of the bits under the control of the selector 210. The correction instruction values ​​selectively output by the multiplexers 223a and 223b are input to the adder 225.

[0070] The multiplexer 224 connects the capacitor Cm corresponding to the MSB <n-1>In this example, the multiplexer 224 is provided with multiplexers 224a and 224b. The selector 210 selects the capacitor Cm corresponding to the MSB. <n-1>When correcting the n-1 bits (MSB), the multiplexers 224a and 224b are controlled so that a correction instruction value for the n-1 bits (MSB) is selected. In response to this, the multiplexer 224a selectively outputs the correction instruction value for the MSB as the correction instruction signal D_AUX0, while the multiplexer 224b selectively outputs the correction instruction value for the MSB as the correction instruction signal D_AUX1.

[0071] The adder 225 is a circuit that performs a logical OR operation on the output from the multiplexer 222 and the output from the multiplexer 223. In this example, the adder 225 is configured to include adders 225a to 225c. As shown in the figure, the output from the multiplexer 222 is branched into two, one of which is added by the adder 225a to the output C from the multiplexer 223a. k-1 The result is input to the flip-flop 221a as a pre-correction instruction signal PreD_AUX0, and the other is first added to the output C k This is then added to the output from the multiplexer 223a by an adder 225c, and the result is input to the flip-flop 221a as a pre-correction instruction signal PreD_AUX1.

[0072] In the correction capacitance value instruction circuit 220 configured as above, the relationship between the pre-correction instruction signal preD_AUX0 / 1 and the correction instruction signal D_AUX0 / 1 is expressed as follows. PreD_AUX0[k-1]=PreD_AUX[k] PreD_AUX1[k-1]=PreD_AUX[k]+C k D_AUX0[k-1]=PreD_AUX[k]+C k-1 D_AUX1[k-1]=PreD_AUX[k]+C k +C k-1 Here, k indicates a predetermined bit to be corrected (i.e., capacitor Cm) and is in the range of 0≦k≦n−1 (i.e., the MSB is indicated as the kth bit). Also, PreD_AUX[k] indicates the output of multiplexer 222.

[0073] Here, the correction target is the capacitor Cm <n-1>In the case where k=n−1, the previous bit does not exist, so the correction instruction signal D_AUX0 / 1 output to the CDAC 110 is D_AUX0[n-1]=C n-1 D_AUX1[n-1]=C n-1 is.

[0074] Also, for example, if the correction target is the 1st lower bit of the MSB (capacitor Cm <n-2>), the initial value of the pre-correction instruction signal PreD_AUX0 / 1 for the MSB is set to "0", and the correction instruction signal D_AUX0 / 1 output to the CDAC 110 is D_AUX0[n-2]=PreD_AUX[n-1]+C n-2 =C n-2 D_AUX1[n-2]=PreD_AUX[n-1]+C n-1 +C k-2 =C n-1 +C n-2 Therefore, the pre-correction instruction signal PreD_AUX0 / 1 is PreD_AUX0[n-2]=PreD_AUX[n-1]+C n-2 PreD_AUX1[n-2]=PreD_AUX[n-1]+C n-1 +C n-2 This becomes:

[0075] In addition, the correction target is the two lower bits of the MSB (capacitor Cm <n-3>) (k=n−3), the pre-correction instruction signal PreD_AUX0 / 1 is D_AUX0[n-3]=PreD_AUX[n-2]+C n-3 =C n-2 +C n-3 D_AUX1[n-3]=PreD_AUX1[n-2]+C n-2 +C n-3 =C n-1 +C n-2 +C n-3 Therefore, the pre-correction instruction signal PreD_AUX0 / 1 is PreD_AUX0[n-3]=PreD_AUX[n-1]+C n-2 +C n-3 PreD_AUX1[n-3]=PreD_AUX[n-1]+C n-1 +C n-2 +C n-3 Thereafter, for the correction target bit k, the correction instruction signal D_AUX0 / 1 is calculated in the same manner, and accordingly, the pre-correction instruction signal PreD_AUX0 / 1 is obtained (see FIG. 8).

[0076] Next, the flow of the correction process for the CDAC in the successive approximation type ADC 1 configured as above will be described.

[0077] (flowchart) 5A and 5B are flowcharts showing an example of correction processing for the CDAC in the successive approximation register ADC according to the first embodiment of the present invention. This processing is realized by the ADC control circuit 20 of the successive approximation register ADC 1 controlling the ADC main circuit 10 under the control of the system control circuit 30. As described above, in the correction processing of the present disclosure, after offset correction as shown in FIG. 5A is performed, linearity correction as shown in FIG. 5B is then performed.

[0078] As shown in A in the figure, when the ADC control circuit 20 receives the correction enable signal CAL_EN from the system control circuit 30, it starts executing offset correction for the comparator as shown below (S501 to S507). In the offset correction, for example, multiple scannings are executed to identify the offset correction value.

[0079] That is, the ADC control circuit 20 performs initialization processing of the successive approximation type ADC 1 upon starting execution of offset correction (S501). For example, the ADC control circuit 20 initializes the correction capacitance value instruction circuit 220 to fix the correction instruction signals D_AUX0 and D_AUX1 (hereinafter, unless otherwise necessary, referred to as "correction instruction signals D_AUX0 / 1") to a predetermined value (e.g., "0"), and initializes the offset correction control circuit 240 to set the current adjustment signal SEL_ADC_OFFCAL to an initial value (e.g., "0x00"). In addition, the ADC control circuit 20 outputs an offset correction enable signal EN_ADC_OFFCAL to the offset correction circuit 150, and in response to this, the offset correction circuit 150 becomes active. Furthermore, the ADC control circuit 20 outputs a set signal SET to the CDAC 110, which causes the CDAC 110 to start holding the potential of the differential analog input signal Vin.

[0080] Next, the ADC control circuit 20 increases or decreases the value of the current adjustment signal SEL_ADC_OFFCAL in a stepwise or gradual manner (S502) in order to increase or decrease the output current value of the offset correction circuit 150, and as a result, determines whether the state (value) of the comparison result signal COMP has changed (S503).

[0081] If the ADC control circuit 20 determines that the value of the comparison result signal COMP has changed (Yes in S503), the ADC control circuit 20 temporarily stores the output current value indicated by the current adjustment signal SEL_ADC_OFFCAL at the time of the change (point of change) (S504). Next, the ADC control circuit 20 determines whether scanning has ended (S505). If the ADC control circuit 20 determines that scanning has not yet ended (No in S505), the ADC control circuit 20 increases or decreases the value of the current adjustment signal SEL_ADC_OFFCAL stepwise or gradually (S502).

[0082] On the other hand, if the ADC control circuit 20 determines that the value of the comparison result signal COMP has not changed (No in S503), the ADC control circuit 20 increases or decreases the value of the current adjustment signal SEL_ADC_OFFCAL stepwise or gradually until scanning is completed (S502).

[0083] Since the offset correction is performed to detect errors in the comparison result signal COMPout of the analog comparator 120, the value of the current adjustment signal SEL_ADC_OFFCAL is controlled to increase or decrease within a predetermined range centered on a theoretical value ("0" in this example).

[0084] If the ADC control circuit 20 determines that scanning has ended (Yes in S505), the ADC control circuit 20 further determines whether scanning has been performed a predetermined number of times (S506).If the ADC control circuit 20 determines that scanning has not been performed a predetermined number of times (No in S506), the ADC control circuit 20 repeats the above processing steps (S502 to S505) until multiple scannings have been completed.

[0085] On the other hand, if the ADC control circuit 20 determines that scanning has been performed a predetermined number of times (Yes in S506), the ADC control circuit 20 calculates the average value of the temporarily stored output current values ​​and holds this as the definitive output current value (S507).

[0086] As a result of the above, the ADC control circuit 20 completes the offset correction for the comparator, and then proceeds to perform linearity correction for the CDAC 110. The linearity correction is performed by adjusting the capacitance of the capacitor Cm <n-1>Capacitor Cm corresponding to any lower bit x (the smallest is LSB (x=0)) <x>In descending order, the capacitors Cm <k>In this example, the sequence is executed in descending order up to the LSB.

[0087] That is, the ADC control circuit 20 detects the capacitance of the capacitor Cm <k>The ADC control circuit 20 then performs initialization processing for linearity correction (S508). For example, the ADC control circuit outputs a set signal SET to the CDAC 110, and in response to this, the CDAC 110 controls the switch SWm to form a predetermined capacitor connection configuration and performs sample / hold (see, for example, FIG. 9). After sample / hold, the ADC control circuit 20 switches the capacitor connection configuration for sample / hold to the capacitor connection configuration for linearity correction. Thereafter, the ADC control circuit 20 performs initialization processing for linearity correction of the value of the digital output signal D_MAIN by switching the capacitor Cm <k>The digital code to be output by the capacitor Ca <n-1>If so, it is set to 2^(n-1)×C. Furthermore, the ADC control circuit 20 initializes the correction capacitance value instruction circuit 220, and sets the correction instruction signals D_AUX0 / 1 to predetermined values ​​according to the capacitor Cm to be corrected.

[0088] Next, the ADC control circuit 20 calculates the capacitance of the capacitor Cm <k>In order to identify the optimal correction instruction value, the value of the correction instruction signal D_AUX0 / 1 is increased or decreased stepwise or gradually, and in response thereto, the capacitance value supplied from the auxiliary capacitor bank 111b to the capacitor Cm is increased or decreased (S509), and as a result, it is determined whether the state (value) of the comparison result signal COMP has changed (S510).

[0089] If the ADC control circuit 20 determines that the value of the comparison result signal COMP has changed (Yes in S510), the ADC control circuit 20 temporarily stores the value indicated by the correction instruction signal D_AUX0 / 1 at the time of the change as a pre-correction instruction value (S511). Next, the ADC control circuit 20 determines whether scanning has ended (S512). If the ADC control circuit 20 determines that scanning has not yet ended (No in S512), it increases or decreases the value of the correction instruction signal D_AUX0 / 1 stepwise or gradually (S509). In other words, since the value of the correction target bit of the digital output signal D_MAIN output from the logic circuit 140 has two patterns, "0" or "1," in the linearity correction of the present disclosure, when the value of the comparison result signal COMP is fed back to the correction capacitance value instruction circuit 220, two correction instruction values ​​are stored in advance as values ​​of the pre-correction instruction signal PreD_AUX0 / 1 (i.e., pre-correction instruction values), and one of the two pre-correction instruction values ​​is selected based on the value of the comparison result signal COMP, and the next (latest) two correction instruction signals D_AUX0 / 1 are generated based on this.

[0090] On the other hand, when the ADC control circuit 20 determines that scanning has been performed a predetermined number of times (Yes in S512), the ADC control circuit 20 calculates the average value of the temporarily stored correction indication values ​​and outputs this to the capacitor Cm <k>The output current value is held as a definite value for the output current (S514).

[0091] The ADC control circuit 20 performs the above process on the capacitor Cm <k>This is repeated until the correction instruction value is specified.

[0092] Next, various operations of the correction process for the CDAC in the successive approximation type ADC 1 will be described.

[0093] (offset correction) 6 is a sequence diagram for explaining offset correction for the analog comparator in the successive approximation type ADC according to the first embodiment of the present invention. Such offset correction is typically performed by increasing or decreasing the output current value of the offset correction circuit 150 under the control of the ADC control circuit 20. In the diagram, hatched portions indicate that the values ​​are indefinite.

[0094] As shown in the figure, the system control circuit 30 first outputs a correction enable signal CAL_EN to the ADC control circuit 20 to start correction of the CDAC 110. In response to this, the ADC control circuit 20 starts operating in correction mode, and the state machine 230 outputs a set signal SET to the CDAC 110 and an offset correction enable signal EN_ADC_OFFCAL to the offset correction circuit 150. The offset correction control circuit 240 outputs a current adjustment signal SEL_ADC_OFFCAL with an initial value of "0x00" to the CDAC 110. The current adjustment signal SEL_ADC_OFFCAL is a signal for setting the output current value of the IDAC of the offset correction circuit 150. In this example, the current adjustment signal SEL_ADC_OFFCAL is a 7-bit signal, the MSB of which is the sign bit. The value of the current adjustment signal SEL_ADC_OFFCAL is expressed in two's complement. In response to the set signal SET, the CDAC 110 begins to hold the potential of the differential analog input signal Vin. At this time, the correction instruction signals D_AUX0 / 1 for linearity correction output from the correction capacitance value instruction circuit 220 are each fixed to the value "0." Subsequently, in response to the offset correction enable signal EN_ADC_OFFCAL, the CDAC 110 starts operating, and the comparison result signal COMP output from the latch circuit 130 via the analog comparator 120 stabilizes at a predetermined value.

[0095] Next, the offset correction control circuit 240 executes a search sequence to identify or detect an optimal offset correction value while stepwise or gradually changing the value of the current adjustment signal SEL_ADC_OFFCAL. In this example, the search sequence is executed three times, and the average of the detected values ​​becomes the final offset correction value for the analog comparator 120.

[0096] That is, the offset correction control circuit 240 changes the value of the current adjustment signal SEL_ADC_OFFCAL by one step in each search sequence, and in response to this, the offset correction circuit 150 changes the output current difference of the IDAC by one step in each search sequence. As a result, the offset correction control circuit 240 observes whether the value of the comparison result signal COMP changes.

[0097] If the offset correction control circuit 240 determines that the state (value) of the comparison result signal COMP has changed (inverted) while the value of the current adjustment signal SEL_ADC_OFFCAL is being changed, the offset correction control circuit 240 holds the value of the current adjustment signal SEL_ADC_OFFCAL at the time of the change as a detection value. The offset correction control circuit 240 calculates an average value based on the detection values ​​detected in each search sequence and sets this in a register as an offset correction value.

[0098] When the setting of the offset correction value is completed, the state machine 230 stops outputting the set signal SET, and the offset correction control circuit 240 stops outputting the offset correction enable signal EN_ADC_OFFCAL.

[0099] By performing the offset correction as described above, the offset correction circuit 150 supplies an output current based on the set offset correction value to the input side of the latch circuit 130. As a result, during operation of the successive approximation type ADC 1, the difference between the differential comparison result signals COMPout_P and COMPout_N input from the analog comparator 120 to the latch circuit 130 becomes "0" or approximately "0", and therefore the threshold value of the output logic of the latch circuit 130 is set with high precision.

[0100] (linearity correction) FIG. 7 is a schematic sequence diagram for explaining an example of linearity correction for the CDAC of the successive approximation type ADC according to the first embodiment of the present invention.

[0101] The linearity correction is performed by executing a sequence sq for specifying an appropriate correction capacitance value for each capacitor Cm in the main capacitor bank 111a while gradually changing the correction instruction value output from the correction capacitance value instruction circuit 220 to the CDAC 110. As described above, the offset correction for the comparator is completed before the linearity correction for the CDAC 110.

[0102] As described above, the linearity correction for the CDAC 110 is performed by using the capacitor Cm <n>to the capacitor Cm corresponding to the LSB <0> The state machine 230 outputs a set signal SET to the CDAC 110, and then outputs a linearity correction enable signal EN_ADC_CAL to the CDAC 110. In response to this, the CDAC 110 sequentially charges the capacitors Cm_unit and Cm <n>The switch SWm is controlled so that only the switch SWm operates. In this state, the correction capacitance value specifying circuit 220 starts to output the digital output signal D_MAIN as, for example, "0x800".

[0103] The correction capacitance value instruction circuit 220 changes the correction instruction signal D_AUX0 / 1 in stages under the control of the selector 210. The selector 210 monitors whether the value of the comparison result signal COMP, which is output via the latch circuit 130, changes. When the selector 210 detects a change in the value of the comparison result signal COMP, it notifies the correction capacitance value instruction circuit 220. In response, the correction capacitance value instruction circuit 220 holds the value of the correction instruction signal D_AUX0 / 1 at that time as a correction instruction value that specifies the correction capacitance value for the capacitor Cm to be corrected. In other words, the correction capacitance value instruction circuit 220 changes the correction instruction signal D_AUX0 / 1 in stages to identify the change point. In this way, the correction capacitance value instruction circuit 220 identifies and stores a complementary capacitance value for each capacitor Cm.

[0104] Next, details of linearity correction for the CDAC 110 of the successive approximation type ADC 1 will be described with reference to Fig. 7. Fig. 7 is a detailed sequence diagram for explaining an example of linearity correction for the CDAC of the successive approximation type ADC according to the first embodiment of the present invention.

[0105] As described above, the logic circuit 140 performs serial-to-parallel conversion by sequentially associating one bit of the input comparison result signal COMP with a parallel code bit, and outputs this as a digital output signal D_MAIN of an N-bit digital code in the cycle of the conversion end signal EOC. In the successive approximation type ADC 1, in the process of conversion to an N-bit digital code, it is determined whether the output value (value of the comparison result signal COMP) based on the value of the difference comparison result signal COMPout will be "0" or "1" from the MSB to the LSB of the digital output signal D_MAIN.

[0106] As described above, the output value of the latch circuit 130 can take two patterns, “0” or “1.” Therefore, in the linearity correction of the present disclosure, when the output value is fed back to the correction capacitance value instruction circuit 220, two correction instruction values ​​corresponding to the output value are prepared in advance as pre-correction instruction values. One of the two pre-correction instruction values ​​is selected based on the value of the comparison result signal COMP, and the two latest correction instruction values ​​are calculated based on the value of the comparison result signal COMP. One of the calculated two correction instruction values ​​is selected based on the value of the comparison result signal COMP. In other words, the correction capacitance value instruction circuit 220 stores in advance, as pre-correction instruction values, values ​​calculated one bit before the latch circuit 130 outputs the comparison result signal COMP corresponding to the next bit, selects one of the two pre-correction instruction signals PreD_AUX0 / 1 according to the value of the fed-back comparison result signal COMP, and performs calculation based on the selected pre-correction instruction signal PreD_AUX0 / 1. The CDAC 110 uses the multiplexer 112 to select one of the two calculated correction instruction signals D_AUX0 / 1 according to the comparison result signal COMP, thereby switching and controlling the connection configuration of the capacitor Ca to ensure the capacitance value to be supplied to the capacitor Cm.

[0107] That is, as shown in FIG. 8, the CDAC 110 is initialized by the set signal SET, and at this time, the value of the pre-correction instruction signal PreD_AUX0 / 1 is set to the initial value (in this example, C n )

[0108] Next, the capacitor Cm corresponding to the MSB <n>In this sequence, the digital output signal D_MAIN is set to the target n-bit digital code {1,0,...,0}, and the correction instruction signal D_AUX0 / 1 is supplied to the ADC main circuit 10. As a result, the comparison result signal COMP is output. In the figure, the value of the comparison result signal COMP is D n-1 (1 bit). At this time, the capacitor Cm <n-2>The correction instruction value specifying the correction capacity for the AUX0 / AUX1 is calculated as the pre-correction instruction value PreD_AUX0 / 1, but since there are no dependent values ​​prior to this, each is calculated with an initial value of "0".

[0109] Next, the capacitor Cm corresponding to the next bit (the 1st lower bit of the MSB) <n-2>In this sequence, the digital output signal D_MAIN is the next target n-bit digital code {D n-1 , 1, 0, ..., 0}. Here, the digital code corresponding to the MSB is the value of the comparison result signal COMP obtained one sequence before (i.e., D n-1 ) Then, the pre-correction instruction value PreD_AUX0 / 1 is supplied as the correction instruction signal D_AUX0 / 1, and the comparison result signal COMP is output in the same manner.

[0110] Similarly, the value of the correction instruction signal D_AUX0 / 1 from one sequence before is held as a pre-correction instruction signal PreD_AUX0 / 1 before the comparison result signal COMP is output, and is supplied as the correction instruction signal D_AUX0 / 1 in the sequence of a specified bit to be corrected, and one of them is selected according to the value of the comparison result signal COMP.

[0111] Next, the linearity correction will be described while showing the circuit connection configuration in the CDAC 110. Figures 9 to 11 are diagrams showing an example of the capacitor connection configuration during linearity correction for the CDAC of the successive approximation type ADC according to the first embodiment of the present invention.

[0112] Specifically, FIG. 9 shows the capacitor Cm corresponding to the MSB. <n-1>11(a) and 11(b), the left side of the dashed dotted line shows the capacitor connection configuration of the main capacitor bank 111a, while the right side shows the connection configuration of the auxiliary capacitor bank 111b, with each capacitor shown as its capacitance value (the same applies to the following FIGS. 9 to 11).

[0113] First, as shown in FIG. 1(a), in the main capacitor bank 111a of the CDAC 110, a set signal SET is used to set the capacitor Cm corresponding to the MSB to be corrected. <n-1>is connected to the reference voltage VREF_N, and the remaining capacitor Cm (i.e., ΣCm <n-2:0>) and capacitor Cm_unit are connected to a reference voltage VREF_P.

[0114] On the other hand, in the auxiliary capacitor bank 111b, the capacitor Ca <n a -1> is connected to the reference voltage VREF_N, and the remaining capacitor Ca (i.e., Ca <n a -2:0>;The capacitance value is ΣCa <n a -2:0>) is connected to the reference voltage VREF_P. <n a -1> is the capacitor Cm <n-1>Here, Cex indicates the capacitance value of the unused capacitor Ca due to the above-mentioned capacitor connection configuration. The capacitance value Cex varies depending on the capacitor Cm used to supply the capacitance value to be complemented. That is, in the auxiliary capacitor bank 111b, the capacitance of the capacitor Cm to be corrected is <n-1>The capacitor Ca is configured so that the difference α between the ideal value and the value (in this example, the value a(n-1)×C subtracted from the ideal value; see FIG. 2) is complemented.

[0115] Also, the switch SW_VCM is closed, and the capacitance reallocation signal VC (see FIG. 2) is forcibly set to the common voltage VCM.

[0116] In this state, the capacitor Cm <n-1>9B, the switch SW_VCM is first opened, and the connection configuration of each capacitor Cm, Cm_unit, and each capacitor Ca for each of the reference voltages VREF_P and VREF_N is reversed. After that, the connection of the capacitor Ca is sequentially switched according to the correction instruction value until the optimum correction capacitance value that correctly outputs the desired digital output signal value is identified. <n-1>A search is performed to change the compensation capacitance value.

[0117] That is, the capacitor Cm <n-1>In the linearity correction for the capacitor Cm <n-1>and the remaining capacitor Cm (i.e., Cm <n-2:0>) and capacitor Cm_unit to the reference voltage are reversed. Similarly, the connection configuration to the reference voltage in the auxiliary capacitor bank 111b is reversed. Then, the capacitor Ca <n a The capacitance value of the capacitor Ca is incremented or decremented stepwise or gradually (and thus the amount is transferred to the reference voltage VREF_N). <n a The correction capacitance value α is added or subtracted stepwise or gradually to the capacitor Ca −1>, and the increment or decrement is selected based on the value indicated by the comparison result signal COMP (see FIG. 7). <n a If the value indicated by the comparison result signal COMP is inverted during the phase in which the correction capacitance value α is incremented (decremented) relative to -1>, the phase is switched to the decrement (increment) phase, and this is repeated until the optimal correction capacitance value α is identified. This shortens the search time until the optimal correction capacitance value α is identified. In practice, if too much time is taken from the setting of the common voltage VCM by the set signal SET to the completion of linearity correction, capacitance leakage in the wiring becomes significant, and the accuracy of linearity correction decreases. However, by efficiently searching for the correction capacitance value α as disclosed herein, the search time can be shortened and the accuracy of linearity correction can be improved. Note that, when the capacitor Cm to be corrected is <n-1>If there is no variation in the capacitance, the capacitance value Ca <n a When the value indicated by the comparison result signal COMP is inverted, the capacitance value at that time becomes that of the capacitor Cm <n-1>The correction capacitance value α is specified as the correction capacitance value α for the

[0118] In such linearity correction, preferably, a search is performed multiple times to identify the optimal correction capacitance value, and the average value calculated based on the correction instruction values ​​corresponding to the identified multiple correction capacitance values ​​α is stored, for example, in a register as a definitive correction instruction value.

[0119] FIG. 10 shows the capacitor Cm <n-2>1 shows the circuit connection configuration of the CDAC when performing linearity correction for the

[0120] Capacitor Cm corresponding to the 1 least significant bit of the MSB (MSB-1) <n-2>The linearity correction for the above-mentioned MSB is also performed by the capacitor Cm <n-1>The linearity correction is performed in the same way as for the capacitor Cm <n-1>and the corresponding capacitor Ca <n a -1> is the capacitor Cm <n-2>In the linearity correction for the reference voltage VREF_N, the reference voltage VREF_N is always fixed to the reference voltage VREF_N side.

[0121] That is, as shown in FIG. 1(a), in the main capacitor bank 111a of the CDAC 110, the capacitor Cm <n-1>and the capacitor Cm to be corrected <n-2>is connected to the reference voltage VREF_N, and the remaining capacitor Cm (i.e., Cm <n-3:0>) and capacitor Cm_unit are connected to a reference voltage VREF_P.

[0122] On the other hand, in the auxiliary capacitor bank 111b, the capacitor Ca <n a -1> and Ca <n a -2> is connected to the reference voltage VREF_N, and the remaining capacitor Ca (i.e., ΣCa <n a -3:0>) is connected to the reference voltage VREF_P. <n a -2> is the capacitor Cm <n-2>The capacitance value is supplied assuming that there is no variation.

[0123] Furthermore, the switch SW_VCM is closed, and the voltages of the capacitors Cm and Ca are forcibly set to the common voltage VCM.

[0124] In this state, the capacitor Cm <n-2>That is, as shown in FIG. 1(b), first, the switch SW_VCM is opened, and the connection configuration of each capacitor Cm and Cm_unit and each capacitor Ca for each of the reference voltages VREF_P and VREF_N is reversed. After that, the connection of the capacitor Ca is sequentially switched in accordance with the correction instruction until the optimum correction capacitance value α that correctly outputs the desired digital output signal value is identified. <n-2>A search is performed to change the capacitance value to be complemented.

[0125] In addition, the capacitor Cm <n-1>The compensation capacitance value for the capacitor Ca <n a -1>+α) (where α=a(n-1)) is the next bit, capacitor Cm <n-2>The correction capacitance value α does not need to be adjusted according to the correction value for the capacitor Cm, and is independent of the correction capacitance value α for the other capacitors Cm. The reason for this is that in the normal mode operation of the successive approximation type ADC 1, the comparison is made at the nth bit, then based on that result, the comparison is made at the next bit (n-2th bit), then based on that result, the comparison is made at the bit after that (n-3th bit), and so on, and so on, because the capacitors Cm corresponding to each bit are used independently of one another. In addition, the capacitors Cm <n-1>When correcting the linearity of the remaining capacitors Cm, which may vary, the total capacitance value (i.e., ΣCm <n-2:0>The capacitance value of the capacitor Cm <n-1>Therefore, there will be no discrepancy between them.

[0126] FIG. 11 shows the capacitor Cm <n-3>1 shows the circuit connection configuration of the CDAC when performing linearity correction for the

[0127] Capacitor Cm corresponding to the 2 least significant bits of the MSB (MSB-2) <n-3>The linearity correction for the capacitor Cm <n-1:n-2>and the corresponding capacitor Ca <n a -1:n a -2> is the capacitor Cm <n-3>In the linearity correction for the reference voltage VREF_N, the reference voltage VREF_N is always fixed to the reference voltage VREF_N side.

[0128] First, as shown in FIG. 1(a), in the main capacitor bank 111a of the CDAC 110, the capacitor Cm <n-1:n-2>and the capacitor Cm to be corrected <n-3>is connected to the reference voltage VREF_N, and the remaining capacitor Cm (i.e., Cm <n-4:0>) and capacitor Cm_unit are connected to a reference voltage VREF_P.

[0129] On the other hand, in the auxiliary capacitor bank 111b, the capacitor Ca <n a -1:n a -3> is connected to the reference voltage VREF_N, and the remaining capacitor Ca (i.e., ΣCa <n a -4:0>) is connected to the reference voltage VREF_P. <n a -3> is the capacitor Cm <n-3>A correction capacitance value α is supplied to

[0130] Also, the switch SW_VCM is closed, and the capacitance reallocation signal VC is forcibly set to the common voltage VCM.

[0131] In this state, the capacitor Cm <n-3>That is, as shown in FIG. 1(b), first, the switch SW_VCM is opened, and the connection configuration of each capacitor Cm and Cm_unit and each capacitor Ca for each of the reference voltages VREF_P and VREF_N is reversed. After that, the connection of the capacitor Ca is sequentially switched until the optimum correction capacitance value α that correctly outputs the desired digital output signal value is identified. <n-3>A search is performed to change the correction capacitance value α.

[0132] The linearity correction described above is performed for each capacitor Cm of the CDAC 110, for example, by adjusting the capacitor Cm corresponding to the LSB. <0> This allows an optimum correction capacitance value α for each capacitor Cm to be obtained. The obtained correction capacitance value α is supplied when the capacitance is redistributed by the capacitor Cm in the normal mode.

[0133] (Normal mode operation) Next, operation in normal mode of the successive approximation type ADC 1 after linearity correction is completed will be described with reference to an example of a circuit connection configuration in the CDAC 110. Note that in operation in normal mode of the successive approximation type ADC 1, correction instruction signals D_AUX0 / 1 for specific capacitors Cm corresponding to predetermined bits to be corrected are directly fed back in the correction capacitance value instruction circuit 220 of the ADC control circuit 20 and are stored in advance as pre-correction instruction signals D_AUX0 / 1, and when the next bit becomes the predetermined bit to be corrected, one of the pre-correction instruction signals D_AUX0 / 1 for the specific capacitor Cm corresponding to the current predetermined bit to be corrected is selected in accordance with the comparison result signal COMP output from the latch circuit 130 to generate the correction instruction signal D_AUX0 / 1.

[0134] FIG. 12 is a diagram showing an example of a capacitor connection configuration in a CDAC in a normal mode of the successive approximation register ADC according to the first embodiment of the present invention. More specifically, FIG. 12 shows an example of a capacitor connection configuration during sample / hold of the CDAC.

[0135] As shown in the figure, the CDAC 110 performs sample / hold before capacitance redistribution by the capacitor Cm. That is, under the control of the ADC control circuit 20, the CDAC 110 connects all of the capacitors Cm in the main capacitor bank 111a and all of the capacitors Ca in the auxiliary capacitor bank 111b to the input terminal Vin in response to a set signal SET. At this time, the output voltage of the CDAC 110 is forcibly set to the common voltage VCM by closing SW_VCM. As a result, all of the capacitors Cm and Ca are charged. Thereafter, under the control of the ADC control circuit 20, SW_VCM is opened and the CDAC 110 starts capacitance redistribution based on the input analog signal Vin.

[0136] FIG. 13 is a diagram showing an example of a capacitor connection configuration in a CDAC in a normal mode of the successive approximation register ADC according to the first embodiment of the present invention. More specifically, the diagram shows a capacitor Cm corresponding to the MSB. <n-1>1 shows an example of a capacitor connection configuration in the CDAC 110 when capacitance is redistributed by the above.

[0137] That is, as shown in the figure, under the control of the ADC control circuit 20, the CDAC 110 converts the capacitor Cm <n-1>is connected to the reference voltage VREF_P, and the compensation capacitance value (Ca <n a A capacitor Ca configured to supply a reference voltage VREF_P is connected to the reference voltage VREF_P. This forms a capacitance distributor. At this time, of all the capacitors Ca in the auxiliary capacitor bank 111b, the unused capacitors Ca are connected to the reference voltages VREF_P and VREF_N so that the capacitance value Cex due to the connection configuration of the unused capacitors Ca as a result of the linearity correction is distributed in half (i.e., Cex / 2). This prevents bias in the dynamic range of the successive approximation type ADC 1.

[0138] CDAC110 capacitor Cm <n-1>outputs a capacitance redistribution signal VC according to the voltage charged by the input analog signal Vin. <n-1>When the voltage of the capacitance redistribution signal VC output from is smaller than 1 / 2 of the reference voltage VREF, the output (comparison input signal COMPout) of the analog comparator 120 becomes High, and as a result, the MSB is coded as "1".

[0139] FIG. 14 is a diagram showing an example of a capacitor connection configuration in a CDAC in a normal mode of the successive approximation register ADC according to the first embodiment of the present invention. More specifically, the diagram shows a capacitor Cm <n-2>1 shows an example of a capacitor connection configuration in the CDAC 110 when capacitance is reallocated to the next lower bit of the MSB (MSB-1) according to the above.

[0140] That is, as shown in the figure, the CDAC 110, under the control of the ADC control circuit 20, <n-2>and capacitor Ca <n a -2>+α (where α=a(n-2) is connected to the reference voltage VREF_P, and the capacitance comparison is already completed for the capacitor Cm <n-1>and the remaining capacitor Cm <n-3:0>is connected to the reference voltage VREF_N. Also, under the control of the ADC control circuit 20, the CDAC 110 connects the capacitor Ca <n a -2>+α (where α=a(n-2)) is connected to the reference voltage VREF_P, and the remaining capacitor Ca is connected to the reference voltage VREF_N. In this state, the capacitor Cm <n-2>outputs a capacitance redistribution signal VC according to the voltage charged by the input analog signal Vin.

[0141] FIG. 15 is a diagram showing an example of a capacitor connection configuration in a CDAC in a normal mode of the successive approximation register ADC according to the first embodiment of the present invention. More specifically, the diagram shows a capacitor Cm <n-3>10 shows an example of a capacitor connection configuration in the CDAC 110 when capacitance is reallocated to the two least significant bits of the MSB (MSB-2) according to the above.

[0142] That is, as shown in the figure, the CDAC 110, under the control of the ADC control circuit 20, <n-3>and capacitor Ca <n a -3>+α (where α=a(n-3)) is connected to the reference voltage VREF_P, and the capacitance comparison is already completed for the capacitor Cm <n-1>and Cm <n-2>and the remaining capacitors Cm <n-4:0>is connected to the reference voltage VREF_N. Also, under the control of the ADC control circuit 20, the CDAC 110 connects the capacitor Ca <n a -3>+α (where α=a(n-3)) is connected to the reference voltage VREF_P, and the remaining capacitor Ca is connected to the reference voltage VREF_N. In this state, the capacitor Cm <n-3>outputs a capacitance redistribution signal VC according to the voltage charged by the input analog signal Vin.

[0143] In this way, under the control of the ADC control circuit 20, the CDAC 110 converts the capacitance of the capacitor Cm <k>is connected to the reference voltage VREF_P, and the capacitor Cm <k>The capacitors Cm other than the reference voltage VREF_N are connected to the reference voltage VREF_P or VREF_N depending on the correction target bit k, while the capacitor Ca is connected to either the reference voltage VREF_P or VREF_N depending on the correction target bit k. <k>outputs a capacitance redistribution VC according to the voltage charged by the input analog signal Vin.

[0144] (Advantages or effects, etc.) As described above, according to this embodiment, the CDAC 110 performs capacitance redistribution by each capacitor Cm from the MSB to the capacitor Cm corresponding to any lower bit (for example, the capacitor Cm corresponding to the LSB). <0> ) As a result, an optimal correction capacitance value is supplied to each capacitor Cm, and the CDAC 110 can redistribute the capacitance of the capacitors Cm with higher accuracy, thereby outputting an accurate digital output signal D_MAIN.

[0145] In particular, according to this embodiment, offset correction is performed on the analog comparator before linearity correction is performed on the CDAC 110, thereby realizing linearity correction with higher accuracy.

[0146] Furthermore, according to this embodiment, the correction capacitance value instruction circuit 220 of the ADC control circuit 20 directly feeds back the correction instruction signals D_AUX0 / 1 for the specific capacitors Cm corresponding to the specific bit to be corrected and stores them in advance as pre-correction instruction signals D_AUX0 / 1, and when the next bit becomes the specific bit to be corrected, one of the pre-correction instruction signals D_AUX0 / 1 for the specific capacitors Cm corresponding to the current specific bit to be corrected is selected according to the comparison result signal COMP output from the latch circuit 130 to generate the correction instruction signal D_AUX0 / 1, thereby suppressing an increase in the size of the circuit configuration of the successive approximation type ADC 1 and preventing a decrease in operating speed.

[0147] Furthermore, according to this embodiment, the correction capacitance value instruction circuit 220 is dual-wired for the correction instruction signal D_AUX0 / 1, and the next bit of the correction instruction signal D_AUX0 / 1 is calculated using a pre-correction instruction signal D_AUX0 / 1 that is directly fed back to the correction instruction signal D_AUX0 / 1. Therefore, critical calculation timing is not required compared to the conventional art, and the margin for calculation timing is increased, making it possible to further improve the operating frequency of the successive approximation type ADC 1.

[0148] [Second embodiment] This embodiment is a modification of the above embodiment, and is characterized in that x^2 patterns of correction instruction values ​​up to p bits (where p is a positive number equal to or greater than 2) before are stored in advance, and one of the p^2 ​​patterns of correction instruction values ​​is selected based on the result of the comparison result signal COMP to generate the latest correction instruction value. In the following description, it is assumed that four patterns of correction instruction values ​​up to 2 bits (i.e., p=2) before are stored in advance.

[0149] 16 is a diagram showing an example of the configuration of a correction capacitance value instruction circuit in a successive approximation type ADC according to a second embodiment of the present invention. As shown in the figure, a correction capacitance value instruction circuit 220 of this embodiment is generally different from that shown in FIG. 4 in that it includes four flip-flops 221a to 221d for holding pre-correction instruction signals D_AUX0 / 1 and two multiplexers 222a and 222b corresponding to the four flip-flops. In the figure, the same components as those shown in FIG. 4 are denoted by the same reference numerals. Note that the configuration of the flip-flop 221 shown in the figure is merely an example, and the configuration can be changed as appropriate depending on the logic design based on the initial value to be held.

[0150] According to this embodiment, the same advantages or effects as those of the above-described embodiment can be achieved. In particular, according to this embodiment, the successive approximation type ADC 1 can store the correction instruction value of the previous two bits in advance, thereby achieving further speedup.

[0151] The above-described embodiments are merely examples for explaining the present invention, and are not intended to limit the present invention to these embodiments. The present invention can be embodied in various forms without departing from the spirit of the present invention.

[0152] For example, in the methods disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, provided that the results do not conflict. The steps, operations, and functions described are provided merely as examples, and some of the steps, operations, and functions may be omitted, combined into one, or additional steps, operations, or functions may be added, without departing from the spirit of the invention.

[0153] Furthermore, although various embodiments are disclosed in this specification, specific features (technical matters) in one embodiment can be added to or substituted for specific features in other embodiments, with appropriate modifications, and such forms are also included in the spirit of the present invention. [Explanation of symbols]

[0154] 1…Successive approximation type ADC 10...ADC main circuit 110...CDAC 111...CDAC core 111a...Main capacitor bank 111b...Auxiliary capacitor bank 112...Multiplexer 120...Analog comparator 130...Latch circuit 140...Logic circuit 150...Offset correction circuit 20...ADC control circuit 210...Selector 220...Compensation capacitance value indication circuit 221...Flip-flops 222...Multiplexer 223...Multiplexer 224...Multiplexer 225...adder 230…State Machine 240...Offset correction control circuit 30...System control circuit< / k> < / k> < / k> < / n> < / n> < / n> < / k> < / k> < / k> < / k> < / k> < / k> < / x> < / x> < / x>

Claims

1. A capacitance redistribution type successive approximation type analog-to-digital converter, an ADC control circuit; an ADC main circuit that converts an input analog input signal into a digital output signal under the control of the ADC control circuit, and outputs the digital output signal; The ADC main circuit comprises: a CDAC including: a main capacitor bank configured with a plurality of first capacitors connected in parallel; and an auxiliary capacitor bank configured with a plurality of second capacitors connected in parallel, the auxiliary capacitor bank being connected so as to be able to supply a correction capacitance value to any of the plurality of first capacitors in the main capacitor bank; a comparator that outputs a bit signal based on a capacitance redistribution signal output in response to the analog input signal in accordance with capacitance redistribution by the CDAC; a logic circuit that outputs the digital output signal in a predetermined format based on the bit signal output from the comparator; a correction capacitance value instruction circuit that outputs a correction instruction value for instructing a correction capacitance value to be supplied to the first capacitor in the main capacitor bank, the correction capacitance value indication circuit holds in advance at least two sets of the correction indication values ​​at a timing at least one bit earlier as pre-correction indication values, selects one of the pre-correction indication values ​​in accordance with the bit signal fed back from the comparator, and calculates the two latest sets of the correction indication values ​​based on one of the selected pre-correction indication values. Successive approximation analog-to-digital converter.

2. the CDAC controls the correction capacitance value to be supplied to the first capacitor based on one of the two correction instruction values; 2. The successive approximation type analog-to-digital converter according to claim 1.

3. the ADC main circuit selects one of the two correction indication values ​​in accordance with the bit signal fed back from the comparator; 3. The successive approximation type analog-to-digital converter according to claim 2.

4. the CDAC controls a connection configuration of the second capacitor based on one of the two correction instruction values ​​so that the correction capacitance value is supplied to the first capacitor; 3. The successive approximation type analog-to-digital converter according to claim 2.

5. an offset correction control circuit that controls execution of offset correction for the comparator; an offset correction circuit that supplies an offset correction value to the comparator under the control of the offset correction control circuit.

2. The successive approximation type analog-to-digital converter according to claim 1.

6. The offset correction control circuit controlling the offset correction circuit to increase or decrease an output current value for the comparator; the output current value when the bit signal output from the comparator changes due to an increase or decrease in the output current value is specified as the offset correction value; 6. The successive approximation type analog-to-digital converter according to claim 5.

7. The comparator an analog comparator that outputs a comparison result signal based on the capacitance redistribution signal; a latch circuit that outputs the bit signal based on the comparison result signal output from the analog comparator.

7. The successive approximation type analog-to-digital converter according to claim 6.

8. the offset correction circuit supplies the offset correction value to the comparison result signal; 8. The successive approximation type analog-to-digital converter according to claim 7.

9. The ADC control circuit Controlling the ADC main circuit to operate in either a correction mode or a normal mode; in the correction mode, a correction capacitance value to be supplied from the auxiliary capacitor bank to the first capacitor to be corrected is identified based on the bit signal output from the comparator by performing linearity correction on the CDAC so that a target digital output signal is output based on a first capacitor to be corrected that corresponds to a predetermined bit; In the normal mode, the specified correction capacitance value is supplied from some of the second capacitors to the first capacitor to be corrected in accordance with the correction instruction value based on the bit signal output from the comparator.

2. The successive approximation type analog-to-digital converter according to claim 1.

10. the ADC control circuit increases or decreases the capacitance value supplied from the auxiliary capacitor bank by changing the correction instruction value stepwise or gradually, and specifies the capacitance value at the time when the bit signal output from the comparator changes as the correction capacitance value for the first capacitor to be corrected.

10. The successive approximation type analog-to-digital converter according to claim 9.

11. the CDAC supplies the capacitance value based on some of the plurality of second capacitors to the first capacitor to be corrected in accordance with the correction instruction value; 11. The successive approximation type analog-to-digital converter according to claim 10.

12. The ADC control circuit connecting the first capacitor to be corrected to a first reference voltage and connecting the first capacitors other than the first capacitor to be corrected to a second reference voltage; controlling the CDAC so as to supply a capacitance value based on some of the plurality of second capacitors connected to the first reference voltage to the first capacitor to be corrected; 12. The successive approximation type analog-to-digital converter according to claim 11.

13. the ADC control circuit controls a connection configuration of second capacitors so that a capacitance value of a second capacitor that is not used for supplying the identified correction capacitance value to the first capacitor to be corrected is distributed to each of the first reference voltage and the second reference voltage in the normal mode.

13. The successive approximation type analog-to-digital converter according to claim 12.

14. In the correction mode, the ADC control circuit performs offset correction on the comparator and then performs the linearity correction.

10. The successive approximation type analog-to-digital converter according to claim 9.

15. the auxiliary capacitor bank includes split capacitors for dividing the plurality of second capacitors into predetermined upper bits and predetermined lower bits; 2. The successive approximation type analog-to-digital converter according to claim 1.

16. the correction capacitance value indication circuit is configured to hold p^2 correction indication values ​​p bits (where p is a positive number of 2 or more) before as pre-correction indication values, one of two pre-correction indication values ​​one bit before is selected as the latest correction indication value based on the bit signal; 2. The successive approximation type analog-to-digital converter according to claim 1.

17. A method for operating a successive approximation type analog-to-digital converter that converts an input analog input signal into a digital output signal and outputs the digital output signal, comprising: outputting a capacitance redistribution signal in response to the analog input signal according to capacitance redistribution by a CDAC; outputting a bit signal by a comparator in response to the capacity redistribution signal; outputting the digital output signal in a predetermined format based on the bit signal; outputting the capacity redistribution signal outputting a correction instruction value that specifies a correction capacitance value to be supplied to a plurality of first capacitors connected in parallel in a main capacitor bank of the CDAC; controlling the correction capacitance value specified by the correction instruction value for any of the plurality of first capacitors to be supplied by a plurality of second capacitors connected in parallel in an auxiliary capacitor bank of the CDAC; The output of the correction instruction value includes storing in advance at least two kinds of the correction instruction values ​​at a timing at least one bit earlier as pre-correction instruction values; selecting one of the pre-correction indication values ​​according to the bit signal fed back from the comparator; calculating the latest two sets of correction indication values ​​based on one of the selected pre-correction indication values; How a successive approximation analog-to-digital converter works.

18. performing linearity correction to specify, based on the bit signal output from the comparator, the correction capacitance value to be supplied from the auxiliary capacitor bank to the first capacitor to be corrected, so that a target digital output signal is output based on the first capacitor to be corrected corresponding to a predetermined bit; 18. A method for operating a successive approximation analog-to-digital converter according to claim 17.

19. performing the linearity correction increasing or decreasing the capacitance value supplied from the auxiliary capacitor bank by changing the correction instruction value in a stepwise or gradual manner; specifying a capacitance value when the bit signal output from the comparator changes in response to an increase or decrease in the capacitance value as the correction capacitance value for the first capacitor to be corrected.

20. A method for operating a successive approximation analog-to-digital converter according to claim 18.

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