Semiconductor device and data read / write method

Abstract

To provide a semiconductor device capable of suppressing an increase in a register size in a multi-chip package, and a data read / write method.SOLUTION: A semiconductor device includes a multi-chip package mounted with a plurality of chips. Each of the plurality of chips includes a register provided by chips other than the self chip, and a register where at least a part of the assigned register addresses differs.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a data read / write method. [Background technology]

[0002] A so-called multi-chip package is known as a semiconductor device that mounts multiple chips, and each mounted chip is provided with a register (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-196739 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional multi-chip packages, the registers on each chip store the same data, which poses the problem of requiring larger registers to store a larger amount of data.

[0005] An object of the present disclosure is to provide a semiconductor device and a data read / write method that can prevent the size of a register from increasing in a multi-chip package. [Means for solving the problem]

[0006] In order to achieve the above object, the semiconductor device of the present disclosure is a semiconductor device having a multi-chip package equipped with multiple chips, and each of the multiple chips has a register that has at least a portion of its assigned register address different from registers that are equipped on chips other than the chip itself.

[0007] In addition, in order to achieve the above-mentioned object, the data reading and writing method disclosed herein has a processor included in a multi-chip package that has multiple chips equipped with registers that have at least some of the assigned register addresses different from registers equipped on chips other than the processor itself, and identifies which of the multiple chips the register address of the read or write destination is assigned to, and performs data reading or writing to the register that is identified as matching. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to prevent the size of the resistor from increasing in a multi-chip package. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of a configuration of a semiconductor device that is a multi-chip package according to an embodiment; [Figure 2] 10A and 10B are diagrams for explaining an example of register addresses assigned to registers provided in each chip of the multi-chip package of the embodiment; [Figure 3] 10 is a flowchart illustrating an example of the flow of a read / write process executed by an identification unit of the embodiment. [Figure 4] 10A and 10B are diagrams for explaining another example of register addresses assigned to registers provided in each chip of the multi-chip package of the embodiment. [Figure 5] 10A and 10B are diagrams for explaining another example of register addresses assigned to registers provided in each chip of the multi-chip package of the embodiment. [Figure 6] FIG. 10 is a diagram for explaining an example of register addresses assigned to registers provided in each chip of a conventional multi-chip package. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the following embodiments do not limit the technology of the present disclosure.

[0011] 1 shows a block diagram illustrating an example of the configuration of a semiconductor device 10 according to this embodiment. The semiconductor device 10 according to this embodiment is a semiconductor device having a so-called multi-chip package (MCP) on which multiple chips are mounted. The semiconductor device 10 according to this embodiment includes an MCU (Micro Controller Unit) 12 and two chips CHIP (CHIP1, CHIP2).

[0012] 1, the chip CHIP1 and the chip CHIP2 have the same configuration. In this embodiment, when the chips CHIP1 and CHIP2 are collectively referred to without distinguishing which one they are, the reference numerals "1" and "2" used to distinguish between the chips CHIP1 and CHIP2 are omitted. For example, each chip CHIP is said to include a communication unit 20, a register block 22, and a circuit unit 24.

[0013] The communication unit 20 has a function of communicating various types of information between the register block 22 and the MCU 12. When writing data to a register 30 of the register block 22, the data to be written and the register address of the write destination are transmitted from the MCU 12 to the register block 22 via the communication unit 20. When reading data from the register 30 of the register block 22, the register address of the read destination is transmitted from the MCU 12 to the register block 22 via the communication unit 20.

[0014] The register block 22 has a register 30, an identification unit 32, and a demultiplexer 34. The register 30 pre-stores a chip bit 31 as identification information for identifying each chip. As an example, in this embodiment, a two-bit chip bit 31 is used. Specifically, the register 30_1 of the chip CHIP1 stores "0h", i.e., "0", as the chip bit 31_1, and the register 30_2 of the chip CHIP2 stores "1h", i.e., "1", as the chip bit 31_2.

[0015] The register 30_1 of the chip CHIP1 and the register 30_2 of the chip CHIP2 have different register addresses (addresses) assigned to the address spaces within the registers. FIG. 2 illustrates the register addresses assigned to the registers 30 of each chip. In the example shown in FIG. 2, the register 30_1 of the chip CHIP1 has six address spaces, and register addresses 0 to 5 are assigned to each address space. On the other hand, the register 30_2 of the chip CHIP2 has six address spaces, and register addresses 6 to 11 are assigned to each address space. The MCU 12 keeps track of the register addresses assigned to the registers 30 of all chips mounted thereon, and in the example shown in FIG. 2, it keeps track of the register addresses 0 to 12.

[0016] The identification unit 32 has a function of identifying whether or not the register address of the storage destination of data instructed to be read or written matches the register address of the register 30 provided in its own chip, and if they match, executing the read or write instruction. Specifically, the identification unit 32 identifies whether or not the register address instructed as the read destination or write destination matches the address assigned to the register 30 provided in its own chip, based on the chip bits 31 stored in the register 30. As an example of such an identification unit 32, the identification unit 32 of this embodiment includes a processor such as a CPU (Central Processing Unit) and memories such as a ROM (Read Only Memory) and a RAM (Random Access Memory).

[0017] The demultiplexer 34 outputs the data read from the register 30 to a predetermined output destination of the circuit section 24 in accordance with the chip bit 31 .

[0018] Next, a method for reading and writing data to the register 30 by the identification unit 32 of this embodiment will be described. Fig. 3 shows a flowchart illustrating an example of the flow of data read and write processing executed in the identification unit 32 of each chip CHIP. In this embodiment, the processor of the identification unit 32 executes a program (not shown) stored in memory, thereby executing the data read and write processing shown in Fig. 3. Also, as an example, in this embodiment, when the communication unit 20 receives an instruction to read or write data from the MCU 12, the data read and write processing shown in Fig. 3 is executed.

[0019] 3, the identification unit 32 refers to the chip bits 31 stored in the register 30. If the referenced chip bits 31 are "0h", i.e., "0", the identification unit 32 can determine that register addresses 0 to 5 are assigned to the register 30. Furthermore, if the referenced chip bits 31 are "1h", i.e., "1", the identification unit 32 can determine that register addresses 6 to 11 are assigned to the register 30.

[0020] In the next step S102, the identification unit 32 determines whether the register address specified by the MCU 12 is an address assigned to the register 30 of its own chip. Specifically, when the register address specified by the MCU 12 is any one of 0 to 5, if the chip bit 31 referenced in step S100 above is "0", the identification unit 32 determines that the address is assigned to the register 30 of its own chip (positive determination). On the other hand, if the referenced chip bit 31 is "1", the identification unit 32 determines that the address is not assigned to the register 30 of its own chip (negative determination). Furthermore, when the register address specified by the MCU 12 is any one of 6 to 11, if the chip bit 31 referenced in step S100 above is "0", the identification unit 32 determines that the address is not assigned to the register 30 of its own chip (negative determination). On the other hand, if the referenced chip bit 31 is "1", the identification unit 32 determines that the address is assigned to the register 30 of its own chip (positive determination).

[0021] If the determination in step S102 is negative, the read / write process shown in Fig. 3 ends. On the other hand, if the determination in step S102 is positive, the process proceeds to step S104.

[0022] In step S104, the identification unit 32 determines whether or not a data write instruction has been issued. If a data write instruction has been issued, the determination in step S104 is affirmative, and the process proceeds to step S106. In step S106, the identification unit 32 writes the data to the specified register address in the register 30.

[0023] On the other hand, if a command to read data has been issued, the determination in step S104 is negative, and the process proceeds to step S 108. In step S 108, the identification unit 32 reads data from the register 30 at the specified register address.

[0024] When step S106 or S108 is completed, the read / write process shown in FIG. 3 is completed.

[0025] As described above, the semiconductor device 10 of the above embodiment is a semiconductor device having a multi-chip package on which multiple chips CHIP are mounted, and each of the multiple chips CHIP has a register 30 in which at least a portion of the assigned register address is different from the register 30 provided on chips other than the chip itself.

[0026] On the other hand, as shown in FIG. 6 , in a semiconductor device 100 that is a conventional multi-chip package different from the present embodiment, the same register address is assigned to the register 130_1 of the chip CHIP1 and the register 130_2 of the chip CHIP2. In the example shown in FIG. 6 , register addresses 0 to 5 are assigned to both the registers 130_1 and 130_2. Therefore, when viewed as a whole, the semiconductor device 100 can be considered to have a register similar to the register 30 included in one register 130. For example, in FIG. 6 , if each of the registers 130_1 and 130_2 is 64 bytes, the semiconductor device 100 as a whole can be considered to have a 64-byte register. Thus, in the conventional semiconductor device 100 shown in FIG. 6 , even if the number of chips CHIPs mounted thereon increases, the register size of the semiconductor device 100 as a whole does not change.

[0027] In contrast to such a conventional semiconductor device 100, in the semiconductor device 10 of this embodiment, as described above, the register 30 of each chip CHIP is assigned a register address that is not assigned to the register 30 of another chip CHIP. Therefore, when viewed as a whole, the semiconductor device 10 can be regarded as a single register made up of the registers 30 of each chip CHIP. For example, in FIG. 1, if each of the registers 30_1 and 30_2 is 64 bytes, the semiconductor device 10 as a whole can be regarded as having a 128-byte register. Thus, in the semiconductor device 10 of this embodiment, the larger the number of chip CHIPs mounted, the larger the register size of the semiconductor device 10 as a whole can be.

[0028] Therefore, the size of the registers used in the semiconductor device 10 as a whole can be increased without increasing the capacity of the registers 30 provided in each chip CHIP in the semiconductor device 10. Therefore, it is possible to prevent the size of the registers 30 from increasing in a multi-chip package. Also, by allocating register addresses as in this embodiment, data sheets and the like to be presented to customers can be arranged in address order that matches the semiconductor device 10, which is a multi-chip package, thereby improving readability and controllability.

[0029] Furthermore, in the semiconductor device 10 of this embodiment, each of the multiple chips CHIPs includes an identification unit 32. The identification unit 32 identifies whether the register address of the data read destination or write destination matches the register address assigned to the register 30 included in the chip itself, and if they match, executes the data read or write. Therefore, as described above, even if different register addresses are assigned to the registers 30 of each chip CHIP, data can be read and written appropriately.

[0030] In the above embodiment, the semiconductor device 10 is described as having two chips mounted thereon. However, the number of chips mounted on the semiconductor device 10, which is a multi-chip package, is not limited to a specific number as long as it is plural. As the number of chips mounted on the semiconductor device 10 increases, the size of the registers in the semiconductor device 10 as a whole can be increased, or the size of the registers 30 provided on each chip can be reduced. When multiple chips are mounted on the semiconductor device 10, some of the chips may be provided with registers 30 that have at least some of the assigned register addresses different from those of the registers 30 provided on the chips other than the chip itself, as in the above embodiment.

[0031] Furthermore, the method of allocating register addresses for the register 30 is not limited to the form shown in the above embodiment (see FIG. 2). Another example of the method of allocating register addresses for the register 30 is shown in FIG. 4. In the example shown in FIG. 4, even-numbered register addresses "0", "2", "4", "6", "8", and "10" are allocated to the register 30_1 of the chip CHIP1. Furthermore, odd-numbered register addresses "1", "3", "5", "7", "9", and "11" are allocated to the register 30_2 of the chip CHIP2.

[0032] In the above embodiment, all register addresses allocated to the registers 30 are different for each chip CHIP, but some of the register addresses may be different. In other words, some of the register addresses allocated to the registers 30 of each chip CHIP may overlap. In the example shown in FIG. 5, register addresses 0 to 2 are allocated to both the register 30_1 of the chip CHIP1 and the register 30_2 of the chip CHIP2. Furthermore, register addresses 3 to 5 are allocated to the register 30_1 of the chip CHIP1, and register addresses 6 to 8 are allocated to the register 30_2 of the chip CHIP2.

[0033] The following additional notes are provided regarding the above-described embodiments. (Appendix 1) A semiconductor device having a multi-chip package on which a plurality of chips are mounted, Each of the plurality of chips has a register with at least a part of the assigned register address different from that of a register of a chip other than the chip itself. Semiconductor device.

[0034] (Appendix 2) Each of the plurality of chips further includes an identification unit that identifies whether a register address from which data is read or written matches a register address assigned to a register included in the chip itself, and, if they match, executes the reading or writing of data. 2. The semiconductor device according to claim 1.

[0035] (Appendix 3) The register is provided with identification information, The identification unit identifies whether or not the register addresses match based on the identification information. 3. The semiconductor device according to claim 2.

[0036] (Appendix 4) A processor included in a multi-chip package on which multiple chips are mounted, each chip having a register with at least a part of the assigned register address different from that of a register included in a chip other than the chip itself, Identifying a register address allocated to a register of a chip among the plurality of chips, the register address being a read or write destination; The data is read or written to the register that is identified as a match. Data reading and writing methods

[0037] (Appendix 5) A processor included in a multi-chip package on which multiple chips are mounted, each chip having a register with at least a part of the assigned register address different from that of a register included in a chip other than the chip itself, Identifying a register address allocated to a register of a chip among the plurality of chips, the register address being a read or write destination; The data is read or written to the register that is identified as a match. A program for executing a process. [Explanation of symbols]

[0038] 10 Semiconductor devices 22_1, 22_2 register blocks 30_1, 30_2 registers 31_1, 31_2 chip bits 32_1, 32_2 Identification section CHIP1, CHIP2 chips

Claims

1. A semiconductor device having a multi-chip package on which a plurality of chips are mounted, Each of the plurality of chips has a register with at least a part of the assigned register address different from that of a register of a chip other than the chip itself. Semiconductor device.

2. Each of the plurality of chips further includes an identification unit that identifies whether a register address from which data is read or written matches a register address assigned to a register included in the chip itself, and, if they match, executes the reading or writing of data. The semiconductor device according to claim 1 .

3. The register is provided with identification information, The identification unit identifies whether or not the register addresses match based on the identification information. The semiconductor device according to claim 2 .

4. A processor included in a multi-chip package on which multiple chips are mounted, each chip having a register with at least a part of the assigned register address different from that of a register included in a chip other than the chip itself, Identifying a register address allocated to a register of a chip among the plurality of chips, the register address being a read or write destination; The data is read or written to the register that is identified as a match. How to read and write data.

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