Semiconductor device

Abstract

To provide a semiconductor device having lead capable of securing junction reliability to a mounting substrate even in the case of a non-lead type package.SOLUTION: A semiconductor device 100 has: a semiconductor chip 110; plural leads 102 isolated from each other around the semiconductor chip 110 and extending from the semiconductor chip 110 in a plane view; sealing resin 140 to form an outer shape so that at least lower and end faces of the plural leads 102 are respectively exposed; and a metal film 150 formed on a lower face of the lead 102. The lower face of the lead 102 is formed at a position above the lower face of the sealing resin 140.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art As electronic devices such as mobile phones and other mobile devices become more sophisticated, there is an increasing demand for smaller and thinner semiconductor devices used in such electronic devices.

[0003] A typical package for a semiconductor device molded from epoxy resin has a structure in which a semiconductor chip is mounted on a die pad, which is part of a lead frame, and is then covered with epoxy resin, which forms the outer shape. One form of small package with this structure is the non-leaded type DFN (Dual Flat Nonleaded) package.

[0004] DFN packages are generally sealed with resin so that the undersides of the leads are nearly flush with the underside of the sealing resin and are exposed. A plating layer is then formed on the undersides of the leads, and the lead frame is then cut into individual pieces using a dicing machine. In DFN packages manufactured in this way, the undersides of the leads on which the plating layer is formed function as outer leads.

[0005] As mentioned above, in a DFN package, if only the underside of the lead on which the plating layer is formed is joined to the mounting board using solder or the like, it is difficult to ensure sufficient bonding strength between the lead and the mounting board.

[0006] In order to prevent this decrease in the bonding strength between the lead and the mounting board, for example, Patent Document 1 discloses a semiconductor device in which a long, thin groove-shaped recess is formed on the lower surface of the lead. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-294719 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one aspect of the present invention is to provide a semiconductor device having leads that can ensure reliable bonding with a mounting substrate even in a non-lead type package. [Means for solving the problem]

[0009] The semiconductor device according to one embodiment of the present invention comprises: A semiconductor chip; a plurality of leads arranged at intervals around the semiconductor chip in a plan view and extending from the semiconductor chip; a sealing resin that is formed to expose at least the bottom surfaces and end surfaces of the leads; a metal film formed on the lower surface of the lead; A semiconductor device having The lower surfaces of the leads are formed at a position higher than the lower surface of the sealing resin. [Effects of the Invention]

[0010] According to one aspect of the present invention, it is possible to provide a semiconductor device having leads that can ensure reliable bonding with a mounting substrate even in a non-lead type package. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic top view (perspective view) of a semiconductor device according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a schematic side view (perspective view) of the semiconductor device shown in FIG. [Figure 2B] FIG. 2B is an enlarged view of part A in FIG. 2A. [Figure 3] FIG. 3 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 4] 4A to 4C are diagrams showing the manufacturing process of the semiconductor device according to the embodiment of the present invention, following FIG. [Figure 5] 5A to 5C are diagrams showing the manufacturing process of the semiconductor device according to the embodiment of the present invention, following FIG. [Figure 6A] FIG. 6A is a schematic side view (perspective view) showing a semiconductor device according to a second embodiment of the present invention. [Figure 6B] FIG. 6B is an enlarged view of part B in FIG. 6A. [Figure 7A] FIG. 7A is a schematic side view (perspective view) of a conventional semiconductor device. [Figure 7B] FIG. 7B is an enlarged view (schematic diagram) of part C in FIG. 7A when a conventional semiconductor device is bonded to a mounting substrate. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and duplicated explanations may be omitted.

[0013] Furthermore, the X-axis, Y-axis, and Z-axis shown in the drawings are perpendicular to one another. The Z-axis direction is sometimes referred to as the "height direction" or "thickness direction." The +Z-axis direction is sometimes referred to as the "upper side," and the -Z-axis direction is sometimes referred to as the "lower side." The surface of each component facing the +Z direction is sometimes referred to as the "front surface" or "top surface," and the surface facing the -Z direction is sometimes referred to as the "rear surface" or "bottom surface." A "planar view" refers to viewing each component from the +Z direction toward the -Z direction. A "side view" refers to viewing each component through the +Y direction toward the -Y direction.

[0014] Furthermore, the drawings are schematic, and the ratios of width, depth, and thickness are not as shown. The number, position, shape, structure, size, etc. of each member are not limited to the embodiments shown below, and may be any number, position, shape, structure, size, etc. that are preferable for implementing the present invention.

[0015] 7A is a schematic side view (perspective view) of a conventional semiconductor device. As shown in FIG. 7A, in a conventional DFN package semiconductor device 900, electrodes on the surface of a semiconductor chip 910 fixed to a die pad 901 with conductive adhesive 920 are electrically connected to multiple leads 902 by conductive wires 930. A step 902a is formed at the corner between a lower surface 902b of each lead 902 and an end surface 902s of the lead. A sealing resin 940 forms the outer shape of the semiconductor device 900 so that at least a portion of the multiple leads 902 is exposed. The die pad 901 and the multiple leads 902 are formed of a metal material such as a copper alloy.

[0016] 7B is an enlarged view (schematic diagram) of portion C in FIG. 7A when a conventional semiconductor device is bonded to a mounting substrate. A lower surface 902b of the lead 902 is formed flush with a lower surface 940b of the sealing resin 940. A metal film 950 is formed on the lower surface 902b of the lead 902. This metal film 950 is formed of a material with good solder wettability, and is bonded to a mounting substrate 980 by solder 970.

[0017] 7A and 7B, the lower surface 902b of the lead is generally formed on the same plane as the lower surface 940b of the sealing resin, and the interface between the lead 902 and the metal film 950 is flush with the lower surface 940b of the sealing resin. In addition, solder 970 is formed on the end of the interface between the lead 902 and the metal film 950.

[0018] In such a structure, when a reliability test is conducted in which high and low temperature changes are repeated, stress generated by differences in the thermal expansion coefficients of the leads 902, the sealing resin 940, and the mounting substrate 980 is concentrated at the interface between the leads 902 and the metal film 950. This stress may cause cracks to occur at the interface between the leads 902 and the metal film 950. The same applies to other non-lead type packages in which the bottom surfaces of the leads and the bottom surface of the sealing resin are formed on approximately the same plane.

[0019] Therefore, in one embodiment of the present invention, the lower surfaces of the leads are formed above the lower surface of the encapsulating resin, which makes it possible to prevent cracks from occurring at the interface between the leads and the metal film, and to provide a semiconductor device having leads that can ensure reliable bonding with the mounting board even in a non-lead type package.

[0020] (First embodiment) 1 is a schematic top view (perspective view) of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, a semiconductor device 100 according to the first embodiment of the present invention includes a semiconductor chip 110, a plurality of leads 102, and a sealing resin 140.

[0021] The semiconductor chip 110 is a semiconductor chip for causing the semiconductor device 100 to function, and is mounted on the upper surface of the die pad 101 by being fixed with a conductive adhesive or the like. The multiple leads 102 are arranged at a fixed distance apart on two opposing sides of the die pad 101 in the +X direction and the −X direction in a plan view.

[0022] A plurality of electrode pads (not shown) formed on the upper surface of the semiconductor chip 110 are electrically connected to the upper surfaces of the plurality of leads 102 by conductive wires 130. The upper surfaces of the leads 102 are formed to be smooth. This ensures a wide area on the upper surfaces of the leads 102 for making second bonds of the conductive wires 130. This ensures a sufficient bonding area for wire bonding and prevents a decrease in connection strength. The conductive wires 130 are, for example, gold wires, copper wires, etc.

[0023] The suspension portion 103 extends from two sides of the die pad 101 in the +Y direction and the -Y direction. In this embodiment, the die pad 101, the multiple leads 102, and the suspension portion 103 are made of the same copper alloy material, and have an integrated lead frame structure. Figure 1 shows one combination that forms one semiconductor device. Finally, they are separated into individual semiconductor devices.

[0024] 2A is a schematic side view (perspective view) of the semiconductor device shown in FIG. 1. As shown in FIG. 2A, a semiconductor chip 110 is mounted on the upper surface of a die pad 101 by being fixed with a conductive adhesive 120. A metal film 150 is formed on the lower surface of the die pad 101, and is exposed from the sealing resin 140 in order to improve the heat dissipation of the semiconductor chip 110. The periphery of the lower surface of the die pad 101 is formed to be thin. This results in a structure in which the sealing resin 140 penetrates into the lower surface around the die pad 101, making it possible to prevent the die pad 101 from falling off the sealing resin 140.

[0025] The thickness of the underside of the lead 102 on the die pad 101 side is formed to be thin. This allows the sealing resin 140 to penetrate into the underside of the lead 102 on the die pad 101 side, preventing the lead 102 from falling off the sealing resin 140. An end face 102s of the lead 102 in the extension direction is exposed from the side face of the sealing resin 140. A step portion 102a is formed at the corner between the underside 102b of the lead and the end face 102s of the lead.

[0026] The metal film 150 is formed continuously on the lower surface 102b and the step portion 102a of the lead 102. The metal film 150 is exposed from the sealing resin 140 and functions as an external terminal.

[0027] 2B is an enlarged view of portion A in FIG. 2A. As shown in FIG. 2B, the lower surface 102b of the lead 102 is formed at a height t1 above the lower surface 140b of the sealing resin 140. There are no particular limitations on the height t1, but it is, for example, 1 um or more and 10 um or less. The thickness t2 of the metal film 150 is 10 um or more and 50 um or less, and the lower surface of the metal film 150 protrudes slightly from the lower surface of the sealing resin 140. The thickness t2 of the metal film 150 may be changed as appropriate. The material of the metal film 150 may be any material that has good solder wettability, such as lead, bismuth, tin, copper, silver, palladium, or gold, or an alloy thereof.

[0028] As a result, the lower surface 102b of the lead 102 is formed at a position higher than the lower surface 140b of the sealing resin 140, and stress generated due to the difference in thermal expansion coefficient between the sealing resin 140 and the mounting substrate is not concentrated at the interface between the lower surface 102b of the lead 102 and the metal film 150. Therefore, this semiconductor device 100 can suppress the occurrence of cracks at the interface between the lead 102 and the metal film 150, and can ensure the reliability of the joint with the mounting substrate.

[0029] A method for manufacturing the semiconductor device 100 will now be described with reference to FIGS.

[0030] 3, a semiconductor chip 110 is fixed to the upper surface of a die pad 101 with a conductive adhesive 120. Then, a plurality of electrode pads (not shown) formed on the upper surface of the semiconductor chip 110 are electrically connected to the upper surfaces of the plurality of leads 102 with conductive wires 130. In this embodiment, the die pad 10 and the plurality of leads 102 are made of the same material, a copper alloy, and have an integrated lead frame structure.

[0031] 4, the lead frame is sandwiched between two molds (not shown), and sealing resin is injected into the molds and solidified to seal the lead frame. The lower surface of die pad 101 and lower surfaces 102b of leads 102 are exposed from sealing resin 140.

[0032] Thereafter, a first cutting is performed using a dicing device to form a step portion 102a of the lead 102 to a predetermined depth. The first cutting is performed to cut the depth t4 of the step portion 102a from the lower surface 102b of the lead 102 to a thickness of 5% to 80% of the thickness t3 of the lead 102.

[0033] Next, the lower surface 102b of the lead 102, the step portion 102a, and the lower surface of the die pad 101 are formed at a position higher than the lower surface of the sealing resin by etching using a chemical solution. During the first cutting, burrs of the copper alloy, which is the material of the lead 102, may occur on the step portion 102a and the lower surface 102b of the lead 102, and these burrs may cause short circuits between adjacent leads. Therefore, by using etching using a chemical solution, it is possible to remove these burrs and prevent short circuits between leads. Examples of the chemical solution include sulfuric acid / hydrogen peroxide mixture, and hydrochloric acid / hydrogen peroxide mixture.

[0034] Thereafter, a metal film 150 is formed on the lower surface 102b of the lead 102 exposed from the sealing resin 140, the step portion 102a, and the lower surface of the die pad 101 by electrolytic plating.

[0035] 5, a dicing machine is used to perform a second cutting step to cut predetermined positions of the leads 102 and the sealing resin 140 and separate them into individual pieces, thereby manufacturing the semiconductor device 100. At this time, the blade width of the dicing machine used in the second cutting step is narrower than the blade width used in the first cutting step. As a result, end faces 102s of the leads 102 are formed on the side surfaces of the sealing resin 140.

[0036] In this way, in the semiconductor device 100 of this embodiment, the lower surfaces of the leads 102 are formed at a position higher than the lower surface of the sealing resin, so that stress caused by differences in thermal expansion coefficients does not concentrate at the interface between the leads 102 and the metal film 150. Therefore, the semiconductor device 100 can suppress the occurrence of cracks at the interface between the leads 102 and the metal film 150, and can ensure the reliability of the joint with the mounting board even in a non-lead type package.

[0037] (Second embodiment) FIG. 6A is a schematic side view (perspective view) showing a semiconductor device according to a second embodiment of the present invention, and FIG. 6B is an enlarged view of part B in FIG. 6A.

[0038] 6A and 6B, a semiconductor device 200 according to the second embodiment of the present invention is similar to the first embodiment of the present invention, except that a chamfered portion 202r is formed at the corner between the lower surface 202b and the step portion 202a of a lead 202. Chamfering means removing a corner, and in the second embodiment, a rounding process is used to make the corner rounded, but one or more angled surfaces may be provided at the corner.

[0039] 6A and 6B, when the lead 202 is connected to the mounting board, stress concentration at the corner can be suppressed, and solder creeping from the lower surface 202b of the lead 202 to the step portion 202a can be improved.

[0040] Therefore, the semiconductor device 200 according to the second embodiment of the present invention can ensure the reliability of the joint with the mounting board even if it is a non-lead type package.

[0041] Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and includes designs within the scope of the present invention that do not deviate from the gist of the present invention.

[0042] For example, in this embodiment, the package of the semiconductor device is a DFN package, but this is not limited to this and other packages may be used. The semiconductor chip is mounted by being fixed to the upper surface of the die pad with a conductive adhesive or the like, but this is not limited to this and the chip may be mounted on a resin film. The die pad need not be present. Furthermore, while the embodiment uses conductive wires for electrical connection between the leads and the semiconductor chip, a flip-chip configuration may also be used. In this flip-chip configuration, the die pad does not exist, and bumps formed on the upper surface of the semiconductor chip may be used for electrical connection between the leads and the semiconductor chip.

[0043] Although the material of the lead frame is a copper alloy, it is not limited to this and other materials may be used. Although the method for forming the metal film is an electrolytic plating method, an electroless plating method may also be used. [Explanation of symbols]

[0044] 100, 200, 900 Semiconductor equipment 101, 901 die pad 102, 202, 902 leads 102a, 202a, 902a Stepped section 102b, 202b, 902b bottom surface (bottom surface of lead) 102s, 202s, 902s End face (Lead end face) 202r Chamfered part 103, 903 Hanging part 110, 910 semiconductor chips 120, 920 Conductive adhesive 130, 930 Conductive wire 140, 940 Sealing resin 140b, 940b Bottom surface (bottom surface of sealing resin) 150, 950 Metal film 970 solder 980 Mounting Board t1 Height (height of the bottom surface of the lead from the bottom surface of the sealing resin) t2 Metal film thickness t3 Lead thickness t4 Depth (depth of step from bottom of lead)

Claims

1. A semiconductor chip; a plurality of leads arranged at intervals around the semiconductor chip in a plan view and extending from the semiconductor chip; a sealing resin that is formed to expose at least the bottom surfaces and end surfaces of the leads; a metal film formed on the lower surface of the lead; A semiconductor device having The semiconductor device is characterized in that the lower surfaces of the leads are formed at a position higher than the lower surface of the sealing resin.

2. 2. The semiconductor device according to claim 1, wherein the lead has a step formed at a corner between the bottom surface and the end surface of the lead.

3. 3. The semiconductor device according to claim 2, wherein the lead has a chamfered portion formed at a corner between the lower surface of the lead and the step portion.

4. The semiconductor device according to claim 3 , wherein the chamfered portion is rounded.

5. 4. The semiconductor device according to claim 3, wherein the chamfered portion is formed of an inclined surface.

6. 6. The semiconductor device according to claim 2, wherein the height of the step is equal to or greater than half the thickness of the lead.

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