Semiconductor device

Abstract

To provide a semiconductor device having lead capable of securing junction reliability to a mounting substrate even in the case of a non-lead type package.SOLUTION: A semiconductor device 100 has: a semiconductor chip 110; plural leads 102 isolated from each other around the semiconductor chip 110 and extending from the semiconductor chip 110 in a plane view; and sealing resin 140 to form an outer shape so that at least lower and end faces of the plural leads 102 are respectively exposed. The lead 102 comprises: a lead body part 102b, which is positioned on the semiconductor chip 110 side, on which a first end face 102bs is formed in an extension direction, and which has a chamfering part 102br at a corner between the lower face and the first end face 102bs; and a lead outer end 102c which extends from the first end face 102bs, which is coplanar with the lead body part 102b on its upper face, which is thinner than the lead body part 102b, and on which a second end face 102cs is formed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art As electronic devices such as mobile phones and other mobile devices become more sophisticated, there is an increasing demand for smaller and thinner semiconductor devices used in such electronic devices.

[0003] A typical package for a semiconductor device molded from epoxy resin has a structure in which a semiconductor chip is mounted on a die pad, which is part of a lead frame, and is then covered with epoxy resin, which forms the outer shape. One form of small package with this structure is the non-leaded type DFN (Dual Flat Nonleaded) package.

[0004] DFN packages are generally manufactured by cutting a resin-encapsulated lead frame so that the underside of the leads is exposed using a dicing machine to separate the lead frames. As a result, DFN packages have a structure in which the lead end faces are exposed from the cut side of the encapsulating resin, and the lead end faces and the encapsulating resin are flush with each other.

[0005] As mentioned above, DFN packages are cut into individual pieces using a dicing machine, leaving the lead material exposed at the lead end surfaces. For this reason, when joining the leads to the mounting board using solder or other methods, it is difficult to form a sufficient fillet at the lead end surfaces if the lead material has low solder wettability. If the lead is joined to the mounting board only via the underside of the lead, which has a plated layer, the bonding area is reduced, which may reduce the bonding strength between the lead and the mounting board.

[0006] In order to prevent a decrease in the bonding strength between the lead and the mounting substrate, for example, the invention described in Patent Document 1 describes a semiconductor device in which a plating layer is formed in recesses formed at the corners of the lower surface and end surface of the lead. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-219520 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one aspect of the present invention is to provide a semiconductor device having leads that can ensure reliable bonding with a mounting substrate even in a non-lead type package. [Means for solving the problem]

[0009] The semiconductor device according to one embodiment of the present invention comprises: A semiconductor chip; a plurality of leads arranged at intervals around the semiconductor chip in a plan view and extending from the semiconductor chip; a sealing resin that is formed to expose at least the bottom surfaces and end surfaces of the leads; A semiconductor device having The lead a lead body portion located on the semiconductor chip side, having a first end face formed in the extension direction, and having a chamfered portion at a corner between a lower surface and the first end face; a lead outer end portion having a second end surface extending from the first end surface, the upper surface of which is flush with the lead body portion, the thickness of which is thinner than the lead body portion, and the second end surface of which is exposed from a side surface of the sealing resin; Equipped with The lower surface of the lead body, the first end surface, the chamfered portion, and the lower surface of the lead outer end are covered with a metal film. [Effects of the Invention]

[0010] According to one aspect of the present invention, it is possible to provide a semiconductor device having leads that can ensure reliable bonding with a mounting substrate even in a non-lead type package. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic top view (perspective view) of a semiconductor device according to a first embodiment of the present invention. [Figure 2A] FIG. 2A is a schematic side view (perspective view) of the semiconductor device shown in FIG. [Figure 2B] FIG. 2B is an enlarged view of part A in FIG. 2A. [Figure 3] FIG. 3 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. [Figure 4] 4A to 4C are diagrams showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention, following FIG. [Figure 5] 5A to 5C are diagrams showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention, following FIG. [Figure 6A] FIG. 6A is a schematic side view (perspective view) showing a semiconductor device according to a modified example of the first embodiment of the present invention. [Figure 6B] FIG. 6B is an enlarged view of part B in FIG. 6A. [Figure 7A] FIG. 7A is a schematic side view (perspective view) showing a semiconductor device according to a second embodiment of the present invention. [Figure 7B] FIG. 7B is an enlarged view of part C in FIG. 7A. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and duplicated explanations may be omitted.

[0013] Furthermore, the X-axis, Y-axis, and Z-axis shown in the drawings are perpendicular to one another. The Z-axis direction is sometimes referred to as the "height direction" or "thickness direction." The +Z-axis direction is sometimes referred to as the "upper side," and the -Z-axis direction is sometimes referred to as the "lower side." The surface of each component facing the +Z direction is sometimes referred to as the "front surface" or "top surface," and the surface facing the -Z direction is sometimes referred to as the "rear surface" or "bottom surface." A "planar view" refers to viewing each component from the +Z direction toward the -Z direction. A "side view" refers to viewing each component through the +Y direction toward the -Y direction.

[0014] Furthermore, the drawings are schematic, and the ratios of width, depth, and thickness are not as shown. The number, position, shape, structure, size, etc. of each member are not limited to the embodiments shown below, and may be any number, position, shape, structure, size, etc. that are preferable for implementing the present invention.

[0015] (First embodiment) 1 is a schematic top view (perspective view) of a semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, a semiconductor device 100 according to the first embodiment of the present invention includes a semiconductor chip 110, a plurality of leads 102, and a sealing resin 140.

[0016] The semiconductor chip 110 is a semiconductor chip for making the semiconductor device 100 function, and is mounted on the upper surface of the die pad 101. In a plan view, the multiple leads 102 are arranged at a fixed distance on two opposing sides of the die pad 101 in the +X direction and the -X direction. The multiple leads 102 each have a lead tip portion 102a, a lead main body portion 102b, and a lead outer end portion 102c.

[0017] A plurality of electrode pads (not shown) formed on the upper surface of the semiconductor chip 110 are electrically connected to the upper surfaces of the lead tip portions 102a and lead body portions 102b of the plurality of leads 102 by conductive wires 130. Therefore, the upper surfaces of the lead tip portions 102a and lead body portions 102b are formed into the same smooth surface. This ensures a wide area on the upper surface of the lead 102 for making a second bond of the conductive wire 130. This ensures a sufficient bonding area for wire bonding and prevents a decrease in connection strength. The conductive wires 130 are, for example, gold wires, copper wires, etc.

[0018] The suspension portion 103 extends from two sides of the die pad 101 in the +Y direction and the -Y direction. In this embodiment, the die pad 101, the multiple leads 102, and the suspension portion 103 are made of the same copper alloy material, and have an integrated lead frame structure. Figure 1 shows one combination that forms one semiconductor device. Finally, they are separated into individual semiconductor devices.

[0019] 2A is a schematic side view (perspective view) of the semiconductor device shown in FIG. 1. As shown in FIG. 2A, a semiconductor chip 110 is mounted on the upper surface of a die pad 101 with a conductive adhesive 120. A metal film 150 is formed on the lower surface of the die pad 101, and is exposed from the sealing resin 140 in order to improve the heat dissipation of the semiconductor chip 110. The periphery of the lower surface of the die pad 101 is formed to be thin. This results in a structure in which the sealing resin 140 penetrates below the periphery of the die pad 101, making it possible to prevent the die pad 101 from falling off the sealing resin 140.

[0020] Fig. 2B is an enlarged view of part A in Fig. 2A. As shown in Fig. 2B, the leads 102 each include a lead tip portion 102a, a lead body portion 102b, and a lead outer end portion 102c.

[0021] The upper surface of the lead tip 102a is flush with the upper surface of the lead body 102b, and the thickness of the lead tip 102a is formed thinner than the thickness of the lead body 102b. This allows the sealing resin 140 to penetrate into the lower surface of the lead tip 102a, preventing the lead 102 from falling off the sealing resin 140.

[0022] The lead body 102b has a chamfered portion 102br formed at the corner between the bottom surface and the first end surface 102bs in the extension direction. Chamfering means removing the corner, and in the first embodiment, the corner is rounded, but one or more angled surfaces may be provided at the corner, as in the modified example described below.

[0023] In conventional DFN packages, where recesses are formed on the bottom and end surfaces of the leads, corners are typically formed between the bottom surfaces of the leads and the recesses. In such a structure, when reliability tests are conducted that repeatedly change between high and low temperatures, stress generated by differences in the thermal expansion coefficients of the leads, the encapsulating resin, and the mounting substrate is concentrated at the corners. This stress can cause cracks in the solder at the joints between the corners and the mounting substrate. Therefore, compared to the leads of the semiconductor device in the above-mentioned conventional DFN package, the semiconductor device 100 can suppress stress concentration.

[0024] The second end surface 102cs of the lead outer end 102c is exposed from the side surface of the sealing resin. The top surface of the lead outer end 102c is flush with the top surface of the lead body 102b, and the thickness t2 of the lead outer end 102c is formed to be thinner than the thickness t1 of the lead body 102b. By making the thickness t2 of the lead outer end 102c equal to or less than half the thickness t1 of the lead body 102b, it becomes easy to form a sufficient fillet on the lead end surface.

[0025] The metal film 150 is formed on the underside of the die pad 101, and is continuously formed on the underside of the lead body portion 102b of each of the multiple leads 102, the first end face 102bs in the extension direction, the chamfered portion 102br, and the underside of the lead outer end portion 102c. The metal film 150 formed on each of the multiple leads 102 is exposed from the sealing resin and is used as an external terminal of the semiconductor device. The metal film 150 on the chamfered portion 102br maintains a rounded shape.

[0026] The thickness t3 of the metal film 150 is 10 μm or more and 50 μm or less, and the metal film 150 slightly protrudes from the sealing resin 140. The thickness of the metal film 150 may be changed as appropriate.

[0027] The material of the metal film 150 may be any material that has good solder wettability, such as lead, bismuth, tin, copper, silver, palladium, or gold, or an alloy thereof.

[0028] As a result, compared to a lead having no chamfered portion 102br, in this semiconductor device 100, solder creeps up more easily, and it becomes easier to form a sufficient fillet on the lead end face.

[0029] A method for manufacturing the semiconductor device 100 will now be described with reference to FIGS.

[0030] 3, a semiconductor chip 110 is fixed to the upper surface of a die pad 101 with a conductive adhesive 120. Then, a plurality of electrode pads (not shown) formed on the upper surface of the semiconductor chip 110 are electrically connected to the upper surfaces of the plurality of leads 102 with conductive wires 130. In this embodiment, the die pad 10 and the plurality of leads 102 are made of the same material, a copper alloy, and have an integrated lead frame structure. In this state, the outer lead ends 102c of the plurality of leads 102 have the same thickness as the lead main body portions 102b.

[0031] 4, the lead frame is sandwiched between two molds (not shown), and sealing resin is injected into the molds and solidified to seal the lead frame. The lower surface of the die pad 101, the lower surface of the lead main body 102b, and the lower surface of the lead outer end 102c are exposed from the sealing resin 140.

[0032] Then, the lead outer end 102c is formed to a predetermined thickness by a first cutting using a dicing device. The first cutting is performed to cut the lead outer end 102c to a thickness that is 5% to 80% of the thickness of the lead body 102b. In this state, the first end surface 102bs of the lead body 102b is formed and exposed from the sealing resin 140.

[0033] Next, a chamfered portion 102br is formed at the corner between the lower surface of the lead body 102b and the first end surface 102bs by etching using a chemical solution. At this time, the lower surface of the lead body 102b may be recessed in the +Z direction from the lower surface of the sealing resin 140.

[0034] During the first cutting, burrs of the copper alloy, which is the material of the lead 102, may occur on the first end surface 102bs of the lead body 102b and on the underside of the lead body 102b, and these burrs may cause short circuits between adjacent leads. Therefore, by using etching with a chemical solution to form the chamfered portion 102br, it is possible to remove these burrs and prevent short circuits between the leads. Examples of the chemical solution include sulfuric acid / hydrogen peroxide mixture and hydrochloric acid / hydrogen peroxide mixture.

[0035] Thereafter, a metal film 150 is formed by electrolytic plating on the lower surface of the die pad 101 exposed from the sealing resin 140, the lower surface of the lead body portion 102b, the first end surface 102bs, and the lower surface of the lead outer end portion 102c.

[0036] 5, a second cutting is performed using a dicing machine to cut predetermined positions of the lead outer end 102c and the sealing resin 140 and separate the semiconductor device 100. At this time, the blade width of the dicing machine used in the second cutting is narrower than the blade width used in the first cutting. As a result, the lead outer end 102c of each semiconductor device 100 is formed, and the second end face 102cs of the lead outer end 102c is formed on the side surface of the sealing resin 140.

[0037] As described above, in the semiconductor device 100 of this embodiment, the lead body 102b has a chamfered portion 102br formed at the corner between the lower surface and the first end surface 102bs in the extension direction, and a metal film 150 with good solder wettability is formed on the chamfered portion 102br.

[0038] As a result, the semiconductor device 100 does not experience stress concentration at the corners due to differences in thermal expansion coefficients, and the solder easily creeps up, ensuring reliable bonding with the mounting board even in a non-lead type package.

[0039] (Modification of the first embodiment) FIG. 6A is a schematic side view (perspective view) showing a semiconductor device according to a modified example of the first embodiment of the present invention, and FIG. 6B is an enlarged view of part B in FIG. 6A.

[0040] As shown in Figures 6A and 6B, the semiconductor device 200 according to the modification of the first embodiment of the present invention is similar to the first embodiment of the present invention, except that the rounded shape of the chamfered portion 102br is configured with three inclined surfaces. The configurations shown in Figures 6A and 6B also reduce the likelihood of cracks occurring in the solder at the joint between the chamfered portion and the mounting board when connecting the leads to the mounting board, and also improve the rate at which the solder creeps up from the underside of the lead main body 202b to the underside of the lead outer end 202c. Therefore, the modification of the first embodiment of the present invention can ensure reliable bonding with the mounting board even in a non-lead type package.

[0041] (Second embodiment) FIG. 7A is a schematic side view (perspective view) showing a semiconductor device according to a second embodiment of the present invention, and FIG. 7B is an enlarged view of part C in FIG. 7A.

[0042] 7A and 7B, the lower surface of the lead body 302b is formed at a height t4 above the lower surface of the sealing resin 140. There are no particular restrictions on the height t4, but it is, for example, between 1 μm and 10 μm. The rest is the same as that of the semiconductor device 100.

[0043] In DFN packages, the bottom surfaces of the leads and the encapsulating resin are generally flush with each other. If a metal film is formed on the bottom surfaces of the leads in such a structure, stress caused by differences in the thermal expansion coefficients of the leads, encapsulating resin, and mounting board will concentrate at the interface between the leads and the metal film. This stress may cause cracks at the interface between the leads and the metal film.

[0044] The semiconductor device 300 in the second embodiment has a structure in which the lower surface 102b of the lead body 302b is formed at a position higher than the lower surface 140b of the sealing resin 140. This prevents stress caused by differences in the thermal expansion coefficients of the leads, the sealing resin, and the mounting substrate from concentrating at the interface between the lead body 302b and the metal film 150, thereby preventing cracks from occurring at the interface between the lead body 302b and the metal film 150. Therefore, the semiconductor device 300 can ensure bonding reliability with the mounting substrate even in a non-lead type package.

[0045] Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and includes designs within the scope of the present invention that do not deviate from the gist of the present invention.

[0046] For example, in this embodiment, the package of the semiconductor device is a DFN package, but this is not limited to this and other packages may be used. The semiconductor chip is mounted by being fixed to the upper surface of the die pad with a conductive adhesive or the like, but this is not limited to this and the chip may be mounted on a resin film. The die pad need not be present. Furthermore, while the embodiment uses conductive wires for electrical connection between the leads and the semiconductor chip, a flip-chip configuration may also be used. In this flip-chip configuration, the die pad does not exist, and bumps formed on the upper surface of the semiconductor chip may be used for electrical connection between the leads and the semiconductor chip.

[0047] Furthermore, although the material of the lead frame is a copper alloy, it is not limited to this, and other materials may be used. The method for forming the metal film is electrolytic plating, but electroless plating may also be used. In the modified example, the chamfered portion is configured with three surfaces, but it is not limited to this, and it may be configured with one or more surfaces. [Explanation of symbols]

[0048] 100, 200, 300 Semiconductor equipment 101 die pad 102, 202, 302 leads 102a, 202a, 302a Lead tip 102b, 202b, 302b Lead body 102bs, 202bs 1st end surface 102br, 202br chamfered part 102c, 202c, 302c Outer end of lead 102cs, 202cs 2nd end surface 103 Hanging part 110 Semiconductor Chips 120 Conductive adhesive 130 Conductive Wire 140 Sealing resin 150 Metal Film t1 Lead body thickness t2 Thickness of outer lead end t3 Metal film thickness t4 Height (height of the bottom surface of the lead body from the bottom surface of the sealing resin)

Claims

1. A semiconductor chip; a plurality of leads arranged at intervals around the semiconductor chip in a plan view and extending from the semiconductor chip; a sealing resin that is formed to expose at least the bottom surfaces and end surfaces of the leads; A semiconductor device having The lead a lead body portion located on the semiconductor chip side, having a first end face formed in an extension direction, and having a chamfered portion at a corner between a lower surface and the first end face; a lead outer end portion extending from the first end surface, having an upper surface flush with the lead body portion and a thickness thinner than that of the lead body portion, and having a second end surface formed thereon; Equipped with The semiconductor device is characterized in that the lower surface of the lead body, the first end surface, the chamfered portion, and the lower surface of the lead outer end are covered with a metal film.

2. The semiconductor device according to claim 1 , wherein the chamfered portion is rounded.

3. The semiconductor device according to claim 1 , wherein the chamfered portion is formed of an inclined surface.

4. 2. The semiconductor device according to claim 1, wherein the thickness of the outer lead end is equal to or less than half the thickness of the lead body.

5. 5. The semiconductor device according to claim 1, wherein the lower surface of the lead body is formed at a position higher than the lower surface of the sealing resin.

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