Display device

Abstract

To provide a display device capable of improving overcurrent.SOLUTION: A display device comprises: a display panel including a plurality of data lines and pixels connected to the data lines; a first data driving portion including a plurality of pieces of first data IC connected to one ends of the plurality of data lines; a second data driving portion including a plurality of pieces of second data IC connected to the other ends of the plurality of data lines; a timing control portion that provides an input first lock signal and an input second lock signal to the first data driving portion and the second data driving portion, respectively; and a comparison circuit that receives an output first lock signal and an output second lock signal generated from the first data driving portion and the second data driving portion according to the input first lock signal and the input second lock signal, respectively, compares, and provides a synchronized synchronous lock signal to the timing control portion. The timing control portion transmits image data to the first data driving portion and the second data driving portion in a lock state of the synchronous lock signal. The first data driving portion and the second data driving portion output data voltage.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] 2. Description of the Related Art As the information society advances, various demands for display devices for displaying images are increasing, and recently, various flat display devices such as organic light emitting display devices and liquid crystal display devices have been utilized.

[0003] Recently, organic light emitting display devices have been driven in a double bank structure in which data drivers are arranged at both ends of a data line. In the double bank structure, the same lock signal is input simultaneously to a front data driver and a rear data driver, and in response, each of the front data driver and the rear data driver generates and outputs an output lock signal.

[0004] However, due to differences in electrical characteristics between the data driver at the front stage and the data driver at the rear stage, the timing of the output clock signals may not match, resulting in asynchronous operation.

[0005] In this case, the output timing of the data driver at the front stage and the data driver at the rear stage are not synchronized, resulting in asynchronous operation, which may cause a difference in the data voltage between the upper and lower ends of the channel, resulting in overcurrent. This overcurrent may also cause the data IC to overheat or burn. Summary of the Invention [Problem to be solved by the invention]

[0006] The present specification aims to provide a solution that can improve the problem of overcurrent occurring between the front and rear stages of a channel when the output clock signals of the front and rear stages become asynchronous in a data driver with a double bank structure. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, the present invention provides a display device including: a display panel including a plurality of data lines and pixels connected to the data lines; a first data driver including a plurality of first data ICs connected to one ends of the plurality of data lines; a second data driver including a plurality of second data ICs connected to the other ends of the plurality of data lines; a timing controller for providing an input first lock signal and an input second lock signal to the first data driver and the second data driver, respectively; and a comparison circuit for receiving, comparing, and synchronizing an output first lock signal and an output second lock signal generated by the first data driver and the second data driver, respectively, according to the input first lock signal and the input second lock signal, and providing a synchronized synchronous lock signal to the timing controller, wherein the timing controller transmits image data to the first data driver and the second data driver in a locked state of the synchronous lock signal, and the first data driver and the second data driver output data voltages.

[0008] During a period in which the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, the synchronous lock signal has an unlock state, and in the unlock state of the synchronous lock signal, the timing control unit turns off transmission of the video data, and outputs of the first data driver and the second data driver may be turned off.

[0009] During an interval in which at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronous lock signal has an unlocked state, and in the unlocked state of the synchronous lock signal, the timing control unit turns off transmission of the video data, and outputs of the first data driver and the second data driver may be turned off.

[0010] In a section where the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, one of the output first lock signal and the output second lock signal may be in a locked state and the other may be in an unlocked state.

[0011] At least one of the output first lock signal and the output second lock signal may have an abnormal waveform in a lock failure condition.

[0012] When the input first lock signal is input, the plurality of first data ICs operate sequentially and output lock signals, the lock signal output from the first data IC is input to the next first data IC, and the lock signal output from the last first data IC may be the output first lock signal; when the input second lock signal is input, the plurality of second data ICs operate sequentially and output lock signals, the lock signal output from the second data IC is input to the next second data IC, and the lock signal output from the last second data IC may be the output second lock signal.

[0013] The first data driver may include a first source board to which the plurality of first data ICs are connected, and the second data driver may include a second source board to which the plurality of second data ICs are connected, the first source board including a first lock signal wiring for transmitting a lock signal input and output to the plurality of first data ICs, and the second source board including a second lock signal wiring for transmitting a lock signal input and output to the plurality of second data ICs.

[0014] The pixels may include light emitting diodes.

[0015] In another aspect, the present invention provides a display device including: a display panel including a plurality of data lines and pixels connected to the data lines; a first data driver including a plurality of first data ICs connected to one ends of the plurality of data lines; a second data driver including a plurality of second data ICs connected to the other ends of the plurality of data lines; a timing controller providing an input first lock signal and an input second lock signal to the first data driver and the second data driver, respectively; and a comparator circuit receiving an output first lock signal and an output second lock signal generated by the first data driver and the second data driver, respectively, in accordance with the input first lock signal and the input second lock signal, comparing the output first lock signal and the output second lock signal, and providing a synchronized synchronous lock signal to the timing controller, wherein data voltage outputs of the first data driver and the second data driver are adjusted in accordance with the synchronous lock signal.

[0016] In a locked state of the synchronous lock signal, the first and second data drivers may output synchronized data voltages.

[0017] During the period when the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, the synchronous lock signal has an unlock state, and in the unlock state of the synchronous lock signal, the outputs of the first data driver and the second data driver may be turned off.

[0018] During an interval in which at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronous lock signal has an unlocked state, and in the unlocked state of the synchronous lock signal, the outputs of the first data driver and the second data driver may be turned off.

[0019] In a section where the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, one of the output first lock signal and the output second lock signal may be in a locked state and the other may be in an unlocked state.

[0020] At least one of the output first lock signal and the output second lock signal may have an abnormal waveform in a lock failure condition.

[0021] The first data driver may include a first source board to which the plurality of first data ICs are connected, and the second data driver may include a second source board to which the plurality of second data ICs are connected, the first source board including a first lock signal wiring for transmitting a lock signal input and output to the plurality of first data ICs, and the second source board including a second lock signal wiring for transmitting a lock signal input and output to the plurality of second data ICs.

[0022] The pixels may include light emitting diodes.

[0023] The data voltages output from the first data driver and the second data driver may be the same. [Effects of the Invention]

[0024] In the present invention, a first lock signal and a second lock signal are input to the front and rear data drivers of a double bank structure, respectively, and the first lock signal and the second lock signal output from the front and rear data drivers are compared by a comparator to generate a synchronized synchronous lock signal. The synchronous lock signal is then provided to a timing controller, and the timing controller adjusts the transmission timing of the video data according to the synchronous lock signal, thereby synchronizing the output of the data voltages from the front and rear data drivers.

[0025] This makes it possible to improve the phenomenon in which a potential difference occurs in the output voltage between the upper and lower ends of the channel in an asynchronous section or a section where locking has failed, causing an overcurrent.

[0026] As a result, it is possible to prevent overheating and burning of data ICs in the data drivers at the front and rear stages due to overcurrent.Furthermore, it is possible to prevent image quality defects such as block dim when the asynchronous interval is long. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention. [Figure 2] FIG. 1 is a circuit diagram illustrating an example of a pixel according to an embodiment of the present invention. [Figure 3] 1 is a diagram illustrating a schematic configuration of a gate driver of a display device according to an embodiment of the present invention. [Figure 4] 4 is a timing diagram illustrating an example of a driving signal output from a gate driver according to an embodiment of the present invention; FIG. [Figure 5] 1 is a cross-sectional view schematically illustrating an example of a cross-sectional structure of a display panel according to an embodiment of the present invention. [Figure 6] 2 is a diagram illustrating a timing control unit, a data driving unit, and a comparison circuit of a display device according to an embodiment of the present invention; [Figure 7] 3 is a timing diagram illustrating an input lock signal, an output lock signal, a sync lock signal, and a data voltage output according to an embodiment of the present invention; [Figure 8] 10A and 10B are timing diagrams illustrating examples of input lock signals, output lock signals, synchronized lock signals, and data voltage outputs when asynchronization and lock failure of the output lock signal occurs in an embodiment of the present invention. [Figure 9] 10 is a timing diagram illustrating an example of an input lock signal, an output lock signal, and a data voltage output when asynchronous output lock signal and lock failure occur in a comparative example of the present invention. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0028] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed description of the embodiments in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. However, the embodiments are provided so that the disclosure of the present invention will be complete and so that those skilled in the art will be able to fully understand the scope of the invention, and the present invention is defined by the scope of the claims.

[0029] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely examples and are not intended to limit the present invention. The same reference numerals refer to the same components throughout the specification.

[0030] Furthermore, when describing the present invention, if a detailed description of related prior art is deemed to obscure the gist of the present invention, the detailed description will be omitted. When words such as "comprise," "include," "have," "have," and "become" are used in this specification, other parts may be added unless "only" is also used. Furthermore, when a component is described in the singular, it may be interpreted as being plural unless otherwise explicitly stated.

[0031] Furthermore, when interpreting elements, a margin of error is included even if not explicitly stated.

[0032] For example, when describing the positional relationship between two elements using "adjacent" or "adjacent," unless "directly" or "directly" is used, one or more other elements may be located between the two elements.

[0033] Furthermore, when describing a temporal relationship, for example, when describing a temporal precedence / subsequence relationship using terms such as "after," "following," "next," or "before," non-sequential cases are included unless the term "directly" or "immediately" is used. Furthermore, terms such as "first" and "second" are used to distinguish between elements, but elements are not limited to such terms. Therefore, the first element referred to below may also be the second element within the technical spirit of the present invention.

[0034] The features of the various embodiments of the present invention may be partially or entirely combined or combined, and various technical interlocking and driving mechanisms may be possible. In addition, the various embodiments may be implemented independently or in conjunction with each other.

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Meanwhile, in the following embodiments, the same or similar components are denoted by the same or similar reference numerals, and detailed description thereof may be omitted.

[0036] Fig. 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention, Fig. 2 is a circuit diagram schematically illustrating an example of a pixel according to an embodiment of the present invention, Fig. 3 is a diagram schematically illustrating a configuration of a gate driver of a display device according to an embodiment of the present invention, and Fig. 4 is a timing diagram schematically illustrating an example of a driving signal output from the gate driver according to an embodiment of the present invention.

[0037] Before going into a detailed description, the display device 10 according to this embodiment includes a light-emitting display device having a light-emitting diode, and can include any display device to which data driving of a double bank structure is applied.

[0038] For convenience of explanation, the display device 10 in this embodiment will be described as an organic light-emitting display device.

[0039] 1 to 4, a display device 10 of this embodiment may include a display panel 100 and a driving circuit unit for driving the display panel 100.

[0040] Here, the driving circuit unit may include, for example, a gate driver (or gate driving circuit) 210, a data driver (or data driving circuit) 220, and a timing control unit (or timing control circuit) 240. The driving circuit unit may further include a power supply unit (or power circuit) 280 that supplies power required to drive the display panel 100, the gate driver 210, the data driver 220, and the timing control unit 240.

[0041] Furthermore, the driving circuit unit may include a comparison circuit 250 that compares the lock signals output from the double-bank data driver 220, i.e., the output lock signals (LCK_out: LCK_out1, LCK_out2), synchronizes them, generates a synchronized lock signal LCKS, and provides the synchronized lock signal LCKS to the timing controller 240. Here, the potential of the lock signal may be, for example, lower than the gate high voltages (VGH, VEH) and lower than the source driving voltage (SVDD in FIG. 6), but is not limited thereto.

[0042] The display panel 100 can include a display area AA that displays an image, and a non-display area NA that is disposed outside the display area AA (or that surrounds the display area AA).

[0043] In the display area AA, a plurality of pixels P can be arranged in a matrix along a plurality of horizontal lines (or row lines) and a plurality of vertical lines (or column lines).

[0044] Here, the plurality of pixels P may be of different colors, for example, red pixels, green pixels, and blue pixels that respectively display red, green, and blue, but are not limited thereto.

[0045] In the display panel 100, any signal wiring for transmitting a drive signal for driving the pixel P can be formed on the substrate.

[0046] For example, a plurality of data lines DL for transmitting data signals (or data voltages) of video signals may extend along the vertical direction and be connected to pixels P on corresponding vertical lines.

[0047] Furthermore, gate lines GL that transmit gate signals (or gate voltages) may extend along the horizontal direction and be connected to pixels P on a corresponding horizontal line.

[0048] In this embodiment, a plurality of gate signals, such as the first scan signal SC1 to the fourth scan signal SC4 and the light emission control signal EM, can be used to drive each pixel P. Therefore, a plurality of gate lines GL can be used to transmit each of the plurality of gate signals, such as the first scan line SCL1 to the fourth scan line SCL4 and the light emission control line EML.

[0049] In this manner, the pixels P can be defined by a plurality of data lines DL and gate lines GL that intersect with each other.

[0050] Each pixel P is a light-emitting element and can include a light-emitting diode OD, a plurality of transistors for driving the light-emitting diode OD, and at least one capacitor.

[0051] On the other hand, in this embodiment, for convenience of explanation, an 8T1C structure in which the pixel P is provided with eight transistors T1 to T7 and DT, and one capacitor Cst, as shown in FIG. 2, is taken as an example.

[0052] Referring to FIG. 2, a pixel P may include a plurality of switching transistors, ie, a first transistor T1 to a seventh transistor T7, a driving transistor DT, a storage capacitor Cst, and a light emitting diode OD.

[0053] Each of the first transistor T1 to the seventh transistor T7 and the driving transistor DT may include a first electrode, a second electrode, and a gate electrode, one of which may be a source electrode and the other of which may be a drain electrode.

[0054] Each of the first transistor T1 to the seventh transistor T7 and the driving transistor DT may be a P-type transistor or an N-type transistor. Meanwhile, in FIG. 2, the second transistor T2 to the sixth transistor T6 are P-type transistors, the first transistor T1 and the seventh transistor T7 are N-type, and the driving transistor DT is a P-type transistor, but this is not limiting. For example, the driving transistor DT may be an N-type transistor.

[0055] The first through seventh transistors T1 through T7 and the driving transistor DT may include semiconductor layers of the same material or different materials. For example, some of the first through seventh transistors T1 through T7 and the driving transistor DT may include one of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, and other parts of the first through seventh transistors T1 through T7 and the driving transistor DT may include one of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, or another semiconductor layer.

[0056] On the other hand, oxide semiconductors have good off-current characteristics and can have characteristics suitable for switching transistors, so at least one of the first transistor T1 to the seventh transistor T7 can include an oxide semiconductor layer. Furthermore, polycrystalline silicon has excellent mobility, so the driving transistor DT can include a polycrystalline silicon layer. The first transistor T1 to the seventh transistor T7 and the driving transistor DT can also be configured in other forms. For example, the driving transistor DT can include an oxide semiconductor layer.

[0057] On the other hand, in this embodiment, a case is taken as an example in which the first transistor T1 and the seventh transistor T7 include oxide semiconductor layers, and the other transistors T2 to T6 and DT include polycrystalline silicon layers.

[0058] The gate signals provided to the nth horizontal line (more specifically, the odd-numbered horizontal line or the even-numbered horizontal line constituting the nth horizontal line) in FIG. 2 are provided from the corresponding nth stage of the gate driver 210. For example, four scan signals, i.e., first to fourth scan signals SC1 to SC4: SC1(n) to SC4(n), and two light emission control signals, i.e., first and second light emission control signals EM: EM1(n), EM2(n), may be provided. In this case, the display area AA may be provided with first to fourth scan lines SCL1 to SCL4 and first and second light emission control lines EML1 and EML2, which are connected to the nth stage and transmit the first to fourth scan signals SC1(n) to SC4(n) and the first and second light emission control signals EM1(n), EM2(n) to the pixels P. Alternatively, the gate driver 210 may be configured to provide one light emission control signal instead of two light emission control signals EM1(n), EM2(n).

[0059] The first transistor T1 can function as a sampling transistor, the second transistor T2 as a data supply transistor, the third and fourth transistors T3 and T4 as light-emitting control transistors, the fifth transistor T5 as a bias transistor, the sixth transistor T6 as a reset transistor (or a first initialization transistor), and the seventh transistor T7 as an initialization transistor (or a second initialization transistor).

[0060] The light emitting diode OD may include an anode and a cathode, the anode of the light emitting diode OD being connected to the fifth node N5, and the cathode being able to receive the low potential driving voltage EVSS.

[0061] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current to the light emitting diode OD based on the voltage of the first node N1 (i.e., the data voltage Vdata stored in the storage capacitor Cst).

[0062] The first transistor T1 includes a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode receiving the first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1, and a data voltage Vdata can be applied (or written or sampled) to the gate electrode.

[0063] The storage capacitor Cst may be connected between the first node N1 and the fourth node N4, and may store or hold the high potential driving voltage EVDD.

[0064] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) to transmit the data voltage Vdata to the second node N2.

[0065] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) are connected between the high-potential drive voltage EVDD and the light-emitting diode OD, and can form a path through which the drive current generated by the drive transistor DT travels.

[0066] The third transistor T3 may include a first electrode connected to the fourth node N4 and receiving a high-potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving a first light-emitting control signal EM1(n).

[0067] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode of the light-emitting diode OD), and a gate electrode receiving a second light-emitting control signal EM2(n).

[0068] The third and fourth transistors T3 and T4 are turned on in response to the corresponding first and second light-emitting control signals EM1(n) and EM2(n), and a driving current is provided to the light-emitting diode OD, so that the light-emitting diode OD can emit light at a brightness corresponding to the driving current.

[0069] The fifth transistor T5 may include a first electrode connected to a bias voltage line VobsL that transmits a bias voltage Vobs, a second electrode connected to a second node N2, and a gate electrode that receives a third scan signal SC3(n).

[0070] The sixth transistor T6 may include a first electrode connected to a reset voltage line (or a first initialization voltage line) VarL that transmits an anode reset voltage (or a first initialization voltage) Var, a second electrode connected to a fifth node N5, and a gate electrode that receives a third scan signal SC3(n).

[0071] The fifth and sixth transistors T5 and T6 may be turned on in response to the third scan signal SC3(n), and the bias voltage Vobs may be applied to the second node N2 and the anode reset voltage Var may be applied to the fifth node N5 (i.e., the anode of the light emitting diode OD).

[0072] The seventh transistor T7 may include a first electrode connected to an initialization voltage line ViniL that transmits an initialization voltage Vini, a second electrode connected to a first node N1, and a gate electrode that receives a fourth scan signal SC4(n).

[0073] The seventh transistor T7 is turned on in response to the fourth scan signal SC4(n) to apply an initialization voltage Vini to initialize the gate electrode of the drive transistor DT. The high-potential drive voltage EVDD applied to the storage capacitor Cst can cause unnecessary charges to remain on the gate electrode of the drive transistor DT. Therefore, applying the initialization voltage Vini to the gate electrode of the drive transistor DT via the seventh transistor T7 can initialize the remaining charges.

[0074] The 8T1C structure of the pixel P described above is an example, and the pixel P of this embodiment may have other structures.

[0075] 1, the timing controller 240 processes image data Do input from the host system to suit the size and resolution of the display panel 100 and supplies the processed data to the data driver 220. The timing controller 240 generates gate control signals GCS and data control signals DCS using externally input synchronization signals, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal HSY, and a vertical synchronization signal VSY. The generated gate control signals GCS and data control signals DCS are supplied to the gate driver 210 and the data driver 220, respectively, to control the gate driver 210 and the data driver 220.

[0076] The timing control unit 240 may be configured in combination with various processors, such as a microprocessor, a mobile processor, or an application processor, depending on the device in which it is implemented.

[0077] On the other hand, the host system may be, for example, a drive system that drives an electronic device that employs the display device 10. Such an electronic device may be, for example, any one of a TV (television) navigation system, a monitor, a mobile device, and a wearable device.

[0078] The gate driver 210 receives a gate control signal GCS from the timing controller 240, generates gate signals, and sequentially applies the gate signals to the gate lines GL. For example, the gate signals may be sequentially output from the previous stage to the next stage in the vertical direction.

[0079] The gate driver 210 may be disposed on at least one side of the display area AA, for example. In this embodiment, the gate driver 210 is configured to include a first gate driver 211 and a second gate driver 212 disposed on both sides of the display area AA, for example, on the left and right sides.

[0080] The gate driver 210 may have, for example, a GIP (gate-in-panel) structure and may be formed directly in the non-display area NA on the substrate of the display panel 100. In this case, the gate driver 210 may be formed during the process of forming the elements of the display panel 100.

[0081] The gate driver 210 of the GIP structure may include, for example, a first scan drive circuit that sequentially outputs first scan signals SC1, a second scan drive circuit that sequentially outputs second scan signals SC2, a third scan drive circuit that sequentially outputs third scan signals SC3, a fourth scan drive circuit that sequentially outputs fourth scan signals SC4, a first light-emitting drive circuit that sequentially outputs first light-emitting control signals EM1, and a second light-emitting drive circuit that sequentially outputs second light-emitting control signals EM2.

[0082] Each of the first to fourth scan drive circuits and the first and second light emission drive circuits can be configured with a shift register including a plurality of stages that output corresponding signals.

[0083] The gate driver 210 will be described with reference to Fig. 3. Fig. 3 shows a portion of the gate driver 210, and for convenience of explanation, shows the configuration of the portion of the gate driver 210 that drives the nth horizontal line consisting of the nth odd horizontal line (or the 2n-1th horizontal line) and the nth even horizontal line (or the 2nth horizontal line) in the display area AA.

[0084] The first gate driver 211 of the gate driver 210 may be provided with, for example, a first scan stage SSC1(n), a third scan stage SSC3(n), and a fourth scan stage SSC4(n) that respectively constitute the first scan drive circuit, the third scan drive circuit, and the fourth scan drive circuit; a first light-emitting stage SEM1(n) and a second light-emitting stage SEM2(n) that respectively constitute the first light-emitting drive circuit and the second light-emitting drive circuit; and odd-numbered second scan stages SSC2_0(n) and even-numbered second scan stages SSC2_E(n) that constitute the second scan drive circuit.

[0085] In addition, the second gate driver 212 of the gate driver 210 may be provided with, for example, a first scan stage SSC1(n), a third scan stage SSC3(n), and a fourth scan stage SSC4(n) that respectively constitute the first scan drive circuit, the third scan drive circuit, and the fourth scan drive circuit; a first light-emitting stage SEM1(n) and a second light-emitting stage SEM2(n) that respectively constitute the first light-emitting drive circuit and the second light-emitting drive circuit; and odd-numbered second scan stages SSC2_0(n) and even-numbered second scan stages SSC2_E(n) that constitute the second scan drive circuit.

[0086] The arrangement of the first scan stage SSC1(n) through the fourth scan stage SSC4(n) and the first light-emitting stage SEM1(n) and the second light-emitting stage SEM2(n) shown in FIG. 3 is an example, and they can be arranged in various combinations in the first gate driver 211 and the second gate driver 212.

[0087] The first scan stage SSC1(n) generates a first scan signal SC1(n) and outputs it to the corresponding first scan line SCL1, so that the pixel P_O(n) on the nth odd horizontal line and the pixel P_E(n) on the nth even horizontal line can receive the first scan signal SC1(n) in common.

[0088] The odd-numbered second scan stages SSC2_O(n) can generate odd-numbered second scan signals SC2_O(n) and output them to the corresponding odd-numbered second scan lines SCL2, and the even-numbered second scan stages SSC2_E(n) can generate even-numbered second scan signals SC2_E(n) and output them to the corresponding even-numbered second scan lines SCL2, so that the pixel P_O(n) on the nth odd-numbered horizontal line can receive the odd-numbered second scan signal SC2_O(n), and the pixel P_E(n) on the nth even-numbered horizontal line can receive the even-numbered second scan signal SC2_E(n). Here, the odd-numbered second scan signal SC2_O(n) and the even-numbered second scan signal SC2_E(n) have different timings. For example, the odd-numbered second scan signal SC2_O(n) and the even-numbered second scan signal SC2_E(n) may be applied in the data write period of the nth odd-numbered horizontal line and the data write period of the subsequent nth even-numbered horizontal line.

[0089] The third scan stage SSC3(n) generates a third scan signal SC3(n) and outputs it to the corresponding third scan line SCL3, so that the pixels P_O(n) and P_E(n) on the n-th odd and even horizontal lines can receive the third scan signal SC3(n) in common.

[0090] The fourth scan stage SSC4(n) generates a fourth scan signal SC4(n) and outputs it to the corresponding fourth scan line SCL4, so that the pixels P_O(n) and P_E(n) on the n-th odd and even horizontal lines can receive the fourth scan signal SC4(n) in common.

[0091] The first light-emitting stage SEM1(n) generates a first light-emitting control signal EM1(n) and outputs it to the corresponding first light-emitting control signal EML1, so that the pixels P_O(n) and P_E(n) of the n-th odd and even horizontal lines can commonly receive the first light-emitting control signal EM1(n).

[0092] The second light-emitting stage SEM2(n) generates a second light-emitting control signal EM2(n) and outputs it to the corresponding second light-emitting control signal EML2, so that the pixels P_O(n) and P_E(n) on the n-th odd and even horizontal lines can commonly receive the second light-emitting control signal EM2(n).

[0093] Meanwhile, referring to FIG. 3, a bias voltage line VobsL, a reset voltage line VarL, and an initialization voltage line ViniL can be arranged between the gate driver 210 configured as described above and the display area AA.

[0094] The bias voltage wiring VobsL, reset voltage wiring VarL, and initialization voltage wiring ViniL can supply the bias voltage Vobs, anode reset voltage Var, and initialization voltage Vini, respectively, from the power supply unit 280 to the pixels P in the display area AA.

[0095] 3, the bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL are shown to be located on only one of the left and right sides of the display area AA, but this is not limitative and they may be located on both sides, and even if they are located on one side, they are not limited to either the left or right side.

[0096] Furthermore, referring to FIG. 3, one or more optical areas OA1, OA2 can be arranged in the display area AA.

[0097] The one or more optical regions OA1 and OA2 may be arranged to overlap one or more optical-electronic devices, such as a photographing device such as a camera (or image sensor) or a detection sensor such as a proximity sensor or an illuminance sensor. The one or more optical regions OA1 and OA2 may have a light-transmitting structure and a transmittance above a predetermined level for the operation of the optical-electronic devices. In other words, the number of pixels P per unit area in the one or more optical regions OA1 and OA2 may be smaller than the number of pixels P per unit area in the general area of ​​the display area AA excluding the optical regions OA1 and OA2. That is, the resolution of the one or more optical regions OA1 and OA2 may be lower than the resolution of the general area within the display area AA.

[0098] Referring again to FIG. 1, the data driver 220 receives the image data Do and the data control signal DSC from the timing controller 240, converts the image data Do into a data voltage Vdata of analog image data in accordance with the data control signal DCS, and outputs the data voltage Vdata to the corresponding data line DL.

[0099] The data driver 220 may have a double bank structure that outputs the data voltage Vdata to both ends of the data line DL.

[0100] In this regard, the data driver 220 may be configured with a first data driver 221 arranged (or connected) on one side of the display panel 100 (or display area AA), for example, on the upper side (or front stage), and a second data driver 222 arranged (or connected) on the other side of the display panel 100, for example, on the lower side (rear stage).

[0101] Each of the first data driver 221 and the second data driver 222 may be configured to include at least one data IC, in which case the data IC may be mounted on a flexible printed circuit film and connected to the non-display area NA on one side of the corresponding display panel 100, or may be directly mounted in the non-display area NA.

[0102] The first data driver 221 and the second data driver 222 may have channels (or output channels) corresponding to and connected to, for example, each of the plurality of data lines DL provided in the display panel 100. The first data driver 221 may have a channel for outputting a corresponding data voltage Vdata to the upper end of each data line DL. The second data driver 222 may have a channel for outputting a corresponding data voltage Vdata to the lower end of each data line DL.

[0103] In this manner, the first data driver 221 and the second data driver 222 disposed on the upper and lower sides of the display panel 100, respectively, may be provided with the image data Do output from the timing control unit 240 in common (or the same).

[0104] As a result, the same data voltage Vdata output from the first data driver 221 and the second data driver 222 can be applied to the upper and lower ends of each data line DL.

[0105] In this way, in the double bank structure, the data line DL receives the same data voltage Vdata at both ends, so that the data voltage Vdata can be stably supplied to the inside of the display area AA.

[0106] The power supply unit 280 uses, for example, a DC-DC converter to generate DC power necessary to drive the pixel array and the driving circuit unit of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc.

[0107] The power supply unit 280 receives, for example, a power voltage Vcc, which is a driving voltage for driving the display device 10, from a host system, and generates DC voltages such as gate low voltages VGL and VEL, gate high voltages VGH and VEH, a high-potential driving voltage EVDD, a low-potential driving voltage EVSS, and a source driving voltage (SVDD in FIG. 6). The gate low voltages VGL and VEL and the gate high voltages VGH and VEH may be supplied to the gate driver 210. The high-potential driving voltage EVDD and the low-potential driving voltage EVSS may be supplied in common to the pixels P in the display panel 100. The source driving voltage SVDD may be supplied to a first data driver 221 and a second data driver 222 constituting the data driver 220.

[0108] Here, the source drive voltage SVDD may be, for example, higher in potential than the high-potential drive voltage EVDD and lower in potential than the gate high voltages VGH and VEH, but is not limited to this. Also, the low-potential drive voltage EVSS may be, for example, lower in potential than, higher in potential than, or the same as the gate low voltages VGL and VEL.

[0109] The gate signals applied to the pixels P of the display panel 100 will be described with reference to Fig. 4. For convenience of explanation, Fig. 4 does not show the first and second light-emitting control signals EM(n) individually, but shows one representative light-emitting control signal EM(n) as an example.

[0110] A frame in which data is written and an image is refreshed (or a refresh frame) can be divided into a non-light emitting interval Tne and a light emitting interval Te.

[0111] The non-light emitting interval Tne and the light emitting interval Te can be defined by the light emitting control signal EM(n). A high-level scan pulse interval where the light emitting control signal EM(n) (e.g., the first and second light emitting control signals EM1(n), EM2(n)) is at a turn-off level corresponds to the non-light emitting interval Tne, and a low-level interval where the light emitting control signal EM(n) (e.g., the first and second light emitting control signals EM1(n), EM2(n)) is at a turn-on level corresponds to the light emitting interval Te.

[0112] During the non-light emitting period Tne, the data voltage Vdata is applied and a write operation can be performed.

[0113] For example, during a data write period (or sampling period) Ts during which the odd and even second scan signals SC2_O(n), SC2_E(n), more specifically, scan pulses of low level, which are their turn-on levels, are applied, the data voltages Vdata of the odd and even pixels P_O(n), P_E(n) are applied and written to the gate electrodes of the drive transistors DT. Meanwhile, during the data write period Ts, the threshold voltages of the drive transistors DT are sampled and reflected on the gate electrodes of the drive transistors DT.

[0114] In the data write period Ts, the first scan signal SC1(n) has a scan pulse of a high level, which is a turn-on level, and the corresponding first transistor T1 is turned on.

[0115] Meanwhile, within the non-light-emitting period Tne, there may be at least one bias period (or anode reset period) Tobs in which a bias voltage Vobs and an anode reset voltage Var are applied. In this embodiment, an example is given in which the bias period Tobs is set before or after the data write period Ts. In this case, for convenience of explanation, the bias period Tobs set before data write may be referred to as a first bias period Tobs1, and the bias period Tobs set after data write may be referred to as a second bias period Tobs2.

[0116] In each of the first bias section Tobs1 and the second bias section Tobs2, the third scan signal SC3(n) may have a scan pulse of a low level, which is a turn-on level.

[0117] In this case, the fifth transistor T5 is turned on, and the bias voltage Vobs may be applied to the second node N2 and the third node N3, resulting in an on-bias stress operation for the driving transistor DT.

[0118] In addition, the sixth transistor T6 is turned on, and the anode reset voltage Var is applied to the fifth node N5, thereby performing an anode reset operation on the anode electrode of the light emitting diode OD.

[0119] Meanwhile, an initialization voltage Vini may be applied between the data write period Ts and the preceding first bias period Tobs1. During the initialization period Ti, the fourth scan signal SC4(n) may have a high-level scan pulse, which is a turn-on level. As a result, the corresponding seventh transistor T7 is turned on, and the initialization voltage Vini may be applied to the first node N1, i.e., the gate electrode of the driving transistor DT. Also, an initialization operation for the driving transistor DT may be performed.

[0120] An example of the cross-sectional structure of the display panel 100 in this embodiment will be described below with reference to Fig. 5. Fig. 5 is a cross-sectional view that schematically shows an example of the cross-sectional structure of a display panel according to an embodiment of the present invention.

[0121] For convenience of explanation, two thin film transistors TFT1 and TFT2 are shown in pixel P in display area AA in Figure 5. Here, the thin film transistor TFT1 located closer to the substrate 101 and at a relatively lower position is referred to as the first thin film transistor TFT1, which may be a polycrystalline silicon thin film transistor. The thin film transistor TFT2 located further from the substrate 101 and at a relatively higher position is referred to as the second thin film transistor TFT2, which may be an oxide thin film transistor.

[0122] Meanwhile, the first thin film transistor TFT1 may be, but is not limited to, a driving transistor (DT in FIG. 2). For convenience of explanation, FIG. 5 shows an example in which the first thin film transistor TFT1 is connected to a light emitting diode OD. The second thin film transistor TFT2 may be, but is not limited to, one of the first to seventh transistors (T1 to T7 in FIG. 2) that are switching thin film transistors, more specifically, the first transistor T1 connected to a storage capacitor Cst.

[0123] The substrate 101 can be made of, for example, a thin glass substrate (or glass film) or a plastic substrate (or plastic film) so that the display panel 100 can have flexible properties.

[0124] Here, when the substrate 101 is made of a glass substrate, the substrate 101 may have a thickness of, for example, about 0.2 mm.

[0125] On the other hand, when the substrate 101 is made of a plastic substrate, for example, the substrate 101 may include at least one polyimide layer.

[0126] The first thin film transistor TFT1 may include a first semiconductor layer 105 disposed on the substrate 101, a first gate electrode 115 overlapping the semiconductor layer 105 with a first insulating layer 110 interposed therebetween, and a first source electrode 151 and a first drain electrode 152 located above the first gate electrode 115 and on the fourth insulating layer 145. Here, the first semiconductor layer 105 may be formed of, but is not limited to, polycrystalline silicon.

[0127] The first semiconductor layer 105 includes a central channel region and source and drain regions on either side of the channel region. The first source electrode 151 and the first drain electrode 152 can be connected to the source and drain regions of the first semiconductor layer 105 via a first contact hole 156 and a second contact hole 157 formed in the insulating layers 110, 120, 125, 135, and 145 located below the first source electrode 151 and the first drain electrode 152.

[0128] A second insulating layer 120 may be formed on the first gate electrode 115 of the first thin film transistor TFT1.

[0129] A first interlayer insulating layer 125 may be formed on the second insulating layer 120. A second thin film transistor TFT2 may be formed on the first interlayer insulating layer 125.

[0130] The second thin film transistor TFT2 may include a second semiconductor layer 130 on the first interlayer insulating layer 125, a second gate electrode 140 overlapping the second semiconductor layer 130 with a third insulating layer 135 interposed therebetween, and a second source electrode 153 and a second drain electrode 154 located above the second gate electrode 140 and on the fourth insulating layer 145. Here, the second semiconductor layer 130 may be formed of an oxide semiconductor, but is not limited to this.

[0131] The second semiconductor layer 130 includes a central channel region and source and drain regions on either side of the channel region. The second source electrode 153 and the second drain electrode 154 can be connected to the source and drain regions of the second semiconductor layer 130 via a third contact hole 158 and a fourth contact hole 159 formed in the insulating layers 135 and 145 located below the second semiconductor layer 130.

[0132] A second interlayer insulating layer (or a first planarizing layer) 160 may be formed on the second thin film transistor TFT2.

[0133] Here, the first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the fourth insulating layer 145 may be made of an inorganic insulating material such as silicon nitride or silicon oxide, but are not limited thereto.

[0134] The first interlayer insulating layer 125 and the second interlayer insulating layer 160 may be made of an organic insulating material such as photoacrylic or benzocyclobutene, but are not limited thereto.

[0135] A connection electrode 162 may be formed on the second interlayer insulating layer 160. The connection electrode 162 may be connected to the first drain electrode 152 via a contact hole 161 formed in the second interlayer insulating layer 160.

[0136] A third interlayer insulating layer (or a second planarizing layer) 163 may be formed on the connection electrode 162. The third interlayer insulating layer 163 may be made of an organic insulating material such as photoacrylic or benzocyclobutene, but is not limited thereto.

[0137] On the third interlayer insulating layer 163, a light emitting diode OD and a bank 165 may be formed.

[0138] The light-emitting diode OD may include an anode electrode (or a first electrode) 171 , a light-emitting layer 172 , and a cathode (or a second electrode) 173 .

[0139] The anode 171 can be connected to the connection electrode 162 via a contact hole 164 formed in the third interlayer insulating layer 163 .

[0140] The bank 165 may be disposed along the boundary of the pixel P and may be formed to cover the edge of the anode 171. An emitting layer 172 may be formed on the anode 171 exposed through the opening in the bank 165.

[0141] The cathode 173 is formed on the light-emitting layer 172 and can receive a low potential driving voltage (EVSS in FIG. 2).

[0142] A sealing layer 180 may be formed on the cathode 173. The sealing layer 180 may include, but is not limited to, at least one inorganic sealing layer and at least one organic sealing layer. In the present invention, a structure of the sealing layer 180 in which a first sealing layer 181, a second sealing layer 182, and a third sealing layer 183 are sequentially stacked will be exemplified.

[0143] The first encapsulation layer 181 is formed on the substrate 101 on which the cathode 173 is formed. The third encapsulation layer 183 is formed on the substrate 101 on which the second encapsulation layer 182 is formed, and may be formed to surround the top, bottom, and side surfaces of the second encapsulation layer 182 together with the first encapsulation layer 181. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from penetrating into the light emitting diode OD. The first encapsulation layer 181 and the third encapsulation layer 183 may be formed of an inorganic insulating material that can be deposited at a low temperature, such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide.

[0144] The second encapsulating layer 182 functions as a buffer to relieve stress between layers due to warpage of the display device 10 and can flatten steps between layers. The second encapsulating layer 182 can be formed on the substrate 101 on which the first encapsulating layer 181 is formed, using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbonate (SiOC), or a photosensitive organic insulating material such as photoacrylic, but is not limited thereto. When the second encapsulating layer 182 is formed using an inkjet method, a dam (DAM) can be disposed in the non-display area NA to prevent the liquid second encapsulating layer 182 from spreading to the edge of the substrate 101. The dam (DAM) can be disposed closer to the edge of the substrate 101 than the second encapsulating layer 182. The dam (DAM) can prevent the second encapsulating layer 182 from spreading to the pad area on the outermost side of the substrate 101 where the conductive pads are disposed.

[0145] The dam DAM is designed to prevent diffusion of the second sealing layer 182, but if the second sealing layer 182 is formed in a process so that it exceeds the height of the dam DAM, the second sealing layer 182, which is an organic layer, may be exposed to the outside, allowing moisture and the like to easily penetrate into the light emitting element. For this reason, at least 10 or more dam DAMs may be stacked, but the number of dam DAMs is not limited to this.

[0146] The dam DAM can be formed simultaneously with the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163. The lower layer of the dam DAM can be formed when the first interlayer insulating layer 125 is formed, and the upper layer of the dam DAM can be formed when the second interlayer insulating layer 160 and the third interlayer insulating layer 163 are formed, so that they are stacked to form a three-layer structure. As another example, the dam DAM can be formed using one or two of the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163.

[0147] Therefore, the dam DAM may be made of the same material as the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163, but is not limited to this.

[0148] The dam DAM can be formed so as to overlap the low potential drive voltage wiring VSSL. For example, in the non-display area NA, the low potential drive voltage wiring VSSL can be formed in a layer below the area where the dam DAM is located.

[0149] The low potential driving voltage wiring VSSL and the gate driver 210 having a GIP structure are formed along the outer side of the display panel 100, and the low potential driving voltage wiring VSSL may be located outside the gate driver 210. The low potential driving voltage wiring VSSL is connected to the cathode 173 and can apply a low potential driving voltage EVSS. Although the gate driver 210 in the drawings is simply shown in plan and cross section, it may have the same structure as the first and / or second thin film transistors TFT1 and / or TFT2 in the display area AA.

[0150] A touch layer (or touch element layer) 190 may be disposed on the encapsulation layer 180. A touch buffer film 191 in the touch layer 190 may be located between the touch sensor metal, including the touch electrode connecting lines 192, 194 and the touch electrodes 195, 196, and the cathode 173 of the light-emitting diode OD.

[0151] The touch buffer film 191 can block chemicals (such as a developing solution or an etching solution) used in the manufacturing process of the touch sensor metal disposed on the touch buffer film 191, or external moisture, from penetrating into the light-emitting layer 172 containing organic matter. As a result, the touch buffer film 191 can prevent damage to the light-emitting layer 172, which is sensitive to chemicals or moisture.

[0152] According to the structure of the mutual capacitance touch sensor, touch electrodes 195 and 196 are disposed on a touch buffer film 191, and the touch electrodes 195 and 196 may be disposed so as to cross each other.

[0153] The touch electrode connecting lines 192 and 194 can electrically connect the touch electrodes 195 and 196. One of the touch electrode connecting lines 192 and 194 and the touch electrodes 195 and 196 can be located in different layers with the touch insulating layer 193 interposed therebetween. Also, one of the touch electrode connecting lines 192 and 194 and the other can be located in different layers with the touch insulating layer 193 interposed therebetween.

[0154] The touch electrode connection lines 192 and 194 are arranged so as to overlap with the bank 165, and this can prevent a decrease in the aperture ratio, but the present invention is not limited to this.

[0155] On the other hand, parts of the touch electrodes 195, 196 and parts of the touch electrode connection lines 192 can pass through the top and side surfaces of the sealing layer 180 and the top and side surfaces of the dam DAM, and can be electrically connected to a touch drive circuit (not shown) via touch pads 198, 199.

[0156] A part of the touch electrodes 195, 196 and a part of the touch electrode connecting line 192 can receive a touch driving signal from a touch driving circuit and transmit it to the touch electrodes 195, 196, and transmit the touch sensing signal sensed by the touch electrodes 195, 196 to the touch driving circuit.

[0157] For example, the driving IC (e.g., data IC) of the data driver 220 including the touch driving circuit may be configured as a COF (Chip on Film) and connected to the non-display area NA of the substrate 101 of the display panel 100. In this case, the ends of the touch pads 198 and 199 are connected to the flexible circuit film on which the driving IC is mounted, and signals can be transmitted.

[0158] A touch protective film 197 may be disposed on the touch electrodes 195 and 196. In FIG. 5, the touch protective film 197 is shown disposed only on the touch electrodes 195 and 196, but is not limited thereto. The touch protective film 197 may extend to the front or rear of the dam DAM and may also be disposed on the touch electrode connecting line 192.

[0159] A color filter (not shown) may be further disposed on the encapsulation layer 180. The color filter may be located on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190.

[0160] As described above, the display device 10 of this embodiment uses the data driver 220 with a double-bank structure, and therefore the same lock signals (i.e., input lock signals or lock voltages) LCK_in:LCK_in1, LCK_in2 are input to each of the first data driver 221 and the second data driver 222 of the data driver 220, and clock training, i.e., clock recognition, is performed. When the clock training is completed (or successful), the first data driver 221 and the second data driver 222 can generate the output lock signal LCK_out as a feedback signal for the input lock signal LCK_in.

[0161] Here, clock training corresponds to a process in which the timing control unit 240 provides a training clock to the first data driver 221 and the second data driver 222, and the first data driver 221 and the second data driver 222 correctly recognize the training clock. The clock training may be performed, for example, during an initial driving period after powering on the display device 10 and during a blank period between frames.

[0162] For example, when a power voltage Vcc is input to the power supply unit 500 to drive the display device 10, the power supply unit 500 generates all driving voltages to drive the display device 10, and the timing control unit 240 synchronizes with the input timing of the power voltage Vcc and generates and outputs a lock signal (i.e., an input lock signal) LCK_in.

[0163] In this manner, the lock signal (i.e., lock signal) LCK_in output from the timing control unit 240 can be simultaneously input to the first data driver 221 and the second data driver 222. Here, for convenience of explanation, the lock signal (i.e., input lock signal) LCK_in input to the first data driver 221 in the preceding stage can be referred to as the input first lock signal LCK_in1, and the lock signal (i.e., input lock signal) LCK_in input to the second data driver 222 in the following stage can be referred to as the input second lock signal LCK_in2.

[0164] When the first input clock signal LCK_in1 and the second input clock signal LCK_in2 are transmitted at the same timing, the first data driver 221 and the second data driver 222 can perform clock training individually.

[0165] When the clock training is completed, the first data driver 221 and the second data driver 222 can individually generate and output the output clock signal LCK_out.

[0166] For example, the first data driver 221 and the second data driver 222 may each be configured with a plurality of data ICs connected in a cascade manner and operating sequentially, and each of the plurality of data ICs may sequentially perform clock training upon receiving a lock signal (i.e., input lock signal) LCK_in, to generate and output a lock signal.

[0167] In this case, in the first data driver 221, the first data IC performs clock training using the input first lock signal LCK_in1, generates a corresponding output lock signal, and provides it to the second data IC. In this manner, the last data IC performs clock training and generates a corresponding output lock signal LCK_out, and this output lock signal, the output first lock signal LCK_out1, can be transmitted to the comparison circuit 250. In this way, in the first data driver 221, the multiple data ICs can sequentially receive the input lock signal, perform clock training, and output the output first lock signal LCK_out1.

[0168] Similarly, in the second data driver 222, the first data IC performs clock training using the input second lock signal LCK_in2, generates a corresponding output lock signal, and provides it to the second data IC. In this manner, the last data IC performs clock training and generates a corresponding output lock signal LCK_out, which can be transmitted as the output second lock signal LCK_out2 to the comparison circuit 250. In this manner, in the second data driver 222, the multiple data ICs sequentially receive the lock signal, perform clock training, and output the output second lock signal LCK_out2.

[0169] In this manner, the output first lock signal LCK_out1 output from the last data IC of the first data driver 221 and the output second lock signal LCK_out2 output from the last data IC of the second data driver 222 are provided to the comparison circuit 250, and the comparison circuit 250 can compare the output first lock signal LCK_out1 with the output second lock signal LCK_out2.

[0170] For example, by comparing the output first lock signal LCK_out1 and the output second lock signal LCK_out2, it can be determined whether the output timings of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 match or are synchronized between the first data driver 221 and the second data driver 222. Furthermore, by determining whether either the output first lock signal LCK_out1 or the output second lock signal LCK_out2 is in a lock fail state (e.g., by determining whether it has an abnormal waveform), it can be determined whether at least one of the first data driver 221 and the second data driver 222 has failed in clock training and thus has experienced a lock failure.

[0171] The comparison circuit 250 compares the output first lock signal LCK_out1 and the output second lock signal LCK_out2, synchronizes the lock states of the output first lock signal LCK_out1 and the output second lock signal LCK_out2, generates a synchronized lock signal (i.e., a synchronized lock signal) LCKS, and transmits it to the timing control unit 240.

[0172] The timing control unit 240 can adjust the transmission of the image data Do to the first data driver 221 and the second data driver 222 in response to the synchronous lock signal LCKS whose lock state is synchronized, and synchronize the output timing of the first data driver 221 and the second data driver 222.

[0173] For example, if one of the first output clock signal LCK_out1 and the second output clock signal LCK_out2 is delayed compared to the other and is not synchronized with each other, i.e., they are asynchronous with each other, the transmission timing of the video data Do can be adjusted according to the synchronous clock signal LCKS generated based on the delayed output clock signal LCK_out and provided to the first data driver 221 and the second data driver 222.

[0174] In addition, if a lock failure occurs in either the first data driver 221 or the second data driver 222, the lock failure is reflected and the generated synchronous lock signal LCKS can turn off (or halt) the transmission of the video data Do and turn off the output operation of the data voltage Vdata of the first data driver 221 and the second data driver 222.

[0175] In this way, the comparison circuit 250 can monitor the output lock signals of the first data driver 221 and the second data driver 222 in real time, synchronize the lock states, and adjust the transmission of the image data Do to the first data driver 221 and the second data driver 222.

[0176] This can mitigate or prevent a potential difference in the data voltage Vdata between the upstream and downstream stages during an asynchronous or lock-failure period of the output lock signals, i.e., the first lock signal LCK_out1 and the second lock signal LCK_out2. As a result, it is possible to mitigate or prevent an overcurrent caused by a potential difference in the data voltage Vdata between the upper and lower ends of the channel, thereby mitigating or preventing the data IC from overheating or burning due to the overcurrent. Furthermore, it is possible to mitigate or prevent image quality defects such as block dim caused by a long delay in the output lock signal LCK_out.

[0177] In this way, the output first lock signal LCK_out1 and the output second lock signal LCK_out2 between the first data driver 221 in the front stage and the second data driver 222 in the rear stage are compared and synchronized to adjust the transmission of video data Do to the first data driver 221 and the second data driver 222, and the output timing of the first data driver 221 and the second data driver 222. The configuration and method of this embodiment will now be described in further detail.

[0178] Fig. 6 is a diagram schematically illustrating a timing control unit, a data driver, and a comparison circuit of a display device according to an embodiment of the present invention. Fig. 7 is a timing diagram schematically illustrating an input lock signal, an output lock signal, a synchronous lock signal, and a data voltage output according to an embodiment of the present invention. Fig. 8 is a timing diagram schematically illustrating an example of an input lock signal, an output lock signal, a synchronous lock signal, and a data voltage output when the output lock signal becomes asynchronized and a lock failure occurs in an embodiment of the present invention. Fig. 9 is a timing diagram schematically illustrating an example of an input lock signal, an output lock signal, and a data voltage output when the output lock signal becomes asynchronized and a lock failure occurs in a comparative example of the present invention.

[0179] 6 together with FIGS. 1 to 5, the display device 10 of this embodiment may use a double-bank data driver 220. The double-bank data driver 220 may include a first data driver 221 and a second data driver 222 connected to the front and rear stages of the display panel 100, respectively.

[0180] Meanwhile, the display device 10 of this embodiment is driven at a variable refresh rate (VRR) in which the driving frequency, i.e., the refresh rate, is adjusted to reduce power consumption, thereby achieving low power operation.

[0181] 7 and 8, for example, the frequency at which the display device 10 is driven by receiving the power voltage Vcc, i.e., the refresh rate, can be varied, for example, between 60 Hz and 120 Hz. Here, VRR driving is taken as an example, in which, during high-speed driving at 120 Hz, the image on the display panel 100 (or data voltages Vdata: Vdata1, Vdata2) is divided into refresh frames FRr in which the image is refreshed and skip frames FRs in which the image is not refreshed and the previous image is kept as is, and during low-speed driving at 60 Hz, the display panel 100 is driven with the refresh frames FRr. Meanwhile, SC in FIGS. 7, 8, and 9 indicates the scan signals (SC1 to SC4 in FIGS. 2 and 3) output from the gate driver 210.

[0182] The first data driver 221 and the second data driver 222 of the double bank structure may each include, for example, a plurality of data ICs (DICs). In this embodiment, the first data driver 221 includes three first data ICs (DIC1), namely, first to third first data ICs (DIC1(1) to DIC1(3)), and the second data driver 222 includes three second data ICs (DIC2), namely, first to third second data ICs (DIC2(1) to DIC2(3)).

[0183] The first data driver 221 and the second data driver 222 having such a double bank structure can output the same data voltage Vdata to the upper and lower ends of the data lines DL for each channel.

[0184] Here, for convenience of explanation, the data voltage Vdata output from the first data driver 221 in the preceding stage may be referred to as the first data voltage (or preceding stage data voltage) Vdata1, and the data voltage Vdata output from the second data driver 222 in the succeeding stage may be referred to as the second data voltage (or succeeding stage data voltage) Vdata2.

[0185] In this embodiment, the data ICs (DICs) of the first data driver 221 and the second data driver 222 are mounted on a flexible circuit film (FCF) using a COF method.

[0186] Meanwhile, the first data driver 221 may include a first source board SPCB1, which is a source board SPCB to which a plurality of first data ICs (DIC1) are connected, and the second data driver 222 may include a second source board SPCB2, which is a source board SPCB to which a plurality of second data ICs (DIC2) are connected.

[0187] In this regard, the signal output from the timing control unit 240 can be transmitted to the first data IC (DIC1) via the first source board SPCB1, and can also be transmitted to the second data IC (DIC2) via the second source board SPCB2.

[0188] Here, the first source board SPCB1 may be formed with a first lock signal wiring LCKL1 that is a lock signal wiring LCKL that transmits a lock signal, and the second source board SPCB2 may be formed with a second lock signal wiring LCKL2 that is a lock signal wiring LCKL that transmits a lock signal.

[0189] For example, the input first lock signal LCK_in1 output from the timing control unit 240 may be input to the first first data IC (DIC1(1)), which performs clock training and outputs a lock signal. Next, the lock signal output from the first first data IC (DIC1(1)) (or the first output lock signal) may be input to the second first data IC (DIC1(2)), which performs clock training and outputs a lock signal. Next, the lock signal output from the second first data IC (DIC1(2)) (or the second output lock signal) may be input to the third first data IC (DIC1(3)), which performs clock training and outputs the output first lock signal LCK_out1. In this way, the output first lock signal LCK_out1, which is the lock signal output from the last third first data IC (DIC1(3)), may be transmitted to the comparison circuit 250.

[0190] In this way, a first lock signal wiring LCKL1 can be formed on the first source board SPCB1 to transmit the input first lock signal LCK_in1 provided from the timing control unit 240, the output lock signals generated in the first first data IC (DIC1(1)) and the second first data IC (DIC1(2)), and the output first lock signal LCK_out1 generated in the third first data IC (DIC1(3)).

[0191] Furthermore, a lock signal wiring for inputting and outputting a lock signal can be formed on the flexible printed circuit board (FCF) on which the first data IC (DIC1) is mounted.

[0192] In addition, the input second lock signal LCK_in2 output from the timing control unit 240 can be input to the first second data IC (DIC2(1)), which performs clock training and outputs a lock signal. Next, the lock signal output from the first second data IC (DIC2(1)) (or the first output lock signal) can be input to the second second data IC (DIC2(2)), which performs clock training and outputs a lock signal. Next, the lock signal output from the second second data IC (DIC2(2)) (or the second output lock signal) can be input to the third second data IC (DIC2(3)), which performs clock training and outputs the output second lock signal LCK_out2. In this way, the output second lock signal LCK_out2, which is the lock signal output from the last, third second data IC (DIC2(3)), can be transmitted to the comparison circuit 250.

[0193] In this way, a second lock signal wiring LCKL2 can be formed on the second source board SPCB2 to transmit the input second lock signal LCK_in2 provided from the timing control unit 240, the output lock signals generated in the first second data IC (DIC2(1)) and the second second data IC (DIC2(2)), and the output second lock signal LCK_out2 generated in the third second data IC (DIC2(3)).

[0194] Furthermore, a lock signal wiring for inputting and outputting a lock signal can be formed on the flexible printed circuit board (FCF) on which the second data IC (DIC2) is mounted.

[0195] On the other hand, the timing control section 240 and the comparison circuit 250 can be mounted on, for example, the control board CPCB, but are not limited to this.

[0196] The timing control unit 240 may provide the first and second input lock signals LCK_in1 and LCK_in2, which are the same input lock signal LCK_in, to the corresponding first and second data drivers 221 and 222.

[0197] Referring to FIG. 7 for the input first lock signal LCK_in1 and the input second lock signal LCK_in2, for example, the input first lock signal LCK_in1 and the input second lock signal LCK_in2 can be synchronized with each other and input to the corresponding first data driver 221 and second data driver 222 at the same timing.

[0198] The first input lock signal LCK_in1 and the second input lock signal LCK_in2 may have a high level in synchronization with the time when the display device 10 is powered on and the power voltage Vcc is applied to the power supply unit 280. The high levels of the first input lock signal LCK_in1 and the second input lock signal LCK_in2 may be maintained substantially throughout the driving time of the display device 10 and may be input to the first data driver 221 and the second data driver 222.

[0199] In this regard, referring to Figures 7 and 8, the input first lock signal LCK_in1 and the input second lock signal LCK_in2 can be continuously output from the time of power-on until the last output time (or last frame) of the first data driver 221 and the second data driver 222 before power-off.

[0200] In this way, the input first lock signal LCK_in1 and the input second lock signal LCK_in2 output from the timing control unit 240 from the time of power-on are input to the corresponding first data driver 221 and second data driver 222, and the first data driver 221 and the second data driver 222 can perform clock training and output the output first lock signal LCK_out1 and the output second lock signal LCK_out2.

[0201] For example, immediately after the display device 10 is powered on, the first data driver 221 and the second data driver 222 may perform clock training and output the first output lock signal LCK_out1 and the second output lock signal LCK_out2 during a power-on sequence that is performed for a predetermined time. Furthermore, during a blank period between adjacent frames FR, for example, during an output period of the vertical synchronization signal VSY, clock training may be performed and the first output lock signal LCK_out1 and the second output lock signal LCK_out2 may be output.

[0202] The first and second output lock signals LCK_out1 and LCK_out2 may start to be output after a predetermined time has elapsed from the start of the first and second input lock signals LCK_in1 and LCK_in2, and may be continuously maintained substantially throughout the driving time of the display device 10.

[0203] In this regard, referring to FIG. 7, in the normal driving state of the display device 10, the output first lock signal LCK_out1 and the output second lock signal LCK_out2 start to be output a predetermined time after the power-on point and can be continuously output until the last output point (or last frame) of the first data driver 221 and the second data driver 222 before the power-off point.

[0204] The comparison circuit 250 receives the output first lock signal LCK_out1 and the output second lock signal LCK_out2 output from the first data driver 221 and the second data driver 222, compares the states of the output first lock signal LCK_out1 and the output second lock signal LCK_out2, synchronizes these lock states, and generates a synchronized lock signal LCKS.

[0205] For example, the comparison circuit 250 compares the output first lock signal LCK_out1 and the output second lock signal LCK_out2 to determine whether the output timings are synchronized and matched or asynchronous and mismatched, and if they are asynchronous, it can match the lock states and synchronize them.

[0206] 7 and 8, for example, the first output lock signal LCK_out1 may be output first from the power-on sequence, and then the second output lock signal LCK_out2 may be output with a delay. Conversely, the second output lock signal LCK_out2 may be output first from the power-on sequence, and then the first output lock signal LCK_out1 may be output with a delay.

[0207] As described above, the output delay of either the output first lock signal LCK_out1 or the output second lock signal LCK_out2 may be caused by the RC component of the wiring that transmits the lock signals, external factors, etc. For example, the output timing of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 may differ due to differences in RC resistance between the signal transmission wiring between the input of the input first lock signal LCK_in1 and the output of the output first lock signal LCK_out1 and the signal transmission wiring between the input of the input second lock signal LCK_in2 and the output of the output second lock signal LCK_out2, or due to external factors.

[0208] 7, the output first lock signal LCK_out1 may end normally from the power-off sequence of the display device 10, and then the output second lock signal LCK_out2 may end with a delay. Conversely, referring to FIG. 8, the output first lock signal LCK_out1 may end normally from the power-off sequence, and then the output second lock signal LCK_out2 may end before that.

[0209] In this way, when one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is in a high-level locked state and the other is in a low-level unlocked state, and the lock states do not match and become asynchronous, the comparison circuit 250 can output a synchronous lock signal LCKS having a low level in an unlocked state during such asynchronous period.

[0210] Conversely, when both the first output lock signal LCK_out1 and the second output lock signal LCK_out2 have a high-level locked state, the comparison circuit 250 can output a synchronous lock signal LCKS having a high level in the locked state during the same locked period. In this regard, referring to Figures 7 and 8, for example, the comparison circuit 250 can generate a high-level synchronous lock signal LCKS after the second output lock signal LCK_out2, which is delayed from the power-on sequence, switches to the locked state.

[0211] Furthermore, the comparison circuit 250 compares the output first lock signal LCK_out1 with the output second lock signal LCK_out2 to determine whether at least one of the first data driver 221 and the second data driver 222 is operating abnormally, resulting in a lock failure. If a lock failure occurs, the comparison circuit 250 can synchronize the signal with the unlocked state.

[0212] 8, for example, the second data driver 222 may abnormally drive at a refresh frame FRr driven at 120 Hz, resulting in a lock failure. As a result, the output second lock signal LCK_out2 may not maintain a normal high level and may have an abnormal waveform. When this lock failure occurs, the second data driver 222 may fail to recognize the clock and perform an abnormal output operation, which may cause noise in the second data voltage Vdata2 output from the second data driver 222.

[0213] In this way, when a lock failure occurs in the second data driver 222 and the output second lock signal LCK_out2 is in an abnormal lock failure state, the comparison circuit 250 can output a low-level synchronous lock signal LCKS in an unlocked state during the lock failure period.

[0214] In this way, by comparing the output first lock signal LCK_out1 and the output second lock signal LCK_out2, if the lock states of these signals are asynchronous with each other or at least one of them has a lock failure state, the comparison circuit 250 can set the synchronous lock signal LCKS to a low level indicating an unlocked state. Also, if both the output first lock signal LCK_out1 and the output second lock signal LCK_out2 are in a locked state, the comparison circuit 250 can set the synchronous lock signal LCKS to a high level indicating a locked state.

[0215] In this way, the synchronous lock signal LCKS whose lock state is synchronized by the comparison circuit 250 is provided to the timing control unit 240, and the timing control unit 240 can adjust the transmission timing of the image data Do to the first data driver 221 and the second data driver 222 based on the synchronous lock signal LCKS.

[0216] In this regard, referring to FIG. 8, for example, when the lock states of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 are asynchronous with each other or at least one of them is in a lock failure state, the synchronous lock signal LCKS becomes a low level indicating an unlock state, and according to the unlock state of the synchronous lock signal LCKS, the timing control unit 240 can turn off the transmission of the video data Do to the first data driver 221 and the second data driver 222.

[0217] In this regard, when the first output clock signal LCK_out1 and the second output clock signal LCK_out2 are asynchronous, the timing controller 240 can turn off the transmission of the image data Do during the asynchronous interval, so that the outputs of the data voltages Vdata1 and Vdata2 from the first data driver 221 and the second data driver 222 can be turned off during the asynchronous interval.

[0218] For example, as shown in FIG. 8, in the power-on sequence, the output second lock signal LCK_out2 is delayed from the output first lock signal LCK_out1. In this case, if the output of the output second lock signal LCK_out2 is delayed until the initial period within the 60 Hz drive refresh frame FRr at which the output of the first data driver 221 and the second data driver 222 starts, the synchronous lock signal LCKS may remain at a low level until the initial period of the refresh frame FRr at which it is delayed, and then switch to a high level.

[0219] Also, as shown in FIG. 8, in the power-off sequence, the output second lock signal LCK_out2 ends before the output first lock signal LCK_out1. In this case, if the output of the output second lock signal LCK_out2 ends before the final section of the 60 Hz driven refresh frame FRr where the output of the first data driver 221 and the second data driver 222 ends, the synchronous lock signal LCKS may maintain a high level until just before the final section of the refresh frame FRr, at which point it ended first, and then switch to a low level.

[0220] In this way, when the output second lock signal LCK_out2 is output later than or ends earlier than the output first lock signal LCK_out1, and the output first lock signal LCK_out1 and the output second lock signal LCK_out2 are asynchronous with each other, the timing control unit 240 can turn off transmission of the video data Do during the asynchronous period. Also, in a period when the output second lock signal LCK_out2 has a high-level locked state and the synchronous lock signal LCKS has a high-level locked state, the timing control unit 240 can transmit the video data Do according to the locked state of the synchronous lock signal LCKS.

[0221] In this way, during the period when the output first lock signal LCK_out1 and the output second lock signal LCK_out2 are asynchronous, the transmission of the video data Do is turned off and the output of the first data voltage Vdata1 and the second data voltage Vdata2 of the preceding and succeeding stages is turned off, and during the period when both are in a locked state, the transmission of the video data Do is performed and the same first data voltage Vdata1 and second data voltage Vdata2 can be synchronized and output.

[0222] As a result, during the asynchronous interval between the output first lock signal LCK_out1 and the output second lock signal LCK_out2, the output timing of the upstream first data driver 221 and the downstream second data driver 222 becomes asynchronous, generating a potential difference in the output voltage between the upper and lower ends of the channel, thereby mitigating or preventing overcurrent.As a result, it is possible to mitigate or prevent overheating or burning of the data IC (DIC) caused by overcurrent that occurs when the outputs of the upstream and downstream stages become asynchronous.Furthermore, it is possible to mitigate or prevent image quality defects such as block dim when the output asynchronous interval is long.

[0223] In this regard, referring to the comparative example of FIG. 9, in the display device of the comparative example, the power supply unit 280 provides a single input lock signal LCK_in to the first data driver 221 and the second data driver 222, and the timing control unit 240 receives the output first lock signal LCK_out1 and the output second lock signal LCK_out2 of the first data driver 221 and the second data driver 222. If either the output first lock signal LCK_out1 or the output second lock signal LCK_out2 is in a locked state, the timing control unit 240 transmits the image data Do to the first data driver 221 and the second data driver 222 regardless of whether synchronization is present, and the first data driver 221 and the second data driver 222 can output the corresponding data voltages Vdata1 and Vdata2.

[0224] In the driving of this comparative example, the video data Do is transmitted even in the asynchronous section between the output first lock signal LCK_out1 and the output second lock signal LCK_out2, and in the asynchronous section, for example, the asynchronous section of the power-on sequence or the power-off sequence, the first data driver 221 outputs the first data voltage Vdata1, and the second data driver 222 cannot output the second data voltage Vdata2 that is the same as the first data voltage Vdata1. As a result, a voltage potential difference occurs between the upper and lower ends of the channel, which may cause an overcurrent.

[0225] In contrast, in this embodiment, as described above, the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are synchronized to generate the synchronous lock signal LCKS. Therefore, the outputs of the first data driver 221 and the second data driver 222 are turned off during the asynchronous period between the first output lock signal LCK_out1 and the second output lock signal LCK_out2, and the outputs of the first data driver 221 and the second data driver 222 are enabled during the period when both are in the locked state. As a result, the potential difference in the output voltage between the upper and lower ends of the channel is alleviated or reduced during the asynchronous period, thereby limiting overcurrent caused by the potential difference.

[0226] In addition, if at least one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is in a lock failure state, the timing control unit 240 can turn off the transmission of the image data Do during the lock failure period, and as a result, the output of the data voltages Vdata1 and Vdata2 from the first data driver 221 and the second data driver 222 can be turned off during that period.

[0227] For example, as shown in FIG. 8, if the output second lock signal LCK_out2 is in a lock failure state in a 120 Hz driven refresh frame FRr (i.e., if the second data driver 222 fails to lock), the synchronous lock signal LCKS may have a low level during the refresh frame FRr in which the lock failure occurs.

[0228] In this way, when the output second lock signal LCK_out2 is in the lock failure state, the timing control unit 240 can turn off the transmission of the video data Do during the lock failure period. Also, in the period when the output second lock signal LCK_out2 switches to the high-level locked state and the synchronous lock signal LCKS is in the high-level locked state, the timing control unit 240 can transmit the video data Do according to the locked state of the synchronous lock signal LCKS.

[0229] In this way, during the period when the output second lock signal LCK_out2 is in an abnormal lock failure state, the transmission of the video data Do is turned off, and the output of the first data voltage Vdata1 and the second data voltage Vdata2 of the preceding and succeeding stages is turned off, and during the period when the normal lock state is maintained, the transmission of the video data Do is performed, and the same first data voltage Vdata1 and second data voltage Vdata2 can be synchronized and output.

[0230] As a result, during the locking failure period, the first data driver 221 in the front stage outputs normally, and the second data driver 222 in the rear stage outputs abnormally, which generates a potential difference in the output voltage between the upper and lower ends of the channel, thereby mitigating or preventing the occurrence of overcurrent. As a result, it is possible to mitigate or prevent the data IC (DIC) from overheating or burning due to the overcurrent that occurs during locking failure.

[0231] In this regard, referring to the comparative example of Figure 9, if either the output first lock signal LCK_out1 or the output second lock signal LCK_out2 is in a locked state, the display device of the comparative example transmits image data Do to the first data driver 221 and the second data driver 222 regardless of whether a lock failure occurs, and the first data driver 221 and the second data driver 222 can output the corresponding data voltages Vdata1 and Vdata2.

[0232] In the driving of this comparative example, the video data Do is transmitted even during the locking failure period, and the first data driver 221 normally outputs the first data voltage Vdata1, while the second data driver 222 cannot normally output the second data voltage Vdata2, which is the same as the first data voltage Vdata1, and outputs an abnormal voltage. For example, noise occurs in the output voltage of the second data driver 222 due to the locking failure.

[0233] As a result, a potential difference occurs in the output voltage between the upper and lower ends of the channel, which may cause an overcurrent. For example, the output voltage of the second data driver 222 is fixed to the source driving voltage SVDD, which may cause an overcurrent to flow to the first data driver 221.

[0234] In contrast, in this embodiment, as described above, the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are synchronized to generate the synchronized lock signal LCKS. Therefore, during the lock failure period of the second output lock signal LCK_out2, the outputs of the first data driver 221 and the second data driver 222 are turned off. As a result, during the lock failure period, the potential difference in the output voltage between the upper and lower ends of the channel is alleviated or reduced, thereby limiting overcurrent caused by the potential difference.

[0235] As described above, in this embodiment of the present invention, the first and second input lock signals are input to the front and rear data drivers of the double bank structure, and the first and second output lock signals output from the front and rear data drivers are compared by a comparator to generate a synchronized synchronous lock signal, which is then provided to the timing controller. The timing controller adjusts the transmission timing of the video data based on the synchronous lock signal, thereby synchronizing the output of the data voltages from the front and rear data drivers.

[0236] This makes it possible to improve the phenomenon in which a potential difference occurs in the output voltage between the upper and lower ends of the channel in an asynchronous section or a section where locking has failed, resulting in the generation of an overcurrent.

[0237] As a result, it is possible to prevent overheating and burning of the data ICs in the data drivers at the front and rear stages due to overcurrent, and also to prevent image quality defects such as block dim when the asynchronous interval is long.

[0238] The above-described embodiments of the present invention are merely examples, and the present invention can be freely modified without departing from the technical spirit of the present invention. Therefore, the present invention includes modifications of the present invention within the scope of the claims and their equivalents. [Explanation of symbols]

[0239] 10…Display device 100...Display panel 210...Gate driver 220...Data driver 221...first data driver 222...second data driver 240...Timing control section 250…Comparison circuit 280...Power supply section AA…display area NA…Hidden area GL...Gate wiring DL: Data wiring P...pixel DIC: Data IC DIC1: First data IC DIC2: Second data IC LCK_in: Input lock signal LCK_in1: Input 1st lock signal LCK_in2: Input second clock signal LCK_out...Output lock signal LCK_out1: Output 1st lock signal LCK_out2: Output second lock signal LCKS: Synchronous lock signal

Claims

1. a display panel including a plurality of data lines and pixels connected to the data lines; a first data driver including a plurality of first data ICs connected to one ends of the plurality of data lines; a second data driver including a plurality of second data ICs connected to the other ends of the plurality of data lines; a timing control unit that provides an input first lock signal and an input second lock signal to the first data driver and the second data driver, respectively; a comparison circuit that receives the first and second output lock signals generated from the first and second data drivers, respectively, according to the first and second input lock signals, compares the first and second output lock signals, and provides a synchronized synchronous lock signal to the timing control unit; The timing control unit transmits image data to the first data driver and the second data driver in a locked state of the synchronous lock signal, and the first data driver and the second data driver output data voltages.

2. During a period in which the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, the synchronous lock signal has an unlock state; The display device of claim 1 , wherein, in the unlocked state of the synchronous lock signal, the timing control unit turns off transmission of the video data, and outputs of the first data driver and the second data driver are turned off.

3. During a period in which at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronous lock signal has an unlock state; The display device of claim 1 , wherein, in the unlocked state of the synchronous lock signal, the timing control unit turns off transmission of the video data, and outputs of the first data driver and the second data driver are turned off.

4. 3. The display device according to claim 2, wherein, in a section in which the lock states of the output first lock signal and the output second lock signal become asynchronous with each other, one of the output first lock signal and the output second lock signal is in a locked state and the other is in an unlocked state.

5. 4. The display device according to claim 3, wherein at least one of the output first lock signal and the output second lock signal has an abnormal waveform in a lock failure state.

6. When the input first lock signal is input, the plurality of first data ICs operate sequentially to output lock signals, the lock signal output from the first data IC is input to the next first data IC, and the lock signal output from the last first data IC is the output first lock signal; 2. The display device of claim 1, wherein when the input second lock signal is input, the plurality of second data ICs operate sequentially and output lock signals, the lock signal output from the second data IC is input to the next second data IC, and the lock signal output from the last second data IC is the output second lock signal.

7. the first data driver includes a first source board to which the plurality of first data ICs are connected; the second data driver includes a second source board to which the plurality of second data ICs are connected; the first source board includes a first lock signal wiring for transmitting a lock signal input to and output from the plurality of first data ICs; The display device of claim 6 , wherein the second source board includes second lock signal wiring that transmits lock signals input to and output from the plurality of second data ICs.

8. The display device of claim 1 , wherein the pixel comprises a light emitting diode.

9. The display device of claim 1 , wherein in a locked state of the synchronous lock signal, the first data driver and the second data driver output data voltages synchronized with each other.

10. a display panel including a plurality of data lines and pixels connected to the data lines; a first data driver including a plurality of first data ICs connected to one ends of the plurality of data lines; a second data driver including a plurality of second data ICs connected to the other ends of the plurality of data lines; a timing control unit that provides an input first lock signal and an input second lock signal to the first data driver and the second data driver, respectively; a comparison circuit that receives the first and second output lock signals generated from the first and second data drivers, respectively, according to the first and second input lock signals, compares the first and second output lock signals, and provides a synchronized synchronous lock signal to the timing control unit; The display device, wherein the data voltage outputs of the first data driver and the second data driver are adjusted according to the synchronous lock signal.

11. The display device of claim 10 , wherein in the locked state of the synchronous lock signal, the first data driver and the second data driver output data voltages synchronized with each other.

12. During a period in which the lock states of the output first lock signal and the output second lock signal are asynchronous with each other, the synchronous lock signal has an unlock state; The display device of claim 10 , wherein outputs of the first data driver and the second data driver are turned off when the synchronous lock signal is in an unlocked state.

13. During a period in which at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronous lock signal has an unlock state; The display device of claim 10 , wherein outputs of the first data driver and the second data driver are turned off when the synchronous lock signal is in an unlocked state.

14. 13. The display device of claim 12, wherein, in a section in which the lock states of the output first lock signal and the output second lock signal become asynchronous with each other, one of the output first lock signal and the output second lock signal is in a locked state and the other is in an unlocked state.

15. 14. The display device of claim 13, wherein at least one of the output first lock signal and the output second lock signal has an abnormal waveform in a lock failure state.

16. the first data driver includes a first source board to which the plurality of first data ICs are connected; the second data driver includes a second source board to which the plurality of second data ICs are connected; the first source board includes a first lock signal wiring for transmitting a lock signal input to and output from the plurality of first data ICs; The display device of claim 10 , wherein the second source board includes second lock signal wiring that transmits lock signals input to and output from the plurality of second data ICs.

17. The display device of claim 10 , wherein the pixel comprises a light emitting diode.

18. The display device of claim 10, wherein the data voltages output from the first data driver and the second data driver are the same.

Images