Semiconductor device

Abstract

To provide a technology that can enhance the magnetic coupling effect.SOLUTION: A semiconductor device includes a P-electrode having a first main surface portion and a first external connection portion, an N-electrode having a second main surface portion and a second external connection portion, and a C-electrode having a third main surface portion and a third-1 external connection portion and a third-2 external connection portion. The first external connection portion and the third-1 external connection portion face each other in the direction in which the first main surface portion and the third main surface portion face each other, and the second external connection portion and the third-2 external connection portion face each other in the direction in which the second main surface portion and the third main surface portion face each other.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] In a semiconductor device in which a three-level circuit is housed in one package, it has been proposed to connect three-level DC potentials and multiple semiconductor elements with multiple electrodes, and to arrange the main surfaces of the multiple electrodes so that they face each other (for example, Patent Document 1). With this technology, a magnetic coupling effect that reduces inductance occurs due to the current passing through the opposing main surfaces, making it possible to suppress surge voltages caused by the interaction between the inductance and abrupt current changes when switching the semiconductor elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-155287 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the prior art, the position of the external connection portion, which is part of the electrode and is connected to a smoothing capacitor or the like, is not optimized, so there is room for improvement in the magnetic coupling effect that reduces inductance.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a technique that can enhance the magnetic coupling effect. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element included in a three-level circuit, a first main surface portion, a first external connection portion connected to a positive electrode of a DC circuit, a P-electrode connecting the positive electrode and the first semiconductor element, a second main surface portion, a second external connection portion connected to a negative electrode of the DC circuit, an N-electrode connecting the negative electrode and the second semiconductor element, a third main surface portion, and a 3-1 external connection portion connected to a neutral point of the DC circuit. and a 3-2 external connection portion, and a C electrode connecting the neutral point and the third semiconductor element, wherein the first main surface portion and the second main surface portion each face and overlap the third main surface portion, the first external connection portion and the 3-1 external connection portion face each other in the direction in which the first main surface portion and the third main surface portion face each other, and the second external connection portion and the 3-2 external connection portion face each other in the direction in which the second main surface portion and the third main surface portion face each other. [Effects of the Invention]

[0007] According to the present disclosure, the first external connection portion and the 3-1 external connection portion face each other in the direction in which the first main surface portion and the third main surface portion face each other, and the second external connection portion and the 3-2 external connection portion face each other in the direction in which the second main surface portion and the third main surface portion face each other. This configuration can enhance the magnetic coupling effect. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing a three-level circuit including a semiconductor device according to a first embodiment. [Figure 2] 1 is a perspective view schematically showing the configuration of a semiconductor device according to a first embodiment. [Figure 3] 1A and 1B are a perspective view and a front view schematically showing a configuration of a part of a semiconductor device according to a first embodiment. [Figure 4] 10A and 10B are a perspective view and a front view schematically showing a configuration of a part of a semiconductor device according to a second embodiment. [Figure 5] 3A and 3B are a perspective view and a front view schematically showing a first related configuration. [Figure 6] 10A and 10B are a perspective view and a front view schematically showing a second related configuration. [Figure 7] 11A and 11B are a perspective view and a front view schematically showing a configuration of a part of a semiconductor device according to a third embodiment. [Figure 8] 10A and 10B are a perspective view and a front view schematically showing a configuration of a part of a semiconductor device according to a fourth embodiment. [Figure 9] 13A and 13B are a perspective view and a front view schematically showing a configuration of a part of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," and "right" may not necessarily correspond to positions and directions in actual implementation.

[0010] <First Embodiment> 1 is a circuit diagram showing a three-level circuit including a semiconductor device according to the present embodiment 1. The semiconductor device according to the present embodiment 1 includes a first semiconductor element 111, a second semiconductor element 112, a third semiconductor element 113, a fourth semiconductor element 114, a P electrode P, an N electrode N, a C electrode C, an AC electrode AC, an insulating substrate and a package which will be described later.

[0011] The first to fourth semiconductor elements 111 to 114 include IGBTs (Insulated Gate Bipolar Transistors) 111a to 114a and FWDs (Free Wheeling Diodes) 111b to 114b connected in anti-parallel to the IGBTs 111a to 114a, respectively.

[0012] The first to fourth semiconductor elements 111 to 114 may include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or RC-IGBTs (Reverse Conducting IGBTs) instead of the IGBTs 111a to 114a. The FWDs 111b to 114b are, for example, SBDs (Schottky Barrier Diodes) or PNDs (PN junction diodes).

[0013] The first to fourth semiconductor elements 111 to 114 may be made of silicon (Si) or a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or diamond. If the first to fourth semiconductor elements 111 to 114 are made of a wide bandgap semiconductor, the first to fourth semiconductor elements 111 to 114 can operate stably under high temperatures and high voltages, and the first to fourth semiconductor elements 111 to 114 can switch at high speed. The first to fourth semiconductor elements 111 to 114 may be made of a single semiconductor chip, or may be made of multiple semiconductor chips connected in parallel.

[0014] One end of the set of series-connected smoothing capacitors 301 corresponds to the positive electrode of the DC circuit and has a positive electrode potential 121. The other end of the set of series-connected smoothing capacitors 301 corresponds to the negative electrode of the DC circuit and has a negative electrode potential 122. The connection point between the smoothing capacitors 301 corresponds to the neutral point of the DC circuit and has a neutral point potential 123. A connection point 115 connecting the first semiconductor element 111, the second semiconductor element 112, and the fourth semiconductor element 114 has an AC potential 124.

[0015] The collector of the IGBT 111a is connected to a positive electrode having a positive electrode potential 121. The emitter of the IGBT 111a is connected to a collector of the IGBT 112a via a connection point 115. The emitter of the IGBT 112a is connected to a negative electrode having a negative electrode potential 122. As described above, the first semiconductor element 111 and the second semiconductor element 112 are connected in series between the positive electrode having the positive electrode potential 121 and the negative electrode having the negative electrode potential 122.

[0016] The emitter of the IGBT 113a is connected to a neutral point having a neutral point potential 123. The collector of the IGBT 113a is connected to the collector of the IGBT 114a. The emitter of the IGBT 114a is connected to a connection point 115 between the first semiconductor element 111 and the second semiconductor element 112. As described above, the third semiconductor element 113 and the fourth semiconductor element 114 are connected in series between the neutral point having the neutral point potential 123 and the connection point 115.

[0017] The three-level circuit configured as described above outputs a stepped voltage by appropriately selecting the voltage clamped by the smoothing capacitor 301 from the third semiconductor element 113 and the fourth semiconductor element 114. While the above description has been given of a case where the semiconductor device is a T-type three-level circuit in which the first to fourth semiconductor elements 111 to 114 are connected in a T-shape, the present invention is not limited to this. For example, the semiconductor device may be an I-type three-level circuit in which four semiconductor elements (e.g., the first to fourth semiconductor elements 111 to 114) are connected in an I-shape and two more semiconductor elements (e.g., the fifth semiconductor element and the sixth semiconductor element) are connected to the neutral point. In this case, the first semiconductor element 111, the second semiconductor element 112, the third semiconductor element 113, and the fourth semiconductor element 114 are connected in series between the positive and negative electrodes. The fifth semiconductor element is connected between the neutral point and the connection point between the first semiconductor element 111 and the second semiconductor element 112, and the sixth semiconductor element is connected between the neutral point and the connection point between the third semiconductor element 113 and the fourth semiconductor element 114.

[0018] Fig. 2 is a perspective view schematically showing the configuration of the semiconductor device according to the first embodiment. A conductive pattern 272 is provided on an insulating substrate 271, and first to fourth semiconductor elements 111 to 114 (not shown in Fig. 2) are provided on the conductive pattern 272. The conductive patterns 272 are selectively connected to each other by wires (not shown) so that the circuit of Fig. 1 is established.

[0019] In addition to the P electrode P, the N electrode N, and the C electrode C, an AC electrode (not shown) that connects the AC potential 124 to an external output circuit is also provided on the conductive pattern 272. The configuration in FIG. 2 is mostly covered by a package (not shown).

[0020] FIG. 3 is a perspective view and a front view showing the configuration of the P-electrode P, the N-electrode N, and the C-electrode C according to the first embodiment.

[0021] As shown in FIG. 3, the P electrode P has a P main surface portion 221 which is a first main surface portion, a P external connection portion 231 which is a first external connection portion, and a P internal connection portion 251 which is a first internal connection portion.

[0022] P external connection portion 231 is provided on the upper side of P main surface portion 221, and is connected to a positive electrode having positive electrode potential 121 in FIG. 1 via external wiring such as a bus bar. P external connection portion 231 is provided with mounting holes 241 for connecting to external wiring with screws. P internal connection portion 251 is provided on the lower side of P main surface portion 221, and is connected to first semiconductor element 111 in FIG. 1 via conductive pattern 272 in FIG. 2. Note that although there is one P external connection portion 231 and one P internal connection portion 251 in the first embodiment, there may be more than one.

[0023] As shown in FIG. 3, the N electrode N has an N principal surface portion 222 which is the second principal surface portion, an N external connection portion 232 which is the second external connection portion, and an N internal connection portion 252 which is the second internal connection portion.

[0024] The N external connection portion 232 is provided on the upper side of the N main surface portion 222, and is connected to the negative electrode having the negative electrode potential 122 in FIG. 1 via external wiring such as a bus bar. The N external connection portion 232 is provided with a mounting hole 242 for connecting to external wiring with a screw. The N internal connection portion 252 is provided on the lower side of the N main surface portion 222, and is connected to the second semiconductor element 112 in FIG. 1 via the conductive pattern 272 in FIG. 2. Note that although the number of each of the N external connection portion 232 and the N internal connection portion 252 is one in the first embodiment, there may be more than one.

[0025] As shown in Figure 3, the C electrode C has a C main surface portion 223 which is the third main surface portion, a first C external connection portion 233a which is the 3-1 external connection portion, a second C external connection portion 233b which is the 3-2 external connection portion, and a C internal connection portion 253 which is the third internal connection portion.

[0026] The first C external connection portion 233a and the second C external connection portion 233b are provided on the upper side of the C main surface portion 223 and are connected to the neutral point having the neutral point potential 123 in FIG. 1 via external wiring such as a bus bar. The first C external connection portion 233a and the second C external connection portion 233b are provided with mounting holes 243a and 243b, respectively, for connecting to external wiring with screws. The C internal connection portion 253 is provided on the lower side of the C main surface portion 223 and is connected to the third semiconductor element 113 in FIG. 1 via the conductive pattern 272 in FIG. 2.

[0027] In the first embodiment, the number of each of the first C external connection portion 233a and the second C external connection portion 233b is one, but this is not limited to this. The number of the first C external connection portion 233a may be the same as the number of the P external connection portions 231, and the number of the second C external connection portions 233b may be the same as the number of the N external connection portions 232. In the first embodiment, the number of the C internal connection portion 253 is one, but there may be more than one as in the third embodiment described later.

[0028] 3, each of the P principal surface portion 221 and the N principal surface portion 222 faces and overlaps with the C principal surface portion 223. In the first embodiment, the P principal surface portion 221 and the N principal surface portion 222 face one surface of the C principal surface portion 223, and the P principal surface portion 221 and the N principal surface portion 222 are close to each other. Each of the P principal surface portion 221 to the C principal surface portion 223 may be substantially flat, and may be partially bent to facilitate connection with the conductive pattern 272 and the bus bar.

[0029] The P external connection portion 231 and the first C external connection portion 233a face each other in a direction 262 in which the P main surface portion 221 and the C main surface portion 223 face each other, and the P external connection portion 231 and the first C external connection portion 233a are positioned at the same position on the horizontal axis 261. The mounting holes 241 and 243a are also positioned at the same position on the horizontal axis 261.

[0030] The N external connection portion 232 and the second C external connection portion 233b face each other in a direction 263 in which the N main surface portion 222 and the C main surface portion 223 face each other, and the N external connection portion 232 and the second C external connection portion 233b are positioned at the same position on the horizontal axis 261. In addition, the mounting hole 242 and the mounting hole 243b are positioned at the same position on the horizontal axis 261.

[0031] In this embodiment 1, the P external connection portion 231 and the N external connection portion 232 are arranged in a row along the horizontal axis 261, and the first C external connection portion 233a and the second C external connection portion 233b are arranged in another row along the horizontal axis 261.

[0032] When multiple sets of P external connection portion 231 and first C external connection portion 233a are provided, it is preferable that in each set, P external connection portion 231 and first C external connection portion 233a face each other in direction 262. Similarly, when multiple sets of N external connection portion 232 and second C external connection portion 233b are provided, it is preferable that in each set, N external connection portion 232 and second C external connection portion 233b face each other in direction 263. Furthermore, P external connection portion 231 and N external connection portion 232 may or may not be adjacent to each other.

[0033] <Summary of the First Embodiment> In the first embodiment, each of the P principal surface portion 221 and the N principal surface portion 222 faces and overlaps with the C principal surface portion 223. With such a configuration, the magnetic coupling effect can reduce the inductance between the positive pole and the neutral point, and between the neutral point and the negative pole, and therefore the surge voltage generated when the semiconductor element is switched can be reduced.

[0034] Furthermore, in the first embodiment, the P external connection portion 231 and the first C external connection portion 233a face each other in the direction 262, and the N external connection portion 232 and the second C external connection portion 233b face each other in the direction 263. With this configuration, the input and output ports of the current paths of the P electrode P and the C electrode C overlap each other, and the input and output ports of the current paths of the C electrode C and the N electrode N overlap each other, so that the magnetic coupling effect can be enhanced and the inductance and surge voltage can be further reduced. Similarly, the input and output ports of the current paths of the bus bars can be expected to overlap each other, so that a further improvement in the magnetic coupling effect can be expected.

[0035] Furthermore, in the first embodiment, the P external connection portion 231 and the N external connection portion 232 are arranged in a line, and the first C external connection portion 233a and the second C external connection portion 233b are arranged in another line. With this configuration, the bus bars connected to the first C external connection portion 233a and the second C external connection portion 233b can be formed into a simple flat plate shape. As a result, the manufacture of the external wiring can be simplified and the cost can be reduced.

[0036] <Embodiment 2> FIG. 4 is a perspective view and a front view showing the configuration of a P-electrode P, an N-electrode N, and a C-electrode C according to the second embodiment.

[0037] In this embodiment 2, the P external connection portion 231 and the second C external connection portion 233b are arranged in a row along the horizontal axis 261, and the N external connection portion 232 and the first C external connection portion 233a are arranged in another row along the horizontal axis 261.

[0038] This allows the P principal surface portion 221 to face a first surface of the C principal surface portion 223, and the N principal surface portion 222 to face a second surface opposite the first surface of the C principal surface portion 223. In other words, it is possible to increase the area where the P principal surface portion 221 overlaps with the C principal surface portion 223 and the area where the N principal surface portion 222 overlaps with the C principal surface portion 223. This increases the magnetic coupling effect and further reduces the inductance between the current paths between the P electrode P and the C electrode C and the current paths between the C electrode C and the N electrode N, thereby further reducing the surge voltage.

[0039] In addition, in this embodiment 2, as shown in the front view of the P electrode P, the N electrode N, and the C electrode C, the C internal connection portion 253 is provided closer to the center of each main surface portion than the P internal connection portion 251 and the N internal connection portion 252.

[0040] 5 is a perspective view and a front view schematically showing a configuration (hereinafter referred to as a "first related configuration") related to the configurations of the P electrode P, the N electrode N, and the C electrode C according to Embodiment 2. In the first related configuration, as shown in the front view of the P electrode P, the N electrode N, and the C electrode C in FIG. 5, the P internal connection portion 251 or the N internal connection portion 252 is provided closer to the center of each main surface portion than the C internal connection portion 253.

[0041] 5, the distance 611 between the P internal connection portion 251 and the C internal connection portion 253 is greater than the distance 612 between the C internal connection portion 253 and the N internal connection portion 252. This increases the difference between the magnetic coupling effect between the P electrode P and the C electrode C and the magnetic coupling effect between the C electrode C and the N electrode N. As a result, the difference between the inductance of the current path between the P electrode P and the C electrode C and the inductance of the current path between the C electrode C and the N electrode N increases, resulting in a larger difference in surge voltages generated in different operation modes.

[0042] In contrast to this, in the second embodiment, as shown in the front view of the P electrode P, the N electrode N, and the C electrode C in Fig. 4, the C internal connection portion 253 is provided closer to the center of each main surface portion than the P internal connection portion 251 and the N internal connection portion 252 in front view. With this configuration, it is possible to reduce the difference between the distance 613 between the P internal connection portion 251 and the C internal connection portion 253 and the distance 614 between the C internal connection portion 253 and the N internal connection portion 252. As a result, it is possible to reduce the difference in surge voltages generated in different operation modes, making it unnecessary or easy to optimize the drive conditions for each operation mode.

[0043] <Third Embodiment> 6 is a perspective view and a front view schematically showing a configuration (hereinafter referred to as a "second related configuration") related to the configuration of the P electrode P, the N electrode N, and the C electrode C according to the third embodiment. In the second related configuration, either the multiple P internal connection parts 251 or the multiple N internal connection parts 252 is provided closer to the center of each main surface part than the multiple C internal connection parts 253 in a front view.

[0044] 6 flows from the C internal connection portion 253 and passes outside the current region 711 of the current flowing through the P electrode P. Therefore, the overlapping region between the current region 711 flowing through the P electrode P and the current region flowing through the C electrode C is small, and the inductance reduction effect due to magnetic coupling is also small.

[0045] 7A and 7B are perspective and front views schematically illustrating the configuration of a P electrode P, an N electrode N, and a C electrode C according to the third embodiment. In the third embodiment, the plurality of C internal connections 253 are provided closer to the center of each main surface than the plurality of P internal connections 251 and the plurality of N internal connections 252 when viewed from the front. This configuration increases the area where the current region 811 flowing through the P electrode P and the current region flowing through the C electrode C overlap, thereby enhancing the effect of reducing inductance due to magnetic coupling between the P electrode P and the C electrode C, thereby reducing surge voltage. The same applies to the magnetic coupling between the C electrode C and the N electrode N.

[0046] <Fourth Embodiment> 8 is a perspective view and a front view showing a schematic configuration of a P electrode P, an N electrode N, and a C electrode C according to the fourth embodiment. In the fourth embodiment, a slit 911 is provided in the P main surface portion 221 extending in the horizontal direction. It is sufficient that one or more slits 911 are provided in at least one of the P main surface portion 221, the N main surface portion 222, and the C main surface portion 223 extending in the horizontal direction. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more types extracted from the group A, B, C, ..., and Z.

[0047] With this configuration, as shown by the arrow in Fig. 8, the current path of the current is changed by the slit 911 so that it passes through the vicinity of the center of the electrode where the slit 911 is provided. This makes it possible to increase the overlapping area between the current area of ​​the current flowing through the P electrode P and the current area of ​​the current flowing through the C electrode C, for example, or to increase the amount of current passing through the overlapping area. As a result, the inductance reduction effect due to the magnetic coupling between the P electrode P and the C electrode C can be enhanced, thereby reducing the surge voltage. The same applies to the magnetic coupling between the C electrode C and the N electrode N.

[0048] <Fifth Embodiment> 9 is a perspective view and a front view showing a schematic configuration of a P electrode P, an N electrode N, and a C electrode C according to the fifth embodiment. In the fifth embodiment, one or more (one in FIG. 9) P external connection parts 231 are generally line-symmetrical with respect to, for example, a vertical axis 1011 of the electrode plane as the axis of symmetry. In other words, one or more (one in FIG. 9) P external connection parts 231 are generally line-symmetrical with respect to the vertical axis 1011, or one or more (one in FIG. 9) P external connection parts 231 are generally substantially line-symmetrical with respect to the vertical axis 1011.

[0049] Similarly, one or more (two in Figure 9) N external connection parts 232 have overall linear symmetry, and one or more (one in Figure 9) first C external connection parts 233a and one or more (two in Figure 9) second C external connection parts 233b have overall linear symmetry.

[0050] This configuration can reduce bias in the current paths of the currents flowing through the P electrode P and the N electrode N. This increases the inductance reduction effect due to magnetic coupling with the C electrode C, thereby reducing surge voltage. Furthermore, because the difference in inductance between each current path can be reduced, the current balance between multiple chips can be improved, reducing the resulting bias in chip temperature.

[0051] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0052] Various aspects of the present disclosure are summarized below as appendices.

[0053] (Appendix 1) a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element included in a three-level circuit; a P electrode having a first main surface portion and a first external connection portion connected to a positive electrode of a DC circuit, the P electrode connecting the positive electrode and the first semiconductor element; an N electrode having a second main surface portion and a second external connection portion connected to a negative electrode of the DC circuit, the N electrode connecting the negative electrode and the second semiconductor element; a C electrode having a third principal surface portion, a 3-1 external connection portion and a 3-2 external connection portion connected to a neutral point of the DC circuit, and connecting the neutral point and the third semiconductor element; Equipped with the first main surface portion and the second main surface portion each face the third main surface portion and overlap with each other; the first external connection portion and the 3-1 external connection portion face each other in a direction in which the first main surface portion and the third main surface portion face each other, The semiconductor device, wherein the second external connection portion and the 3-2 external connection portion face each other in a direction in which the second main surface portion and the third main surface portion face each other.

[0054] (Appendix 2) 10. The semiconductor device according to claim 1, the first semiconductor element and the second semiconductor element are connected in series between the positive electrode and the negative electrode, The semiconductor device, wherein the third semiconductor element and the fourth semiconductor element are connected in series between the neutral point and a connection point between the first semiconductor element and the second semiconductor element.

[0055] (Appendix 3) 10. The semiconductor device according to claim 1, Further comprising a fifth semiconductor element and a sixth semiconductor element included in the three-level circuit, the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are connected in series between the positive electrode and the negative electrode; the fifth semiconductor element is connected between the neutral point and a connection point between the first semiconductor element and the second semiconductor element, The sixth semiconductor element is connected between the neutral point and a connection point between the third semiconductor element and the fourth semiconductor element.

[0056] (Appendix 4) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, the first external connection portion and the second external connection portion are arranged in a line, A semiconductor device in which the 3-1 external connection portion and the 3-2 external connection portion are arranged in separate rows.

[0057] (Appendix 5) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, the first external connection portion and the third-second external connection portion are arranged in a line, The semiconductor device, wherein the second external connection portion and the 3-1 external connection portion are arranged in separate rows.

[0058] (Appendix 6) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 5, the P electrode, the N electrode, and the C electrode further have a first internal connection portion, a second internal connection portion, and a third internal connection portion connected to the first semiconductor element, the second semiconductor element, and the third semiconductor element, respectively; The semiconductor device, wherein the third internal connection portion is provided closer to the center than the first internal connection portion and the second internal connection portion when viewed from the front.

[0059] (Appendix 7) 7. The semiconductor device according to claim 6, A semiconductor device, wherein the third internal connection portions are provided closer to the center than the first internal connection portions and the second internal connection portions when viewed from the front.

[0060] (Appendix 8) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, The semiconductor device has a slit extending in a horizontal direction on at least one of the first main surface portion, the second main surface portion, and the third main surface portion.

[0061] (Appendix 9) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 8, A semiconductor device in which one or more of the first external connection portions have overall line symmetry, one or more of the second external connection portions have overall line symmetry, and one or more of the 3-1 external connection portions and one or more of the 3-2 external connection portions have overall line symmetry. [Explanation of symbols]

[0062] 111 first semiconductor element, 112 second semiconductor element, 113 third semiconductor element, 114 fourth semiconductor element, 115 connection point, 221 P main surface section, 222 N main surface section, 223 C main surface section, 231 P external connection section, 232 N external connection section, 233a 1C external connection section, 233b 2C external connection section, 251 P internal connection section, 252 N internal connection, 253 C internal connection, 911 slit, PP electrode, NN electrode, CC electrode.

Claims

1. a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element included in a three-level circuit; a P-electrode having a first main surface portion and a first external connection portion connected to a positive electrode of a DC circuit, the P-electrode connecting the positive electrode and the first semiconductor element; an N-electrode having a second main surface portion and a second external connection portion connected to a negative electrode of the DC circuit, the N-electrode connecting the negative electrode and the second semiconductor element; a C electrode having a third main surface portion, a 3-1 external connection portion and a 3-2 external connection portion connected to a neutral point of the DC circuit, and connecting the neutral point and the third semiconductor element; Equipped with the first main surface portion and the second main surface portion each face the third main surface portion and overlap with each other; the first external connection portion and the 3-1 external connection portion face each other in a direction in which the first main surface portion and the third main surface portion face each other, The second external connection portion and the 3-2 external connection portion face each other in a direction in which the second main surface portion and the third main surface portion face each other.

2. 2. The semiconductor device according to claim 1, The first semiconductor element and the second semiconductor element are connected in series between the positive electrode and the negative electrode, The semiconductor device, wherein the third semiconductor element and the fourth semiconductor element are connected in series between the neutral point and a connection point between the first semiconductor element and the second semiconductor element.

3. 2. The semiconductor device according to claim 1, further comprising a fifth semiconductor element and a sixth semiconductor element included in the three-level circuit; The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are connected in series between the positive electrode and the negative electrode, the fifth semiconductor element is connected between the neutral point and a connection point between the first semiconductor element and the second semiconductor element, The sixth semiconductor element is connected between the neutral point and a connection point between the third semiconductor element and the fourth semiconductor element.

4. 4. The semiconductor device according to claim 1, the first external connection portion and the second external connection portion are arranged in a line, The semiconductor device, wherein the third-1 external connection portion and the third-2 external connection portion are arranged in separate rows.

5. 4. The semiconductor device according to claim 1, the first external connection portion and the third-second external connection portion are arranged in a line, The semiconductor device, wherein the second external connection portion and the 3-1st external connection portion are arranged in separate rows.

6. 4. The semiconductor device according to claim 1, the P electrode, the N electrode, and the C electrode further have a first internal connection portion, a second internal connection portion, and a third internal connection portion connected to the first semiconductor element, the second semiconductor element, and the third semiconductor element, respectively; The semiconductor device, wherein the third internal connection portion is provided closer to the center than the first internal connection portion and the second internal connection portion when viewed from the front.

7. 7. The semiconductor device according to claim 6, A semiconductor device, wherein the third internal connection portions are provided closer to the center than the first internal connection portions and the second internal connection portions when viewed from the front.

8. 4. The semiconductor device according to claim 1, A semiconductor device, wherein a slit is provided in at least one of the first main surface portion, the second main surface portion, and the third main surface portion, extending in a horizontal direction.

9. 4. The semiconductor device according to claim 1, A semiconductor device in which one or more of the first external connection parts have line symmetry overall, one or more of the second external connection parts have line symmetry overall, and one or more of the 3-1 external connection parts and one or more of the 3-2 external connection parts have line symmetry overall.

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