Voltage controlled oscillator

Abstract

To provide a voltage controlled oscillator capable of suppressing jitter due to disturbance in a frequency range of a wide band, in a voltage controlled oscillator for outputting a multi-phase clock signal.SOLUTION: A voltage controlled oscillator includes: a ring oscillator configured by connecting a plurality of delay blocks each of which has a plurality of inverting elements and a stage number selection part for selecting the stage number of the inverting elements connected in series between input and output based on a stage number selection signal for selecting the stage number of inverting elements to be enabled, for outputting multi-phase clock signals at a frequency according to a control voltage from each connection point between the plurality of delay blocks; and a stage number determination part for determining the stage number of the inverting elements to be enabled at each of the plurality of delay blocks based on a slew rate of the multi-phase clock signal, and for outputting the stage number selection signal with the determined stage number of the inverting elements to the stage number selection part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to voltage controlled oscillators. [Background technology]

[0002] Patent documents 1 and 2 describe voltage-controlled oscillators that output a single clock signal and switch the number of stages of inverting elements that function as delay elements in order to suppress jitter caused by disturbances in a wide frequency range. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 3014566 [Patent Document 2] Patent No. 3769718 Summary of the Invention [Problem to be solved by the invention]

[0004] Voltage-controlled oscillators that output multi-phase clock signals are also required to suppress increases in jitter due to disturbances over a wide frequency range. However, voltage-controlled oscillators that output multi-phase clock signals must maintain constant the relative phase positions of multiple clock signals, and therefore cannot simply increase or decrease the number of stages of inverting elements that function as delay elements, as is the case with voltage-controlled oscillators that output a single clock signal.

[0005] An object of the present disclosure is to provide a voltage-controlled oscillator that outputs multi-phase clock signals and suppresses jitter caused by disturbances over a wide frequency range. [Means for solving the problem]

[0006] The voltage-controlled oscillator of the present invention comprises a ring oscillator in which a plurality of delay blocks, each including a plurality of inverting elements and a stage selection unit that selects the number of stages of inverting elements connected in series between an input and an output based on a stage selection signal that selects the number of stages of inverting elements to be enabled, are connected in a ring shape, and which outputs a multiphase clock signal having a frequency corresponding to a control voltage from each connection point between the plurality of delay blocks; and a stage determination unit that determines the number of stages of inverting elements to be enabled in each of the plurality of delay blocks based on the slew rate of the multiphase clock signal, and outputs a stage selection signal of the determined number of stages of inverting elements to the stage selection unit. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a voltage-controlled oscillator according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a delay block of a voltage-controlled oscillator according to an embodiment. [Figure 3] 10A and 10B are diagrams for explaining the effects of the voltage-controlled oscillator according to the embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0008] Next, an embodiment of the present disclosure will be described in detail with reference to the drawings. Fig. 1 is a diagram showing the configuration of a voltage-controlled oscillator according to an embodiment of the present disclosure. Fig. 2 is a diagram showing the configuration of a delay block of the voltage-controlled oscillator according to this embodiment.

[0009] As shown in FIG. 1, the voltage-controlled oscillator of this embodiment includes a ring oscillator 11 having a plurality of delay blocks 12 connected in a ring shape, a VI conversion unit 13, a plurality of current sources 14 connected to each of the plurality of delay blocks 12, a slew rate detection unit 15, a control voltage monitoring unit 16, a stage number determination unit 17, and a counter unit 18.

[0010] The ring oscillator 11 outputs multi-phase clock signals having frequencies corresponding to the control voltage from each connection point between the multiple delay blocks 12. In this embodiment, the ring oscillator 11 includes five delay blocks 12 and outputs five-phase clock signals having phases 1 to 5.

[0011] 2, the delay blocks 12 each include a plurality of inverting elements 21 and a stage number selection unit 22 that selects the number of stages of the inverting elements 21 connected in series between the input and output based on a stage number selection signal that selects the number of stages of the inverting elements 21 to be enabled.

[0012] The inverter elements 21 function as delay elements. The stage number selection unit 22 is configured with a multiplexer. In the delay block 12, the number of stages of inverter elements 21 connected in series between the input and output is configured to be an odd number.

[0013] In this embodiment, as an example, an output signal of one stage of inverting elements 21 is input to input 1 of the stage number selection unit 22. An output signal of three stages of inverting elements 21 is input to input 2 of the stage number selection unit 22. An output signal of (1+(n-2)×2) stages of inverting elements 21 is input to input n-1 of the stage number selection unit 22. An output signal of (1+(n-1)×2) stages of inverting elements 21 is input to input n of the stage number selection unit 22.

[0014] The stage number selection unit 22 outputs one signal from input 1 to input n based on the stage number selection signal. That is, every time the number of stages of the inverting elements to be enabled is changed by one stage, the number of stages of the inverting elements 21 connected in series between the input and output is changed by two stages.

[0015] 1, the VI converter 13 outputs a current corresponding to the control voltage. Each of the current sources 14 supplies a current proportional to the current output from the VI converter 13 to the delay block 12.

[0016] The counter unit 18 counts the number of clock edges of the clock signal (in this embodiment, the clock signal of phase 5) input to the slew rate detection unit 15, and outputs a timing signal that specifies the operation timing to the slew rate detection unit 15, the control voltage monitoring unit 16, and the number of stages determination unit 17 every time a predetermined number of clock edges are reached.

[0017] The slew rate detection unit 15 receives as input one of the multi-phase clock signals (the clock signal of phase 5 in this embodiment), and when the slew rate of the input clock signal falls below a threshold, outputs a signal to the stage number determination unit 17 instructing it to increase the number of stages of inversion elements 21 to be enabled in each of the multiple delay blocks 12.

[0018] In this embodiment, as an example, the slew rate detection unit 15 determines whether the slew rate is below a threshold for each clock edge of the input clock signal, and if it is below the threshold, i.e., if unacceptable jitter is occurring, outputs a counter pulse inside the slew rate detection unit 15.

[0019] Based on the timing signal received at regular intervals from the counter unit 18, when the counter pulses output inside the slew rate detection unit 15 reach a certain number of times within the reception interval of the timing signal, the slew rate detection unit 15 outputs a signal to the stage number determination unit 17 instructing it to increase the number of stages of the inverting elements 21 to be enabled in each of the multiple delay blocks 12.

[0020] Furthermore, the slew rate detection unit 15 resets the number of counter pulses that it measures internally every time it receives a timing signal.

[0021] When the control voltage input to the ring oscillator 11 exceeds the threshold voltage, the control voltage monitoring unit 16 outputs a signal to the stage number determination unit 17 instructing it to reduce the number of stages of the inverting elements 21 to be enabled in each of the multiple delay blocks 12.

[0022] In this embodiment, as an example, the control voltage monitoring unit 16 compares the control voltage with a threshold voltage using an internal comparator, and outputs a pulse inside the control voltage monitoring unit 16 when the control voltage exceeds the threshold voltage.

[0023] Based on the timing signal received at regular intervals from the counter unit 18, when a pulse is output within the control voltage monitoring unit 16 within the reception interval of the timing signal, the control voltage monitoring unit 16 outputs a signal to the stage number determination unit 17 instructing it to reduce the number of stages of the inversion elements 21 to be enabled in each of the multiple delay blocks 12.

[0024] Furthermore, every time the control voltage monitor 16 receives a timing signal from the counter 18, it resets the pulses outputted internally.

[0025] The stage number determination unit 17 determines the number of stages of the inverting elements 21 to be enabled in each of the multiple delay blocks 12 based on the slew rate of the multi-phase clock signal, and outputs a stage number selection signal of the determined number of stages of the inverting elements 21 to the stage number selection unit 22.

[0026] In detail, every time the stage number determination unit 17 receives a timing signal from the counter unit 18, it determines the number of stages of the inverting elements 21 to be enabled based on the signals input from the slew rate detection unit 15 and the control voltage monitoring unit 16. When there is a change in the number of stages of the inverting elements 21 to be enabled, the stage number determination unit 17 outputs a stage number selection signal to the stage number selection unit 22.

[0027] Next, the effects of the voltage controlled oscillator of this embodiment will be described below with reference to Fig. 3, which is a diagram for explaining the effects of the voltage controlled oscillator of this embodiment.

[0028] In the voltage-controlled oscillator of this embodiment, the counter unit 18 counts the number of clock edges of the clock signal (in this embodiment, the clock signal of phase 5) input to the slew rate detection unit 15, and outputs a timing signal that specifies the operation timing to the slew rate detection unit 15, the control voltage monitoring unit 16, and the number-of-stage determination unit 17 every time a predetermined number of clock edges are reached.

[0029] Based on the timing signal received at regular intervals from the counter unit 18, the slew rate detection unit 15 outputs a signal to the stage number determination unit 17 instructing it to increase the number of stages of inversion elements 21 to be enabled in each of the multiple delay blocks 12 when the number of times the slew rate of the input clock signal falls below a threshold, i.e., the number of times unacceptable jitter occurs, reaches a certain number within the timing signal reception interval.

[0030] Based on the timing signal received at regular intervals from the counter unit 18, the control voltage monitoring unit 16 outputs a signal to the stage number determination unit 17 instructing a reduction in the number of stages of the inverting elements 21 to be enabled in each of the multiple delay blocks 12 when the control voltage input to the ring oscillator 11 exceeds a threshold voltage within the reception interval of the timing signal.

[0031] Every time the stage number determination unit 17 receives a timing signal from the counter unit 18, it determines the number of stages of the inverting elements 21 to be enabled based on the signals input from the slew rate detection unit 15 and the control voltage monitoring unit 16. If there is a change in the number of stages of the inverting elements 21 to be enabled, the stage number determination unit 17 outputs a stage number selection signal to the stage number selection unit 22.

[0032] Specifically, when the stage determination unit 17 receives a signal from the slew rate detection unit 15 instructing it to increase the number of stages of the inverting elements 21 to be activated, the stage determination unit 17 increases the number of stages of the inverting elements to be activated by one stage, in accordance with the timing at which the timing signal is received from the counter unit 18.

[0033] In addition, when the stage number determination unit 17 receives a signal from the control voltage monitoring unit 16 instructing a reduction in the number of stages of the inverting elements 21 to be activated, the stage number determination unit 17 reduces the number of stages of the inverting elements to be activated by one stage, in accordance with the timing at which the timing signal is received from the counter unit 18.

[0034] Furthermore, when the stage number determination unit 17 does not receive a signal from the slew rate detection unit 15 and the control voltage monitoring unit 16, it maintains the number of stages of inverting elements to be enabled in accordance with the timing at which it receives a timing signal from the counter unit 18.

[0035] The stage number determination unit 17 outputs a stage number selection signal to the stage number selection unit 22 when there is a change in the number of stages of inverter elements to be enabled.

[0036] In this embodiment, every time the number of stages of inverting elements to be enabled is changed by one stage, the number of stages of inverting elements 21 connected in series between the input and output of each delay block 12 is changed by two stages.

[0037] In the voltage-controlled oscillator of this embodiment, the above process is repeated every time a timing signal is output from the counter unit 18, thereby autonomously determining the number of stages of inverting elements 21 connected in series between the input and output of each delay block 12.

[0038] Next, the jitter generated in the ring oscillator 11 will be described.

[0039] In the ring oscillator 11, the frequency of the multiphase clock signal output from each connection point between the multiple delay blocks 12 is determined by the amount of current supplied from the current source 14 in response to the control voltage and the number of stages of inverting elements 21 connected in series between the input and output of each delay block 12.

[0040] Here, as shown in the upper part of FIG. 3, it is assumed that when the number of stages of inverting elements 21 enabled between the input and output of the delay block 12 is one, an unacceptable jitter occurs in the ring oscillator 11 due to a disturbance.

[0041] In the voltage controlled oscillator of this embodiment, the number of stages of inverting elements 21 connected in series between the input and output of each delay block 12 is variable.

[0042] If the number of inverter elements 21 connected in series between the input and output of each delay block 12 is increased without changing the frequency of the multiphase clock signal output from the ring oscillator 11, the slew rate per inverter element 21 increases, as shown in the lower part of Figure 3, and as a result, jitter in the ring oscillator 11 can be suppressed.

[0043] In order to increase the number of stages of inverter elements 21 connected in series between the inputs and outputs of each delay block 12 without changing the frequency of the multiphase clock signal output from the ring oscillator 11, the control voltage may be adjusted according to the number of stages of inverter elements 21.

[0044] Furthermore, the frequency of the multiphase clock signal output from the ring oscillator 11 can be changed over a wide band using a control voltage. Regardless of the frequency, jitter in the ring oscillator 11 can be suppressed by adjusting the number of stages of the inverting elements 21 connected in series between the input and output of each delay block 12 as described above.

[0045] As described above, the voltage controlled oscillator of this embodiment can suppress jitter caused by disturbances over a wide frequency range.

[0046] Although the preferred embodiments of the voltage-controlled oscillator of the present disclosure have been described above, the voltage-controlled oscillator of the present disclosure is not limited to the above-described embodiments and may be modified in various ways. [Explanation of symbols]

[0047] 11 Ring Oscillator 12 Delay Block 13 Conversion unit 14 Current source 15 Slew rate detection section 16 Control voltage monitor 17 Number of stages determination section 18 Counter section 21 Inverting element 22 Stage selection section

Claims

1. a ring oscillator in which a plurality of delay blocks, each including a plurality of inverting elements and a stage number selection unit that selects the number of stages of inverting elements connected in series between an input and an output based on a stage number selection signal that selects the number of stages of inverting elements to be enabled, are connected in a ring shape, and which outputs multiphase clock signals having frequencies corresponding to a control voltage from each connection point between the plurality of delay blocks; a stage number determination unit that determines the number of stages of inverter elements to be enabled in each of the plurality of delay blocks based on a slew rate of the multiphase clock signal, and outputs a stage number selection signal representing the determined number of stages of inverter elements to the stage number selection unit; A voltage controlled oscillator comprising:

2. a slew rate detection unit that receives an input of one of the multiphase clock signals, and when the slew rate of the input clock signal falls below a threshold, outputs a signal to the stage number determination unit instructing an increase in the number of stages of inverter elements to be enabled in each of the plurality of delay blocks; a control voltage monitoring unit that outputs a signal to the stage number determining unit to instruct a reduction in the number of stages of inverter elements to be enabled in each of the plurality of delay blocks when a control voltage input to the ring oscillator exceeds a threshold value; The stage number determination unit determines the number of stages of inverter elements to be enabled based on signals input from the slew rate detection unit and the control voltage monitoring unit.

2. The voltage controlled oscillator of claim 1.

3. a counter unit that measures the number of clock edges of the clock signal input to the slew rate detection unit, The slew rate detection unit and the control voltage monitoring unit output a signal instructing an increase or decrease in the number of stages of inverting elements to the stage number determination unit every time a certain number of clock edges are measured in the counter unit.

3. The voltage controlled oscillator according to claim 2.

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