Semiconductor element

Abstract

To provide a semiconductor element with improved electric characteristics.SOLUTION: The present invention provides a semiconductor element. More specifically, the semiconductor element includes a substrate, a source / drain pattern on the substrate, including a first pattern and a second pattern that are separated from each other horizontally, a channel pattern between the first pattern and the second pattern, including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern stacked with a space therebetween, an interlayer insulating film on the source / drain pattern, an active contact penetrating the interlayer insulating film and being in contact with the second pattern, and a back surface contact penetrating the substrate and being in contact with the first pattern. The first pattern has a first dopant concentration. The first dopant concentration can gradually decrease vertically upward with respect to the substrate.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices including field effect transistors. [Background technology]

[0002] Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) field effect transistors (FETs). As the size and design rules of semiconductor devices continue to shrink, the scale-down of MOS field effect transistors is also accelerating. As the size of MOS field effect transistors shrinks, the operating characteristics of semiconductor devices may deteriorate. Therefore, various methods are being researched to overcome the limitations imposed by the high integration of semiconductor devices and to form semiconductor devices with better performance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent No. 11,031,395 B2 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having improved electrical characteristics.

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with improved reliability.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] A semiconductor device according to the present invention may include a substrate; a source / drain pattern on the substrate, the source / drain pattern including a first pattern and a second pattern spaced apart from each other in a horizontal direction; a channel pattern between the first pattern and the second pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern stacked and spaced apart from each other; an interlayer insulating film on the source / drain pattern; an active contact penetrating the interlayer insulating film and contacting the second pattern; and a back contact penetrating the substrate and contacting the first pattern, wherein the first pattern has a first dopant concentration, and the first dopant concentration may gradually decrease vertically upward on the substrate.

[0008] According to another aspect of the present invention, a semiconductor device includes a substrate, a power transmission network layer on a lower surface of the substrate, source / drain patterns on the substrate, and back contacts that penetrate the substrate and electrically connect each of the source / drain patterns to the power transmission network layer, the back contacts including first and second back contacts that are horizontally spaced apart from each other, each of the first and second back contacts including a first portion and a second portion on the first portion, and a width of the first portion that decreases vertically upward on the substrate, and a width of the second portion that is constant and then decreases vertically upward on the substrate.

[0009] According to another aspect of the present invention, a semiconductor device includes a substrate including an insulating layer and an active pattern, a power transmission network layer on a lower surface of the insulating layer, a source / drain pattern on the insulating layer, the source / drain pattern including first and second patterns spaced apart from each other in a horizontal direction, a channel pattern on a side of the source / drain pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and stacked, the plurality of semiconductor patterns including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern, a gate electrode between the plurality of semiconductor patterns, the gate electrode including a first inner electrode, a second inner electrode, and a third inner electrode interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns, and an outer electrode on a top semiconductor pattern, a gate insulating pattern on the gate electrode, and a gate capping layer on an upper surface of the outer electrode. a first interlayer insulating film on the source / drain pattern; a second interlayer insulating film on the first interlayer insulating film and the gate capping pattern; a third interlayer insulating film on the second interlayer insulating film, the third interlayer insulating film including a metal pattern and a via; active contacts penetrating the first and second interlayer insulating films and electrically connecting the second one of the source / drain patterns and the metal pattern; and a back contact penetrating the insulating layer of the substrate and electrically connecting the first one of the source / drain patterns and the power transmission network layer, wherein the first pattern has a first dopant concentration and the second pattern has a second dopant concentration, and the first dopant concentration of a portion of the first pattern adjacent to a side of the first semiconductor pattern may be greater than the second dopant concentration of a portion of the second pattern adjacent to the side of the first semiconductor pattern. [Effects of the Invention]

[0010] The 3D field effect transistor according to the present invention can reduce the parasitic capacitance between the gate electrode and the back contact by forming the back contact at an optimized depth. That is, since the back contact is not deeply recessed in the source / drain pattern, the parasitic capacitance can be reduced, thereby improving the electrical characteristics of the semiconductor device.

[0011] In the 3D field effect transistor according to the present invention, the back contacts can be formed at an optimized depth by performing an ion implantation process on the source / drain patterns from the backside of the substrate before forming the back contacts. That is, the dose and energy of the ion implantation process can be adjusted to selectively activate desired channels among multiple channel layers, so the back contacts do not need to be formed too deep. Because the back contacts are formed at an appropriate depth, deterioration due to stress applied to the source / drain patterns can be prevented, thereby improving the reliability of the semiconductor device. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view illustrating a semiconductor device according to some embodiments of the present invention. [Figure 2A] FIG. 2 is a cross-sectional view corresponding to the line AA' in FIG. [Figure 2B] FIG. 2 is a cross-sectional view corresponding to the line BB′ in FIG. [Figure 2C] FIG. 2 is a cross-sectional view corresponding to the line CC' in FIG. [Figure 2D] FIG. 2 is a cross-sectional view corresponding to the line DD′ in FIG. [Figure 2E] FIG. 2 is a cross-sectional view corresponding to the line EE' in FIG. [Figure 3] 2B is a graph showing dopant concentrations of first and second patterns according to the depth of the source / drain pattern of FIG. 2A. [Figure 4A] 4A to 4C are cross-sectional views for explaining another embodiment of FIG. 2A. [Figure 4B] 4A to 4C are cross-sectional views for explaining another embodiment of FIG. 2A. [Figure 4C] 4A to 4C are cross-sectional views for explaining another embodiment of FIG. 2A. [Figure 5A] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 5B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 6A] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 6B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 7A] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 7B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 7C] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 8A] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 8B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 9A] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 9B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 10] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 11A]5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 11B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 11C] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 12A] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 12B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 12C] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 13A] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 13B] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. [Figure 13C] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more specifically explain the present invention, embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

[0014] Figure 1 is a plan view illustrating a semiconductor device according to some embodiments of the present invention, and Figures 2A to 2E are cross-sectional views corresponding to lines A-A', B-B', C-C', D-D', and E-E' in Figure 1, respectively.

[0015] 1 and 2A to 2E, a substrate 105 including a PMOSFET region PR and an NMOSFET region NR may be provided. For example, the substrate 105 may include a silicon-based insulating layer. In other words, the substrate 105 may be an insulating substrate. For example, the substrate 105 may include at least one of silicon dioxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON). A first active pattern AP1 and a second active pattern AP2 may be provided on the substrate 105. The first active pattern AP1 may be provided on the PMOSFET region PR, and the second active pattern AP2 may be provided on the NMOSFET region NR. In this specification, each of phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C” may include any one or all possible combinations of the items listed in the phrase.

[0016] The PMOSFET region PR and the NMOSFET region NR may each extend in a first direction D1 and may be spaced apart from each other in a second direction D2. The first and second directions D1 and D2 may be parallel to the bottom surface of the substrate 105 or may intersect (e.g., perpendicular to) each other.

[0017] The first and second active patterns AP1 and AP2 may be defined by trenches TR in the substrate 105. In a plan view, the first and second active patterns AP1 and AP2 may be provided on protruding portions of the substrate 105. For example, the first and second active patterns AP1 and AP2 may be protruded in a third direction D3. The third direction D3 may be perpendicular to the bottom surface of the substrate 105.

[0018] An isolation pattern ST may be provided between the first and second active patterns AP1 and AP2 and may fill the trench TR. The isolation pattern ST may surround the first and second active patterns AP1 and AP2. The isolation pattern ST may include an insulating material. For example, the isolation pattern ST may include silicon oxide (SiO2).

[0019] The first channel pattern CH1 may be provided on the first active pattern AP1 on the PMOSFET region PR, and the second channel pattern CH2 may be provided on the second active pattern AP2 on the NMOSFET region NR. The first channel pattern CH1 may be provided in plurality and spaced apart from each other in the first direction D1. The second channel pattern CH2 may be provided in plurality and spaced apart from each other in the first direction D1. Each of the first and second channel patterns CH1 and CH2 may include, but is not limited to, a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 adjacent to each other in the third direction D3. For example, each of the first and second channel patterns CH1 and CH2 may include four or more semiconductor patterns. For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon. For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include single-crystalline silicon. In one embodiment of the present invention, the first to third semiconductor patterns SP1, SP2, and SP3 may be stacked nanosheets.

[0020] A first recess RS1 (to be described later) may be defined between adjacent first channel patterns CH1 in the first direction D1, and a second recess RS2 (to be described later) may be defined between adjacent second channel patterns CH2 in the first direction D1.

[0021] A first source / drain pattern SD1 may be provided on the substrate 105 in the PMOSFET region PR, and a second source / drain pattern SD2 may be provided on the substrate 105 in the NMOSFET region NR. That is, the first source / drain pattern SD1 and the second source / drain pattern SD2 may be provided on portions protruding from the substrate 105 in the third direction D3. The first source / drain pattern SD1 may fill a first recess RS1, and the second source / drain pattern SD2 may fill a second recess RS2. The first and second source / drain patterns SD1 and SD2 may be electrically connected to the first to third semiconductor patterns SP1, SP2, and SP3, respectively. The first source / drain pattern SD1 may be an impurity region having a first conductivity type (e.g., p-type), and the second source / drain pattern SD2 may be an impurity region having a second conductivity type (e.g., n-type). For example, a pair of first source / drain patterns SD1 may be electrically connected to each other through a first channel pattern CH1. For example, a pair of second source / drain patterns SD2 may be electrically connected to each other through a second channel pattern CH2.

[0022] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the first channel pattern CH1. Therefore, the pair of first source / drain patterns SD1 may provide compressive stress to the first channel pattern CH1 between them. The second source / drain pattern SD2 may include the same semiconductor element (e.g., Si) as the second channel pattern CH2.

[0023] The first source / drain pattern SD1 may include a buffer layer BFL covering the inner surface of the first recess RS1 and a main layer MAL filling most of the remaining area of ​​the first recess RS1. As an example, the buffer layer BFL and the main layer MAL may each include silicon-germanium (SiGe). The buffer layer BFL may contain a relatively low concentration of germanium (Ge). The main layer MAL may contain a relatively high concentration of germanium (Ge). As another example, the buffer layer BFL may contain only silicon (Si).

[0024] The first source / drain pattern SD1 and the second source / drain pattern SD2 may include a first pattern T1 electrically connected to a power transmission network layer PDN described below and a second pattern T2 electrically connected to an active contact AC described below.

[0025] A gate electrode GE may be provided on the first and second channel patterns CH1 and CH2 and may cross the first and second channel patterns CH1 and CH2. A plurality of gate electrodes GE may be provided. The gate electrodes GE may each extend in the second direction D2 and may be spaced apart from each other in the first direction D1.

[0026] The gate electrode GE may include inner electrodes GE1-GE3 and an outer electrode GE4. The inner electrodes GE1-GE3 of the gate electrode GE may be provided between the plurality of semiconductor patterns SP1, SP2, and SP3 and the active pattern AP1 or AP2. The outer electrode GE4 of the gate electrode GE may be provided on the uppermost semiconductor pattern among the plurality of semiconductor patterns SP1, SP2, and SP3. For example, the inner electrodes GE1-GE3 of the gate electrode GE may include, but are not limited to, a first inner electrode GE1, a second inner electrode GE2, and a third inner electrode GE3. For another example, the inner electrodes of the gate electrode GE may include four or more inner electrodes. Specifically, the first inner electrode GE1 may be interposed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1. The second inner electrode GE2 may be interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third inner electrode GE3 may be interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. For example, the outer electrode GE4 of the gate electrode GE may be provided on the third semiconductor pattern SP3.

[0027] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may include a work function metal that adjusts the threshold voltage of the transistor. For example, the first metal pattern may include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the first metal pattern may further include carbon (C). For example, the first metal patterns may include metal materials having different work functions.

[0028] For example, the second metal pattern may include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) having a lower resistance than the first metal pattern.

[0029] For example, the first to third inner electrodes GE1, GE2, and GE3 of the gate electrode GE may include a first metal pattern, and the outer electrode GE4 of the gate electrode GE may include a first metal pattern and a second metal pattern.

[0030] A gate capping pattern GC may be provided on an upper surface of the gate electrode GE. Specifically, the gate capping pattern GC may be provided on an outer electrode GE4 of the gate electrode GE. For example, the gate capping pattern GC may include at least one of SiON, SiCN, SiOCN, and SiN.

[0031] Gate spacers GS may be provided on the sides of the outer electrode GE4 of the gate electrode GE and may extend onto the sides of the gate capping pattern GC. The gate spacers GS may include a single layer or a composite layer. For example, the gate spacers GS may include at least one of SiON, SiCN, SiOCN, and SiN.

[0032] A gate insulating pattern GI may be interposed between the gate electrode GE and the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating pattern GI may cover the top, bottom, and both side surfaces of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating pattern GI may cover the top surface of the isolation pattern ST below the gate electrode GE. The gate insulating pattern GI may be interposed between the outer electrode GE4 and the gate spacer GS. For example, the gate insulating pattern GI may include at least one of silicon oxide (SiO2), silicon oxynitride (SiON), and a high-k material. In this specification, a high-k material is defined as a material having a higher dielectric constant than silicon oxide.

[0033] Inner spacers ISP may be interposed between the second source / drain pattern SD2 and the side surfaces of the gate electrode GE. For example, the inner spacers ISP may be interposed between the first to third inner electrodes GE1-GE3 and the second source / drain pattern SD2. For example, the inner spacers ISP may include an insulating material.

[0034] A first interlayer insulating film ILD1 may be provided on the substrate 105. The first interlayer insulating film ILD1 may cover the gate spacer GS and the first and second source / drain patterns SD1 and SD2. The top surface of the first interlayer insulating film ILD1 may be located at substantially the same level as the top surfaces of the gate capping pattern GC and the gate spacer GS.

[0035] A second interlayer insulating film ILD2 may cover the gate capping pattern GC on the first interlayer insulating film ILD1. A third interlayer insulating film ILD3 may be provided on the second interlayer insulating film ILD2. For example, the first to third interlayer insulating films ILD1, ILD2, and ILD3 may include silicon oxide (SiO2).

[0036] The active contacts AC may penetrate the first and second interlayer insulating films ILD1 and ILD2 along the third direction D3. A plurality of active contacts AC may be provided, and the lower portion of each active contact AC may be embedded in the upper portion of the second pattern T2 of the source / drain patterns SD1 and SD2. That is, the active contacts AC may be contacts formed from the front side of the substrate 105.

[0037] For example, the lower surface of the active contact AC may be located between the upper surface and the bottom surface of the second semiconductor pattern SP2 and may be located at a higher level in the third direction D3 than the upper surface of the back contact BCS (described later).

[0038] The active contacts AC may include a conductive pattern CP penetrating the first and second interlayer insulating films ILD1 and ILD2 and a barrier pattern BM surrounding the conductive pattern CP. For example, the conductive pattern CP may include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the barrier pattern BM may include a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0039] An ohmic pattern OM may be interposed between the active contact AC and the second pattern T2 of the source / drain patterns SD1 and SD2. Therefore, the contact resistance between the active contact AC and the second pattern T2 of the source / drain patterns SD1 and SD2 may be improved. For example, the ohmic pattern OM may include a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.).

[0040] A metal pattern MT may be provided in the third interlayer dielectric film ILD3. A via VI may be interposed between the metal pattern MT and the active contact AC. The metal pattern MT may be electrically connected to the active contact AC through the via VI. For example, the gate contact GT may be connected to the gate electrode GE, and the metal pattern MT may be electrically connected to the gate contact GT through the via VI. For example, although not shown in the drawings, each of the metal pattern MT and the via VI may be provided in multiple layers, and each metal pattern MT and each via VI may be stacked alternately. The metal pattern MT and the via VI may include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the metal pattern MT in the third interlayer dielectric film ILD3 may be wiring for applying a drain voltage.

[0041] A power transmission network layer PDN may be provided on the lower surface of the substrate 105. The power transmission network layer PDN may include a plurality of lower wirings (not shown) electrically connected to the source / drain patterns SD1 and SD2 through rear contacts BCS (described later). For example, the power transmission network layer PDN may include a wiring network for applying a source voltage.

[0042] A back contact BCS may be provided in the substrate 105. The back contact BCS may penetrate the substrate 105 and be interposed between the first pattern T1 of the source / drain patterns SD1, SD2 and the power transmission network layer PDN. The back contact BCS may electrically connect the first pattern T1 of the source / drain patterns SD1, SD2 and the power transmission network layer PDN to each other. That is, the back contact BCS may be a back active contact formed from the backside of the substrate 105, unlike the above-described active contact AC.

[0043] The top surface of the back contact BCS may be located between the top and bottom surfaces of the first semiconductor pattern SP1. The bottom surface of the back contact BCS may be in contact with the lower wiring (not shown) of the power transmission network layer PDN. The top surface of the back contact BCS may be in direct contact with the first pattern T1 of the source / drain patterns SD1 and SD2. Specifically, the top surface of the back contact BCS may be in direct contact with the main layer MAL of the first pattern T1. The top surface of the back contact BCS may be curved, convexing toward the first pattern T1.

[0044] The back contact BCS may include a back conductive pattern BT and a back barrier pattern BBM surrounding the back conductive pattern BT. For example, the back conductive pattern BT may include a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the back barrier pattern BBM may include a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0045] 2A, 2B, and 3, the first source / drain pattern SD1 may include impurities (e.g., boron (B), gallium (Ga), or indium (In)) to have a p-type, and the second source / drain pattern SD2 may include impurities (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) to have an n-type.

[0046] The first pattern T1 of the source / drain patterns SD1 and SD2 may have a first dopant concentration C_T1. The second pattern T2 of the source / drain patterns SD1 and SD2 may have a second dopant concentration C_T2. The first and second dopant concentrations C_T1 and C_T2 may be defined as the concentrations of the impurities contained in the source / drain patterns SD1 and SD2, respectively.

[0047] The first dopant concentration C_T1 may gradually decrease in a third direction D3 perpendicular to the substrate 105, and the second dopant concentration C_T2 may gradually increase in a third direction D3 perpendicular to the substrate 105. As another example, the first dopant concentration C_T1 may exponentially decrease, and the second dopant concentration C_T2 may exponentially increase.

[0048] 3, the first dopant concentration C_T1 and the second dopant concentration C_T2 for each section depending on the depth SD1_D of the first source / drain pattern SD1 can be seen. The depth SD1_D of the first source / drain pattern SD1 may be the length of each of the first and second patterns T1 and T2, which corresponds to the vertical distance from the bottom surface of the first semiconductor pattern SP1 to the top surface of the third semiconductor pattern SP3. That is, the depth SD1_D of the first source / drain pattern SD1 may include sections corresponding to each of the first through third semiconductor patterns SP1, SP2, and SP3 and sections corresponding to each of the second and third inner electrodes GE2 and GE3.

[0049] The first pattern T1 may include a first region on one side of the first semiconductor pattern SP1, a second region on one side of the second semiconductor pattern SP2, and a third region on one side of the third semiconductor pattern SP3. The second pattern T2 may include a fourth region on the other side of the first semiconductor pattern SP1, a fifth region on the other side of the second semiconductor pattern SP2, and a sixth region on the other side of the third semiconductor pattern SP3. The first and fourth regions may correspond to the height SP1_H of the first semiconductor pattern SP1. The second and fifth regions may correspond to the height of the second semiconductor pattern. The third and sixth regions may correspond to the height of the third semiconductor pattern.

[0050] The first dopant concentration C_T1 in the first region may be a second concentration C2 through a fourth concentration C4. The first dopant concentration C_T1 in the second region and the first dopant concentration C_T1 in the third region may be 0 through the first concentration C1. The first dopant concentration C_T1 in the first region may be greater than the first dopant concentration C_T1 in each of the second and third regions.

[0051] The second dopant concentration C_T2 in the fourth region may be from the first concentration C1 to the second concentration C2. The second dopant concentration C_T2 in the fifth region may be from the first concentration C1 to the third concentration C3. The second dopant concentration C_T2 in the sixth region may be from the third concentration C3 to the fourth concentration C4. The second dopant concentration C_T2 in the sixth region may be greater than the second dopant concentration C_T2 in each of the fourth and fifth regions. The second dopant concentration C_T2 in the fifth region may be greater than the second dopant concentration C_T2 in the fourth region.

[0052] For example, the first concentration C1 is 1.0×10 18 atom / cm 3 and the second contact concentration C2 is 1.0 × 10 19 atom / cm 3 The third concentration C3 can be 1.0×10 20 atom / cm 3 and the fourth concentration C4 is 5.0 × 10 22atom / cm 3 It could be.

[0053] The first dopant concentration C_T1 in the first region of the first pattern T1 may be greater than the second dopant concentration C_T2 in the fourth region of the second pattern T2. ​​This is because an ion implantation process is performed from the backside of the substrate before forming the back contact BCS in the manufacturing method described below. That is, because the ion implantation process is performed on the backside rather than the front side of the substrate, the dose and energy of the ion implantation process can be adjusted to selectively activate a desired semiconductor pattern among the multiple semiconductor patterns of the channel pattern CH1 or CH2. In this embodiment, for example, the first semiconductor pattern SP1 of the channel pattern CH1 or CH2 can be selectively activated.

[0054] In other words, by adjusting the dopant concentrations C_T1 and CT_2 of the first pattern T1 and the second pattern T2, at least one of the first to third semiconductor patterns SP1, SP2, and SP3 can be selected as a path through which charge carriers move. For example, only the first semiconductor pattern SP1 can be selected as a path through which charge carriers move. As another example, by adjusting the dopant concentrations C_T1 and CT_2 of the first pattern T1 and the second pattern T2, at least one of the first to third semiconductor patterns SP1, SP2, and SP3 can be selected as a path through which charge carriers move.

[0055] The second dopant concentration C_T2 in the fourth region of the second pattern T2 may be the concentration of impurities contained in the lower portion of the second pattern T2. ​​Specifically, an ion implantation process and an annealing process may be performed on the upper portion of the second pattern T2 from the front side of the substrate, and the implanted ions (impurities) may diffuse to the lower portion of the second pattern T2. ​​That is, the second dopant concentration C_T2 in the fourth region may have the concentration of ions (impurities) diffused from the upper portion of the second pattern T2, and therefore the second dopant concentration C_T2 in the fourth region may be lower than the second dopant concentrations C_T2 in the fifth and sixth regions.

[0056] The first dopant concentration C_T1 in the first region of the first pattern T1 may be the concentration of impurities contained in the lower portion of the first pattern T1. Specifically, because an ion implantation process is performed directly under the first pattern T1 from the backside of the substrate, the implanted ions (impurities) may diffuse to the upper portion of the first pattern T1. That is, because an ion implantation process with a targeted dose and energy is performed under the first pattern T1, the first dopant concentration C_T1 in the first region may be greater than the first dopant concentrations C_T1 in the second and third regions. In this case, because the first dopant concentration C_T1 in the first region is relatively high, the back contact BCS can be formed at an appropriate depth to prevent deterioration due to stress applied to the source / drain patterns. Therefore, the reliability of the semiconductor device according to the present invention can be improved.

[0057] 4A to 4C, a semiconductor device according to another embodiment of the present invention will be described. For the sake of simplicity, a description of the overlapping content with the above content will be omitted, and differences from the above content will be mainly described.

[0058] 4A, the top surface of the back contact BCS may be located at a first level LV1 in the third direction D3. The bottom surface of the active contact AC may be located at a second level LV2 in the third direction D3. The first and second levels LV1 and LV2 may be located between the top level SP1_UL of the first semiconductor pattern SP1 and the bottom level SP1_BL of the first semiconductor pattern SP1. That is, the first and second levels LV1 and LV2 may be higher than the bottom surface of the first semiconductor pattern SP1 and lower than the top surface of the first semiconductor pattern SP1. The second level LV2 may be higher than or the same level as the first level LV1.

[0059] The active contacts AC may be buried up to the bottom of the second pattern T2. ​​That is, the active contacts AC may be formed from the front side of the substrate 105 and buried in the top and bottom of the second pattern T2. ​​The active contacts AC may be buried in the main layer MAL of the second pattern T2 and may not be in direct contact with the buffer layer BFL of the second pattern T2. ​​The top surface of the back contact BCS may be in direct contact with the main layer MAL of the first pattern T1.

[0060] 4B, a back contact BCS may be provided that directly contacts the first and second patterns T1 and T2 of the source / drain pattern SD1. The back contact BCS may include a first back contact BCS1 electrically connected to the first pattern T1 and a second back contact BCS2 electrically connected to the second pattern T2. ​​That is, a buried active contact may not be formed on the top of the second pattern T2 from the front side of the substrate 105 in FIG. 2A.

[0061] A power transmission network layer PDN may be provided on the lower surface of the substrate 105. Specifically, lower wirings (not shown) included in the power transmission network layer PDN may be provided under each of the first and second rear contacts BCS1 and BCS2 and electrically connected to the source / drain pattern SD1. In this case, the lower wiring provided under the first rear contact BCS1 may be a wiring for applying a drain voltage, and the lower wiring provided under the second rear contact BCS2 may be a wiring for applying a source voltage. The lower wirings may be provided in the form of patterns horizontally spaced apart from each other within the power transmission network layer PDN.

[0062] Each of the first and second back contacts BCS1 and BCS2 may include a first portion provided in the substrate 105 and a second portion on the first portion. The second portion may be provided in the first active pattern AP1. The width of the first portion in the first direction D1 may decrease toward the third direction D3. The width of the second portion in the first direction D1 may be constant and then decrease toward the third direction D3. Specifically, the width of the second portion may be constant between the first active patterns AP1 and then decrease as it contacts the source / drain patterns SD1.

[0063] The top surface of the first back contact BCS1 may be in direct contact with the main layer MAL of the first pattern T1, and the top surface of the second back contact BCS2 may be in direct contact with the main layer MAL of the second pattern T2. ​​The top surface of the first back contact BCS1 may be at the same level as the top surface of the second back contact BCS2 in the third direction D3, or may be at a different level. That is, for example, the top surface of the first back contact BCS1 may be higher than the top surface of the second back contact BCS2, and for another example, the top surface of the first back contact BCS1 may be lower than the top surface of the second back contact BCS2.

[0064] In this embodiment, an ion implantation process is also performed on the back surface of the substrate, not the front surface, before forming the back contact BCS, so that the dose and energy of the ion implantation process can be adjusted to selectively activate desired semiconductor patterns among the multiple semiconductor patterns of the channel pattern CH1.

[0065] 4C, the top surface of the back contact BCS' may be located at a third level LV3 in the third direction D3. The bottom surface of the active contact AC may be located at a second level LV4 in the third direction D3. The third and fourth levels LV3 and LV4 may be located between the top level SP2_UL of the second semiconductor pattern SP2 and the bottom level SP2_BL of the second semiconductor pattern SP2. That is, the third and fourth levels LV3 and LV4 may be higher than the bottom surface of the second semiconductor pattern SP2 and lower than the top surface of the second semiconductor pattern SP2. The fourth level LV2 may be higher than or the same level as the third level LV3.

[0066] The active contacts AC may be embedded up to the center of the second pattern T2. ​​That is, the active contacts AC may be formed from the front side of the substrate 105 and embedded in the upper and middle parts of the second pattern T2. ​​The active contacts AC may be embedded in the main layer MAL of the second pattern T2 and may not be in direct contact with the buffer layer BFL of the second pattern T2. ​​The top surface of the back contact BCS' may be in direct contact with the main layer MAL of the first pattern T1.

[0067] In this case, in this embodiment, for example, the second semiconductor pattern SP2 of the channel pattern CH1 may be selectively activated. Alternatively, the first and second semiconductor patterns SP1 and SP2 may be selectively activated.

[0068] 5A to 13C are diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0069] 1, 5A, and 5B, a semiconductor substrate 100 including a PMOSFET region PR and an NMOSFET region NR may be provided. For example, the semiconductor substrate 100 may be a semiconductor substrate including a semiconductor material such as a silicon single crystal substrate, a silicon-germanium substrate, or an SOI substrate.

[0070] A trench may be formed in the semiconductor substrate 100 to form a lower support pattern BBP that fills the trench. The lower support pattern BBP may be formed to fill the trench through a SEG process using the semiconductor substrate 100 as a seed. An intermediate layer BBL may be formed to cover the semiconductor substrate 100 and the lower support pattern BBP. The intermediate layer BBL may be formed through a SEG process using the semiconductor substrate 100 and the lower support pattern BBP as a seed. For example, the lower support pattern BBP and the intermediate layer BBL may include silicon-germanium (SiGe). A silicon single crystal may be additionally formed on the intermediate layer BBL. The semiconductor substrate 100 may include the portion where the silicon single crystal is additionally formed.

[0071] A stack pattern STP may be formed on the PMOSFET region PR and the NMOSFET region NR. For example, forming the stack pattern STP may include alternately stacking semiconductor layers SL and sacrificial layers SAL on the semiconductor substrate 100, forming a mask pattern (not shown) extending in a first direction D1, and performing a patterning process using the mask pattern as an etching mask. During the patterning process, portions of the semiconductor substrate 100 may be removed, and trenches TR defining first and second active patterns AP1 and AP2 may be formed.

[0072] The first active pattern AP1 may be formed on the PMOSFET region PR, and the second active pattern AP2 may be formed on the NMOSFET region NR. The first and second active patterns AP1 and AP2 may extend in a first direction D1. An isolation pattern ST may be formed to fill the trench TR.

[0073] The sacrificial layer SAL may include a material that has an etching selectivity with respect to the semiconductor layer SL. Therefore, when the sacrificial layer SAL is removed in a process described below, the semiconductor layer SL may not be removed or may be removed to a small extent. For example, the semiconductor layer SL may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layer SAL may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe) that is different from the semiconductor layer SL.

[0074] 1, 6A, and 6B, sacrificial patterns PP may be formed on the semiconductor substrate 100 to extend along the second direction D2. The sacrificial patterns PP may be formed to cover the top surfaces of the isolation patterns ST and the side and top surfaces of the stack patterns STP. For example, forming the sacrificial patterns PP may include forming a sacrificial layer (not shown) on the front surface of the semiconductor substrate 100, forming a hard mask pattern MP on the sacrificial layer, and removing a portion of the sacrificial layer using the hard mask pattern MP as an etching mask to form the sacrificial pattern PP. For example, the sacrificial pattern PP may include polysilicon. Then, gate spacers GS may be formed on the side surfaces of the sacrificial patterns PP.

[0075] 1 and 7A to 7C, a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. For example, the first and second recesses RS1 and RS2 may be formed by removing a portion of the stack pattern STP using the hard mask pattern MP as an etching mask.

[0076] The semiconductor layer SL on the first active pattern AP1 may be separated by first channel patterns CH1 spaced apart in the first direction D1 by first recesses RS1. The semiconductor layer SL on the second active pattern AP2 may be separated by second channel patterns CH2 spaced apart in the first direction D1 by second recesses RS2. The first and second channel patterns CH1 and CH2 may include first to third semiconductor patterns SP1, SP2, and SP3, respectively.

[0077] The portion of the sacrificial layer SAL exposed by the second recess RS2 is replaced with an insulating material, so that inner spacers ISP can be formed on both sides of the sacrificial layer SAL (see FIG. 7B).

[0078] A first lower recess LRS1 may be formed under the first recess RS1. A second lower recess LRS2 may be formed under the second recess RS2. An upper support pattern UBP may be formed to fill the first and second lower recesses LRS1 and LRS2 through a SEG process using the semiconductor substrate 100 as a seed. For example, the upper support pattern UBP may include silicon-germanium (SiGe).

[0079] 7C, the backside alignment pattern BA may be defined to include a lower support pattern BBP, an intermediate layer BBL, and an upper support pattern UBP. That is, the backside alignment pattern BA may be provided below each of the first and second source / drain patterns SD1 and SD2 described below. Although not shown, the lower support pattern BBP, the intermediate layer BBL, and the upper support pattern UBP may include the same material (e.g., silicon-germanium), so the backside alignment pattern BA may not have distinct boundaries between the lower support pattern BBP, the intermediate layer BBL, and the upper support pattern UBP.

[0080] A first source / drain pattern SD1 may be formed in the first recess RS1. The first source / drain pattern SD1 may be formed by performing a SEG process using the first to third semiconductor patterns SP1, SP2, and SP3 and the backside alignment pattern BA on the PMOSFET region PR as a seed. Specifically, the first source / drain pattern SD1 may be formed by performing a SEG process using the first to third semiconductor patterns SP1, SP2, and SP3 and the upper support pattern UBP as a seed.

[0081] For example, during the process of forming the first source / drain pattern SD1, the first source / drain pattern SD1 may be an undoped pattern that does not contain impurities. That is, p-type impurities may be implanted after the first source / drain pattern SD1 is formed. As another example, during the process of forming the first source / drain pattern SD1, impurities (e.g., boron, gallium, or indium) that cause the first source / drain pattern SD1 to have p-type conductivity may be implanted in-situ into the first source / drain pattern SD1.

[0082] The second source / drain pattern SD2 may be formed in the second recess RS2. The second source / drain pattern SD2 may be formed through a SEG process using the first to third semiconductor patterns SP1, SP2, and SP3 and the backside alignment pattern BA on the NMOSFET region NR as a seed. Specifically, the second source / drain pattern SD2 may be formed by performing a SEG process using the first to third semiconductor patterns SP1, SP2, and SP3 and the upper support pattern UBP as a seed.

[0083] For example, during the process of forming the second source / drain pattern SD2, the second source / drain pattern SD2 may be an undoped pattern that does not contain impurities. That is, after the second source / drain pattern SD2 is formed, n-type impurities may be implanted. As another example, during the process of forming the second source / drain pattern SD2, impurities (e.g., phosphorus, arsenic, or antimony) that cause the second source / drain pattern SD2 to have n-type conductivity may be implanted in-situ into the second source / drain pattern SD2.

[0084] 1, 8A, and 8B, a first interlayer insulating film ILD1 may be formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. Then, the first interlayer insulating film ILD on the top surface of the sacrificial pattern PP may be removed. During the removal process, the hard mask pattern MP may be removed together with the sacrificial pattern PP, and the sacrificial pattern PP may be exposed.

[0085] Thereafter, the exposed sacrificial pattern PP may be removed, and an outer region ORG may be formed in the region where the sacrificial pattern PP has been removed. The first and second channel patterns CH1 and CH2 and the sacrificial layer SAL may be exposed to the outside by the outer region ORG.

[0086] Thereafter, the exposed sacrificial layer SAL may be selectively removed, and at this time, the first to third semiconductor patterns SP1, SP2, and SP3 may not be removed or may be removed relatively little due to the high etching selectivity of the sacrificial layer SAL.

[0087] The inner region IRG may be formed in an area where the sacrificial layer SAL has been removed. Specifically, the inner region IRG may be formed between the first to third semiconductor patterns SP1, SP2, and SP3. The inner region IRG may include first to third inner regions IRG1, IRG2, and IRG3 spaced apart from each other in the third direction D3.

[0088] The gate insulation patterns GI may be formed in each of the inner regions IRG and the outer region ORG. The gate insulation patterns GI may be formed to surround each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulation patterns GI may be formed to have a uniform thickness.

[0089] 1, 9A, and 9B, a gate electrode GE may be formed on the gate insulation pattern GI. The gate electrode GE may include inner electrodes (e.g., first to third inner electrodes GE1, GE2, and GE3) formed in each of the first to third inner regions IRG1, IRG2, and IRG3, and an outer electrode GE4 formed in the outer region ORG. Then, a gate capping pattern GC may be formed on the outer electrode GE4.

[0090] A second interlayer insulating film ILD2 may be formed on the first interlayer insulating film ILD1 and the gate capping pattern GC. A mask pattern (not shown) may be formed on the second interlayer insulating film ILD2. The mask pattern may be used to recess the first and second interlayer insulating films ILD1 and ILD2 to the top of the source / drain pattern SD1 or SD2. Recessing the first and second interlayer insulating films ILD1 and ILD2 and the source / drain pattern SD1 or SD2 may be performed by a dry etching process.

[0091] An ion implantation process may be performed on the recessed region at the front side of the substrate. By performing the ion implantation process, impurities may be implanted into the first source / drain pattern SD1. That is, p-type impurities may be implanted into the undoped first source / drain pattern SD1. By performing the ion implantation process, impurities may be implanted into the second source / drain pattern SD2. That is, n-type impurities may be implanted into the undoped second source / drain pattern SD2.

[0092] Active contacts AC may be formed through the first and second interlayer insulating layers ILD1 and ILD2 and may be connected to the first and second source / drain patterns SD1 and SD2, respectively. Each of the first and second source / drain patterns SD1 and SD2 may include a first pattern T1 that is not connected to the active contact AC and a second pattern T2 that is electrically connected to the active contact AC.

[0093] A gate contact GT may be formed to penetrate the second interlayer insulating film ILD2 and the gate capping pattern GC and may be connected to the gate electrode GE.

[0094] Forming the active contact AC and the gate contact GT may include forming a barrier pattern BM and forming a conductive pattern CP on the barrier pattern BM. An ohmic pattern OM may be further formed between the active contact AC and the second pattern T2 of each of the first and second source / drain patterns SD1 and SD2.

[0095] 10 and 11A to 11C, a third interlayer dielectric film ILD3 may be formed on the second interlayer dielectric film ILD2 and the active contacts AC. A metal pattern MT and a via VI may be formed in the third interlayer dielectric film ILD3.

[0096] After the BEOL process is completed, the semiconductor substrate 100 described with reference to Figures 4A and 4B may be inverted. Because the semiconductor substrate (100 of Figure 4A) is inverted, in the following description with reference to Figures 10 to 11C, the terms "upper surface" and "upper portion" may refer to the "lower surface" and "lower portion" of the semiconductor device whose fabrication has been completed as described with reference to Figures 2A to 2E, respectively, and the terms "lower surface" and "lower portion" may refer to the "upper surface" and "upper portion" of the semiconductor device whose fabrication has been completed as described with reference to Figures 2A to 2E, respectively.

[0097] 11A to 11C, after the BEOL process is completed, the semiconductor substrate 100 may be inverted to expose the bottom surface of the semiconductor substrate 100. A portion of the exposed semiconductor substrate 100 may be removed.

[0098] In one embodiment of the present invention, removing a portion of the semiconductor substrate 100 may include performing a planarization process on the bottom surface of the semiconductor substrate 100 to reduce the thickness of the semiconductor substrate 100 and performing a cleaning process on the semiconductor substrate 100 to selectively remove silicon (Si). The cleaning process may be performed until the intermediate layer BBL and lower support pattern BBP of the backside alignment pattern BA are exposed. The backside alignment pattern BA may include a first backside alignment pattern BA1 provided under the first pattern T1 and a second backside alignment pattern BA2 provided under the second pattern T2. ​​That is, after the portion of the semiconductor substrate 100 is removed, the intermediate layer BBL, lower support pattern BBP, and device isolation layer ST may be exposed.

[0099] 1 and 12A to 12C, an etching process may be performed to selectively remove the exposed rear alignment pattern BA. The etching process may be a dry etching process or a wet etching process. After the etching process is performed, the device isolation layer ST and the first and second active patterns AP1 and AP2 may be exposed.

[0100] The substrate 105 may be formed to fill the semiconductor substrate (100 in FIG. 4A) and the region where the backside alignment pattern BA has been removed. Specifically, the substrate 105 may be formed to fill the backside trench formed after the backside alignment pattern BA has been removed. For example, the substrate 105 may be formed by filling an insulating material to a level higher than the removed region of the semiconductor substrate (100 in FIG. 4A). Then, a chemical mechanical polishing (CMP) process may be performed using a stopper film formed on the periphery of the substrate 105.

[0101] 1 and 13A to 13C, a back contact hole BVH may be formed on the first pattern T1 to penetrate the substrate 105. In this case, the back contact hole BVH may be formed such that the upper portion of the first pattern T1 of each of the first and second source / drain patterns SD1 and SD2 is further recessed. The back contact hole may not be formed on the first and second active patterns AP1 and AP2 on the gate electrode GE.

[0102] Specifically, forming the back contact hole BVH may include forming a hard mask pattern on the substrate 105, performing a dry etching process on the substrate 105 using the hard mask pattern, and removing the hard mask pattern.

[0103] 1 and 2A to 2E, a back contact BCS may be formed to fill the inside of the back contact hole BVH. Forming the back contact BCS may include forming a back barrier pattern BBM conformally covering each of the inner wall and the lower inner surface of the back contact hole BVH, and forming a back conductive pattern BT to fill the inside of the back contact hole BVH on the back barrier pattern BBM. For example, the back conductive pattern BT may be formed through a single process, and therefore, a separate interface within the back conductive pattern BT may not be formed. As a result, the electrical resistance of the back conductive pattern BT may be relatively smaller, and the electrical characteristics of the semiconductor device may be improved. Thereafter, a power transmission network layer PDN may be formed on the lower surface of the substrate 105.

[0104] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0105] 105 PCB AC Active Contact AP1 and AP2 activity patterns BCS rear contact BFL buffer layer BBM back barrier pattern BM Barrier Pattern BT Back Conductive Pattern CH1, CH2 channel pattern CP conductive pattern GC Gate Capping Pattern GE gate electrode GI Gate Insulation Pattern GS Gate Spacer GT Gate Contact ILD1, ILD2 Interlayer insulating film ISP inner spacer MAL Main Layer MT Metal Pattern NR NMOSFET area OM Ohmic pattern PDN Power Transmission Network Layer PR PMOSFET area RS1, RS2 recess SD1, SD2 source / drain patterns SP1, SP2, SP3 semiconductor patterns ST isolation pattern T1 First Pattern T2 2nd pattern TR Trench VI Via

Claims

1. A substrate; a source / drain pattern on the substrate, the source / drain pattern including a first pattern and a second pattern spaced apart from each other in a horizontal direction; a channel pattern between the first pattern and the second pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern that are stacked and spaced apart from each other; an interlayer insulating film on the source / drain pattern; an active contact penetrating the interlayer insulating film and contacting the second pattern; a back contact that penetrates the substrate and contacts the first pattern; the first pattern has a first dopant concentration; A semiconductor device, wherein the first dopant concentration gradually decreases vertically upward of the substrate.

2. the first pattern includes a first region on a side surface of the first semiconductor pattern, a second region on a side surface of the second semiconductor pattern, and a third region on a side surface of the third semiconductor pattern; the first dopant concentration in each of the second region and the third region is between 0 and a first concentration; the first dopant concentration in the first region is a second concentration to a fourth concentration; The semiconductor device of claim 1 , wherein the first dopant concentration of the first region is greater than the first dopant concentration of each of the second and third regions.

3. the second pattern has a second dopant concentration; The semiconductor device of claim 1 , wherein the second dopant concentration gradually increases vertically upward in the substrate.

4. the second pattern includes a fourth region on a side surface of the first semiconductor pattern, a fifth region on a side surface of the second semiconductor pattern, and a sixth region on a side surface of the third semiconductor pattern; the second dopant concentration in the fourth region is between a first concentration and a second concentration; the second dopant concentration in the fifth region is a first concentration to a third concentration; the second dopant concentration in the sixth region is a third concentration to a fourth concentration; The semiconductor device of claim 3 , wherein the second dopant concentration of the sixth region is greater than the second dopant concentration of each of the fourth and fifth regions.

5. The semiconductor device of claim 4 , wherein the second dopant concentration of the fifth region is greater than the second dopant concentration of the fourth region.

6. the second pattern has a second dopant concentration; the second dopant concentration gradually increases vertically upward of the substrate; The semiconductor device of claim 1 , wherein the first semiconductor pattern is selected as a path through which charge carriers move.

7. 2. The semiconductor device of claim 1, wherein a lower surface of the active contact is at a level higher than an upper surface of the back contact.

8. The semiconductor device of claim 7 , wherein a bottom surface of the active contact is located between a top surface and a bottom surface of the second semiconductor pattern.

9. The semiconductor device of claim 7 , wherein a top surface of the back contact is located between a top surface and a bottom surface of the first semiconductor pattern.

10. the first pattern includes a buffer layer and a main layer on the buffer layer; The semiconductor device of claim 7 , wherein a top surface of the back contact is in direct contact with the main layer.

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