Integrated circuit with debugger and arbitration interface

Abstract

To implement embedded secure debugging of integrated circuit (IC) subsystems to achieve a target reliability, while meeting performance, size, and overall cost targets.SOLUTION: An integrated circuit (100) includes a debugger (102) and an interface (104) coupled to the debugger (102). The interface (104) includes arbitration logic (106) coupled to the debugger (102), a power processor (108) coupled to the arbitration logic (106), and a power management network (112) coupled to the power processor (108). The integrated circuit (100) includes subsystems (114A-114N) coupled to the interface (104). The debugger (102) performs debug operation on the subsystems (114A-114N) via the interface (104).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] As new electronic devices are developed and integrated circuit (IC) technology advances, new IC products are commercialized. One exemplary IC product for an electronic device is a system-on-chip (SoC) that includes one or more processor cores. The SoC market is increasingly focused on efficiency and productivity. Industries such as factory automation equipment manufacturers, aerospace, defense, power grid infrastructure, building automation, and medical are increasingly demanding SoCs with enhanced reliability. To meet required reliability specifications, many SoC designs include embedded solutions while balancing performance, size, and overall cost targets. For SoCs, reliability challenges arise due to their reliance on various memory elements and the use of small geometry silicon process technologies. Summary of the Invention

[0002] In one example embodiment, an integrated circuit includes a debugger and an interface coupled to the debugger. The interface has arbitration logic coupled to the debugger, a power processor coupled to the arbitration logic, and a power management network coupled to the power processor. The integrated circuit also includes a subsystem coupled to the interface, and the debugger is configured to perform debug operations of the subsystem via the interface.

[0003] In another exemplary embodiment, a system includes an integrated circuit having terminals adapted to be coupled to peripheral components, a processor core coupled to the terminals, and a memory coupled to the processor core and storing a debugger for execution by the processor core. The integrated circuit also includes an interface coupled to the processor. The interface has arbitration logic, a power processor coupled to the arbitration logic, and a power management network coupled to the power processor. The integrated circuit also includes a subsystem coupled to the interface, and the processor core is configured to perform debug operations of the subsystem via the interface.

[0004] In yet another example embodiment, a method includes generating, by a processor core of an integrated circuit, a debug request to a subsystem of the integrated circuit, and generating, by an interface between the processor core and the subsystem, a power processor interrupt in response to the generated debug request. The method also includes providing, by the power processor, a notification to the interface when a subsystem associated with the debug request is identified as being in an on state, and performing a debug operation via the interface by the processor core in response to the notification. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an integrated circuit in some examples.

[0006] [Figure 2] FIG. 1 is a block diagram of a system in accordance with some examples.

[0007] [Figure 3] FIG. 1 is a block diagram of an integrated circuit in some examples.

[0008] [Figure 4] FIG. 1 is a block diagram of an integrated circuit in some examples.

[0009] [Figure 5] 1 is a diagram of arbitration logic for an embedded IC with an embedded debugger in some examples.

[0010] [Figure 6] 1 is a flowchart of an embedded debug operation of an integrated circuit in some examples.

[0011] [Figure 7] 1 is a flowchart of a power-down sequence for look-up table (LUT) operation in some examples.

[0012] [Figure 8] 1 is a flowchart of a debugging method for an IC according to some examples. DETAILED DESCRIPTION OF THE INVENTION

[0013] As described herein, an integrated circuit (IC) includes an embedded debugger for debugging a subsystem of the IC. In some example embodiments, the IC includes at least one processor core and a memory, and the debugger is an application stored by the memory for execution by the at least one processor core. The IC also includes an interface between the debugger and the subsystem, and the debugger is configured to perform debug operations on the subsystem via the interface. In some example embodiments, the interface includes arbitration logic coupled to the debugger, a power processor coupled to the arbitration logic, and a power management network coupled to the power processor. As used herein, a "power processor" is a processor that manages clocks, resets, or other power management tasks of the IC. The power processor may also perform other operations in addition to power management tasks.

[0014] In some example embodiments, the arbitration logic is configured to receive a debug request from the debugger and generate an interrupt to the power processor in response to the received debug request, the power processor is configured to determine a power state of a subsystem associated with the debug request in response to the interrupt, perform a first set of operations associated with the debug request if the determined power state of the subsystem associated with the debug request is an off state, and perform a second set of operations associated with the debug request if the determined power state of the subsystem associated with the debug request is an on state.

[0015] In some example embodiments, the first set of operations includes providing a control signal to the power management network to activate the subsystem associated with the debug request, sending a notification to arbitration logic to ensure that the subsystem associated with the debug request is in an on state, receiving a notification from the arbitration logic that the debug operation associated with the debug request has completed, and, in response to the received notification, providing a control signal to the power management network to restore the subsystem associated with the debug request to an off state. In some example embodiments, the second set of operations includes sending a notification to arbitration logic to ensure that the subsystem associated with the debug request is in an on state, receiving a notification from the arbitration logic that the debug operation associated with the debug request has completed, and, in response to the received notification, maintaining the subsystem associated with the debug request in an on state.

[0016] In some example embodiments, the IC includes a secure microcontroller (MCU) domain (sometimes referred to as an "MCU island") that includes some of the debugger and interface components. For example, the secure microcontroller domain may include a processor that executes at least a portion of the debugger. In some example embodiments, the secure microcontroller domain may also include a power processor and arbitration logic. In some example embodiments, the described methods optionally include an on-chip emulator to facilitate communication between the secure microcontroller domain and other components of the IC.

[0017] In some exemplary embodiments, the IC is an infotainment IC that includes interfaces to facilitate communication with displays, sensors, and / or other peripherals. In some exemplary embodiments, the IC includes an advanced driver assistance system (ADAS) physical (PHY) interface that facilitates communication with ADAS-compatible peripherals or applications. In other exemplary embodiments, the IC is an industrial application IC with interfaces to facilitate communication with displays, sensors, and / or other peripherals in factory or industrial applications (e.g., factory automation equipment manufacturers, aerospace, defense, power grid infrastructure, building automation, and / or medical applications).

[0018] In operation, the interface and / or power processor can track the power state of the subsystems using a system-on-chip (SoC) map or look-up table (LUT). When a debugger desires that the power processor wake up one of the sub-domains, the map or LUT is used by the power processor to determine the power state of the subsystem associated with the debug request. Compared to other embedded debugger IC options, the described technique is less intrusive and avoids complex hardware for securely performing debug operations. The described embedded debugger IC option leverages available power processors and interrupt protocols to perform power management of the subsystems associated with debug operations. In this way, the IC or SoC achieves embedded secure debug of the IC subsystems to achieve target reliability while meeting performance, size, and overall cost targets.

[0019] FIG. 1 is a block diagram of an IC 100 in some examples. As shown, the IC 100 includes an interface 104 coupled between a debugger 102 and subsystems 114A-114N. In some example embodiments, the debugger 102 is an application stored in memory and executed by a processor core of the IC 100. Additionally or alternatively, the debugger 102 may include hard-coded logic to perform at least some of the debugging operations described herein. In FIG. 1, the debugger 102 interacts with subsystems 114A-114N via the interface 104, which include arbitration logic 106, a power processor 108, and a power management network 112.

[0020] In some example embodiments, arbitration logic 106 is configured to receive a debug request from debugger 102 and generate an interrupt to power processor 108 in response to the received debug request. Power processor 108 is configured to determine a power state of a subsystem (e.g., one of subsystems 114A-114N) associated with the debug request in response to the interrupt, and to perform a first set of operations associated with the debug request if the determined power state of the subsystem associated with the debug request is an off state, and to perform a second set of operations associated with the debug request if the determined power state of the subsystem associated with the debug request is an on state.

[0021] In some example embodiments, a first set of operations of power processor 108 includes providing a control signal to the power management network 112 to activate the subsystem associated with the debug request, sending a notification to arbitration logic 106 to ensure that the subsystem associated with the debug request is in an ON state, receiving notification from arbitration logic 106 that the debug operation associated with the debug request is complete, and, in response to the received notification, providing a control signal to power management network 112 to restore the subsystem associated with the debug request to an OFF state. In some examples, power processor 108 uses LUT 110 or other organized data to determine the power state of subsystems 114A-114N and perform subsequent operations. In some example embodiments, a second set of operations includes sending a notification to arbitration logic 106 to ensure that the subsystem associated with the debug request is in an ON state, receiving notification from arbitration logic 106 that the debug operation associated with the debug request is complete, and, in response to the received notification, maintaining the subsystem associated with the debug request in an ON state.

[0022] Using IC 100, debug apparatus 102 leverages the availability of power processor 108 and interrupt protocols to perform power management of any of subsystems 114A-114N related to debug operations. In this manner, IC 100 achieves built-in secure debug of subsystems 114A-114N as needed to achieve target reliability while meeting performance, size, and overall cost targets for IC 100.

[0023] FIG. 2 is a block diagram of a system 200 in some examples. As shown, the device 200 includes an IC 100A (an example of the integrated circuit 100 in FIG. 1). In some examples, the IC 100A is an infotainment IC (e.g., for a vehicle). As shown, the IC 100A is coupled to peripherals such as a display 202, sensors 204, and an ADAS PHY interface 208. In some example embodiments, the ADAS PHY interface 208 is omitted. The system 200 also includes a power management IC (PMIC) 206 coupled to the IC 100A and configured to provide a power source to at least the IC 100A. The PMIC 206 is configured to supply power to the integrated circuit 100A. In some example embodiments, the IC 100A is an infotainment IC (e.g., for a vehicle) with debugger operations as described herein. In another exemplary embodiment, IC 100A is an industrial IC (such as for factory automation equipment manufacturers, aerospace, defense, power grid infrastructure, building automation, medical applications, etc.). Regardless of the particular use or application, IC 100A achieves built-in secure debug of its subsystems as described herein to achieve target reliability while meeting performance, size, and overall cost targets for IC 100.

[0024] FIG. 3 is a block diagram of an IC 300 (an example of IC 100 of FIG. 1 or IC 100A of FIG. 2) in some examples. In FIG. 3, IC 300 is an example of an infotainment IC with a debugger, interface, and subsystems as described herein. When relating IC 100 of FIG. 1 to IC 300 of FIG. 3, debugger 102 of FIG. 1 includes debugger operations operating in secure MCU domain or MCU island 336 and other portions of IC 300 of FIG. 3. Interface 104 of FIG. 1 is part of microcontroller island 336 of FIG. 3. Additionally, processor cores 302 and 308 and memory subsystem 326 of FIG. 3 are examples of subsystems 114A-114N of FIG. 1. Other example subsystems include controllers, communication interfaces, programmable circuitry, or application-specific circuitry. IC 300 of FIG. 3 is for illustrative purposes only and is not intended to limit the described techniques to a particular set of ICs and associated components.

[0025] As shown, IC 300 includes a first processor core 302 including a processor 304 and memory 306 (e.g., a 512 KB L2 cache with error correction code (ECC)). Integrated circuit 300 also includes a second processor core 308 including a processor 310 and memory 312 (e.g., a 512 KB L2 cache with ECC). In the example of FIG. 3, first and second cores 302 and 308 are configured to execute software applications that may be stored at least partially in one or both of processor cores 302 or 308 (e.g., memories 306 and 312) or in memory subsystem 326. As shown, memory subsystem 326 includes various example blocks, such as a multi-core shared memory controller (MSMC) (e.g., a 2 MB static random access memory SRAM with ECC), a general-purpose memory controller (GPMC), an extreme learning machine (ELM), an external memory interface (EMIF), etc.

[0026] 3, IC 300 also includes a graphics module 314 with a graphics processing unit (GPU) 316, an industrial subsystem module 320 with a microcontroller 322 (labeled PRI_CUSSG) for supporting an Ethernet port, and a navigator subsystem 324. In some example embodiments, navigator subsystem 324 includes a unified direct memory access (UDMA) block, a proxy block, a peripheral virtualization unit (PVU) block, a common platform time stamp (CPTS), a ring accelerator (RA) proxy data buffer, a memory cyclic redundancy check (MCRC) accelerator, interrupt blocks (INTR and INTA), a mailbox block, a spinlock block, a timer manager (TIMER_MGR) block, and a channelized firmware (FW) block.

[0027] As shown, the IC 300 also includes a display subsystem 328. In some exemplary embodiments, the display subsystem 328 includes a video pipeline block (e.g., a blend / scale / color space converter or "CSC"), a digital video interface (e.g., Open LDI) block, and a MIPI interface and display port interface (MIPI DPI) block. Additionally, the IC 300 includes a system services module 330. In some exemplary embodiments, the system services module 330 includes a general-purpose (GP) timer, a real-time interrupt (RTI) and windowed watchdog timer (WWDT) block, a peripheral direct memory access (PDMA) block, and a debug block. The IC 300 also includes a video input module 332. In some exemplary embodiments, the video input module 332 includes a CAL block, a MIPI CSI-2 block, a low-voltage differential signaling receiver (LVDSRX) block, and a video processing (e.g., BT.656 / 1120) block.

[0028] 3, IC 300 also includes a security accelerator module 334. In some example embodiments, security accelerator module 334 includes an Advanced Encryption Standard (AES) block, a Secure Hash Standard (SHA) block, a Public Key Accelerator (PKA) block, a Deterministic Random Bit Generator (DRBG), a Message Digest Algorithm (MD5) block, and a Data Encryption Standard (3DES) block.

[0029] As shown, the IC's MCU island 336 includes a navigator subsystem 338 and a processor 340. In some exemplary embodiments, the navigator subsystem 338 includes an RA block, a UDMA block, a proxy block, an MCRC block, interrupt blocks (INTR and INTA), and a channelized FW block. In one example, the processor 340 in the MCU island 336 may be used as a power processor, and a debugger may interact with the processor 340 to control various signals provided to the subsystem being debugged, such as power, clock, and / or reset, or to perform other power management tasks. The MCU island 336 also includes various other components, including a PDMA block, a GP timer, an error signal module (ESM), an RTI / WDT block, and memory (e.g., scratchpad RAM 512B and MCU SRAM 512KB). In some example embodiments, MCU island 336 includes various components associated with the techniques described herein, such as debugger 102 and at least a portion of interface 104 (e.g., arbitration logic 106 and power processor 108) of FIG. 1 .

[0030] The IC 300 also includes an interconnect 342 that enables communication between the MCU island 336 and other components or subsystems of the IC 300. Exemplary components of the IC 300 include an automotive interface 344, media and data storage 346, a control interface 348, and audio peripherals 350. The automotive interface 344 includes, for example, a controller area network with a flexible data rate (MCAN_FD) block. The media and data storage 346 includes, for example, a multimedia card (MMC) / secure digital (SD) card block. The control interface 348 includes, for example, an enhanced high-resolution pulse-width modulation (eHRPWM) block, an enhanced capture (eCAP) block, and an enhanced quadrature encoder pulse (eQEP) block. The audio peripherals 350 includes, for example, a multi-channel audio serial port (MCASP) block.

[0031] As shown, IC 300 also includes a generic connectivity module 352. In some exemplary embodiments, the generic connectivity module includes a general-purpose input / output (GPIO) block, an Octal Serial Peripheral Interface (OSPI) and Hyperbus block, a communications interface (e.g., I2C) block, a multi-channel serial port interface (MCSPI) block, an analog-to-digital converter (ADC), and a universal asynchronous receiver / transmitter (UART) block. IC 300 also includes a high-speed serial interface module 354. In some exemplary embodiments, the high-speed serial interface module 354 includes a Peripheral Component Interconnect Express (PCIe) block, a Universal Serial Bus (USB) 2.0 block, a USB 3.1 block, and an Ethernet block.

[0032] In IC 300, a debugger operating within MCU island 336 leverages the availability of a power processor (e.g., one of processors 340) and interrupt protocols to perform power management of any of the subsystems compatible with debug operations (e.g., processor cores 302, 308, memory subsystem 326, or other subsystems). In this way, IC 300 achieves built-in secure debug of subsystems as needed to achieve target reliability while meeting performance, size, and overall cost targets for IC 300.

[0033] FIG. 4 is a block diagram of an IC 400 (an example of IC 100 in FIG. 1, IC 100A in FIG. 2, or IC 300 in FIG. 3). As shown, IC 400 includes a debugger subsystem 102A (an example of debugger 102 in FIG. 1) that is coupled to subsystems 416A-416N (an example of subsystems 114A-114N in FIG. 1) via arbitration logic 414 (an example of arbitration logic 106 in FIG. 1). Arbitration logic 414 is also coupled to power processor 108A (an example of power processor 108 in FIG. 1). In the example of FIG. 4, each of subsystems 416A-416N includes a debug target central processing unit (CPU) 418A-418N or other target component. Each of subsystems 416A-416N also includes a power and sleep controller (PSC) and / or local power and sleep controller (LPSSC) module 420A-420N. In some examples, the PSC / LPSSC modules 420A-420N are part of a power management network (eg, power management network 112) for controlling clocks and / or power supplies for the subsystems 416A-416N of the IC 400.

[0034] More specifically, debugger subsystem 102A includes a debug pin (DP) interface 402 configured to receive JTAG (joint test action group) communications. DP interface 402 is coupled to a bus (DAPBUS) 404. As shown, debugger subsystem 102A also includes a bridge 406 and a debug authentication interface (referred to as a power AP) 408 coupled to bus 404. In operation, debug authentication interface 408 is configured to communicate debug requests to arbitration logic 414.

[0035] In response to a debug request from debugger subsystem 102A, arbitration logic 414 asserts an interrupt (Debug Req Int) to power processor 108A. Power processor 108A is configured to determine a power state of a subsystem associated with the debug request in response to the interrupt and, if the determined power state of the subsystem associated with the debug request is an off state, perform a first set of operations to power up the subsystem associated with the debug request. In some example embodiments, the first set of operations performed by power processor 108A includes providing a control signal 413 to a power management network (e.g., a respective one of PSC / LPSSC modules 420A-420N) to power on the subsystem associated with the debug request and sending a notification (a secure device notification) to arbitration logic 414 to confirm that the subsystem associated with the debug request is in an on state. In some example embodiments, the first set of operations performed by power processor 108A also receives notification from arbitration logic 414 (e.g., using Debug Req Int) that the debug operation associated with the debug request has completed, and provides a control signal to a power management network (e.g., a respective one of PSC / LPSSC modules 420A-420N) to restore the subsystem associated with the debug request to an off state in response to the received notification.

[0036] In some example embodiments, power processor 108A is configured to perform a second set of operations if the determined power state of the subsystem associated with the debug request is an on state. In one example, the second set of operations includes sending a notification (a secure device notification) to arbitration logic 414 to confirm that the subsystem associated with the debug request is in an on state, receiving a notification from arbitration logic 414 (e.g., using Debug Req Int) that the debug operation associated with the debug request has completed, and, in response to the received notification, maintaining the subsystem associated with the debug request in an on state.

[0037] In the example of FIG. 4, arbitration logic 414 includes memory-mapped registers (MMRs) 415 or other storage for tracking configuration or status bits related to debug operations. Additionally, in some illustrative embodiments, arbitration logic 414 couples to power processor 108A via interconnect 410 (labeled SoC interconnect). In the example of FIG. 4, power processor 108A and arbitration block 414 provide an interface (e.g., interface 104 of FIG. 1) for performing debug on any of subsystems 416A-416N. IC 400 allows arbitration logic 414 to leverage the availability of power processor 108A and interrupt protocols to perform power management on any of subsystems 416A-416N related to debug operations of debugger 102A. In this manner, IC 400 achieves built-in secure debug of subsystems 416A-416N as needed to achieve target reliability while meeting performance, size, and overall cost targets for IC 400.

[0038] FIG. 5 is a diagram of arbitration logic 500 (an example of arbitration logic 106 of FIG. 1 or arbitration logic 414 of FIG. 4 ) for an IC with an embedded debugger (e.g., IC 100 of FIG. 1 , IC 100A of FIG. 2 , IC 300 of FIG. 3 , or IC 400 of FIG. 4 ), in some examples. As shown, arbitration logic 500 includes inputs 502, 504, 508, 534, and 538. Input 502 is configured to receive a notification (e.g., a secure device notification) from a power processor, as described herein. Input 504 is configured to receive a control signal (ForceActive) from a debugger (e.g., debugger subsystem 102A of FIG. 4 ). Input 508 is configured to receive another control signal (InhibitSleep) from a debugger (e.g., debugger subsystem 102A of FIG. 4 ). Input 534 is configured to receive a notification (ForceActiveACK) from the power management network (e.g., each one of PSC / LPSSC modules 420A-420N in FIG. 4). Input 538 is configured to receive a notification (InhibitSleepACK) from the power management network (e.g., each one of PSC / LPSSC modules 420A-420N in FIG. 4).

[0039] As shown, arbitration logic 500 also includes outputs 506, 510, 532, 536, and 548. Output 506 is configured to provide a first type of notification (e.g., ForceActiveACK) to a debugger. Output 510 is configured to provide a second type of notification (e.g., InhibitSleepACK) to a debugger. Output 532 is configured to provide a first type of control signal (e.g., ForceActive) to a power management network (e.g., each one of PSC / LPSSC modules 420A-420N in FIG. 4). Output 536 is configured to provide a first type of control signal (e.g., InhibitSleep) to a power management network (e.g., each one of PSC / LPSSC modules 420A-420N in FIG. 4). Output 548 is configured to provide an interrupt (debug_forceactive_int) to a power processor (eg, power processor 108 in FIG. 1 or power processor 108A in FIG. 4) as described herein.

[0040] 5, arbitration logic 500 includes logic or gates between inputs 502, 504, 508, 534, and 538 and 506, 510, 532, and 536. As shown, arbitration logic 500 includes a buffer 511 coupled to input 502. The output of buffer 511 is one input to AND gate 528. The output of the AND gate is provided to output 532. As shown, the other input to AND gate 528 comes from the output of another AND gate 524, one of the inputs to AND gate 524 is coupled to input 504. The other input to AND gate 524 is coupled to a bypass override register 550 (BYPASS_OVERRIDE). In Figure 5, bypass override register 550 is one of various registers 550, 552, 554, 556, 558, 560, 562, 564, 566, 568, 570, 572, and 574 of arbitration logic 500, which are examples of MMRs 415 in Figure 4. In the example of Figure 5, these registers are coupled to interface 540, which allows a debugger or other IC component to examine or clear configuration and / or status bits related to the operation of arbitration logic 500.

[0041] As shown, input 504 is also coupled to a first control signal port state register (FORCEACTIVE_PORT_STAT) 558 and to an input of another AND gate 530. The output of AND gate 530 is coupled to output 536. The other input of AND gate 530 comes from the output of another AND gate 526. As shown, one input of AND gate 526 is coupled to input 508, and the other input to AND gate 526 is coupled to bypass override register 550. As shown, input 508 is also coupled to a second control signal port state register 552 (INHIBITSLEEP_PORT_STAT).

[0042] 5, output 506 is coupled to the output of a multiplexer 512. As shown, input 534 is coupled to a first input to multiplexer 512. A second input of multiplexer 512 is coupled to a first control signal acknowledge set register (FORCEACTIVE_ACK_SET) 560, the control signal for multiplexer 512 being provided by a bypass override block 550. Output 510 is also coupled to the output of another multiplexer 514. As shown, input 538 is coupled to a first input to multiplexer 514. A second input of multiplexer 514 is coupled to a second control signal acknowledge set register (INHIBITSLEEP_ACK_SET) 554, the control signal for multiplexer 514 being provided by the bypass override register 550.

[0043] Arbitration logic 500 also includes an XOR gate 516 having a first input coupled to input 504 and a second input coupled to a first control signal acknowledge set block 560. The output of XOR gate 516 is coupled to a control block (REQ EVT SET / CLR) 518 configured to provide a signal to a first control signal interrupt status register (FORCEACTIVE_INT_RAW_STAT_SET) 570 to set or clear an interrupt associated with the first control signal (ForceActive). Arbitration logic 500 also includes an XOR gate 520 having a first input coupled to input 508 and a second input coupled to a second control signal acknowledge set register 554. The output of the XOR gate 520 is coupled to a control block (REQ EVT SET / CLR) 522 configured to provide a signal to a second control signal interrupt status register (INHIBITSLEEP_INT_RAW_STAT_SET) 568 to set or clear the interrupt associated with the second control signal (InhibitSleep).

[0044] 5, arbitration logic 500 also includes an interrupt generator 546 coupled to a second control signal interrupt status block 568 and a first control signal interrupt status block 570 via an OR gate 544. OR gate 544 also receives requests from interrupt request sources (IRQ_*_STAT ports[31:1]) 542 that notify when interrupt requests are received on various ports. The output of interrupt generator 546 is coupled to output 548. In some example embodiments, interrupt generator 546 is selectively enabled by a control signal from an interrupt enable clear register (INT_EN_CLR) 574.

[0045] As shown, arbitration logic 500 also includes a second control signal acknowledge clear register 556 (INHIBITSLEEP_ACK_CLR), a first control signal acknowledge clear register 562 (FORCEACTIVE_ACK_CLR), a second control signal interrupt enable state clear register 564 (INHIBITSLEEP_INT_EN_STAT_CLR), and a first control signal interrupt enable state clear register 566 (FORCEACTIVE_INT_EN_STAT_CLR). In different example embodiments, arbitration logic 500 varies with respect to the particular logic, gates, and registers used to handle debug requests, interrupts, and notifications as described herein.

[0046] FIG. 6 is a flowchart of embedded debug operations 600 of an IC (e.g., IC100 of FIG. 1 , IC100A of FIG. 2 , IC300 of FIG. 3 , IC400 of FIG. 4 , etc.) in some examples. As shown, embedded debug operations 600 include authenticating a secure session in block 602 in response to a request to debug a subsystem, as described herein. If authentication is not successful (decision block 604), the power processor does not service the request in block 608. If authentication is successful (decision block 604), the power processor services the request in block 606. In block 610, the power processor checks the arbitration logic for the ID requestor, enables the phase-locked loop (PLL), firmware (FW), additional MMR setup, enforces power wake-up dependencies, enables a channel from the arbitration logic to the target subsystem, and completes the subsystem enable process.

[0047] FIG. 7 is a flowchart of a power-down sequence 700 of LUT operations for an IC (e.g., IC100 of FIG. 1 , IC100A of FIG. 2 , IC300 of FIG. 3 , or IC400 of FIG. 4 ) in some examples. As shown, the power-down sequence 700 includes a debugger power-on lookup action at block 702. At block 704, the debugger requests one of the subsystems to be active. At block 706, the clock source for the requested subsystem active is set. At block 708, other clocks on which the requested subsystem depends are set. At block 710, other power domains on which the requested subsystem depends are set. At block 712, the power domain of the requested subsystem is set. At block 714, clock gating for the requested subsystem is removed. At block 716, all security is configured to allow access to / from the requested subsystem. At block 718, all other settings are configured to allow the requested subsystem to become active. The requested subsystem is released, reset, or not stopped in block 720. In some example embodiments, the subsystem is disabled by performing sequence 700 in reverse (e.g., after a secure debug session).

[0048] FIG. 8 is a flowchart of a method 800 in some examples. Method 800 is performed by an IC (e.g., IC 100 of FIG. 1 , IC 100A of FIG. 2 , IC 300 of FIG. 3 , or IC 400 of FIG. 4 ). As shown, method 800 includes generating a debug request (e.g., ForceActive or InhibitSleep of FIG. 5 ) by a processor core of the integrated circuit (one of processor cores 302 and 308, debugger subsystem 102A of FIG. 4 ) to a subsystem of the integrated circuit (e.g., one of subsystems 114A-114N of FIG. 1 or one of subsystems 416A-416N of FIG. 4 ) in block 802. In response to the generated debug request, a power processor is generated by an interface between the processor and the subsystem (e.g., interface 104 of FIG. 1 , arbitration logic 414 and power processor 108A of FIG. 4 ). At block 806, if the subsystem associated with the debug request is identified as being in an on state, a notification (e.g., ForceActiveACK or InhibitSleepACK in FIG. 5) is provided to the interface by the power processor. At block 808, in response to the notification, the processor core performs a debug operation over the interface.

[0049] In some example embodiments, method 800 includes additional operations, such as determining, by the power processor, a power state of a subsystem associated with the debug request in response to a power processor interrupt, and performing, by the power processor, a first set of operations to activate the subsystem if the determined power state of the subsystem associated with the debug request is an off state. In some example embodiments, performing the first set of operations by the power processor for method 800 includes providing a control signal to a power management network of the integrated circuit to provide power to the subsystem associated with the debug request, sending a notification to arbitration logic of the integrated circuit to confirm that the subsystem associated with the debug request is in an on state, receiving a notification from the arbitration logic that the debug operation associated with the debug request has completed, and providing a control signal to the power management network to restore the subsystem associated with the debug request to an off state in response to the received notification. In some example embodiments, method 800 also includes performing, by the power processor, a second set of operations if the determined power state of the subsystem associated with the debug request is an on state. In some example embodiments, performing the second set of operations for method 800 by the power processor includes sending a notification to arbitration logic of the integrated circuit to confirm that the subsystem associated with the debug request is in an on state, receiving a notification from the arbitration logic that the debug operation associated with the debug request is completed, and, in response to the received notification, maintaining the subsystem associated with the debug request in an on state.

[0050] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B if device A generates a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not substantially change the functional relationship between device A and device B.

[0051] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. 1. An integrated circuit comprising: A debugger, an interface coupled to the debugger; a subsystem coupled to the interface; Including, The interface: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; a power management network coupled to the power processor; and an integrated circuit, wherein the debugger is configured to perform debug operations of the subsystem via the interface;

2. 10. The integrated circuit of claim 1, The arbitration logic is: receiving a debug request from the debugger; generating an interrupt to the power processor in response to the received debug request; 1. An integrated circuit configured to:

3. 3. An integrated circuit according to claim 2, the power processor: determining a power state of the subsystem associated with the debug request in response to the interrupt; performing a first set of operations to wake up the subsystem associated with the debug request if the determined power state of the subsystem associated with the debug request is an off state; 1. An integrated circuit configured to:

4. 4. An integrated circuit according to claim 3, The first set of operations comprises: providing a control signal to the power management network to activate the subsystem associated with the debug request; sending a notification to the arbitration logic to verify that the subsystem associated with the debug request is on; , an integrated circuit.

5. 5. An integrated circuit according to claim 4, The first set of operations comprises: receiving notification from the arbitration logic that the debug operation associated with the debug request is completed; providing a control signal to the power management network to restore the subsystem associated with the debug request to the off state in response to the received notification; , an integrated circuit.

6. 4. An integrated circuit according to claim 3, The integrated circuit, wherein the power processor is configured to perform a second set of operations if the determined power state of the subsystem associated with the debug request is an on state.

7. 7. An integrated circuit according to claim 6, The integrated circuit, wherein the second set of operations includes sending a notification to the arbitration logic to verify that the subsystem associated with the debug request is in an on state.

8. 8. An integrated circuit according to claim 7, The second set of operations includes: receiving notification from the arbitration logic that the debug operation associated with the debug request is completed; maintaining the subsystem associated with the debug request in the on state in response to the received notification; , an integrated circuit.

9. 10. The integrated circuit of claim 1, The integrated circuit is an infotainment integrated circuit, the interface is part of a secure microcontroller domain, and the subsystem includes a processor and a memory.

10. 10. The integrated circuit of claim 1, The arbitration logic is: Sets the clock source that the requested subsystem depends on to be active, setting a power domain on which the subsystem depends to be active; removing clock gating for the required subsystem; 1. An integrated circuit configured to:

11. 1. A system comprising: including an integrated circuit, The integrated circuit comprises: a terminal adapted to be coupled to a peripheral component; a processor core coupled to the terminal; a memory coupled to the processor core, the memory storing a debugger for execution by the processor core; an interface coupled to the processor; a subsystem coupled to the interface; and The interface: Arbitration logic and a power processor coupled to the arbitration logic; a power management network coupled to the power processor; and The system, wherein the processor core is configured to perform debug operations of the subsystem via the interface.

12. 12. The system of claim 11, The arbitration logic is: receiving a debug request from the processor core; generating an interrupt to the power processor in response to the received debug request; The system is configured as follows:

13. 13. The system of claim 12, the power processor: determining a power state of the subsystem associated with the debug request in response to the interrupt; performing a first set of operations to wake up the subsystem associated with the debug request if the determined power state of the subsystem associated with the debug request is an off state; The system is configured as follows:

14. 14. The system of claim 13, The first set of operations comprises: providing a control signal to the power management network to activate the subsystem associated with the debug request; sending a notification to the arbitration logic to verify that the subsystem associated with the debug request is on; receiving notification from the arbitration logic that the debug operation associated with the debug request is completed; providing a control signal to the power management network in response to the received notification to restore the subsystem associated with the debug request to the off state; A method comprising:

15. 14. The system of claim 13, The system, wherein the power processor is configured to perform a second set of operations if the determined power state of the subsystem associated with the debug request is an on state.

16. 16. The system of claim 15, The second set of operations includes: sending a notification to the arbitration logic to verify that the subsystem associated with the debug request is on; receiving notification from the arbitration logic that the debug operation associated with the debug request is completed; maintaining the subsystem associated with the debug request in the on state in response to the received notification; A method comprising:

17. 1. A method comprising: The integrated circuit processor core generating a debug request for a subsystem of the integrated circuit; generating, by an interface between the processor core and the subsystem, a power processor interrupt in response to the generated debug request; providing, by the power processor, a notification to the interface when the subsystem associated with the debug request is identified as being in an on state; performing, by the processor core, a debug operation in response to the notification via the interface; A method comprising:

18. 18. The method of claim 17, determining, by the power processor, a power state of the subsystem associated with the debug request in response to the power processor interrupt; performing, by the power processor, a first set of operations to wake up the subsystem associated with the debug request if the determined power state of the subsystem is off; The method further comprises:

19. 20. The method of claim 18, performing, by the power processor, a first set of operations; providing a control signal to a power management network of the integrated circuit to activate the subsystem associated with the debug request; sending a notification to arbitration logic of the integrated circuit to verify that the subsystem associated with the debug request is on; receiving notification from the arbitration logic that the subsystem associated with the debug request has completed; providing a control signal to the power management network in response to the received notification to restore the subsystem associated with the debug request to the off state; A method comprising:

20. 20. The method of claim 18, The method further comprising performing, by the power processor, a second set of operations if the determined power state of the subsystem associated with the debug request is an on state.

21. 21. The method of claim 20, performing the second set of operations by the power processor; sending a notification to arbitration logic of the integrated circuit to verify that the subsystem associated with the debug request is on; receiving notification from the arbitration logic that the debug operation associated with the debug request is completed; maintaining the subsystem associated with the debug request in the on state in response to the received notification; A method comprising:

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