Source driver and display device

Abstract

To provide a source driver that can suppress the occurrence of a trouble of display due to IR drop while suppressing the enlargement of a chip area.SOLUTION: A delay control circuit 23 includes a first delay shift unit 31, a second delay shift unit 32, and a control unit 33. Upon the reception of a start pulse signal supplied from the control unit 33, the first delay shift unit 31 generates latch timing signals e1 to e480. Upon the reception of the start pulse signal supplied from the control unit 33, the second delay shift unit 32 generates latch timing signals e481 to e960. The control unit 33 includes a start pulse generation unit 34, a delay amount control unit 35, and a bias voltage generation unit 36. Based on the signal representing an amount of delay of the timing shift supplied from the delay amount control unit 35, the bias voltage generation unit 36 generates bias voltages BVR and BVL, and supplies the bias voltage BVR to the first delay shift unit 31 and supplies the bias voltage BVL to the second delay shift unit 32.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a source driver and a display device. [Background technology]

[0002] A display device such as a liquid crystal display or organic electroluminescence (EL) display generally includes a display panel in which display cells are formed at the intersections of a plurality of scanning lines and a plurality of data lines, and a source driver for driving the plurality of data lines. The source driver includes a data latch unit that sequentially captures a plurality of pixel data pieces included in a video signal, a plurality of level shifters that increase the voltage of the pixel data pieces captured by the data latch unit, a DA conversion unit that converts the increased voltage pixel data pieces into analog grayscale voltages, and an output amplifier unit that amplifies the grayscale voltages and outputs them to the data lines.

[0003] In such source drivers, in order to suppress the occurrence of display unevenness due to discrepancies in output timing between channels, a display driver has been proposed that is equipped with a configuration that adjusts the output timing by specifying the output timing of each channel for each source driver (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-40752 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, the number of channels in source drivers has increased to accommodate larger display panels and lower prices. Furthermore, the LV voltage used in logic circuits has been reduced to save power.

[0006] In a multi-channel source driver like this, the number of level shifters operating simultaneously increases, causing IR drops due to changes in the output from the logic circuit. This makes it impossible for the level shifter to invert the logic level, or it takes a long time for the inversion operation, causing a through current to flow through the level shifter itself. This causes further IR drops and may lead to malfunctions in the source driver.

[0007] One possible solution to suppress the occurrence of such IR drops is to use analog delay circuits and buffering to shift the pulse timing that latches the data, thereby reducing the number of level shifters that operate simultaneously. However, when attempting to finely adjust the drive timing of the source driver using this method, the delay circuit section needs wiring, decoders, capacitive elements, etc. for the signals to be adjusted, which increases the chip area.

[0008] The present invention has been made in view of the above problems, and has an object to provide a source driver that can suppress display defects caused by IR drop while suppressing an increase in chip area. [Means for solving the problem]

[0009] A source driver according to the present invention is connected to a display panel having a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each intersection of the plurality of source lines and the plurality of gate lines, and has a plurality of output channels that output drive signals to the plurality of source lines based on a video data signal consisting of a series of pixel data pieces, and includes an output delay control circuit that sequentially outputs a plurality of latch timing signals respectively corresponding to the plurality of output channels, and a data latch unit that sequentially takes in the pixel data pieces at timings according to the output timings of the plurality of latch timing signals and sequentially outputs each of the taken-in pixel data pieces, and the output delay control circuit includes a start pulse output unit that outputs a start pulse signal consisting of a single pulse, and a plurality of timing shift registers that are cascaded to each other. and a bias voltage generation unit that generates a bias voltage based on a spread setting signal that sets the delay amount of the start pulse signal in the first delay shift unit and the second delay shift unit, each of the plurality of timing shift circuits including an even number of inverters cascaded to each other, the even number of inverters receiving the start pulse signal at a first stage and outputting the latch timing signal from a final stage, and a delay adjustment unit that receives the bias voltage and changes the delay time of a signal output in at least one inverter of the even number of inverters based on the bias voltage.

[0010] Further, a display device according to the present invention includes a display panel having a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each intersection of the plurality of source lines and the plurality of gate lines, a gate driver that supplies gate signals to the plurality of gate lines, and a source driver that receives a video data signal consisting of a series of pixel data pieces and outputs drive signals to the plurality of source lines, wherein the source driver includes a plurality of output channels that output the drive voltage signals, an output delay control circuit that sequentially outputs a plurality of latch timing signals respectively corresponding to the plurality of output channels, and a data latch unit that sequentially takes in the series of pixel data pieces at timings according to output timings of the plurality of latch timing signals and sequentially outputs each of the taken-in pixel data pieces, and the output delay control circuit includes a start pulse signal that outputs a start pulse signal consisting of a single pulse, a pulse output unit; first and second delay shift units each including a plurality of timing shift circuits cascade-connected to each other, each including the start pulse signal, and each of the plurality of timing shift circuits sequentially delaying the start pulse signal and outputting the start pulse signal to a next stage while outputting the plurality of latch timing signals; a bias voltage generation unit generating a bias voltage based on a spread setting signal that sets the delay amount of the start pulse signal in the first delay shift unit and the second delay shift unit, wherein each of the plurality of timing shift circuits has even-numbered inverters cascade-connected to each other, each receiving the start pulse signal at a first stage and outputting the latch timing signal from a final stage; and a delay adjustment unit that receives the bias voltage and changes the delay time of a signal output in at least one inverter of the even-numbered inverters based on the bias voltage. [Effects of the Invention]

[0011] According to the source driver of the present invention, it is possible to suppress the occurrence of display defects due to IR drop while suppressing an increase in chip area. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a block diagram showing a configuration of a source driver according to an embodiment of the present invention. [Figure 3] 10 is a time chart showing an example of the waveform of each of latch timing signals e1 to e960. [Figure 4] FIG. 2 is a block diagram showing the internal configuration of a delay control circuit. [Figure 5] FIG. 2 is a circuit diagram showing a configuration of a timing shift circuit. [Figure 6] FIG. 10 is a block diagram showing the internal configuration of a delay control circuit of a comparative example. [Figure 7] FIG. 10 is a circuit diagram showing a configuration of a timing shift circuit of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail. In the following description of the embodiments and the accompanying drawings, substantially the same or equivalent parts are designated by the same reference numerals.

[0014] 1 is a block diagram showing the configuration of a display device 100 according to a first embodiment of the present invention. The display device 100 is an active matrix liquid crystal display device. The display device 100 includes a display panel 11, a display controller 12, gate drivers 13A and 13B, and a source driver 14.

[0015] The display panel 11 is composed of a semiconductor substrate on which a plurality of pixel units P11 to Pnm and pixel switches M11 to Mnm (n is an integer of 2 or greater, and m is an integer of 2 or greater and a multiple of 3) are arranged in a matrix of n rows and m columns. The display panel 11 has n gate lines GL1 to GLn which are horizontal scanning lines, and m source lines SL1 to SLm which are arranged orthogonally to intersect the gate lines GL1 to GLn. The pixel units P11 to Pnm and pixel switches M11 to Mnm are provided at the intersections of the gate lines GL1 to GLn and the source lines SL1 to SLm, and are arranged in a matrix.

[0016] The pixel switches M11 to Mnm are controlled to be on or off in response to gate signals Vg1 to Vgn supplied from gate drivers 13A and 13B. The pixel units P11 to Pnm are supplied with pixel drive voltage signals Dv1 to Dvm corresponding to video data from the source driver 14. When the pixel switches M11 to Mnm are each on, the pixel drive voltage signals Dv1 to Dvm are applied to the pixel electrodes of the pixel units P11 to Pnm, charging each pixel electrode. The luminance of the pixel units P11 to Pnm is controlled in response to the pixel drive voltage signals Dv1 to Dvm at the pixel electrodes of the pixel units P11 to Pnm, and display is performed.

[0017] The display controller 12 receives the video data and generates a video data signal VDS including a series of pixel data fragments PD that represent the brightness level of each pixel in, for example, 256 8-bit brightness gradations. The video data signal VDS is configured as a video data signal serialized according to the number of transmission paths for each predetermined number of source lines.

[0018] In this embodiment, one frame of video data signal VDS is formed by serially connecting n pixel data fragment groups, each consisting of m pixel data fragments PD. Each of the n pixel data fragment groups is a pixel data fragment group consisting of pixel data fragments corresponding to the gradation voltages to be supplied to pixels on one horizontal scanning line (i.e., each of the gate lines GL1 to GLn). The operation of the source driver 14 generates a video data signal VDS for n×m pixel sections (i.e., pixel section P) based on the m×n pixel data fragments PD.11 ~P nm ) are generated, and pixel drive voltage signals G1 to Gm corresponding to these voltages are applied via source lines.

[0019] The display controller 12 also generates control signals including a start signal STP and a clock signal CLK. The start signal STP is a single pulse signal synchronized with the horizontal scanning synchronization signal included in the video data signal VDS.

[0020] Furthermore, the display controller 12 supplies gate timing signals indicating the timings for sequentially selecting the gate lines GL1 to GLn to the gate drivers 13A and 13B.

[0021] The gate drivers 13A and 13B receive a gate timing signal from the display controller 12, and sequentially supply gate signals Vg1 to Vgn to the gate lines GL1 to GLn based on the clock timing included in the gate timing signal.

[0022] The source driver 14 converts each of the plurality of pixel data pieces PD included in the video data signal VDS into an analog voltage having a magnitude corresponding to the luminance level indicated by the pixel data piece PD in response to the control signals (STP, CLK) supplied from the display controller 12. The source driver 14 outputs the voltages obtained by converting each of the plurality of pixel data pieces into analog voltages as pixel drive voltage signals G1 to Gm and supplies them to the source lines SL1 to SLm of the display panel 11.

[0023] In this embodiment, the following description will be given on the assumption that m=960, that is, the source driver 14 has 960 outputs.

[0024] 2 is a block diagram showing the configuration of the source driver 14. In this embodiment, the source driver 14 is formed on a single semiconductor IC (Integrated Circuit) chip.

[0025] The source driver 14 includes a shift register 21, a first data latch unit 22, a delay control circuit 23, a second data latch unit 24, a level shift unit 25, a DA (Digital to Analog) conversion unit 26, and an output amplifier unit 27.

[0026] The shift register 21 receives a start signal ST and a clock signal CLK, and generates latch timing signals t1 to t960 having different timings by shifting the start signal ST, which is a single pulse, in accordance with the clock signal CLK. The shift register 21 supplies the latch timing signals t1 to t960 to the first data latch unit 22.

[0027] The first data latch unit 22 receives a series of pixel data fragments PD contained in the video data signal VDS, captures each pixel data fragment PD at the timing of latch timing signals t1 to t960, and supplies the captured 960 pixel data fragments PD to the second data latch unit 24 as pixel data P1 to P960.

[0028] The delay control circuit receives the start signal ST and generates latch timing signals e1 to e960 in response to the start signal ST. The delay control circuit supplies the generated latch timing signals e1 to e960 to the second data latch unit .

[0029] 3 is a time chart showing an example of the signal waveforms of latch timing signals e1 to e960. The delay control circuit 23 generates latch timing signals e1 to e480 by delaying the pulse of start signal ST (shown as LOAD in the figure) in stages by a predetermined time dZ. The delay control circuit 23 also generates latch timing signals e960 to e481 by delaying the pulse of start signal ST in stages by a predetermined time dZ.

[0030] The second data latch section 24 sequentially receives the pixel data P1 to P960 supplied from the first data latch section 22 at timings according to the latch timing signals e1 to e960, and sequentially outputs the data to the level shift section 25 as pixel data Q1 to Q960, respectively.

[0031] That is, the second data latch unit 24 captures pixel data P1 at the rising edge of the latch timing signal e1 shown in Fig. 3 and outputs it as pixel data Q1 after a predetermined period has elapsed. The second data latch unit 24 also captures the captured pixel data P2 as pixel data Q2 at the rising edge of the latch timing signal e2 shown in Fig. 3 and outputs it as pixel data Q2 after a predetermined period has elapsed. In this way, the second data latch unit 24 captures pixel data Pi (i is an integer from 1 to 960) at the rising edge of the latch timing signal ei and outputs it as pixel data Qi at a timing corresponding to this.

[0032] The level shift unit 25 includes a plurality of level shifters, and performs level shift processing on each of the pixel data Q1 to Q960 to increase the amplitude of the signal representing each bit of the pixel data, and supplies the result to the DA conversion unit 26 as high-voltage pixel data signals L1 to L960.

[0033] The DA conversion unit 26 converts each of the pixel data signals L1 to L960 into a grayscale voltage having an analog voltage value corresponding to the brightness level represented by the pixel data signal, and supplies the converted grayscale voltages to the output amplifier unit 27 as the grayscale voltages V1 to V960, respectively.

[0034] The output amplifier section 27 amplifies the grayscale voltages V1 to V960 individually and outputs the amplified voltages as drive signals (pixel drive voltage signals) G1 to G960.

[0035] 4 is a block diagram showing the internal configuration of the delay control circuit 23. The delay control circuit 23 includes a first delay shift unit 31, a second delay shift unit 32, and a control unit 33. The first delay shift unit 31 and the second delay shift unit 32 are arranged on the right and left sides of the center portion of the chip that constitutes the source driver 14.

[0036] The first delay shift unit 31 receives a start pulse signal LD ​​from the control unit 33 and generates latch timing signals e1 to e480 in response to this. The first delay shift unit 31 delays the signal input thereto by a predetermined time dZ and outputs the delayed signal to the next stage, and includes a plurality of timing shift circuits TS (circuit units corresponding to 1ch to 480ch indicated by horizontal arrows in FIG. 4) that output the signals as latch timing signals e1 to e480.

[0037] The second delay shift unit 32 receives a start pulse signal LD ​​from the control unit 33 and generates latch timing signals e481 to e960 in response to this. The second delay shift unit 32 delays the signal input thereto by a predetermined time dZ and outputs the delayed signal to the next stage, and includes a plurality of timing shift circuits TS (circuit units corresponding to channels 481 to 960 indicated by horizontal arrows in FIG. 4) that output the signals as latch timing signals e481 to e960.

[0038] The control unit 33 is disposed in the center of the chip that constitutes the source driver 14. The control unit 33 includes a start pulse generation unit , a delay amount control unit 35, and a bias voltage generation unit .

[0039] The start pulse generating section 34 supplies a start pulse signal LD ​​consisting of a single pulse of logic level 1 to the first delay shift section 31 and the second delay shift section 132 in response to the start signal ST.

[0040] The delay amount control unit 35 supplies a 2-bit spread amount setting signal spdcr<1:0> that sets the delay amount of the timing shift in the first delay shift unit 31 to the bias voltage generation unit 36. The delay amount control unit 35 also supplies a 2-bit spread amount setting signal spdcl<1:0> that sets the delay amount of the timing shift in the second delay shift unit 32 to the bias voltage generation unit 36. For example, the delay amount control unit 35 reads setting information about the delay amounts of the timing shift in the first delay shift unit 31 and the second delay shift unit 32 from a register (not shown) provided in the source driver 14, and generates the spread amount setting signal spdcr<1:0> and the spread amount setting signal spdcl<1:0> based on this information.

[0041] The bias voltage generation unit 36 ​​generates a bias voltage BVR based on the spread amount setting signal spdcr<1:0> supplied from the delay amount control unit 35. The bias voltage generation unit 36 ​​also generates a bias voltage BVL based on the spread amount setting signal spdcl<1:0> supplied from the delay amount control unit 35. The bias voltage generation unit 36 ​​generates bias voltages BVR and BVL, which are voltage signals whose signal levels change between logic level 0 (L level) and logic level 1 (H level), respectively. The bias voltage generation unit 36 ​​supplies the bias voltage BVR to the first delay shift unit 31 and the bias voltage BVL to the second delay shift unit 32.

[0042] FIG. 5 is a circuit diagram showing the configuration of one of the multiple-stage timing shift circuits TS included in the second delay shift section 32. As shown in FIG.

[0043] The timing shift circuit TS includes a first inverter 41, a second inverter 42, a third inverter 43, a fourth inverter 44, and a load resistor unit 45.

[0044] The first inverter 41 receives the output of the preceding timing shift circuit TS as an input signal LDIN and outputs an inverted signal from its output terminal. For example, the first inverter 41 of the first-stage timing shift circuit TS of a multi-stage timing shift circuit TS receives the start pulse signal LD ​​supplied from the start pulse generating unit as the input signal LDIN. The first inverter 41 of the second-stage or later timing shift circuit TS receives the output signal LDOUT of the preceding timing shift circuit TS as the input signal LDIN.

[0045] The second inverter 42 is an inverter circuit that receives the output signal of the first inverter 41 and outputs an inverted signal. The second inverter 42 is composed of transistors NM1 and PM1. In this embodiment, the transistor NM1 is composed of an N-channel MOS transistor, and the transistor PM1 is composed of a P-channel MOS transistor.

[0046] The gates of the transistors NM1 and PM1 are connected to each other and to the output terminal of the first inverter 41. The drains of the transistors PM1 and NM1 are connected to each other and to a node n1. The source of the transistor NM1 is connected to a supply line of a reference voltage. In this embodiment, the reference voltage is a ground potential. The output signal of the second inverter 42 is output to the node n1 via a connection terminal connecting the drains of the transistors NM1 and PM1.

[0047] The third inverter 43 has an input terminal connected to the node n1. The third inverter 43 outputs a signal obtained by inverting the potential of the node n1 from its output terminal. The node n1 is connected to the gate of the transistor NM2, which is an N-channel MOS transistor.

[0048] The input terminal of the fourth inverter 44 is connected to the output terminal of the third inverter 43. The fourth inverter 44 receives the output signal of the third inverter 43, inverts it, and outputs the inverted signal from the output terminal as the output signal LDOUT. The output signal LDOUT is a signal obtained by delaying the input signal LDIN through the first inverter 41 to the fourth inverter 44, in other words, a signal obtained by delaying the start pulse LD through one or more timing shift circuits TS. The output signal LDOUT is supplied to the timing shift circuit TS of the next stage and is also output as the latch timing signal ei (for example, one of the output signals e481 to e960 in the second delay shift unit 32).

[0049] The load resistor 45 is composed of a P-channel MOS transistor PM2. The drain of the transistor PM2 is connected to the source of the transistor PM1, and the source is connected to the voltage supply line of the VDD power supply. A bias voltage BVL is applied to the gate of the transistor PM2.

[0050] The transistor PM2 has properties as a load resistor connected to the second inverter 42. The value of the load resistor connected to the second inverter 42 changes in response to changes in the bias voltage BVL, thereby changing the amount of delay during the inversion operation of the second inverter 42. That is, according to the configuration of this embodiment, it is possible to change the amount of delay in the timing shift circuit TS by changing the value of the bias voltage BVL.

[0051] The second delay shift unit 32 is configured by cascading timing shift circuits TS having such a configuration in a number corresponding to half the number of output channels of the source driver 14 (i.e., 960ch to 481ch). Similarly, the first delay shift unit 31 is configured by cascading a plurality of timing shift circuits (1ch to 480ch) having a configuration obtained by left-right inverting the timing shift circuit TS shown in FIG.

[0052] In the delay control circuit 23 of this embodiment, a control unit 33 arranged in the center of the chip converts the spread amount setting signal spdcr<1:0> to a bias voltage BVR and the spread amount setting signal spdcl<1:0> to a bias voltage BVL, and supplies these to the first delay shift unit 31 and the second delay shift unit 32 to switch the delay amount and adjust the timing (output timing) at which the latch timing signals e1 to e960 are output. Adjusting the output timing of the latch timing signals e1 to e960 adjusts the timing of data latching in the second data latch unit 24, and thereby adjusts the timing at which the pixel drive voltage signals Dv1 to Dvm are output from the source driver 14, i.e., the drive timing of the source driver 14.

[0053] According to this configuration, the signal lines for switching the delay amount are only the bias lines (i.e., the supply lines for the bias voltages BVR and BVL), so it is possible to adjust the drive timing of the source driver 14 without increasing the Y dimension (length in the Y direction) of the bit cell. By adjusting the drive timing of the source driver 14, it is possible to suppress the occurrence of IR drop caused by simultaneous operation of multiple level shifters in the level shift unit 25 and the occurrence of display defects due to the occurrence of IR drop.

[0054] Figure 6 is a block diagram showing the internal configuration of a delay control circuit 23A of a comparative example, which, unlike the present embodiment, switches the delay amount by supplying the spread amount setting signals spdcr<1:0> and spdcl<1:0> directly to the first delay shift section 31 and the second delay shift section 32.

[0055] The control section 33A is made up of a start pulse generation section 34A and a delay amount control section 35. The start pulse generation section 34A supplies a start pulse signal LD ​​to the first delay shift section 31 and the second delay shift section 132.

[0056] The delay amount control unit 35A supplies the spread amount setting signal spdcr<1:0> to the first delay shift unit 31A, and also supplies the spread amount setting signal spdcl<1:0> to the second delay shift unit 32A.

[0057] FIG. 7 is a circuit diagram showing the configuration of one of the multiple-stage timing shift circuits TC included in the second delay shift section 32A of the comparative example.

[0058] The timing shift circuit TC includes a first inverter 51, a second inverter 52, a third inverter 53, a fourth inverter 54, a decoder 55, and a load capacitance unit 56.

[0059] The first inverter 51, the second inverter 52, the third inverter 53, and the fourth inverter 54 are connected in cascade. A start pulse signal LD ​​is input to the first inverter 51 as "LDIN," passes through the second inverter 52 and the third inverter 53, and is output from the fourth inverter 54 as "LDOUT."

[0060] The decoder 55 receives the 2-bit spread amount setting signal spdcl<1:0> and decodes it to generate 4-bit delay amount setting signals spdc<3:0> and xspdc<3:0>.

[0061] The load capacitance unit 56 is connected to a node between the output terminal of the second inverter 52 and the input terminal of the third inverter 53. The load capacitance unit 56 is configured to be able to change the load capacitance connected to the node based on the delay amount setting signals spdc<3:0> and xspdc<3:0> output from the decoder 55.

[0062] The delay amount in the second delay shift unit 32A is changed by changing the load capacitance values ​​in the multiple-stage timing shift circuits TC in response to the spread amount setting signal spdcl<1:0>. The delay amount in the first delay shift unit 31A is also changed in a similar manner.

[0063] In the configuration of the comparative example, the delay amount control unit 35A supplies 2-bit spread amount setting signals spdcl<1:0> and spdcr<1:0> to control the delay amount in the first delay shift unit 31A and the second delay shift unit 32A. Therefore, two signal lines are required to supply 2-bit signals to switch the delay amount. In other words, in the configuration of the delay control circuit 23A of the comparative example, if detailed control of the delay amount switching is desired, signals equivalent to the number of control bits must be sent to each of the first delay shift unit 31A and the second delay shift unit 32A, which increases the size of the bit cell.

[0064] In contrast, in the delay control circuit 23 of this embodiment, the bias voltage generation unit 36 ​​generates bias voltages BVR and BVL based on the spread amount setting signals spdcr<1:0> and spdcl<1:0> and supplies them to the first delay shift unit 31 and the second delay shift unit 32. With this configuration, only one signal line is required for switching the delay amount, so that the delay amount can be switched without increasing the size of the bit cell (the dimension in the Y direction).

[0065] As described above, the delay control circuit 23 of this embodiment can finely adjust the drive timing of the source driver 14 while suppressing an increase in chip area. This makes it possible to adjust the drive timing of the source driver 14 so as to reduce the number of simultaneously operating level shifters, thereby suppressing display defects caused by IR drop.

[0066] The present invention is not limited to the above-described embodiments. For example, in the above-described embodiments, the first delay shift unit 31 and the second delay shift unit 32 are each configured with four inverters. However, the number of inverters is not limited to this, and it is sufficient that the first delay shift unit 31 and the second delay shift unit 32 are configured with an even number of cascaded inverters.

[0067] In the above embodiment, the load resistor 45 receiving the bias voltage BVR or BVL is configured with the transistor PM2, which is a P-channel MOS transistor, and is inserted between the source of the transistor PM1 and the voltage supply line of the VDD power supply. However, the configuration and location of the load resistor 45 are not limited to this, and it may be configured with an N-channel MOS transistor and inserted between the source of the transistor NM1 and the supply line of the reference potential. [Explanation of symbols]

[0068] 100 display device 11 Display panel 12 Display Controller 13 Gate Driver 14 Source Driver 21 Shift Register 22 First data latch section 23 Delay control circuit 24 Second data latch section 25 Level shift section 26 DA conversion section 27 Output amplifier section 31 First delay shift unit 32 Second delay shift section 33 Control Unit 34 Start pulse generator 35 Delay amount control section 36 Bias voltage generation unit 41 First inverter 42 Second inverter 43 Third inverter 44 4th inverter 45 Load resistance section

Claims

1. A source driver is connected to a display panel having a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each of intersections of the plurality of source lines and the plurality of gate lines, the source driver having a plurality of output channels for outputting drive signals to the plurality of source lines based on a video data signal consisting of a series of pixel data pieces, an output delay control circuit that sequentially outputs a plurality of latch timing signals corresponding to the plurality of output channels, respectively; a data latch unit that sequentially acquires the pixel data pieces at timings corresponding to output timings of the plurality of latch timing signals and sequentially outputs each of the acquired pixel data pieces; Including, The output delay control circuit includes: a start pulse output unit that outputs a start pulse signal consisting of a single pulse; a first delay shift unit and a second delay shift unit each including a plurality of timing shift circuits connected in cascade to each other, receiving the start pulse signal, each of the plurality of timing shift circuits sequentially delaying the start pulse signal and outputting the start pulse signal to a next stage, and outputting the plurality of latch timing signals; a bias voltage generation unit that generates a bias voltage based on a spread setting signal that sets the delay amount of the start pulse signal in the first delay shift unit and the second delay shift unit; Including, Each of the plurality of timing shift circuits an even number of inverter stages connected in cascade to each other, the first stage of which receives the start pulse signal and the last stage of which outputs the latch timing signal; a delay adjusting unit configured to receive the bias voltage and change a delay time of a signal output from at least one inverter among the even-numbered inverters based on the bias voltage; A source driver comprising:

2. the delay adjustment unit is composed of a transistor having a control terminal to which the bias voltage is applied, 2. The source driver according to claim 1, wherein the at least one inverter is connected in series between a supply line of a power supply voltage and a supply line of a reference voltage.

3. the at least one inverter is an even-numbered inverter from the input side of the even-numbered inverters, 3. The source driver according to claim 2, wherein the transistor constituting the delay adjustment unit is connected between a supply line of the power supply voltage and a positive power supply input terminal of the at least one inverter, or between a supply line of the reference voltage and a negative power supply input terminal of the at least one inverter.

4. the at least one inverter is composed of a P-channel MOS transistor and an N-channel MOS transistor, the drains of which are connected to each other and the gates of which are connected to each other; 4. The source driver according to claim 3, wherein the transistor constituting the delay adjustment section is inserted between the source of the P-channel MOS transistor and a supply line of the power supply voltage.

5. the at least one inverter is composed of a P-channel MOS transistor and an N-channel MOS transistor, the drains of which are connected to each other and the gates of which are connected to each other; 4. The source driver according to claim 3, wherein the transistor constituting the delay adjustment section is inserted between the source of the N-channel MOS transistor and a supply line of the reference voltage.

6. a display panel including a plurality of source lines and a plurality of gate lines, and a plurality of pixel units arranged in a matrix at each of the intersections of the plurality of source lines and the plurality of gate lines; a gate driver that supplies gate signals to the plurality of gate lines; a source driver that receives a video data signal consisting of a series of pixel data pieces and outputs drive signals to the plurality of source lines; Including, The source driver a plurality of output channels for outputting the driving voltage signals; an output delay control circuit that sequentially outputs a plurality of latch timing signals corresponding to the plurality of output channels, respectively; a data latch unit that sequentially acquires the series of pixel data pieces at timings corresponding to output timings of the plurality of latch timing signals and sequentially outputs each of the acquired pixel data pieces; Including, The output delay control circuit includes: a start pulse output unit that outputs a start pulse signal consisting of a single pulse; a first delay shift unit and a second delay shift unit each including a plurality of timing shift circuits connected in cascade to each other, receiving the start pulse signal, each of the plurality of timing shift circuits sequentially delaying the start pulse signal and outputting the start pulse signal to a next stage, and outputting the plurality of latch timing signals; a bias voltage generation unit that generates a bias voltage based on a spread setting signal that sets the delay amount of the start pulse signal in the first delay shift unit and the second delay shift unit; Including, Each of the plurality of timing shift circuits an even number of inverter stages connected in cascade to each other, the first stage of which receives the start pulse signal and the last stage of which outputs the latch timing signal; a delay adjusting unit configured to receive the bias voltage and change a delay time of a signal output from at least one inverter among the even-numbered inverters based on the bias voltage; A display device comprising:

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