Manufacturing method for semiconductor device

Abstract

To provide a technique of being able to transport a semiconductor substrate suitably.SOLUTION: A manufacturing method for a semiconductor device includes a processing step and a transporting step. In the processing step, a semiconductor substrate formed of silicon carbide and having a diameter W of 200 mm or more is processed to form a semiconductor element. In the transporting step, the semiconductor substrate is accommodated and transported on FOUP, which is a transport carrier that can accommodate 25 semiconductor substrates at maximum either before or after, or both before and after the processing.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] There has been a shift to semiconductor devices made of SiC (silicon carbide), which is expected to have lower loss and higher reliability than semiconductor devices made of Si (silicon). Semiconductor devices made of Si are manufactured from Si semiconductor substrates, and semiconductor devices made of SiC are manufactured from SiC semiconductor substrates. The Si semiconductor substrates and SiC semiconductor substrates are transported between processing equipment while housed in a transport carrier (also called a transport container), and semiconductor elements are formed on the semiconductor substrates by performing different processes in each processing equipment (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-142620 Summary of the Invention [Problem to be solved by the invention]

[0004] SiC semiconductor substrates differ not only in material from Si semiconductor substrates but also in shape, such as thickness, and the amount of deformation due to bending, such as warping, caused by the weight of the SiC semiconductor substrate may be greater than that of the Si semiconductor substrate. Furthermore, the amount of deformation is significant for SiC semiconductor substrates with a diameter of 200 mm or more. Therefore, when a transport carrier is loaded with multiple SiC semiconductor substrates with a diameter of 200 mm or more, adjacent SiC semiconductor substrates may come into contact with each other during transport, causing problems.

[0005] On the other hand, in the conventional technology, a Standard Mechanical Interface (SMIF) is used as a transport carrier for storing and transporting SiC semiconductor substrates. However, in the SMIF, the housing for storing the SiC semiconductor substrates is small and the distance between the stored SiC semiconductor substrates is short, so due to the above-mentioned problem, it is not possible to transport 25 semiconductor substrates as a single unit, which causes a problem of poor manufacturability.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that enables appropriate transport of semiconductor substrates. [Means for solving the problem]

[0007] The method for manufacturing a semiconductor device according to the present disclosure includes the steps of preparing a semiconductor substrate made of silicon carbide and having a diameter W of 200 mm or more, processing the semiconductor substrate to form semiconductor elements, and, at least either before or after the processing, placing and transporting the semiconductor substrate in a FOUP, which is a transport carrier capable of holding up to 25 of the semiconductor substrates. [Effects of the Invention]

[0008] According to the present disclosure, semiconductor substrates are stored and transported in a FOUP that is made of silicon carbide and has a diameter W of 200 mm or more and can accommodate up to 25 semiconductor substrates. With this configuration, the semiconductor substrates can be transported appropriately. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a top view showing the configuration of a FOUP used in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 2] 1 is a cross-sectional view showing the configuration of a part of a FOUP used in a method for manufacturing a semiconductor device according to a first embodiment. [Figure 3] 1 is a top view showing the configuration of a FOUP used in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] 1 is a top view showing the configuration of a FOUP used in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 4 is a two-dimensional map showing the amount of bending of the semiconductor substrate of the semiconductor device according to the first embodiment. [Figure 9] 4 is a two-dimensional map showing the amount of bending of the semiconductor substrate of the semiconductor device according to the first embodiment. [Figure 10] 10 is a diagram showing the relationship between the angles of the upper and lower supports and the maximum amount of deflection of a semiconductor substrate accommodated in a FOUP according to the first embodiment. FIG. [Figure 11] 10 is a cross-sectional view showing a part of the configuration of a FOUP used in a method for manufacturing a semiconductor device according to a second embodiment. [Figure 12] FIG. 11 is a cross-sectional view showing a part of the configuration of a FOUP used in a method for manufacturing a semiconductor device according to a third embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing a part of the configuration of a FOUP used in a method for manufacturing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In addition, in the following description, specific positions and directions such as "upper," "lower," "left," and "right" may not necessarily correspond to positions and directions in actual implementation.

[0011] <First Embodiment> In the method for manufacturing a semiconductor device according to the first embodiment, a FOUP (Front Opening Unified Pod) is used as a transport carrier for storing and transporting SiC semiconductor substrates. Fig. 1 is a top view showing the configuration of a FOUP100 used in the method for manufacturing a semiconductor device according to the first embodiment, and Fig. 2 is a cross-sectional view taken along line A-A' in Fig. 1.

[0012] The semiconductor substrate 106 housed and transported in the FOUP 100 has a diameter W of 200 mm (8 inches) or more and is made of SiC (silicon carbide). Note that the semiconductor substrate 106 may be made of a wide bandgap semiconductor other than SiC, such as GaN (gallium nitride), Ga2O3 (gallium oxide), or diamond. A semiconductor device formed from a semiconductor substrate 106 of a wide bandgap semiconductor enables stable operation at high temperatures and high voltages, and high switching speeds. The following description mainly focuses on the case where the diameter W of the semiconductor substrate 106 is 200 mm. If the semiconductor substrate 106 is a 12-inch semiconductor substrate, the diameter W may be interpreted as 300 mm. Note that the diameter W indicates the dimensions at the time of manufacturing and shipping by the semiconductor substrate manufacturer.

[0013] The semiconductor substrate 106 is composed of, for example, at least one of a normal semiconductor wafer and an epitaxially grown layer. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more types extracted from the group A, B, C, ..., and Z. The semiconductor substrate 106 according to the first embodiment may be a semiconductor substrate 106a with a small amount of bending, or may be a semiconductor substrate 106b with a large amount of bending, as shown in FIG.

[0014] FOUP 100 is a transport carrier that can accommodate a maximum of 25 semiconductor substrates 106. As shown in Figures 1 and 2, FOUP 100 includes a partition 101, an upper support point 102, a lower support point 103, a housing 104, and a lid 105. In the following description, when there is no need to distinguish between the upper support point 102 and the lower support point 103, they may be collectively referred to as "plural support points."

[0015] The housing 104 has an opening that faces the first direction and through which the semiconductor substrate 106 is inserted and removed. When the semiconductor substrate 106 is not being inserted and removed, the opening of the housing 104 is closed by the lid 105.

[0016] As shown in FIG. 2, the partition 101 has an extending portion that extends in a second direction perpendicular to the first direction, and although not shown, both ends of the extending portion in the extending direction are connected (fixed) to the inside of the housing 104. The partition 101 also has a protruding portion that protrudes in a third direction perpendicular to the first and second directions. The partition 101 is configured to be able to accommodate a plurality of semiconductor substrates 106, up to 25 of which are arranged at intervals of 10 mm in the second direction, with the protruding portion separating the outer peripheries of the plurality of semiconductor substrates 106. Note that in this specification, numerical values ​​such as 10 mm may have a normal degree of error.

[0017] 1, when the opening of the housing 104 is closed by the lid 105, the end of the semiconductor substrate 106 accommodated in the partition 101 on the opening side abuts against the lid 105. Therefore, when the opening of the housing 104 is closed by the lid 105, the position of the semiconductor substrate 106 in the first direction and the third direction is fixed by the partition 101 and the lid 105. Note that in FIG. 1, the semiconductor substrate 106 is accommodated in the partition 101 so that the notch 108 of the semiconductor substrate 106 faces in the direction away from the opening, but the semiconductor substrate 106 may be accommodated in the partition 101 so that the notch 108 faces in a direction other than this. Furthermore, when multiple semiconductor substrates 106 are accommodated in the partition 101, the directions in which the notches 108 of the multiple semiconductor substrates 106 face do not have to be the same.

[0018] The plurality of fulcrums includes an upper fulcrum 102 which is the fulcrum closest to the opening, and a lower fulcrum 103 which is the fulcrum farthest from the opening. As shown in FIG. 2, the plurality of fulcrums protrude from the partition portion 101 in the second direction. The distance between the tips of the adjacent fulcrums in the second direction is 10 mm, and the distance between the adjacent fulcrums in the second direction is less than 10 mm. When the FOUP 100 is arranged in a posture with the second direction upward, the plurality of fulcrums support both ends of each of the plurality of semiconductor substrates 106 accommodated in the partition portion 101 along the second direction.

[0019] In the manufacturing process of a semiconductor device such as a power device, the semiconductor substrate 106 is transported from the FOUP 100 to a processing apparatus for processing by a wafer hand not shown. Then, the processing apparatus performs processing for forming semiconductor elements to be products on the upper surface which is the first main surface of the semiconductor substrate 106, or on the lower surface which is the second main surface opposite to the first main surface. Then, the semiconductor substrate 106 is transported from the processing apparatus to the FOUP 100 by a wafer hand.

[0020] Note that, in order to suppress damage to the semiconductor elements, it is desirable that the wafer hand for transporting the semiconductor substrate 106 does not contact the semiconductor element formation region which is the region where the semiconductor elements are formed. In order to achieve this, it is preferable that an invalid region where the wafer hand contacts and where semiconductor elements are not formed is provided within 5.0 mm from the outer peripheral portion of the semiconductor substrate 106. Also, when performing processing to adjust the shape of the outer peripheral portion of the semiconductor substrate 106 as processing on the lower surface side of the semiconductor substrate 106, the lower diameter W of the semiconductor substrate 106 may be, for example, a size of 200 mm or less such as 198 mm (=W - 2 mm). From this also, it is preferable that the above invalid region is provided within 5.0 mm from the outer peripheral portion of the semiconductor substrate 106. When forming such an invalid region on a semiconductor substrate 106 having a diameter W of 200 mm, the range with a radius of 95 mm (diameter 190 mm) from the center of the semiconductor substrate 106 becomes the effective region where semiconductor elements are formed. That is, regarding the diameter W' of the effective region as shown in FIG. 1, it is desirable that W - 10 mm < W' < W holds.

[0021] According to the FOUP 100 described above, the size of the housing 104 and the distances between the multiple fulcrums in the second and third directions can be made larger than those of a Standard Mechanical Interface (SMIF). This allows the distances between the multiple semiconductor substrates 106 housed in the partition section 101 to be increased, so that up to 25 semiconductor substrates 106 can be transported as one unit while preventing contact between the semiconductor substrates 106. As a result, productivity can be improved.

[0022] Furthermore, the multiple fulcrums provided in the partition 101 shift the bent portion of the semiconductor substrate 106 in the direction opposite to the direction of the bend, thereby preventing the wafer hand moving in the first direction from unintentionally coming into contact with the bent portion of the semiconductor substrate 106. Note that, although the partition 101 houses the semiconductor substrate 106a with a small amount of bend and the semiconductor substrate 106b with a large amount of bend in FIG. 2, either the semiconductor substrate 106a or the semiconductor substrate 106b may be housed in the partition 101.

[0023] Furthermore, the partition 101 of the FOUP 100 described above has a bent shape when viewed from the second direction as shown in FIG. 1, but this is not limited thereto and may have, for example, a straight, unbent shape. Also, in FIG. 1, the upper fulcrum 102 and the lower fulcrum 103 are provided in the same partition 101, but this is not limited thereto. For example, as shown in FIG. 3, the partition 101 may include a first partition 101a and a second partition 101b located on the opposite side of the opening from the first partition 101a. The upper fulcrum 102 and the lower fulcrum 103 may be provided in different partitions 101, such as a configuration in which the upper fulcrum 102 protrudes from the first partition 101a and the lower fulcrum 103 protrudes from the second partition 101b.

[0024] 4, like Fig. 1, is a top view showing the configuration of FOUP 100 according to the first embodiment, and shows the arrangement of upper fulcrums 102 and lower fulcrums 103 as viewed from the second direction. Fig. 4 shows a center O of semiconductor substrate 106 accommodated in partition 101, line X-X' that is parallel to the third direction and passes through center O, and line Y-Y' that is parallel to the first direction and passes through center O.

[0025] In the first embodiment, an angle 114 formed by a direction 111 from the center O of a semiconductor substrate 106 accommodated in the partition 101 toward the upper fulcrum 102, which is the closest of the multiple fulcrums to the opening, and the third direction of the X-X' line is 13° or more and 46° or less. Also, an angle 115 formed by a direction 112 from the center O of a semiconductor substrate 106 accommodated in the partition 101 toward the lower fulcrum 103, which is the farthest of the multiple fulcrums from the opening, and the third direction of the X-X' line is 13° or more and 46° or less. As will be described in detail later, this configuration makes it possible to suppress bending of the semiconductor substrate 106 accommodated in the FOUP 100.

[0026] In the first embodiment, the distance L (see FIG. 2) in the third direction between the upper supports 102 capable of supporting both ends of the semiconductor substrate 106 is greater than W×cos 46° mm and less than W×cos 13° mm. W' is the diameter of the effective area of ​​the semiconductor substrate 106 (see FIG. 1). Although not shown, the distance in the third direction between the lower supports 103 capable of supporting both ends of the semiconductor substrate 106 is also greater than W×cos 46° mm and less than W×cos 13° mm.

[0027] <Manufacturing method> Fig. 5 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. Fig. 5 shows a process for storing and transporting semiconductor substrates 106 in a FOUP 100, which is a transport carrier capable of storing up to 25 semiconductor substrates 106. The process of Fig. 5 is performed at least either before or after processing, which will be described later, for forming semiconductor elements on the semiconductor substrates 106.

[0028] In step S1, the FOUP 100 containing the semiconductor substrates 106 is transported from an AGV (Automatic Guided Vehicle) or an OHT (Overhead Hoist Transport) to a load port and loaded thereon.

[0029] In step S2, the load port reads the carrier ID attached to the FOUP 100, and in step S3, the load port moves the FOUP 100 and connects it to a predetermined entrance / exit so that the wafer hand can transport the semiconductor substrates 106 contained in the FOUP 100 to the processing equipment.

[0030] In step S4, the lid 105 of the FOUP 100 is opened, and in step S5, mapping is performed to measure the positions and number of semiconductor substrates 106 accommodated in the FOUP 100. In step S6, the wafer hand transports the semiconductor substrates 106 accommodated in the FOUP 100 from the FOUP 100 to a processing device. In step S7, the processing device processes the transported semiconductor substrates 106 to form semiconductor elements. In step S8, the wafer hand transports the processed semiconductor substrates 106 from the processing device to the FOUP 100 and accommodates them. Steps S6 to S8 are usually performed for each semiconductor substrate 106 accommodated in the FOUP 100.

[0031] In step S9, the lid 105 of the FOUP 100 is closed, and in step S10, the load port releases the connection between the FOUP 100 and the entrance and moves the FOUP 100 so that the AGV or OHT can transport the FOUP 100. In step S11, the AGV or OHT transports the FOUP 100.

[0032] FIG. 6 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment, and shows an example of processing for forming semiconductor elements on a semiconductor substrate 106. FIG. 7 is a cross-sectional view of a semiconductor substrate 106 illustrating the method for manufacturing a semiconductor device according to the first embodiment. Hereinafter, a method for manufacturing an active region of a planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which is one type of semiconductor device, will be described. However, the semiconductor device may also be a trench MOSFET, an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting - IGBT), an SBD (Schottky Barrier Diode), or a PND (PN junction diode). In the first embodiment, the active region is the above-mentioned semiconductor element formation region.

[0033] The processing for forming a semiconductor element on the semiconductor substrate 106 includes a semiconductor substrate preparation step (step S21), an upper surface side p-type region formation step (step S22), an upper surface side n-type region formation step (step S23), an upper surface side gate electrode formation step (step S24), an upper surface side source electrode formation step (step S25), an upper surface side protective film formation step (step S26), a lower surface side grinding step (step S27), a lower surface side drain electrode formation step (step S28), an upper surface side protective film removal step (step S29), and a dicing step (step S30).

[0034] It should be noted that the processing performed before or after the transport of the FOUP 100 does not have to include all of the above steps. For example, if it is necessary to transfer the semiconductor substrate 106 to a dedicated carrier in the dicing step of step S30, the processing performed before or after the transport of the FOUP 100 does not have to include the dicing step of step S30. The steps in FIGS. 6 and 7 will be described below.

[0035] In the semiconductor substrate preparation step (step S21), multiple semiconductor substrates 106 are prepared to become the n-type drift layer 200 in Fig. 7. In this step, semiconductor substrates made of silicon carbide and having a diameter W of 200 mm or more are prepared. For convenience in the following description of the manufacturing steps, a configuration in which other semiconductor layers and electrodes are formed on the n-type drift layer 200 will also be referred to as semiconductor substrate 106.

[0036] In the upper surface side p-type region formation process (step S22), an ion implantation process and a heating process are performed. In the ion implantation process, donor ions are implanted into the upper surface side of the semiconductor substrate 106. For example, boron and aluminum are used as the donor. In the heating process, the semiconductor substrate 106 is heated to electrically activate the donor. As a result of the above, the p-type region 201 is formed.

[0037] The upper surface side n-type region forming process (step S23) includes an exposure process, an etching process, an ion implantation process, and a heating process. In the exposure process, a photoresist having a uniform thickness is applied to the upper surface side of the semiconductor substrate 106. The photoresist may be either photosensitive or non-photosensitive. Then, the photoresist film is selectively exposed from the upper surface side of the semiconductor substrate 106 using a photomask. In the etching process, the photoresist film is selectively removed by dry etching or wet etching the photoresist film.

[0038] In the ion implantation process, acceptor ions are implanted into the upper surface of the p-type region 201 exposed from the photoresist film, and then the remaining photoresist film is removed. Examples of acceptors include nitrogen and phosphorus. In the heating process, the semiconductor substrate 106 is heated to electrically activate the acceptor ions. As a result, the n-type region 202 is formed. By performing the exposure process and etching process in this manner, patterned impurity regions and films can be formed, and the impurity regions and films can be selectively formed in the semiconductor substrate 106. For the sake of convenience, the following description may omit the removal of the remaining photoresist film, the exposure process, and the etching process. By performing the ion implantation process and the heating process, a semiconductor element is formed in the semiconductor substrate.

[0039] The upper gate electrode formation process (step S24) includes an oxide film formation process, a polysilicon film formation process, an exposure process, an etching process, and an oxide film formation process. In the oxide film formation process, the semiconductor substrate 106 is heated in an oxygen-containing atmosphere to form an oxide film 203 on the p-type region 201 and the n-type region 202. In the polysilicon film formation process, a polysilicon film doped with n-type or p-type impurities is deposited by CVD (Chemical Vapor Deposition) or the like. In the exposure process, a photoresist with a uniform thickness is applied to the upper surface of the semiconductor substrate 106. The photoresist may be either photosensitive or non-photosensitive. Then, the photoresist film is selectively exposed from the upper surface of the semiconductor substrate 106 using a photomask.

[0040] In the etching process, the photoresist film is selectively removed by dry etching or wet etching. Then, the polysilicon film exposed from the photoresist film is removed to form a gate electrode 204 that faces the upper part of the p-type region 201 via the oxide film 203. In the oxide film formation process, the semiconductor substrate 106 is heated in an oxygen-containing atmosphere or CVD is performed to form an oxide film 205 that covers the gate electrode 204. Then, the oxide films 203 and 205 between the gate electrodes 204 are removed to expose the n-type region 202.

[0041] In the upper surface source electrode formation process (step S25), a source electrode 206 connected to the n-type region 202 is formed on the upper surface of the semiconductor substrate 106 using a sputtering device or the like. The source electrode 206 is made of a material such as nickel. Note that, in order to reduce the contact resistance of the source electrode 206, the source electrode 206 may be formed after a heat treatment and a silicide process are performed on the upper surface of the n-type region 202.

[0042] In the upper surface protective film forming process (step S26), a protective film 207 is formed on the source electrode 206, i.e., on the upper surface side of the semiconductor substrate 106. For example, a tape or a glass plate is used as the protective film 207, but from a cost perspective, a thin one is more preferable. In the processes up to this point, the thickness of the semiconductor substrate 106 is sufficiently large, so that the deflection of the semiconductor substrate 106 within the FOUP 100 is about a few tenths of a millimeter.

[0043] In the bottom-side grinding process (step S27), the semiconductor substrate 106 is turned over, the protective film 207 on the top side of the semiconductor substrate 106 is adsorbed onto the stage of a grinding device, and the bottom side of the semiconductor substrate 106 is ground so that the thickness of the n-type drift layer 200 becomes several hundred micrometers. For example, Japanese Patent No. 6194210 proposes a grinding method that leaves a rim to prevent the semiconductor substrate 106 from warping. However, when the semiconductor substrate 106 is made of a hard and brittle material such as SiC, it is desirable to grind the semiconductor substrate 106 so that the thickness is uniform throughout in order to prevent wear of the grinding stone and cracking of the semiconductor substrate 106. Since a damaged layer remains on the surface of the bottom side of the semiconductor substrate 106 after grinding, the damaged layer may be removed by etching.

[0044] After grinding, the semiconductor substrate 106 is easily deformed, and like the semiconductor substrate 106a accommodated in the FOUP 100 in FIG. 2, the deflection in the second direction due to its own weight is greatest at the center.

[0045] In the lower surface drain electrode formation step (step S28), a drain electrode 208 is formed on the lower surface of the semiconductor substrate 106 using a sputtering device or the like, as shown in FIG. 7. The drain electrode 208 is made of, for example, nickel or titanium. Note that, in order to reduce the contact resistance of the drain electrode 208, a heat treatment and a silicide process may be performed on the lower surface of the n-type drift layer 200 (corresponding to the upper surface in step S28 of FIG. 7) before the drain electrode 208 is formed. For example, a laser is used for the heat treatment.

[0046] In the upper surface side protective film removal process (step S29), the semiconductor substrate 106 is turned over, and the protective film 207 provided on the upper surface side of the semiconductor substrate 106 is removed. If the protective film 207 is a tape, the tape is physically peeled off from the semiconductor substrate 106, and any tape adhesive residue is removed by wet etching or the like. Note that if the heat resistance temperature of the protective film 207 is lower than the temperature rise in the lower surface side drain electrode process (step S28), it is preferable to reverse the order of the lower surface side drain electrode process (step S28) and the upper surface side protective film removal process (step S29).

[0047] In the dicing process (step S30), each semiconductor element is cut out from the semiconductor substrate 106. Through the above processes, the semiconductor elements are fabricated as semiconductor devices. However, the semiconductor device that is the target of the semiconductor device manufacturing method may be a semiconductor module in which, for example, wires are provided on the semiconductor elements and then sealed with a sealing resin, or may further be a device incorporating such a semiconductor module.

[0048] <Summary of the First Embodiment> According to the method for manufacturing a semiconductor device according to the first embodiment, semiconductor substrates 106 are stored and transported in FOUP 100, which is made of silicon carbide and has a diameter W of 200 mm or more and can accommodate a maximum of 25 semiconductor substrates 106. With this configuration, contact between semiconductor substrates 106 is suppressed, and a maximum of 25 semiconductor substrates 106 can be transported as a single unit, thereby improving productivity.

[0049] The above effect is particularly effective when up to 25 semiconductor substrates 106 are transported after the bottom surface grinding step (step S27), which increases the amount of bending of the semiconductor substrates 106. Also, the above effect is particularly effective when a tape that increases the amount of bending of the semiconductor substrates 106 is used as the protective film 207 in the top surface side protective film forming step (step S26). Also, when a glass plate is used as the protective film 207 in the top surface side protective film forming step (step S26), the amount of bending of the semiconductor substrates 106 can be reduced.

[0050] Furthermore, in the first embodiment, since the partition section 101 is provided with a plurality of fulcrums, it is possible to prevent the wafer hand from unintentionally coming into contact with a bent portion of the semiconductor substrate 106.

[0051] In the first embodiment, angle 114 formed by direction 111 from center O of semiconductor substrate 106 accommodated in partition 101 toward upper fulcrum 102, which is the closest of the multiple fulcrums to the opening, and the third direction of line X-X' is 13° or more and 46° or less. Also, angle 115 formed by direction 112 from center O of semiconductor substrate 106 accommodated in partition 101 toward lower fulcrum 103, which is the farthest of the multiple fulcrums from the opening, and the third direction of line X-X' is 13° or more and 46° or less. The effects of this configuration will be described below.

[0052] 8 and 9 are two-dimensional maps showing the amount of deflection of the semiconductor substrate 106 in the bottom-side drain electrode process (step S28) when the semiconductor substrate 106 is supported in the FOUP 100 by multiple fulcrums with angles 114 and 115 of 30°. FIG. 8 is a two-dimensional map showing the semiconductor substrate 106 accommodated in the partition 101 with its top surface facing TOP (upper side in FIG. 2). FIG. 9 is a two-dimensional map showing the semiconductor substrate 106 accommodated in the partition 101 with its top surface facing BOTTOM (lower side in FIG. 2). FIG. 8 shows that the semiconductor substrate 106 has a maximum deflection amount (3.2 mm) at the center parallel to the first direction. Meanwhile, FIG. 9 shows that the semiconductor substrate 106 has a maximum deflection amount (2.0 mm) at both ends parallel to the third direction.

[0053] 10 is a diagram showing the relationship between the angles 114, 115 of the upper support point 102 and the lower support point 103 in FIG. 4 and the maximum amount of deflection of the semiconductor substrate 106 accommodated in the FOUP 100. Plot 301 shows the maximum amount of deflection when the semiconductor substrate 106 is accommodated with its top surface facing the TOP (hereinafter, also referred to as the "maximum amount of deflection toward the TOP"), as in the amount of deflection in FIG. 8. Plot 302 shows the maximum amount of deflection when the semiconductor substrate 106 is accommodated with its top surface facing the BOTTOM (hereinafter, also referred to as the "maximum amount of deflection toward the BOTTOM"), as in the amount of deflection in FIG. 9. As can be seen from plots 301 and 302, the maximum amount of deflection toward the TOP is greater than the maximum amount of deflection toward the BOTTOM.

[0054] Here, in the description of steps S27 to S29, the semiconductor substrate 106 is turned over, but such turning over reduces throughput. Therefore, below, it is assumed that the semiconductor substrate 106 is processed and transported without being turned over in steps S27 to S29. In this case, the semiconductor substrate 106 is accommodated in the partition section 101 so that the upper surface faces the TOP (upper side in FIG. 2), so a maximum deflection amount in the TOP direction is assumed.

[0055] In order for a wafer hand with a thickness of 5.0 mm in the second direction to move to the mounting position of semiconductor substrate 106 without coming into contact with semiconductor substrate 106 or partition 101, a gap of 1.0 mm is required between the wafer hand and semiconductor substrate 106. Considering that semiconductor substrates 106a and 106b are accommodated in FOUP 100 as shown in FIG. 2, the distance between the tips of adjacent fulcrums in the second direction is 10 mm, so the amount of deflection of semiconductor substrate 106 that can be tolerated is up to 4.0 mm.

[0056] In FIG. 10, angles 114 and 115 can be tolerated up to 13° from the intersection of plot 301 and the maximum TOP-direction deflection amount 4.0 of 4.0 mm. On the other hand, as angle 114 (angle 115) in FIG. 4 increases, the distance in the third direction between the upper supports 102 (between the lower supports 103) decreases. Assuming that the width of the wafer hand in the third direction is 170 mm or less, angles 114 and 115 can be tolerated up to 46°. In the first embodiment, angles 114 and 115 between the upper supports 102 and the lower supports 103 are between 13° and 46°, and therefore the maximum deflection amount of the semiconductor substrate 106 can be appropriately suppressed.

[0057] <Embodiment 2> 11 is a cross-sectional view showing the upper fulcrum 102 and the lower fulcrum 103 according to the second embodiment as viewed from the third direction. In the second embodiment, as shown in FIG. 11, the upper fulcrum 102 is higher in the second direction than the lower fulcrum 103 by, for example, 0.1 mm. With this configuration, the maximum amount of deflection in the TOP direction can suppress deflection of the semiconductor substrate 106 present on the opening side of the FOUP 100 as shown in FIG.

[0058] <Third Embodiment> 12 is a cross-sectional view showing a plurality of fulcrums according to the third embodiment, as viewed from a first direction. Although not shown, a configuration obtained by mirror-mirroring the configuration of FIG. 12 is provided on the right side of FIG. 12. In the third embodiment, as viewed from the first direction, the tip of a first set of fulcrums 401 among the plurality of fulcrums is higher than the tip of a second set of fulcrums 402 among the plurality of fulcrums, which is located more inward than the first set of fulcrums 401. With this configuration, semiconductor substrates 106 having different diameters W can be accommodated in the same FOUP 100, and bending of each of the semiconductor substrates 106 having different diameters W can be suppressed.

[0059] <Fourth Embodiment> 13 is a cross-sectional view showing the upper fulcrum 102 according to the third embodiment as viewed from a first direction. In the third embodiment, as shown in FIG. 12, the upper fulcrum 102 is in surface contact with the semiconductor substrate 106 accommodated in the partition 101. Although not shown, the lower fulcrum 103 is also in surface contact with the semiconductor substrate 106 accommodated in the partition 101. With this configuration, it is possible to reduce stress on the semiconductor substrate 106 and suppress bending of the semiconductor substrate 106 compared to a configuration in which the upper fulcrum 102 and the lower fulcrum 103 are in point contact with the semiconductor substrate 106.

[0060] <Modification> 1, 2, 4, 12, and 13, the partition 101 may be removable. With this configuration, if the partition is replaced with a partition for supporting semiconductor substrates with a diameter W of 300 mm, the same housing 104 can accommodate semiconductor substrates with a diameter W of 300 mm. This allows for a reduction in the number of FOUPs 100 to be prepared, and also reduces the capacity of the stocker that stores the FOUPs 100.

[0061] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0062] Various aspects of the present disclosure are summarized below as appendices.

[0063] (Appendix 1) preparing a semiconductor substrate made of silicon carbide and having a diameter W of 200 mm or more; a step of processing the semiconductor substrate to form a semiconductor element; a step of accommodating and transporting the semiconductor substrates in a FOUP, which is a transport carrier capable of accommodating up to 25 of the semiconductor substrates, at least either before or after the processing; A method for manufacturing a semiconductor device, comprising:

[0064] (Appendix 2) A method for manufacturing a semiconductor device according to claim 1, comprising: The processing is forming a plurality of impurity regions in the semiconductor substrate; forming a protective film on a first main surface of the semiconductor substrate; grinding a second main surface of the semiconductor substrate opposite to the first main surface after the protective film is formed; A method for manufacturing a semiconductor device, comprising at least one of the steps of:

[0065] (Appendix 3) A method for manufacturing a semiconductor device according to claim 2, comprising: The method for manufacturing a semiconductor device, wherein the protective film is a glass plate.

[0066] (Appendix 4) A method for manufacturing a semiconductor device according to claim 2, comprising: The method for manufacturing a semiconductor device, wherein the protective film is a tape.

[0067] (Appendix 5) A method for manufacturing a semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 4, The FOUP is a housing having an opening that opens in a first direction and through which the semiconductor substrate is inserted and removed; A partition portion that is connected to the inside of the housing and can partition and accommodate the outer peripheral portions of a plurality of the semiconductor substrates, which are arranged at intervals of 10 mm in a second direction orthogonal to the first direction, A plurality of fulcrums that project from the partition portion in the second direction and can support each of the plurality of semiconductor substrates accommodated in the partition portion along the second direction and includes When viewed from the second direction, the angle formed by the direction from the center of the semiconductor substrate accommodated in the partition portion to the fulcrum closest to the opening among the plurality of fulcrums, and a third direction orthogonal to the first direction and the second direction is 13° or more and 46° or less, Regarding the diameter W’ of the effective region of the semiconductor substrate, W - 10 mm < W’ < W holds, A method for manufacturing a semiconductor device, wherein the distance in the third direction between the fulcrums capable of supporting the semiconductor substrate among the plurality of fulcrums is greater than W × cos46° mm and less than W × cos13° mm.

[0068] (Appendix 6) A method for manufacturing a semiconductor device according to Appendix 5, wherein the partition portion includes a first partition portion and a second partition portion located on the side opposite to the opening with respect to the first partition portion, the fulcrum closest to the opening among the plurality of fulcrums projects from the first partition portion, the fulcrum farthest from the opening among the plurality of fulcrums projects from the second partition portion. A method for manufacturing a semiconductor device.

[0069] (Appendix 7) A method for manufacturing a semiconductor device according to Appendix 5 or Appendix 6, wherein when viewed from the second direction, the angle formed by the direction from the center of the semiconductor substrate accommodated in the partition portion to the fulcrum farthest from the opening among the plurality of fulcrums, and the third direction is 13° or more and 46° or less. A method for manufacturing a semiconductor device.

[0070] (Appendix 8) A method for manufacturing a semiconductor device according to any one of Appendices 5 to 7, wherein The method for manufacturing a semiconductor device, wherein the fulcrum closest to the opening among the plurality of fulcrums is higher in the second direction than the fulcrum farthest from the opening among the plurality of fulcrums.

[0071] (Appendix 9) A method for manufacturing a semiconductor device according to any one of Supplementary Note 5 to Supplementary Note 8, A method for manufacturing a semiconductor device, wherein, when viewed from the first direction, the tips of a first set of fulcrums among the plurality of fulcrums are higher than the tips of a second set of fulcrums among the plurality of fulcrums that are more inward than the first set of fulcrums.

[0072] (Appendix 10) A method for manufacturing a semiconductor device according to any one of Supplementary Note 5 to Supplementary Note 9, The method for manufacturing a semiconductor device, wherein the plurality of fulcrums are in surface contact with the semiconductor substrate accommodated in the partition section.

[0073] (Appendix 11) A method for manufacturing a semiconductor device according to any one of Supplementary Note 5 to Supplementary Note 10, The method for manufacturing a semiconductor device, wherein the partition is replaceable. [Explanation of symbols]

[0074] 100 FOUP, 101 partition, 102 upper support, 103 lower support, 104 housing, 106 semiconductor substrate, 111, 112 direction, 114, 115 angle, 201 p-type region, 202 n-type region, 207 protective film, 401, 402 support.

Claims

1. preparing a semiconductor substrate made of silicon carbide and having a diameter W of 200 mm or more; a step of processing the semiconductor substrate to form a semiconductor element; a step of accommodating and transporting the semiconductor substrates in a FOUP, which is a transport carrier capable of accommodating a maximum of 25 semiconductor substrates, at least either before or after the processing; A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, The processing is forming a plurality of impurity regions in the semiconductor substrate; forming a protective film on a first main surface of the semiconductor substrate; grinding a second main surface of the semiconductor substrate opposite to the first main surface after the protective film is formed; 10. A method for manufacturing a semiconductor device, comprising:

3. 3. The method for manufacturing a semiconductor device according to claim 2, The method for manufacturing a semiconductor device, wherein the protective film is a glass plate.

4. 3. The method for manufacturing a semiconductor device according to claim 2, The method for manufacturing a semiconductor device, wherein the protective film is a tape.

5. 2. The method for manufacturing a semiconductor device according to claim 1, The FOUP is a housing having an opening that opens in a first direction and through which the semiconductor substrate is inserted and removed; a partitioning section connected to the inside of the housing and capable of partitioning and accommodating 25 or less of the semiconductor substrates arranged at intervals of 10 mm in a second direction perpendicular to the first direction; a plurality of fulcrums that protrude from the partition portion in the second direction and are capable of supporting each of the plurality of semiconductor substrates accommodated in the partition portion along the second direction; Including, an angle formed by a direction from a center of the semiconductor substrate accommodated in the partition portion toward a fulcrum among the plurality of fulcrums that is closest to the opening and a third direction that is orthogonal to the first direction and the second direction is equal to or greater than 13° and equal to or less than 46°, as viewed from the second direction; With respect to the diameter W' of the effective area of ​​the semiconductor substrate, W-10 mm<W'<W holds; A method for manufacturing a semiconductor device, wherein a distance in the third direction between fulcrums that can support the semiconductor substrate among the plurality of fulcrums is greater than W×cos 46° mm and less than W×cos 13° mm.

6. 6. The method for manufacturing a semiconductor device according to claim 5, the partition portion includes a first partition portion and a second partition portion located on an opposite side of the first partition portion from the opening portion, The fulcrum closest to the opening among the plurality of fulcrums protrudes from the first partition portion, The method for manufacturing a semiconductor device, wherein the fulcrum farthest from the opening among the plurality of fulcrums protrudes from the second partition portion.

7. 7. The method for manufacturing a semiconductor device according to claim 5 or 6, a method for manufacturing a semiconductor device, wherein, when viewed from the second direction, an angle formed by a direction from a center of the semiconductor substrate accommodated in the partition toward a fulcrum among the plurality of fulcrums that is farthest from the opening and the third direction is greater than or equal to 13° and less than or equal to 46°.

8. 7. The method for manufacturing a semiconductor device according to claim 5 or 6, The method for manufacturing a semiconductor device, wherein the fulcrum closest to the opening among the plurality of fulcrums is higher in the second direction than the fulcrum farthest from the opening among the plurality of fulcrums.

9. 7. The method for manufacturing a semiconductor device according to claim 5 or 6, A method for manufacturing a semiconductor device, wherein, when viewed from the first direction, the tips of a first set of fulcrums among the plurality of fulcrums are higher than the tips of a second set of fulcrums among the plurality of fulcrums that are more inward than the first set of fulcrums.

10. 7. The method for manufacturing a semiconductor device according to claim 5 or 6, The method for manufacturing a semiconductor device, wherein the plurality of fulcrums are in surface contact with the semiconductor substrate accommodated in the partition section.

11. 7. The method for manufacturing a semiconductor device according to claim 5 or 6, The method for manufacturing a semiconductor device, wherein the partition is replaceable.

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