Semiconductor device

Abstract

To provide a semiconductor device having improved heat dissipation performance.SOLUTION: A semiconductor device according to an embodiment includes: a first terminal 11; a second terminal 12 provided with a first groove part U; a transistor 30 and GaN which is a first transistor provided in the first groove part having a first drain electrode 32, a first source electrode 33, and nitride semiconductor layers 41 and 42 electrically connected to the first terminal; and a MOS transistor 20 which is a second transistor having a second drain electrode 22 electrically connected to the second terminal and a second source electrode 23 electrically connected to a first source electrode.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Power semiconductors including gallium nitride (GaN) transistors are known. GaN transistors are capable of high-speed switching and are used in power conversion devices. These power semiconductors handle large amounts of power, so heat dissipation measures are important. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7233621 Specification [Patent Document 2] Special Publication No. 3-051300 [Patent Document 3] Japanese Patent Application Laid-Open No. 2009-094293 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor device according to the embodiment provides a semiconductor device that improves heat dissipation performance. [Means for solving the problem]

[0005] The semiconductor device of the embodiment has a first terminal and a second terminal provided with a first groove portion. Also, a first drain electrode electrically connected to the first terminal, a first source electrode, and a nitride semiconductor and a first transistor provided in the first groove portion. a second drain electrode electrically connected to the terminal; and a second source electrode electrically connected to the first terminal. A second transistor having two source electrodes is provided. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is an example of a block diagram of a semiconductor device according to a first embodiment. [Figure 2] 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing the cross section AA in FIG. [Figure 5] 2 is an example of a heat dissipation structure of the semiconductor device according to the first embodiment. [Figure 6] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing the cross section BB in FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Common parts are designated by common reference numerals throughout the drawings.

[0008] The present invention is not limited to this embodiment, and the dimensional ratios in the drawings are not necessarily the same as those shown in the drawings. It is not limited to:

[0009] (First embodiment) FIG. 1 is a block diagram showing the configuration of a semiconductor device 1 according to the first embodiment. The semiconductor device according to the first embodiment is a power semiconductor, such as an inverter or converter. This is applied to power conversion devices.

[0010] The semiconductor device 1 includes a configuration in which multiple semiconductor chips are integrated into one package. As shown in FIG. 1, the semiconductor device 1 includes a switching unit 10 and a control unit 50. The switching unit 10 performs switching to, for example, AC signal (AC: Alternative Current) The control unit 50 controls the switching operation of the switching unit 10. Control.

[0011] Next, the circuit configuration of the semiconductor device according to the embodiment will be described with reference to FIG.

[0012] 2 is a circuit diagram showing an example of a circuit configuration of the semiconductor device according to the embodiment. As described above, the semiconductor device 1 includes a first terminal 11, a second terminal 12, a GaN transistor 30, and , and a MOS transistor 20. 20 is cascode-connected between the first terminal 11 and the second terminal 12. The MOS transistor 30 is an example of a first transistor. This is an example of a transistor.

[0013] The GaN transistor 30 is a normally-on transistor that is turned on when there is no input signal to the gate, for example. ON-type HEMT (High Electron Mobility Transistor) When the potential difference between the gate and source is 0V, the drain terminal and the source The terminals are electrically connected.

[0014] The MOS transistor 20 is, for example, a MOSFET (Metal Oxide Semiconductor Device) using silicon. ide Semiconductor Field Effect Transisto The MOS transistor 20 according to the first embodiment has a normally-off characteristic. This includes P-type MOSFETs. That is, when the potential difference between the gate and source is 0V, The in end and the source end are electrically isolated.

[0015] Next, the internal structure of the semiconductor device 1 according to the first embodiment will be described with reference to FIGS. 3 and 4. Reveal.

[0016] FIG. 3 is a top view showing an example of the internal structure of the semiconductor device 1 according to the first embodiment, and FIG. This is a schematic cross-sectional view showing the cross section AA in Fig. 3. Note that the control unit 50 is omitted.

[0017] 3, a GaN transistor 30 and a MOS transistor 20 are connected to the second terminal 12. The first terminal 11, the GaN gate terminal 14, the source terminal 15, and the second terminal 12 are disposed in the same plane. The source control terminal 15 and the MOS gate terminal 16 are provided. is, for example, the reference potential of the voltages applied to the GaN gate terminal 14 and the MOS gate terminal 16. The GaN gate terminal 14 is an example of a first gate terminal, and the MOS gate terminal 16 is an example of a second gate terminal. This is an example of two gate terminals.

[0018] The lead frame, which is a metal member, is connected to the first terminal 11, the second terminal 12, and the GaN gate. The gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 are formed.

[0019] Here, the plane on which the lead frame is arranged is the XY plane, and the GaN transistors intersect with the XY plane. The direction from the bottom surface of the transistor 30 and the MOS transistor 20 to the top surface is referred to as the +Z direction or The direction is upward.

[0020] In addition, among the lead frames arranged on the XY plane, the second terminal 12 is connected to the first terminal 11. The direction in which the first terminal 11 faces the second terminal 12 is defined as the +Y direction. At this time, the GaN gate terminal 14 and the source control terminal 1 5. MOS gate terminals 16 are arranged in parallel in the Y direction.

[0021] Furthermore, in the X direction perpendicular to the Y direction, the GaN gate terminal 14, the source control terminal The direction from the MOS gate terminal 15 and the MOS gate terminal 16 toward the second terminal 12 is defined as the +X direction. The gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 are connected to the second terminal 12, for example. The ends are arranged to face each other in the X direction and are spaced apart from each other.

[0022] Here, the connection relationship of each terminal will be explained.

[0023] First, the GaN gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 are connected to each other, for example, For example, it is connected to a control unit 50 such as a gate driver circuit.

[0024] Also, the GaN gate terminal 14 is connected to the GaN transistor 30, and the source control terminal 1 5 is connected to both the GaN transistor 30 and the MOS transistor 20. The MOS gate terminal 16 is connected to a MOS transistor 20 .

[0025] Furthermore, the GaN transistor 30 and the MOS transistor 20 are electrically connected to each other. The GaN gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 are controlled by As a result, the current flows from the first terminal 11 through the GaN transistor 30 and the MOS transistor 20. Then, the current flows to the second terminal 12.

[0026] Next, the configuration of the GaN transistor will be described.

[0027] As shown in FIG. 4, the GaN transistor 30 includes a first drain electrode 32 and a first source electrode 33. The device includes an electrode 33 , a substrate 31 , and a first semiconductor layer 40 provided on the substrate 31 .

[0028] The substrate 31 is, for example, a silicon substrate. The resistance value of the substrate 31 is, for example, 1 mΩ·c m or more and 1 Ω·cm or less.

[0029] The first semiconductor layer 40 has, for example, a two-layer structure, and is made up of a first nitride semiconductor layer 41 and a second nitride semiconductor layer 42. The first nitride semiconductor layer 41 has a heterojunction structure with the nitride semiconductor layer 42. A second nitride semiconductor layer 42 is provided on the first nitride semiconductor layer 41. The second nitride semiconductor layer 42 has a larger band gap than the first nitride semiconductor layer 41. For example, the first nitride semiconductor layer 41 is an undoped GaN layer, and the second nitride semiconductor layer The layer 42 is an AlGaN layer. A two-dimensional electron gas is formed near the interface with the

[0030] The first semiconductor layer 40 has a thickness of, for example, 5 μm or less, and the substrate 31 has a thickness of about 200 μm. It is done.

[0031] A first drain electrode 32 and a first source electrode 33 are provided on the first semiconductor layer 40. The first drain electrode 32 and the first source electrode 33 are in contact with the second nitride semiconductor layer 42. On the second nitride semiconductor layer 42, the first drain electrode 32 and the first source electrode 33 are In the region between the first and second gate electrodes 34 shown in FIG. 3, a first gate electrode 34 is provided via an insulating film (not shown). do.

[0032] As shown in FIG. 3, the GaN gate terminal 14 is a first gate terminal of the GaN transistor 30. The GaN transistor 30 is driven by the gate voltage applied to the electrode 34. Control.

[0033] The first drain electrode 32 of the GaN transistor 30 is connected in multiple layers by a plurality of first wires 300. It is electrically connected to the first terminal 11.

[0034] The first source electrode 33 of the GaN transistor 30 is connected to the second electrode 302 by a plurality of second wires 301. It is electrically connected to the source electrode 23 .

[0035] A third wire is also formed between the GaN gate terminal 14 and the first gate electrode 34 of the GaN transistor 30. The electrodes are electrically connected by a wire 302.

[0036] The first source electrode 33 of the GaN transistor 30 and the source control terminal 15 are also connected to a fourth wire. They are electrically connected by ear 303.

[0037] The wires include, for example, conductive bonding wires.

[0038] As shown in FIGS. 3 and 4, the GaN transistor 30 has a groove formed on the second terminal 12. The groove portion U is provided with a bonding material 45 such as resin therebetween. The groove portion U is an example of a first groove portion. The bonding material 45 is an example of a first bonding material.

[0039] The bonding material 45 may be a conductive material such as solder.

[0040] The groove U is formed in the same shape as the GaN transistor 30 so that the entire GaN transistor 30 can be accommodated. or larger.

[0041] Here, the height h1 from the bottom surface 12e of the groove U to the upper surface 12a of the second terminal 12 is In this embodiment, the height h1 is greater than the thickness of the substrate 31 of the GaN transistor 30. It is formed small.

[0042] That is, the bottom surface of the first semiconductor layer 40 is disposed above the upper surface 12a of the second terminal 12. For example, the thickness of the second terminal 12 is 500 μm, and the thickness of the substrate 31 of the GaN transistor 30 is When the depth is 200 μm, the height h1 of the groove U is less than 200 μm.

[0043] The bonding material 45 is applied to cover the bottom and side surfaces of the substrate 31 of the GaN transistor 30. Good too.

[0044] In addition, by forming the groove U shallower than the substrate 31 of the GaN transistor 30, The bonding material 45 is a conductive material such as solder, and the first semiconductor layer 40 is spaced from the bonding material 45. This reduces the risk of an electrical short circuit between the body layer 40 and the second terminal 12.

[0045] The groove U is formed by, for example, pressing using a mold or etching by metal corrosion. It may be formed by the above.

[0046] Next, the configuration of the MOS transistor 20 will be described.

[0047] As shown in FIG. 4, the MOS transistor 20 is mounted on the second terminal 12. a second semiconductor layer 21 and a second drain electrode 22 provided on the bottom surface of the second semiconductor layer 21. The second drain electrode 22 is bonded to the second The second drain electrode is bonded to the terminal 12. The bonding material 46 is an example of a second bonding material. 22 is electrically connected to the second terminal 12. A second semiconductor On the other surface of the layer 21 in the thickness direction, a second source electrode 23 and a second gate electrode 24 are provided. The second semiconductor layer 21 is, for example, a silicon layer and includes a P-type channel. The S transistor 20 has a second semiconductor layer 21 extending in the thickness direction (the second drain electrode 22 and the second source electrode 23). This is a vertical device in which current flows in the vertical direction connecting the source electrode 23.

[0048] As shown in FIG. 3, the second source electrode 23 of the MOS transistor 20 and the source control terminal 1 The fifth wire 304 electrically connects the fifth and fifth electrodes of the MOS transistor 20. The second gate electrode 24 and the second gate terminal 16 are electrically connected by a sixth wire 305. The MOS gate terminal 16 is connected to the MOS transistor depending on the magnitude of the gate voltage applied. Controls the driving of the resistor.

[0049] The first source electrode 33 of the GaN transistor 30 is electrically connected to the second source electrode. It is electrically connected to the second terminal 12 via the MOS transistor 20. .

[0050] In this embodiment, the GaN transistor 30 is housed in the groove U of the second terminal 12. Therefore, the first drain electrode 32, the first source electrode 33, and the first gate electrode 34 are arranged in the Z direction. In this case, the thickness of the first drain electrode 32 and the thickness of the first source electrode 33 are are substantially identical.

[0051] At this time, as shown in FIG. 4, the first drain electrode 32 and the first terminal 11 are connected to each other. The wire 300 has a height h2 connecting the first source electrode 33 and the second source electrode 23. The launch height h3 of the second wire 301 may be lower than the launch height h3 of the second wire 301. The lower the launch height, which is determined by the distance between the two points and the difference in elevation, the more advantageous it is for miniaturizing parts. The launch height h2 and the launch height h3 are the first wire 300 and the second wire 301, respectively. 01 is the maximum deflection height.

[0052] The semiconductor device 1 having the above-described internal structure is sealed with a sealing resin (not shown). Has.

[0053] Next, the heat dissipation structure of the semiconductor device 1 according to this embodiment will be described with reference to FIG.

[0054] 5 is a schematic cross-sectional view showing the heat dissipation structure of the semiconductor device 1. The semiconductor device 1 is a GaN The GaN transistor 30 is mounted on the board. Since the GaN transistor 30 handles large power, A main board 70 on which the semiconductor device 1 is mounted is, for example, Intermediate materials such as TIM (Thermal Interfade Material) The heat sink 73 is bonded to the heat sink 73 via a solder paste.

[0055] The main substrate 70 is provided with heat dissipation vias 71 that penetrate from the front to the back. Heat from the device 1 is transferred to the heat sink 73 .

[0056] The cooling method of the semiconductor device is not limited to this embodiment, and may be air cooling using a fan or a heat pipe, water cooling, or the like. A cooling method may also be used.

[0057] In the case of the cooling method shown in FIG. 5, the heat dissipation path of the heat generated from the semiconductor device 1 is Heat is transferred from the bottom of the board 1 to the heat dissipation via 71, the intermediate material 72, and the heat sink 73 in that order, and finally The heat generated by the GaN transistor 30 is dissipated by the heat sink 73. The heat is dissipated through the above-mentioned heat dissipation path via the main surface 12b of the second terminal 12 exposed at the bottom surface of the semiconductor device 1. It's hot.

[0058] According to the semiconductor device 1 of this embodiment, the second terminal on which the GaN transistor 30 is disposed A groove U for accommodating the GaN transistor 30 is formed in the region 12 .

[0059] By forming the groove U, heat is mainly radiated not only from the bottom surface 12e of the groove U but also from the side surface 12c. This allows the semiconductor to be highly reliable in terms of heat dissipation performance and electrical characteristics. The side surface 12c is a peripheral portion of the bottom surface 12e of the groove portion U, and the bottom surface 12e is perpendicular to

[0060] Furthermore, the distance h3 from the bottom surface of the GaN transistor 30 to the main surface 12b is Since the distance is smaller than the thickness of the substrate, the thermal resistance can be reduced compared to a structure without the groove U. do.

[0061] In addition, as in the semiconductor device 1 according to this embodiment, a semiconductor device using a GaN transistor 30 Since the device has high-speed switching characteristics, it is greatly affected by parasitic inductance.

[0062] As in the semiconductor device 1 according to this embodiment, the GaN transistor 30 is housed in the groove portion U. As a result, the height of the first drain electrode 32 of the GaN transistor 30 in the Z direction is reduced. Therefore, the first wire 300 connecting the first drain electrode 32 and the first terminal 11 The launch height h2 is reduced. The shorter wire length between the two terminals reduces the parasitic inductance of the wire. Obtained.

[0063] As a result, by accommodating the GaN transistor in the groove U provided in the second terminal 12, heat dissipation is improved. The performance and electrical characteristics can be improved.

[0064] Furthermore, by providing the groove U, it is possible to prevent misalignment of the GaN transistor when it is mounted, The spreading of the bonding material 45 can be suppressed, thereby reducing the distance between the components. This makes it possible to miniaturize components and mount them at high density.

[0065] (Second embodiment) Next, a second embodiment will be described. As shown in FIG. 6, in the second embodiment, This embodiment differs from the first embodiment in that a groove P for accommodating an S transistor 20 is further provided. The groove portion P is an example of a second groove portion. The semiconductor device 1 of the second embodiment has the groove portion P. The configuration other than the configuration in which the MOS transistor 20 is provided in the portion P is the same as that of the semiconductor device of the first embodiment. The device has a similar configuration to that of the device 1. The groove P is a groove that accommodates the GaN transistor 30. Like U, it has a size equal to or larger than the MOS transistor 20. When the OS transistor 20 is in the ON state, a current flows in the thickness direction of the transistor. In the embodiment, for example, a trench P deeper than the height of the MOS transistor 20 is formed. The side surface 12d in P and the side surface of the MOS transistor 20 are spaced apart. d is the peripheral edge of the bottom surface 12f of the groove P and is perpendicular to the bottom surface 12f.

[0066] The MOS transistor 20 is provided on the bottom surface 12f of the trench P via the bonding material 46. In this case, the bonding material 46 is spaced apart from at least the side surface 12d without contacting it. As a result, the MOS transistor 20 and the second terminal 12 are electrically isolated from each other via the bonding material 46. This reduces the risk of short circuit.

[0067] The semiconductor device according to this embodiment includes a groove U for accommodating a GaN transistor 30 and A groove P for accommodating the MOS transistor 20 is provided on each of the second terminals 12. Therefore, the heat dissipation performance and the power dissipation performance of both the GaN transistor 30 and the MOS transistor 20 are improved. The thermal characteristics can be improved, and a semiconductor device with higher reliability than that of the first embodiment can be obtained.

[0068] By accommodating the MOS transistor 20 in the groove portion P, the thickness of the second terminal 12 is The heat dissipation path can be shortened and thermal resistance can be reduced.

[0069] In addition, the second source electrode 23 of the MOS transistor 20 and the first source electrode 24 of the GaN transistor 30 The height h3 of the second wire 301 between the source electrodes 33 is low. The wire length between the electrode 23 and the first source electrode 33 is shortened, and the parasitic impedance of the wire is reduced. The inductance can be reduced.

[0070] Although the embodiment of the present invention has been described, this embodiment is presented as an example and is not intended to be limiting. These novel embodiments are not intended to limit the scope of the invention. It is possible to carry out the invention in various ways, and various omissions and substitutions can be made within the scope of the gist of the invention. These embodiments and their modifications are within the scope and spirit of the invention. and are included in the scope of the inventions described in the claims and their equivalents. [Explanation of symbols]

[0071] 1. Semiconductor device 10 Switching section 11 1st terminal 12 2nd terminal 12a Top side 12b Main surface 12c, 12d side 12e, 12f bottom 20 MOS transistor 30 GaN transistors 14 GaN gate terminal 15 Source control terminal 16 MOS gate terminal 21 Second semiconductor layer 22 second drain electrode 23 Second source electrode 24 Second gate electrode 31 PCB 32 first drain electrode 33 First source electrode 34 First gate electrode 40 First semiconductor layer 41 First nitride semiconductor layer 42 Second nitride semiconductor layer 45, 46 Bonding material 50 control section 70 Main board 71 Heat dissipation via 72 Intermediate materials 73 Heatsink h1, h2, h3, h4 height 300~305 wire U, P groove

Claims

1. A first terminal; a second terminal having a first groove; a first drain electrode electrically connected to the first terminal; a first source electrode; and a nitride semiconductor a first transistor provided in the first trench portion, the first transistor having a conductor layer; a second drain electrode electrically connected to the second terminal; and a second source electrode electrically connected to the first terminal. a second transistor having a second source electrode connected to A semiconductor device comprising:

2. The first transistor is a GaN transistor, and is a normally-on type HEMT (Hi gh Electron Mobility Transistor), The second transistor is a normally-off MOSFET (Metal Oxide Semiconductor Field Effect Transistor). (including a field effect transistor) The semiconductor device according to claim 1 .

3. a first gate terminal of the first transistor; and a second gate terminal of the second transistor. , a source control terminal is further provided, and the source control terminal is connected to the first source electrode, the second source electrode, and the 3. The semiconductor device according to claim 2, wherein the semiconductor device is electrically connected to a source electrode.

4. The first gate terminal is electrically connected to a first gate electrode provided in the first transistor. Connected, The second gate terminal is provided in the second transistor and is electrically connected to a second gate electrode.

4. The semiconductor device according to claim 3, wherein the semiconductor device is connected to the first and second terminals.

5. The height of the first wire connecting the first terminal and the first drain electrode is 2. The method according to claim 1, wherein the height of the second wire connecting the electrode to the second source electrode is lower than the height of the second wire connecting the electrode to the second source electrode. The semiconductor device described herein.

6. The first groove is filled with a first bonding material, and a first transistor is provided in the first groove.

4. The semiconductor device according to claim 1, wherein:

7. The height from the bottom surface of the first groove to the top surface of the second terminal is 4. The semiconductor according to claim 1, wherein the thickness of the nitride semiconductor layer is smaller than the thickness of the substrate immediately below the nitride semiconductor layer. Device.

8. The second terminal further includes a second groove portion, and the second groove portion is connected to the second terminal via a second bonding material.

4. The semiconductor device according to claim 1, further comprising a transistor.

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