Semiconductor element, semiconductor device, and manufacturing method of semiconductor element

Abstract

To provide a semiconductor element with reduced risk of quality degradation due to burrs.SOLUTION: A semiconductor element includes a semiconductor layer having a circuit pattern formed on its surface, an electrode layer disposed on the back surface of the semiconductor layer, and a covering layer covering the back surface of the electrode layer and the side surfaces of the semiconductor layer and the electrode layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to semiconductor devices, semiconductor devices, and methods for manufacturing semiconductor devices. [Background technology]

[0002] Semiconductor devices manufactured using lead frames include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), FRDs (Fast Recovery Diodes), etc. In these semiconductor devices, semiconductor elements are mounted on lead frames.

[0003] In the manufacturing process of these semiconductor elements, burrs can occur on the side or back surface of the semiconductor elements during the process of dividing the wafer into individual pieces. If such burrs are left as they are, there is a risk that they will degrade the quality of the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4174978 Summary of the Invention [Problem to be solved by the invention]

[0005] Embodiments of the present invention provide semiconductor devices with reduced risk of quality degradation due to burrs. [Means for solving the problem]

[0006] The semiconductor element according to this embodiment comprises a semiconductor layer having a circuit pattern formed on its surface, an electrode layer disposed on the back surface of the semiconductor layer, and a covering layer covering the back surface of the electrode layer and the side surfaces of the semiconductor layer and the electrode layer. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 1 is a cross-sectional view of a semiconductor element according to an embodiment. [Figure 3A] 1A to 1C are diagrams illustrating a state when the semiconductor element according to the embodiment is heated. [Figure 3B] 1A and 1B are diagrams illustrating a state when the semiconductor element according to the embodiment is cooled. [Figure 4] 1 is a flowchart showing a flow of a method for manufacturing a semiconductor device according to an embodiment. [Figure 5A] 1A to 1C are diagrams illustrating a placement step in a manufacturing method of a semiconductor element. [Figure 5B] 5B is a cross-sectional view taken along line VV in region R of FIG. 5A. [Figure 6A] 1A to 1C are diagrams illustrating a coating step in a method for manufacturing a semiconductor element. [Figure 6B] 6B is a cross-sectional view taken along line VI-VI in region R of FIG. 6A. [Figure 7A] 10A to 10C are views illustrating a second dicing step in the method for manufacturing a semiconductor element. [Figure 7B] 7B is a cross-sectional view taken along line VII-VII in region R of FIG. 7A. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor element according to a first modified example. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor element according to a second modification. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0009] Furthermore, terms used in this specification that specify shapes, geometric conditions, and the degree thereof, such as "parallel" and "same," will not be bound by their strict meanings, but will be interpreted to include the range of degrees to which similar functions can be expected.

[0010] <Embodiment> (1. Semiconductor Device 1) A semiconductor device 1 according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view of the semiconductor device according to the embodiment. Figure 2 is a cross-sectional view of a semiconductor element according to the embodiment.

[0011] As shown in FIGS. 1 and 2, the semiconductor device 1 according to this embodiment includes a lead frame 10, a semiconductor element 20, and a bonding material 30.

[0012] The lead frame 10 has a frame main surface 11. The frame main surface 11 serves as an area (mounting area) where the semiconductor element 20 is mounted via a bonding material 30. The lead frame 10 may also have leads and the like (not shown).

[0013] As shown in FIG. 2, the semiconductor element 20 includes a semiconductor layer 21 having a circuit pattern formed on its surface 21a, an electrode layer 22 provided on the back surface 21c of the semiconductor layer 21, and a covering layer 23 covering the back surface 22b of the electrode layer 22 and the side surface 22a of the semiconductor layer 21 and the electrode layer 22.

[0014] In the semiconductor device 1, the electrode layer 22 of the semiconductor element 20 is bonded to the lead frame 10 via a bonding material 30. As an example, the semiconductor element 20 may have a square shape in a planar view, or may have a rectangular shape in a planar view.

[0015] In this embodiment, the semiconductor element 20 is an IGBT. The type of the semiconductor element 20 is not particularly limited, and the semiconductor element 20 may be, for example, a MOSFET, an FRD, or the like.

[0016] The semiconductor layer 21 includes a p-type semiconductor region and an n-type semiconductor region formed according to the type of semiconductor element 20. The semiconductor layer 21 is a semiconductor layer made of a semiconductor containing, for example, any one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). When silicon is used as the material of the semiconductor layer 21, for example, arsenic, phosphorus, or antimony is used as the n-type impurity, and for example, boron is used as the p-type impurity. The semiconductor layer 21 may be an epitaxial layer, or may be a semiconductor substrate obtained by dividing a wafer, or may be composed of an epitaxial layer and a semiconductor substrate.

[0017] In this embodiment, the electrode layer 22 is a collector electrode of the IGBT. In this case, the surface of the semiconductor layer 21 that is in contact with the electrode layer 22 becomes a p-type semiconductor region.

[0018] The bonding material 30 bonds the semiconductor element 20 to the lead frame 10. Various materials such as solder and conductive paste can be used as the bonding material 30. Note that, although the bonding material 30 is wider in the horizontal direction than the semiconductor element 20 in FIG. 1 , this is not limiting, and the bonding material 30 may have the same width as the semiconductor element 20.

[0019] Next, details of the electrode layer 22 will be described. As shown in Figures 1 and 2, burrs (protrusions) 24 are formed on at least one of the side surface 22a and the back surface 22b of the electrode layer 22. As an example, the burrs 24 are formed so as to surround the back surface 22b.

[0020] As shown in FIG. 2 , in this embodiment, the outer surface 24a of the burr 24 is flush with the side surface 21b of the semiconductor layer 21. In other words, the outer surface 24a and the side surface 21b are located on the same plane. More specifically, the side surface 22a of the electrode layer 22 includes the outer surface 24a of the burr 24, and the side surface 22a is flush with the side surface 21b of the semiconductor layer 21. On the other hand, the inner surface 24b of the burr 24 intersects with the outer surface 24a at an acute angle and has a shape that points more inward (toward the center of the back surface 22b) as it moves away from the tip. More specifically, the lateral length of the burr 24 increases from the tip of the burr 24 toward the back surface 22b. As will be described later, the burr 24 has this shape because it is formed during dicing.

[0021] The coating layer 23 covers the back surface 22b of the electrode layer 22, the side surface 21b of the semiconductor layer 21, and the side surface 22a of the electrode layer 22. In other words, the coating layer 23 covers the burrs 24. The coating layer 23 contains a metal material different from that of the electrode layer 22. If the material of the electrode layer 22 is a first metal material and the material of the coating layer 23 is a second metal material, the Young's modulus of the second metal material is higher than that of the first metal material. Note that in metals, the higher the Young's modulus, the lower the linear expansion coefficient tends to be, and the linear expansion coefficient of the second metal material is lower than that of the first metal material.

[0022] The first metallic material may include, for example, aluminum, silver, or both. As an example, in this embodiment, the first metallic material is primarily aluminum. The second metallic material may include, for example, nickel, copper, or both. As an example, in this embodiment, the second metallic material is primarily nickel.

[0023] The thermal expansion of the semiconductor element 20 will be described with reference to FIGS. 3A and 3B. FIG. 3A is a diagram illustrating the state of the semiconductor element 20 when it is heated. As shown in FIG. 3A, when the semiconductor element 20 is heated, an expansion force acts on the electrode layer 22 and the covering layer 23. Here, since the covering layer 23 uses a metal with a higher Young's modulus (or a lower linear expansion coefficient) than the electrode layer 22, the thermal expansion coefficient of the covering layer 23 is lower than the thermal expansion coefficient of the electrode layer 22. Therefore, the strain P1 due to expansion generated in the covering layer 23 by heating is smaller than the strain P2 due to expansion generated in the electrode layer 22. As a result, the expansion that would normally occur in the electrode layer 22 is inhibited or reduced by the covering layer 23.

[0024] 3B is a diagram illustrating the state of the semiconductor element according to the embodiment when it is cooled. As shown in FIG. 3B, when the semiconductor element 20 is cooled, a force that causes contraction acts on the electrode layer 22 and the covering layer 23. Here, since the covering layer 23 uses a metal with a higher Young's modulus (or a lower linear expansion coefficient) than the electrode layer 22, the thermal expansion coefficient of the covering layer 23 is lower than the thermal expansion coefficient of the electrode layer 22. Therefore, the strain P3 due to contraction that occurs in the covering layer 23 upon cooling is smaller than the strain P4 due to contraction that occurs in the electrode layer 22. As a result, the contraction that would normally occur in the electrode layer 22 is inhibited or reduced by the covering layer 23.

[0025] (2. Manufacturing method) 4 to 7B, a method for manufacturing a semiconductor element 20 according to the embodiment will be described. Fig. 4 is a flow diagram showing the flow of a method for manufacturing a semiconductor element 20. As shown in Fig. 4, the method for manufacturing a semiconductor element 20 includes a wafer preparation step (S100), a first dicing step (S200), a placement step (S300), a coating step (S400), and a second dicing step (S500).

[0026] In the wafer preparation step (S100), a wafer having a circuit pattern formed on its front surface and an electrode layer on its back surface is prepared. As an example, the wafer may be prepared by performing a mask manufacturing step, a wafer manufacturing step, a pre-processing step (circuit pattern formation and electrode formation) and the like in a semiconductor manufacturing process.

[0027] In the first dicing step (S200), the wafer prepared in the wafer preparation step (S100) is diced into a plurality of semiconductor elements 40. By the first dicing step (S200), burrs 24 are formed on at least one of the side surface and the back surface of the electrode layer 22 of the semiconductor element 40.

[0028] In the arrangement step (S300), a plurality of semiconductor elements 40 are arranged in a planar manner with their back surfaces facing up and with gaps between them. Specifically, as shown in FIG. 5A, a plurality of semiconductor elements 40 are arranged in a planar manner on a dicing tape 100.

[0029] Fig. 5B is a cross-sectional view taken along line VV in region R in Fig. 5A. As shown in Fig. 5B, by performing the arrangement step (S300), a plurality of semiconductor elements 40 are arranged in a planar manner with electrode layer 22 facing upward.

[0030] In the coating step (S400), the back surfaces of the semiconductor elements 40 and the gaps formed between each of the semiconductor elements 40 are covered with a coating material 50. Specifically, as shown in FIG. 6A, the entirety of the semiconductor elements 40 arranged in a planar manner on the dicing tape 100 is coated with the coating material 50. The coating material 50 is a second metal material, and includes, for example, nickel, copper, or both.

[0031] Fig. 6B is a cross-sectional view taken along line VI-VI in Fig. 6A. As shown in Fig. 6B, by performing the covering step (S400), burrs 24 formed on at least one of the side surface and the back surface of electrode layer 22 of semiconductor element 40 are also covered with covering material 50.

[0032] In the second dicing step (S500), dicing is performed by cutting the gaps between the multiple semiconductor elements 40. Specifically, as shown in Fig. 7A, the gaps between the multiple semiconductor elements 40 (shown by dotted lines in Fig. 7A) are cut from above the coating material 50.

[0033] Fig. 7B is a cross-sectional view taken along line VII-VII in Fig. 7A. As shown in Fig. 7B, by performing the second dicing step (S500), the semiconductor elements 40 covered with the coating material 50 are diced into individual pieces, thereby obtaining the semiconductor elements 20 each having the coating layer 23 on its back surface.

[0034] (3.Summary) As described above, the semiconductor element 20 according to this embodiment includes a semiconductor layer 21 having a circuit pattern formed on its surface, an electrode layer 22 disposed on the back surface of the semiconductor layer 21, and a covering layer 23 covering the back surface of the electrode layer 22 and the side surfaces of the semiconductor layer 21 and the electrode layer 22. This configuration allows burrs that may occur on the side surfaces or back surface of the semiconductor element 20 during the manufacturing process of the semiconductor element 20 to be covered by the covering layer 23, thereby reducing the risk of quality degradation due to burrs. Furthermore, as described above, the effects of thermal expansion can be reduced, which is expected to reduce warpage during die bonding of the semiconductor element 20 or when mounting the semiconductor element 20 as a semiconductor chip. While the above embodiment illustrates a semiconductor device that undergoes frame bonding, the present invention is not limited to this configuration. The technical concepts of the above embodiment may also be applied to semiconductor devices equipped with packages such as LGA (Land Grid Array).

[0035] (4. Variation 1) A first modification of the above embodiment will be described with reference to FIG. 8. In the first modification, the electrode layer 22 has a first layer 22A containing a first metal material and a second layer 22B containing a second metal material different from the first metal material. As an example, the first metal material may be a metal with a low Young's modulus and a high linear expansion coefficient, such as aluminum or silver. The second metal material may be a metal with a high Young's modulus and a low linear expansion coefficient, such as nickel or copper. In this way, the technical concept of the present disclosure can be applied to existing semiconductor elements having multiple electrode layers 22, and the same effects as those of the above embodiment can be obtained.

[0036] (5. Variation 2) Referring to FIG. 9, a second modification of the above embodiment will be described. In this modification, an insulating coating layer 26 containing an insulating material is configured instead of the coating layer 23 in the above embodiment. The insulating material includes, for example, a resin material. Specifically, a granular epoxy resin composition for semiconductor encapsulation may be used as the resin material for the insulating coating layer 26. This configuration not only achieves the same effects as the above embodiment, but also suppresses electrical conduction between the electrode layer 22 and a pad electrode (not shown) disposed on the surface 21a of the semiconductor layer 21, since the electrode layer 22 is coated with an insulating material. Furthermore, it is possible to suppress interference of ionized substances that may be generated within the semiconductor device 1 with the semiconductor layer 21 or the electrode layer 22.

[0037] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can also be implemented in combination with each other.

[0038] The present invention includes the following aspects. (Appendix 1) a semiconductor layer on which a circuit pattern is formed; an electrode layer disposed on a rear surface of the semiconductor layer; A semiconductor element comprising: a cover layer that covers a rear surface of the electrode layer and side surfaces of the semiconductor layer and the electrode layer. (Appendix 2) the electrode layer includes a first metallic material; 2. The semiconductor element of claim 1, wherein the coating layer comprises a second metal material different from the first metal material. (Appendix 3) 3. The semiconductor element of claim 2, wherein the second metal material has a higher Young's modulus than the first metal material. (Appendix 4) 2. The semiconductor element of claim 1, wherein the electrode layer has a first layer including a first metal material and a second layer including a second metal material different from the first metal material. (Appendix 5) 2. The semiconductor element of claim 1, wherein the coating layer includes a resin material. (Appendix 6) a protrusion is formed on at least one of a side surface and a back surface of the electrode layer; 6. The semiconductor element according to claim 1, wherein the covering layer covers the protrusions. (Appendix 7) A lead frame; a semiconductor element disposed on the lead frame; The semiconductor element is a semiconductor layer on which a circuit pattern is formed; an electrode layer disposed on a rear surface of the semiconductor layer; a cover layer that covers a rear surface of the electrode layer and side surfaces of the semiconductor layer and the electrode layer; (Appendix 8) dicing a wafer having a circuit pattern formed on a surface and an electrode layer on a back surface into a plurality of semiconductor elements; arranging the plurality of semiconductor elements in a planar manner with the back surfaces facing up and with gaps between them; covering the back surface and the gap with a coating material; and performing dicing by cutting the gap. (Appendix 9) a protrusion is formed on at least one of the side surface and the back surface of the electrode layer; 9. The method for manufacturing a semiconductor element according to claim 8, wherein covering the rear surface and the gap with a coating material includes covering the protrusion with the coating material. [Explanation of symbols]

[0039] 1: semiconductor device, 10: lead frame, 11: frame main surface, 20: semiconductor element, 21: semiconductor layer, 22: electrode layer, 23: coating layer, 24: burr, 24a: outer surface, 24b: inner surface, 26: insulating coating layer, 30: bonding material, 40: semiconductor element, 50: coating material, 100: dicing tape

Claims

1. a semiconductor layer on which a circuit pattern is formed; an electrode layer disposed on a rear surface of the semiconductor layer; A semiconductor element comprising: a cover layer that covers a rear surface of the electrode layer and side surfaces of the semiconductor layer and the electrode layer.

2. the electrode layer includes a first metal material; The semiconductor device of claim 1 , wherein the covering layer comprises a second metallic material different from the first metallic material.

3. The semiconductor device according to claim 2 , wherein the second metallic material has a higher Young's modulus than the first metallic material.

4. The semiconductor device according to claim 1 , wherein the electrode layer has a first layer including a first metallic material and a second layer including a second metallic material different from the first metallic material.

5. The semiconductor element according to claim 1 , wherein the covering layer includes a resin material.

6. a protrusion is formed on at least one of a side surface and a back surface of the electrode layer; 6. The semiconductor element according to claim 1, wherein the covering layer covers the protrusions.

7. A lead frame; a semiconductor element disposed on the lead frame; The semiconductor element is a semiconductor layer on which a circuit pattern is formed; an electrode layer disposed on a rear surface of the semiconductor layer; a cover layer that covers a rear surface of the electrode layer and side surfaces of the semiconductor layer and the electrode layer;

8. dicing a wafer having a circuit pattern formed on a surface and an electrode layer on a back surface into a plurality of semiconductor elements; arranging the plurality of semiconductor elements in a planar manner with the back surfaces facing up and with gaps between them; covering the back surface and the gap with a coating material; and performing dicing by cutting the gap.

9. a protrusion is formed on at least one of a side surface and a back surface of the electrode layer; The method for manufacturing a semiconductor element according to claim 8 , wherein covering the rear surface and the gap with a coating material includes covering the protrusion with the coating material.

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