Signal collection circuit and wearable device

Abstract

To provide a signal collection circuit that reduce influence of parasitic capacitance on signal collection and a wearable device.SOLUTION: A signal collection circuit 200 includes a difference amplifier 230, a first electrode 210, a second electrode 220, a first negative capacitance circuit C10, and a second negative capacitance circuit C20. The first electrode is connected to a first input end of a difference amplifier via a first lead wire L1, and the second electrode is connected to a second input end of the difference amplifier via a second lead wire L2. The first negative capacitance circuit is electrically connected to the first lead wire and a ground line, the second negative capacitance circuit is electrically connected to the second lead wire and the ground line, and both circuits have a negative capacitance effect. The signal collection circuit may further include a third negative capacitance circuit C30. The third negative capacitance circuit is electrically connected between the first lead wire and the second lead wire and being connected in parallel to inter-lead parasitic capacitance C3.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This application relates to the field of circuit design, and in particular to signal acquisition circuits and wearable devices. [Background technology]

[0002] Conventional bioelectric signal acquisition circuits (such as electrocardiograms and myoelectric signals) convert common-mode power-frequency signals into differential-mode power-frequency noise before inputting it to an amplifier, resulting in a reduced signal-to-noise ratio and often leading to circuit saturation and failure. This necessitates a large input impedance to reduce power-frequency interference. However, in practical circuits, parasitic capacitance often reduces the circuit's input impedance and further exacerbates power-frequency interference. In other words, the presence of parasitic capacitance limits the effectiveness of bioelectric signal acquisition.

[0003] Therefore, it is desirable to provide a signal acquisition circuit and a wearable device that can reduce the effect of parasitic capacitance on signal acquisition. Summary of the Invention [Means for solving the problem]

[0004] A signal acquisition circuit according to an embodiment of the present application includes a differential amplifier, a first electrode and a second electrode, a first negative capacitance circuit and a second negative capacitance circuit, wherein the first electrode is connected to a first input terminal of the differential amplifier via a first lead wire, the second electrode is connected to a second input terminal of the differential amplifier via a second lead wire, the first negative capacitance circuit is electrically connected to the first lead wire and a ground wire, and the second negative capacitance circuit is electrically connected to the second lead wire and a ground wire, and both the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect.

[0005] In some embodiments, a relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit and the parasitic capacitance value to ground of the first lead wire is less than 50%, and a relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit and the parasitic capacitance value to ground of the second lead wire is less than 50%.

[0006] In some embodiments, a first equivalent input capacitance is present at a first input terminal of the differential amplifier, a second equivalent input capacitance is present at a second input terminal of the differential amplifier, a relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit and the sum of the parasitic capacitance value to ground of the first lead wire and the first equivalent input capacitance is less than 50%, and a relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit and the sum of the parasitic capacitance value to ground of the second lead wire and the second equivalent input capacitance is less than 50%.

[0007] In some embodiments, the circuit further includes a third negative capacitance circuit, the third negative capacitance circuit being electrically connected to the first lead wire and the second lead wire and having a negative capacitance effect.

[0008] In some embodiments, a relative error between the absolute value of the equivalent capacitance value of the third negative capacitance circuit and the parasitic capacitance value between the first lead wire and the second lead wire is less than 50%.

[0009] In some embodiments, the first negative capacitance circuit includes a first operational amplifier, a first resistor, a second resistor, and a first capacitor; the second negative capacitance circuit includes a second operational amplifier, a third resistor, a fourth resistor, and a second capacitor; the first operational amplifier has an inverting input terminal grounded via the first resistor and connected to the output terminal of the first operational amplifier via the second resistor, and a non-inverting input terminal connected to the output terminal of the first operational amplifier via the first capacitor; the second operational amplifier has an inverting input terminal grounded via the third resistor and connected to the output terminal of the second operational amplifier via the fourth resistor, and a non-inverting input terminal connected to the output terminal of the second operational amplifier via the second capacitor.

[0010] In some embodiments, the non-inverting input of the first operational amplifier is connected to the first lead and the non-inverting input of the second operational amplifier is connected to the second lead.

[0011] In some embodiments, the circuit further includes a feedback control circuit that adjusts equivalent capacitance values ​​of the first negative capacitance circuit and the second negative capacitance circuit.

[0012] In some embodiments, the input impedance of the differential amplifier is greater than 100 megaohms.

[0013] In some embodiments, the differential amplifier is double-ended powered with positive and negative voltages.

[0014] In some embodiments, the differential amplifier is powered by a single voltage.

[0015] A signal acquisition circuit according to an embodiment of the present application includes a differential amplifier, a first electrode, a second electrode, and a fourth negative capacitance circuit, wherein the first electrode is connected to a first input terminal of the fourth negative capacitance circuit via the first lead wire, the second electrode is connected to a second input terminal of the fourth negative capacitance circuit via a second lead wire, a first output terminal of the fourth negative capacitance circuit is connected to a first input terminal of the differential amplifier, and a second output terminal of the fourth negative capacitance circuit is connected to a second input terminal of the differential amplifier, and the fourth negative capacitance circuit has a negative capacitance effect.

[0016] In some embodiments, the fourth negative capacitance circuit includes a double-ended differential amplifier, a first negative feedback capacitor, and a second negative feedback capacitor, wherein the first negative feedback capacitor is connected between a first input terminal of the double-ended differential amplifier and a first output terminal of the double-ended differential amplifier, and the second negative feedback capacitor is connected between a second input terminal of the double-ended differential amplifier and a second output terminal of the double-ended differential amplifier.

[0017] In some embodiments, the double-ended differential amplifier is a fixed gain amplifier.

[0018] In some embodiments, the fourth negative capacitance circuit includes a first unit and a second unit, the first unit includes a first amplifier and a third negative feedback capacitor, the second unit includes a second amplifier and a fourth negative feedback capacitor, the third negative feedback capacitor is connected between an input end of the first amplifier and an output end of the first amplifier, and the fourth negative feedback capacitor is connected between an input end of the second amplifier and an output end of the second amplifier.

[0019] In some embodiments, a relative error between the absolute value of the equivalent capacitance value of the first unit of the fourth negative capacitance circuit and the parasitic capacitance value to ground of the first lead wire is less than 50%, and a relative error between the absolute value of the equivalent capacitance value of the second unit of the fourth negative capacitance circuit and the parasitic capacitance value to ground of the second lead wire is less than 50%.

[0020] In some embodiments, the first amplifier and the second amplifier are equal and fixed gain amplifiers.

[0021] In some embodiments, the circuit further includes a feedback control circuit that adjusts an equivalent capacitance value of the fourth negative capacitance circuit.

[0022] In some embodiments, the input impedance of the differential amplifier is greater than 100 megaohms.

[0023] In some embodiments, the differential amplifier is double-ended powered with positive and negative voltages.

[0024] In some embodiments, the differential amplifier is powered by a single voltage.

[0025] A wearable device according to an embodiment of the present application includes the signal collection circuit.

[0026] In the signal acquisition circuit according to the embodiment of the present application, a first negative capacitance circuit and a second negative capacitance circuit are connected to the lead wire of the acquisition end, and the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect, which cancels out the parasitic capacitance to ground of the lead wire, reduces the effect of the parasitic capacitance on signal acquisition, and further improves the performance of the signal acquisition circuit and the effect of signal acquisition.

[0027] The present application will be further illustrated by exemplary embodiments, which are illustrated in detail in the drawings, and are not limiting, and in which like reference numerals represent like structures. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a schematic diagram of a power frequency interference principle according to some embodiments of the present application; [Figure 2A] FIG. 1 is a schematic diagram of a power supply scheme for a differential amplifier according to some embodiments of the present application. [Figure 2B] FIG. 1 is a schematic diagram of a power supply scheme for a differential amplifier according to some embodiments of the present application. [Figure 3] FIG. 1 is a schematic diagram of a signal acquisition circuit according to some embodiments of the present application. [Figure 4] FIG. 1 is a schematic diagram of a negative capacitance circuit in a signal acquisition circuit according to some embodiments of the present application. [Figure 5] FIG. 1 is a schematic diagram of a signal acquisition circuit according to some embodiments of the present application. [Figure 6A] FIG. 10 is a schematic diagram of a fourth negative capacitance circuit in a signal acquisition circuit according to some embodiments of the present application. [Figure 6B] FIG. 10 is another schematic diagram of a fourth negative capacitance circuit in a signal acquisition circuit according to some embodiments of the present application. [Figure 7A] FIG. 1 is a schematic diagram of a pre-effects circuit for removing power frequency interference according to some embodiments of the present application. [Figure 7B] FIG. 1 is a schematic diagram of an effect circuit after power frequency interference cancellation according to some embodiments of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0029] In order to more clearly describe the technical means of the embodiments of the present application, the drawings necessary for describing the embodiments will be briefly described below. Obviously, the drawings described below are only examples or parts of the embodiments of the present application, and those skilled in the art can apply the present application to other similar scenarios based on these drawings without any creative effort. Unless otherwise clear from the language environment or otherwise described, the same symbols in the drawings indicate the same structures or operations.

[0030] It should be understood that the terms "system," "device," "unit," and / or "module" used herein are meant to distinguish between various levels of assemblies, elements, components, parts, or structures. However, other terms may be used in place of the above terms if they achieve the same purpose.

[0031] As used in this application and the claims, unless the context clearly dictates otherwise, terms such as "a," "one," "one kind," and / or "the" do not specifically refer to the singular but may also include the plural. In general, the terms "comprise" and "containing" are intended to indicate only the inclusion of explicitly identified steps and elements, and these steps and elements are not an exclusive listing, and a method or apparatus may include other steps or elements.

[0032] The signal collection circuit described in the embodiments of the present application can be applied to various signal monitoring devices that need to collect signals, particularly physiological signal monitoring devices, such as smart wearable devices. In some embodiments, the wearable devices (e.g., clothing, wristbands, straps, etc.) can be attached to various parts of the human body (e.g., lower legs, upper legs, waist, back, chest, shoulders, neck, etc.) to collect physiological signals from various parts of the body when the user is in different states and subsequently process the collected signals. In some embodiments, the physiological signals can be detectable signals that can represent the user's physical state, and can include various signals such as respiratory signals, electrocardiograms (ECG), electromyography (EMG), electroencephalography (EEG), blood pressure signals, temperature signals, etc. In some embodiments, wearable devices that collect physiological signals can be applied to emerging cross-industries such as medicine, gaming entertainment, and health education. For example, when combined with technologies such as virtual reality (VR) and EMG collection, it can promote the development of immersive entertainment and education, and when combined with technologies such as mechanical and electronic devices and exoskeleton devices, it can achieve the purpose of reducing medical costs and promoting the development of medical health.

[0033] FIG. 1 is a schematic diagram of a power frequency interference principle according to some embodiments of the present application.

[0034] In some embodiments, the signal acquisition circuit 100 shown in FIG. 1 includes one or more sensor units (e.g., a first electrode 110 and a second electrode 120) that contact the user's body, a differential amplifier 130, and one or more leads (e.g., a first lead L1, a second lead L2) that connect the sensor units and the differential amplifier 130.

[0035] In some embodiments, the sensor unit may acquire one or more physiological signals of the user. The sensor unit may include, but is not limited to, one or more of an electromyographic sensor, a posture sensor, an electrocardiographic sensor, a respiration sensor, a temperature sensor, a humidity sensor, an inertial sensor, a blood oxygen saturation sensor, a Hall sensor, a galvanic skin response sensor, a rotation sensor, etc. In some embodiments, the physiological signals may include one or more of an electromyographic signal, a posture signal, an electrocardiographic signal, a respiration rate, a temperature signal, a humidity signal, etc. The sensor unit may be positioned at different positions on the wearable device depending on the type of motion signal to be acquired.

[0036] In some embodiments, different signal acquisition circuits may be positioned at different locations on the user's body to acquire the same or different types of physiological signals from the user. For example, signal acquisition circuits positioned on different sides of the user's upper thigh may both acquire electromyographic signals from the upper thigh. For example, a signal acquisition circuit positioned on the user's forearm may acquire electromyographic signals from the forearm, and a signal acquisition circuit positioned over the user's heart may acquire electrocardiographic signals from the user.

[0037] In some embodiments, the sensor unit may include one or more electrode elements that contact the user's body and collect electromyographic signals from the user's body surface through the electrode elements. The electrode elements may be dry or wet electrodes. Dry electrodes are metallic structural electrodes made of metal pieces or woven metal wires. Wet electrodes can be formed by applying a conductive colloid between the human skin and the electrode elements to increase contact strength with the human body. Because the human body is not an absolute conductor, there is a contact impedance between both dry and wet electrodes and the human body. The impedance varies under different physiological conditions, so different electrode types can be selected for each case.

[0038] In some embodiments, the electrode element includes a first electrode 110 and a second electrode 120. The first electrode 110 is connected to a first input terminal A of a differential amplifier 130 via a first lead wire L1, and the second electrode 120 is connected to a second input terminal B of the differential amplifier 130 via a second lead wire L2, and the first lead wire L1 and the second lead wire L2 transmit physiological signals collected by the electrode element to the differential amplifier for appropriate processing (e.g., noise reduction, amplification, etc.).

[0039] In some embodiments, the differential amplifier 130 may perform differential amplification processing on the physiological signal acquired by the electrode element. In some embodiments, the physiological signal processed by the differential amplifier 130, i.e., Vout output from the output terminal, may be transmitted to other elements in the wearable device for further processing. For example, the processed physiological signal may be converted from an analog signal to a digital signal by an analog-to-digital converter ADC, and further processed by a processor, for example, for signal analysis.

[0040] In some embodiments, the differential amplifier 130 may include two power supply methods: a single-ended power supply and a double-ended power supply. As shown in Figure 2A, the differential amplifier 130 has a first power supply terminal (111) connected to a positive power supply +Vcc, a second power supply terminal (112) connected to a negative power supply -Vcc, and a bias voltage receiving terminal (113) grounded. As shown in Figure 2B, the differential amplifier 130 has a first power supply terminal (114) connected to a positive power supply +Vcc, a second power supply terminal (116) grounded, and a bias voltage receiving terminal (117) receiving a bias voltage having a voltage value of +Vcc / 2.

[0041] In some embodiments, if the contact impedances of the first electrode 110 and the second electrode 120 and the user's body do not match, i.e., if the impedances of the two input ends of the differential amplifier 130 do not match (the impedances are unbalanced), the common-mode power frequency signal on the surface of the human body will be converted into differential-mode power frequency noise and input to the amplifier, further reducing the signal-to-noise ratio and eventually causing the circuit to saturate and fail.

[0042] The human body is exposed to various 50 / 60 Hz power lines (50 Hz power lines in China and 60 Hz power lines outside China). These power lines emit electromagnetic waves that couple with the human body, causing potential changes in the body. The amplitude of these changes is generally in the millivolt range, ranging from a few millivolts to hundreds of millivolts, and is related to the position of the human body and the power line. For ease of understanding, if we equate environmental interference with a capacitor-coupled model C0 and represent the impedance between the human body and the ground as Z0, the power line interference model can be equivalent to the left half of Figure 1. That is, the power line is connected to the equivalent capacitor C0, the human body, and the ground impedance in series. As the human body moves, the distance from the power line changes, and the value of the equivalent capacitor C0 also changes accordingly.

[0043] In some embodiments, the power frequency current coupled to the body is Icm, and the common mode power frequency potential on the body surface, Vcm, can be expressed as:

[0044] Vcm=Icm*Z0(1) The impedance to ground of the first input terminal A is Zin1, and the impedance to ground of the second input terminal B is Zin2. In general,

number

[0045] Zcm=Zin / 2(2) In some embodiments, if the contact impedances of the first electrode 110 and the second electrode 120 and the user's body are not matched, the potentials at the first input A and the second input B of the differential amplifier 130 will be unequal, causing the differential amplifier 130 to further amplify the potential difference between the points A and B, thereby causing the circuit to saturate or fail. When a common-mode power frequency potential Vcm is present on the human body, the potential difference V between the first input A and the second input B of the differential amplifier 130 will AB can be expressed by the following equation (3).

[0046]

number

[0047] In the formula, Z1 is the contact impedance value of the first electrode 110, and Z2 is the contact impedance value of the second electrode 120. As can be seen from the above formula, the strength of the differential mode power frequency signal between the first input terminal A and the second input terminal B of the differential amplifier 130 is inversely proportional to the common mode input impedance of the differential amplifier 130, and the lower the common mode input impedance, the greater the power frequency interference.

[0048] In some embodiments, to reduce the impact of power frequency interference on signal collection, the potential difference between the two inputs of the differential amplifier can be reduced by reducing the contact impedance of the electrode element, or the common-mode power frequency potential can be reduced by adding a ground electrode to the human body, and the potential difference between the two inputs of the differential amplifier can be further reduced, for example, by contacting one end of the electrode to the human body and connecting the other end to the circuit GND. However, since the electrode element always has contact impedance, the common-mode power frequency potential cannot be completely eliminated.

[0049] In some embodiments, a method for increasing the (common-mode) input impedance of the differential amplifier may be used to reduce the effect of power frequency interference on signal collection. For example, a differential amplifier with high (common-mode) input impedance (e.g., first input terminal A and second input terminal B both have high impedance to ground) may be used as the input front end of the signal collection circuit. In some embodiments, the (common-mode) input impedance of the differential amplifier 130 is greater than 100 MΩ, and preferably, the (common-mode) input impedance of the differential amplifier 130 is greater than 1 GΩ.

[0050] However, when the signal acquisition circuit 100 is applied to a wearable device, the presence of parasitic capacitance in the actual circuit reduces the input impedance of the differential amplifier. In practical applications, parasitic capacitance exists not only between the lead wires but also between the lead wires and ground. In particular, in physiological signal acquisition scenarios, the impact of these parasitic capacitances is particularly significant because some physiological signals (e.g., electromyography signals, electrocardiogram signals, etc.) are weak. In some embodiments, these parasitic capacitances are connected in parallel to various equivalent impedances in the signal acquisition circuit, significantly reducing the input impedance of the entire circuit and further exacerbating power frequency interference, which cannot be resolved by a differential amplifier using a higher input impedance. As can be seen, the presence of these parasitic capacitances limits the performance and acquisition effect of the signal acquisition circuit.

[0051] FIG. 3 is a schematic diagram of a signal acquisition circuit 200 according to some embodiments of the present application.

[0052] In some embodiments, the signal acquisition circuit 200 shown in FIG. 3 may include a first electrode 210, a second electrode 220, a differential amplifier 230, a first lead L1, a second lead L2, a first negative capacitance circuit C10, and a second negative capacitance circuit C20.

[0053] In some embodiments, the first electrode 210 is connected to a first input terminal A of the differential amplifier 230 via a first lead wire L1, and the second electrode 220 is connected to a second input terminal B of the differential amplifier 230 via a second lead wire L2. For related descriptions of the first electrode 210, the second electrode 220, the differential amplifier 230, the first lead wire L1, and the second lead wire L2, please refer to the related descriptions of FIG. 1, and descriptions thereof will be omitted here.

[0054] In some embodiments, a first ground parasitic capacitance C1 exists between the first lead wire L1 and the ground wire, a second ground parasitic capacitance C2 exists between the second lead wire L2 and the ground wire, and an inter-lead parasitic capacitance C3 exists between the first lead wire L1 and the second lead wire L2. As shown in Fig. 3, the first ground parasitic capacitance C1 is equivalently connected between the first lead wire L1 and the ground wire and can be considered to be connected in parallel with the ground impedance Zin1 of the first input terminal A of the differential amplifier 230, the second ground parasitic capacitance C2 is equivalently connected between the second lead wire L2 and the ground wire and can be considered to be connected in parallel with the ground impedance Zin2 of the second input terminal B of the differential amplifier 230, and the inter-lead parasitic capacitance C3 can be considered to be equivalently connected between the first lead wire L1 and the second lead wire L2. The first ground parasitic capacitance C1 and the second ground parasitic capacitance C2 are connected in parallel to the ground impedance Zin1 and the ground impedance Zin2 of the differential amplifier, respectively, which significantly reduces the input impedance of the entire circuit and worsens the impact of power frequency interference on signal collection.

[0055] In some embodiments, changes in parasitic capacitance cannot be measured in real time, but because they are related to circuit design, they can be measured after the circuit is designed. That is, the first ground parasitic capacitance C1, the second ground parasitic capacitance C2, and the lead-to-lead parasitic capacitance C3 can be measured after the circuit design of the signal acquisition circuit. In actual application, the parasitic capacitance between the human body cannot be accurately measured, but it can be measured when the human body is not moving, and a baseline value of the parasitic capacitance can be determined. When the human body moves, the parasitic capacitance between the human body changes, and a tentative variation range can be determined based on the baseline value of the parasitic capacitance.

[0056] In some embodiments, in order to reduce the influence of parasitic capacitance and increase the input impedance of the differential amplifier, a first negative capacitance circuit C10 and a second negative capacitance circuit C20 are provided in the signal acquisition circuit 200. The first negative capacitance circuit C10 is electrically connected to the first lead wire L1 and a ground line, and the second negative capacitance circuit C20 is electrically connected to the second lead wire L2 and a ground line, and the first negative capacitance circuit C10 and the second negative capacitance circuit C20 have negative capacitance effects, which cancel out the parasitic capacitance of the lead wires to ground, thereby reducing the influence of the parasitic capacitance on the circuit input impedance and signal acquisition, and further improving the performance and signal acquisition effect of the signal acquisition circuit. The negative capacitance effect referred to here can be understood as the tendency of change in the amount of charge in the first negative capacitance circuit C10 and the second negative capacitance circuit C20 being opposite to the tendency of change in the voltage applied thereto; that is, as the voltage decreases, the amount of charge in the first negative capacitance circuit C10 and the second negative capacitance circuit C20 increases accordingly.

[0057] In some embodiments, the manner in which the first negative capacitance circuit C10 and / or the second negative capacitance circuit C20 are electrically connected to a ground line may include connecting the first negative capacitance circuit C10 and / or the second negative capacitance circuit C20 to a common ground terminal on one or more printed circuit boards (PCBs).

[0058] In some embodiments, the first negative capacitance circuit C10 can be considered to be connected in parallel with the first ground parasitic capacitance C1, and the second negative capacitance circuit C20 can be considered to be connected in parallel with the second ground parasitic capacitance C2. The first negative capacitance circuit C10 and the second negative capacitance circuit C20 respectively cancel out the parasitic capacitances at the two input terminals of the differential amplifier, thereby reducing the capacitance values ​​at the input terminals of the differential amplifier and improving the input impedance. In some embodiments, the equivalent capacitance values ​​of the first negative capacitance circuit C10 and the second negative capacitance circuit C20 can be expressed as follows: C10=-C1(4) C20=-C2(5) The total capacitance to the ground of the first lead wire L1 and the total capacitance to the ground of the second lead wire L2 are both 0. In this case, the parasitic capacitance to the ground at the input end of the differential amplifier is completely canceled out, significantly improving the input impedance of the entire signal acquisition circuit and further improving resistance to power frequency interference.

[0059] In some embodiments, in an actual operating environment, the parasitic capacitance may change slightly with the movement of the leads, so the absolute value of the negative capacitance circuit is not exactly equal to the parasitic capacitance. In some embodiments, to effectively cancel the parasitic capacitance to ground at the input of the differential amplifier, the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the parasitic capacitance to ground value C1 of the first lead L1 is less than 50%, and the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit C20 and the parasitic capacitance to ground value C2 of the second lead L2 is less than 50%. In some embodiments, in order to ensure that the input end of the differential amplifier has a larger input impedance, the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the ground parasitic capacitance value C1 of the first lead wire L1 is less than 30%, and the relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit C20 and the ground parasitic capacitance value C2 of the second lead wire L2 is less than 30%.

[0060] In actual application, it should be understood that the smaller the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the ground parasitic capacitance C1 of the first lead wire L1, the more the ground parasitic capacitance C1 of the first lead wire L1 is canceled by the first negative capacitance circuit C10, the greater the input impedance of the entire signal acquisition circuit, and the better the final signal acquisition effect. The same applies to the second negative capacitance circuit C20, and a description thereof will be omitted here.

[0061] In some embodiments, the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the ground parasitic capacitance value of the first lead wire L1 is the ratio of the difference between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the ground parasitic capacitance value of the first lead wire L1 to the ground parasitic capacitance value of the first lead wire L1.

[0062] In some embodiments, the equivalent input impedance Zin1 of the first input A of the differential amplifier 230 may be equivalent to a parallel connection of capacitors Rin1 and Cin1, and the equivalent input impedance Zin2 of the second input B of the differential amplifier 230 may be equivalent to a parallel connection of capacitors Rin2 and Cin2. In some embodiments, to further improve the input impedance performance of the signal acquisition circuit 200, the first negative capacitance circuit C10 and the second negative capacitance circuit C20 can be adjusted to further cancel the effect of the equivalent input capacitance of the differential amplifier 230. In some embodiments, the equivalent capacitance value of the first negative capacitance circuit C10 and the equivalent capacitance value of the second negative capacitance circuit C20 can be adjusted as follows:

[0063] C10=-(C1+Cin1)(6)

[0064] C20=-(C2+Cin2)(7)

[0065] In some embodiments, in order to effectively cancel out the equivalent input capacitance of the input terminal of the differential amplifier, the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the sum of the ground parasitic capacitance value C1 of the first lead wire L1 and the equivalent input capacitance value Cin1 of the first input terminal A of the differential amplifier 230 is less than 50%, and the relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit C20 and the sum of the ground parasitic capacitance value C2 of the second lead wire L2 and the equivalent input capacitance value Cin2 of the second input terminal B of the differential amplifier 230 is less than 50%. In some embodiments, in order to ensure that the input terminal of the differential amplifier has a larger input impedance, the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the sum of the ground parasitic capacitance value C1 of the first lead wire L1 and the equivalent input capacitance value Cin1 of the first input terminal A of the differential amplifier 230 is less than 30%, and the relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit C20 and the sum of the ground parasitic capacitance value C2 of the second lead wire L2 and the equivalent input capacitance value Cin2 of the second input terminal B of the differential amplifier 230 is less than 30%.

[0066] In actual application, it should be understood that the smaller the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the sum of the parasitic capacitance to ground of the first lead wire L1 and the first equivalent input capacitance Cin1 of the differential amplifier, the greater the parasitic capacitance to ground of the first lead wire L1 and the first equivalent input capacitance Cin1 of the differential amplifier that are canceled out by the first negative capacitance circuit C10, which increases the input impedance of the entire signal acquisition circuit and improves the final signal acquisition effect. The same applies to the second negative capacitance circuit C20, and its description will be omitted here.

[0067] As a result, the first negative capacitance circuit C10 and the second negative capacitance circuit C20 cancel out the ground parasitic capacitance of the first lead wire L1 and the first equivalent input capacitance Cin1 of the differential amplifier, and the ground parasitic capacitance of the second lead wire L2 and the second equivalent input capacitance Cin2 of the differential amplifier, respectively, thereby further increasing the input impedance of the entire signal acquisition circuit.

[0068] In some embodiments, the signal acquisition circuit 200 may further include a third negative capacitance circuit C30. The third negative capacitance circuit C30 is electrically connected between the first lead wire L1 and the second lead wire L2 and is connected in parallel to the lead-to-lead parasitic capacitance C3. In some embodiments, the signal acquisition circuit 200 may not include the third negative capacitance circuit C30 because the effect of the lead-to-lead parasitic capacitance C3 on circuit performance is low. In some embodiments, if the requirements for the signal acquisition circuit 200 are high, the signal acquisition circuit 200 may include the third negative capacitance circuit C30. In some embodiments, the value of the third negative capacitance circuit C30 can be expressed as follows:

[0069] C30=-C3(8)

[0070] In some embodiments, the relative error between the absolute value of the equivalent capacitance value of the third negative capacitance circuit C30 and the value of the lead-to-lead parasitic capacitance C3 is less than 50%. In some embodiments, the relative error between the absolute value of the equivalent capacitance value of the third negative capacitance circuit C30 and the value of the lead-to-lead parasitic capacitance C3 is less than 30%. It should be understood that in actual application, the smaller the relative error between the absolute value of the equivalent capacitance value of the third negative capacitance circuit C30 and the value of the lead-to-lead parasitic capacitance C3, the more the lead-to-lead parasitic capacitance C3 is canceled by the third negative capacitance circuit C30, the greater the input impedance of the entire signal acquisition circuit, and the better the final signal acquisition effect.

[0071] In some embodiments, the signal acquisition circuit may further include a feedback control circuit that adjusts the equivalent capacitance values ​​of the first negative capacitance circuit C10 and the second negative capacitance circuit C20, for example, by changing the resistance values ​​of the negative capacitance circuits.

[0072] For specific structures of the first negative capacitance circuit C10, the second negative capacitance circuit C20, and the third negative capacitance circuit C30, reference can be made to the relevant contents of FIGS. 4A and 4B.

[0073] FIG. 4 is a schematic diagram of a negative capacitance circuit in a signal acquisition circuit 200 according to some embodiments of the present application.

[0074] 4, the first negative capacitance circuit C10 may include a first operational amplifier 410, a first resistor R1, a second resistor R2, and a first capacitor C401. In some embodiments, the first operational amplifier 410 has an inverting input terminal grounded via the first resistor R1 and connected to the output terminal of the first operational amplifier 410 via the second resistor R2, and a non-inverting input terminal connected to the output terminal of the first operational amplifier 410 via the first capacitor C401. In some embodiments, point m in FIG. 4 and point a in FIG. 3 are equipotential points, and point a and point m may be electrically connected using a lead wire.

[0075] In some embodiments, the second negative capacitance circuit C20 may have the structure shown in FIG. 4. In this case, point m in FIG. 4 and point b in FIG. 3 are equipotential points, and point m and point b may be electrically connected using a lead wire.

[0076] The negative capacitance circuit shown in FIG. 4 is an equivalent circuit having a negative capacitance effect. Specifically, for the negative capacitance circuit shown in FIG. 4, the equivalent impedance of the negative capacitance circuit is the impedance between point m and GND. The impedance between point m and GND is defined as z a Then, z a The impedance can be expressed by the following equation (9).

[0077]

number

[0078] That is, the impedance between point m and GND may be equivalent to one negative capacitance, or may be generated by one negative capacitance. The negative capacitance between point m and GND is defined as C a Then, C aThe equivalent capacitance value can be expressed by the following equation (10).

[0079]

number

[0080] C a It should be understood that is the equivalent capacitance of the negative capacitance circuit shown in FIG.

[0081] In some embodiments, resistors R1 and R2 may be adjustable resistors (e.g., sliding resistors, resistor boxes, and potentiometers) or fixed resistors. In some embodiments, resistors R1 and R2 may have equal or unequal resistance. In some embodiments, adjusting the resistance of resistors R1 and R2 may reduce the equivalent capacitance C a It should be understood that the size of may be adjusted.

[0082] In some embodiments, the first capacitor C401 may be a paper capacitor, a metallized paper capacitor, a ceramic capacitor, a film capacitor, an oil paper capacitor, an aluminum electrolytic capacitor, a semi-variable capacitor, a variable capacitor, etc. In some embodiments, the capacitance value of the first capacitor C401 can be adjusted to obtain an equivalent capacitance C a You can also adjust the size of.

[0083] In some embodiments, the first operational amplifier 410 may be powered by two power supplies, for example, a voltage +Vcc (411) as a positive power supply and a voltage −Vcc (412) as a negative power supply, and outputs the amplified signal generated by the first operational amplifier 410 at 413. In some embodiments, the first operational amplifier 410 may be powered by a single power supply, which will not be described here.

[0084] In some embodiments, the first negative capacitance circuit C10 and the second negative capacitance circuit C20 may have other structures than those shown in FIG.

[0085] In some embodiments, the signal acquisition circuit 200 may further include a third negative capacitance circuit C30, which is electrically connected to the first lead wire L1 and the second lead wire L2 and has a negative capacitance effect.

[0086] In some embodiments, the third negative capacitance circuit C30 may have the structure shown in FIG. 4. In this case, point m in FIG. 4 and point c in FIG. 3 are equipotential points, and point GND in FIG. 4 and point d in FIG. 3 are equipotential points. Lead wires may be used to electrically connect point c in FIG. 3 and point m in FIG. 4, and to electrically connect point d in FIG. 3 and point GND in FIG. 4, respectively.

[0087] In some embodiments, the third negative capacitance circuit C30 may have a structure other than that shown in FIG. 4, as long as it can cancel out the inter-lead parasitic capacitance C3.

[0088] The above description of the signal acquisition circuit 100, the signal acquisition circuit 200 and their structures is for the convenience of explanation and is not intended to limit the scope of the present application to the examples given.

[0089] FIG. 5 is a schematic diagram of a signal acquisition circuit 300 according to some embodiments of the present application.

[0090] 5 may include a first electrode 210, a second electrode 220, a differential amplifier 230, a first lead wire L1, a second lead wire L2, and a fourth negative capacitance circuit C40. For related explanations of the first electrode 210, the second electrode 220, the differential amplifier 230, the first lead wire L1, and the second lead wire L2, please refer to the related explanations of FIGS. 1 to 4, and explanations thereof will be omitted here.

[0091] As described in the above embodiment, a first ground parasitic capacitance C1 exists between the first lead wire L1 and the ground wire, and a second ground parasitic capacitance C2 exists between the second lead wire L2 and the ground wire. The first ground parasitic capacitance C1 and the second ground parasitic capacitance C2 are connected in parallel to the ground impedance Zin1 and the ground impedance Zin2 of the differential amplifier, respectively, which significantly reduces the input impedance of the entire circuit and worsens the impact of power frequency interference on signal collection.

[0092] Therefore, in some embodiments, a fourth negative capacitance circuit C40 is provided in the signal acquisition circuit 300 to reduce the effect of parasitic capacitance and increase the input impedance of the differential amplifier 230. In some embodiments, the first electrode 210 is connected to a first input terminal P of the fourth negative capacitance circuit C40 via a first lead wire L1, the second electrode 220 is connected to a second input terminal Q of the fourth negative capacitance circuit C40 via a second lead wire L2, and the first output terminal M of the fourth negative capacitance circuit C40 is connected to a first input terminal A of the differential amplifier 230 and a second output terminal N of the fourth negative capacitance circuit C40 is connected to a second input terminal B of the differential amplifier 230. The fourth negative capacitance circuit C40 has a negative capacitance effect, which offsets the parasitic capacitance to ground of the lead wires, thereby reducing the effect of the parasitic capacitance on the input impedance of the circuit and signal acquisition, and further improving the performance and signal acquisition effect of the signal acquisition circuit.

[0093] In some embodiments, the negative capacitance circuit C40 can be realized by using a fixed gain amplifier and a feedback capacitor, thereby simultaneously canceling the first ground parasitic capacitance C1 and the second ground parasitic capacitance C2. For specific implementations of the negative capacitance circuit C40, please refer to the related descriptions of Figures 6A and 6B.

[0094] In some embodiments, the signal acquisition circuit 300 may further include a third negative capacitance circuit C30. The third negative capacitance circuit C30 is electrically connected between the first lead wire L1 and the second lead wire L2 and connected in parallel to the lead-to-lead parasitic capacitance C3. In some embodiments, the signal acquisition circuit 200 may not include the third negative capacitance circuit C30 because the lead-to-lead parasitic capacitance C3 has a low impact on circuit performance. In some embodiments, if the requirements for the signal acquisition circuit 200 are high, the signal acquisition circuit 200 may include the third negative capacitance circuit C30. For specific implementations of the third negative capacitance circuit C30, please refer to the related descriptions of FIGS. 3 and 4, and further description will be omitted here.

[0095] In some embodiments, the signal acquisition circuit may further include a feedback control circuit that adjusts the equivalent capacitance value of the fourth negative capacitance circuit C40, for example, by changing the resistance or capacitance value of the negative capacitance circuit.

[0096] FIG. 6A is a schematic diagram of a fourth negative capacitance circuit C40 in a signal acquisition circuit 300 according to some embodiments of the present application.

[0097] In some embodiments, the fourth negative capacitance circuit C40 may include a first unit C402 and a second unit C404, where the first unit C402 includes a first amplifier G2 and a third negative feedback capacitor C46, ​​and the second unit C404 includes a second amplifier G3 and a fourth negative feedback capacitor C48. In some embodiments, the first amplifier G2 and the second amplifier G3 are both fixed gain amplifiers.

[0098] In some embodiments, the input terminal of the first amplifier G2 is the first input terminal P of the fourth negative capacitance circuit C40, the input terminal of the second amplifier G3 is the second input terminal Q of the fourth negative capacitance circuit C40, and similarly, the output terminal of the first amplifier G2 is the first output terminal M of the fourth negative capacitance circuit C40, and the output terminal of the second amplifier G3 is the second output terminal N of the fourth negative capacitance circuit C40.

[0099] In some embodiments, the input terminal P of the first amplifier G2 and the output terminal M of the first amplifier G2 are connected in series via a third negative feedback capacitor C46, ​​and the input terminal Q of the second amplifier G3 and the output terminal N of the second amplifier G3 are connected in series via a fourth negative feedback capacitor C48.

[0100] In some embodiments, when the gain of the first amplifier G2 is constant at g1, the gain of the second amplifier G3 is also constant at g1, and the equivalent capacitance value of the first unit C402 of the fourth negative capacitance circuit C40 can be expressed as follows:

[0101] C402=-C46(g1-1)(11)

[0102] The equivalent capacitance value of the second unit C404 of the fourth negative capacitance circuit C40 can be expressed as:

[0103] C404=-C48(g1-1)(12)

[0104] In some embodiments, the first amplifier G2 and the second amplifier G3 have equal and fixed gains, for example, if the gain of the first amplifier G2 is constant at g1, the gain of the second amplifier G3 is also constant at g1. In some embodiments, the gain range of the first amplifier G2 and the second amplifier G3 may be 0 to 100 dB, and preferably, the gain range of the first amplifier G2 and the second amplifier G3 is 0 to 10 dB.

[0105] In some embodiments, the third negative feedback capacitor C46 and the fourth negative feedback capacitor C48 have the same value. In this way, the first unit C402 and the second unit C404 of the fourth negative capacitance circuit C40 form a highly symmetric structure so that the signal acquisition circuit 300 as a whole can achieve a large common-mode rejection ratio. In some embodiments, if the gains of the first amplifier G2 and the second amplifier G3 are not equal, the common-mode rejection ratio of the circuit will be reduced, and the effect of reducing power frequency interference will not be achieved.

[0106] In some embodiments, each of the first amplifier G2 and the second amplifier G3 may be configured as a multi-stage cascade of fixed gain amplifiers.

[0107] In some embodiments, the first unit C402 of the fourth negative capacitance circuit C40 may cancel the first ground parasitic capacitance C1, and the second unit C404 of the fourth negative capacitance circuit C40 may cancel the second ground parasitic capacitance C2. This allows the fourth negative capacitance circuit C40 to simultaneously cancel the first ground parasitic capacitance C1 and the second ground parasitic capacitance C2. In some embodiments, the equivalent capacitance value of the first unit C402 and the equivalent capacitance value of the second unit C404 can be expressed as follows:

[0108] C402=-C1(13)

[0109] C404=-C2(14)

[0110] In this way, the total capacitance to the ground of the first lead wire L1 and the total capacitance to the ground of the second lead wire L2 are both 0. In this case, the parasitic capacitance to the ground at the input end of the differential amplifier 230 is completely canceled out, which significantly improves the input impedance of the entire signal acquisition circuit 300 and further improves resistance to power frequency interference.

[0111] In some embodiments, considering that the parasitic capacitance may change slightly with the movement of the leads in an actual operating environment, the relative error between the absolute value of the equivalent capacitance value of the first unit C402 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C1 to ground of the first lead L1 is less than 50%, and the relative error between the absolute value of the equivalent capacitance value of the second unit C404 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C2 to ground of the second lead L2 is less than 50%. In some embodiments, the relative error between the absolute value of the equivalent capacitance value of the first unit C402 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C1 to ground of the first lead L1 is less than 30%, and the relative error between the absolute value of the equivalent capacitance value of the second unit C404 of the fourth negative capacitance circuit C40 and the parasitic capacitance value C2 to ground of the second lead L2 is less than 30%.

[0112] FIG. 6B is another schematic diagram of the fourth negative capacitance circuit C40 in the signal acquisition circuit 300 according to some embodiments of the present application.

[0113] In some embodiments, the fourth negative capacitance circuit C40 may include a double-ended differential amplifier G1, a first negative feedback capacitor C42, and a second negative feedback capacitor C44.

[0114] In some embodiments, the first input terminal of the double-ended differential amplifier G1 is the first input terminal P of the fourth negative capacitance circuit C40, the second input terminal of the double-ended differential amplifier G1 is the second input terminal Q of the fourth negative capacitance circuit C40, and similarly, the first output terminal of the double-ended differential amplifier G1 is the first output terminal M of the fourth negative capacitance circuit C40, and the second output terminal of the double-ended differential amplifier G1 is the second output terminal N of the fourth negative capacitance circuit C40. The first input terminal P of the double-ended differential amplifier G1 and the first output terminal M of the double-ended differential amplifier G1 are connected in series via a first negative feedback capacitor C42, and the second input terminal Q of the double-ended differential amplifier G1 and the second output terminal N of the double-ended differential amplifier G1 are connected in series via a second negative feedback capacitor C44.

[0115] In some embodiments, the double-ended differential amplifier G1 is a fixed gain amplifier. In some embodiments, the gain g0 of the double-ended differential amplifier G1 may range from 0 to 100 dB, and preferably ranges from 0 to 10 dB.

[0116] In some embodiments, the fourth negative capacitance circuit C40 may simultaneously cancel the first ground parasitic capacitance C1 and the second ground parasitic capacitance C2. In some embodiments, the double-ended differential amplifier G1 may be configured by combining multiple amplifiers with fixed gains. For example, the double-ended differential amplifier G1 may be configured by two amplifiers G11 and G12 with a gain of g0. The amplifiers G11 and G12 may be equal amplifiers with fixed gains and may have exactly the same structure. In some embodiments, the amplifier G11 has an input terminal at point P and an output terminal at point M. The first negative feedback capacitor C42 is connected in series between point P and point M. The circuit configuration consisting of the amplifier G11 and the first negative feedback capacitor C42 may cancel the first ground parasitic capacitance C1. In some embodiments, the amplifier G12 has an input terminal at point Q and an output terminal at point N, and a second negative feedback capacitor C44 is connected in series between points Q and N. The circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 may cancel out the first parasitic capacitance to ground C1. In some embodiments, the equivalent capacitance value C11 of the circuit structure consisting of the amplifier G11 and the first negative feedback capacitor C42 and the equivalent capacitance value C12 of the circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 can be expressed as follows:

[0117] C11=-C42(g0-1)(15)

[0118] C12=-C45(g0-1)(16)

[0119] In this case, the circuit structure consisting of the amplifier G11 and the first negative feedback capacitor C42 can cancel out the first ground parasitic capacitance C1, and the circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 can cancel out the second ground parasitic capacitance C2. In this case, the ground parasitic capacitances at the input ends of the differential amplifier are canceled out, which significantly improves the input impedance of the entire signal acquisition circuit and further improves its resistance to power frequency interference.

[0120] In some embodiments, to effectively cancel out the parasitic capacitance to ground at the input end of the differential amplifier, the relative error between the absolute value of the equivalent capacitance value C11 of the circuit structure consisting of the amplifier G11 and the first negative feedback capacitor C42 and the parasitic capacitance to ground value C1 of the first lead wire L1 is less than 50%, and the relative error between the absolute value of the equivalent capacitance value C12 of the circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 and the parasitic capacitance to ground value C2 of the second lead wire L2 is less than 50%. In some embodiments, in order to ensure that the input end of the differential amplifier has a larger input impedance, the relative error between the absolute value of the equivalent capacitance value C11 of the circuit structure consisting of the amplifier G11 and the first negative feedback capacitor C42 and the ground parasitic capacitance value C1 of the first lead wire L1 is less than 30%, and the relative error between the absolute value of the equivalent capacitance value C12 of the circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 and the ground parasitic capacitance value C2 of the second lead wire L2 is less than 30%.

[0121] It should be understood that in actual application, the smaller the relative error between the absolute value of the equivalent capacitance C11 of the circuit structure consisting of the amplifier G11 and the first negative feedback capacitor C42 and the ground parasitic capacitance C1 of the first lead wire L1, and the smaller the relative error between the equivalent capacitance C12 of the circuit structure consisting of the amplifier G12 and the second negative feedback capacitor C44 and the ground parasitic capacitance C2 of the second lead wire L2, the larger the ground parasitic capacitance C1 of the first lead wire L1 and the ground parasitic capacitance C2 of the second lead wire L2 that are canceled out by the fourth negative capacitance circuit C40, and the larger the input impedance of the entire signal acquisition circuit will be, resulting in a higher final signal acquisition effect.

[0122] In some embodiments, the structure of the fourth negative capacitance circuit C40 may be other than that shown in Figures 6A and 6B, and is not limited here, as long as the equivalent capacitance value of C40 can cancel out the first ground parasitic capacitance value C1 of the first lead wire L1 and the ground parasitic capacitance value C2 of the second lead wire L2.

[0123] 7A and 7B are schematic diagrams of an effects circuit before and after power frequency interference cancellation according to some embodiments of the present application;

[0124] In some embodiments, as shown in FIG. 7A , an analog signal acquisition circuit 400 is provided, which includes a common-mode power frequency source 501, a differential amplifier 530, a resistor R5 having a resistance of 10 MΩ, a resistor R6 having a resistance of 100 KΩ, and capacitors C5 and C6, each having a capacitance of 6 pF. The resistor R5 is connected to a first input terminal (A1) of the differential amplifier 530 via a first lead wire L11, and the resistor R6 is connected to a second input terminal (B1) of the differential amplifier 530 via a second lead wire L22. The capacitor C5 has one end connected to the first input terminal (A1) of the differential amplifier 530 and also connected to the first lead wire L11, and the other end grounded. The capacitor C6 has one end connected to the second input terminal (B1) of the differential amplifier 530 and also connected to the second lead wire L22, and the other end grounded.

[0125] The common-mode power supply 501 is an AC power supply with a peak voltage of 300 mV and a frequency of 50 Hz, simulating the common-mode power supply signal generated by the human body. The resistance values ​​of R5 and R6 may differ, simulating the impedance mismatch that occurs between the two electrodes when a real wearable device collects human body signals. The capacitors C5 and C6 simulate the parasitic capacitance that each of the two leads generates to ground when a real wearable device collects human body signals.

[0126] In some embodiments, the differential amplifier 530 uses a double-ended power supply scheme, with a first power supply terminal (511) connected to a positive power supply +Vcc, a second power supply terminal (512) connected to a negative power supply -Vcc, and one terminal (513) receiving a bias voltage being grounded. In some embodiments, the positive power supply +Vcc provides a voltage of 3.3V, and the negative power supply -Vcc provides a voltage of -3.3V.

[0127] In some embodiments, the signal acquisition circuit 400 further includes a first probe T1 disposed on the signal input side and connected to the first input terminal (A1) of the differential amplifier 530, and a second probe T2 disposed on the signal output side and connected to the output terminal (514) of the differential amplifier 530. The first probe T1 and the second probe T2 respectively measure the voltage peak value, effective value, frequency, etc. of the voltage signal before and after it is input to the differential amplifier 530. After testing, the obtained data is shown in Table 1 below.

[0128] [Table 1]

[0129] 7B is a schematic diagram of an effect circuit after power frequency interference is removed according to some embodiments of the present application. Figure 7B shows an example of Figure 7A with the addition of a negative capacitance circuit C510 and a negative capacitance circuit C520. The structures of the negative capacitance circuit C510 and the negative capacitance circuit C520 both use the structure shown in Figure 4, with the x point of the negative capacitance circuit C510 electrically connected to the X point on the first lead wire L11 and the y point of the negative capacitance circuit C520 electrically connected to the Y point on the second lead wire L22.

[0130] In some embodiments, the operational amplifier 502 of the negative capacitance circuit C510 has a first power supply terminal (521) connected to a positive power supply +Vcc and a second power supply terminal (522) connected to a negative power supply -Vcc, and the output terminal (523) of the operational amplifier 502 outputs an amplified voltage. In some embodiments, the positive power supply +Vcc provides a voltage of 3.3V, the negative power supply -Vcc provides a voltage of -3.3V, the capacitor C501 has a value of 6PF, and the resistors R51 and R52 each have a value of 10KΩ.

[0131] According to the above equation (10), the magnitude of the capacitance value of the negative capacitance circuit C510 can be calculated to be −6 PF.

[0132] The negative capacitance circuit C520 has the same configuration and uses elements of the same values ​​as the negative capacitance circuit C510, and therefore the magnitude of the capacitance value of the negative capacitance circuit C520 is also −6 PF.

[0133] After adding the two negative capacitance circuits, to verify that the power frequency interference of the entire signal acquisition circuit 400 was reliably reduced, tests were again conducted using the first probe T1 and the second probe T2, and the obtained data is shown in Table 2 below.

[0134] [Table 2]

[0135] Comparing the data in Tables 1 and 2, it can be seen that before adding the negative capacitance circuit C510 and the negative capacitance circuit C520, the peak voltage values ​​measured by the first probe T1 and the second probe T2 were both 11.4 mV, and after adding the negative capacitance circuit C510 and the negative capacitance circuit C520, the peak voltage value measured by the first probe T1 was 1.17 mV, and the peak voltage value measured by the second probe T2 was 1.10 mV. As can be seen, after adding the negative capacitance circuit C510 and the negative capacitance circuit C520, the power frequency interference of the entire circuit was reduced by more than 10 times.

[0136] These results show that adding a negative capacitance circuit to the input terminal of the differential amplifier significantly increases the input impedance and reduces the interference caused by converting the commercial frequency common mode to differential mode due to impedance mismatch of the electrodes, thereby significantly reducing the risk of circuit saturation.

[0137] In some embodiments, the above-described signal collection circuit 200 and signal collection circuit 300 may be applied to a wearable device. The wearable device (e.g., clothing, wristband, strap, etc.) may be placed on various parts of the human body (e.g., lower leg, upper leg, waist, back, chest, shoulder, neck, etc.), and can collect physiological signals of various parts of the body when the user is in different states, and then further process the collected signals.

[0138] The signal collection circuit can be used in situations where it is necessary to detect signals that can represent a user's physical state. For example, the physiological signals can include various signals such as respiratory signals, electrocardiogram signals, electromyogram signals, electroencephalogram signals, blood pressure signals, and temperature signals. In some embodiments, the wearable device that collects physiological signals can be applied to emerging cross-industries such as medicine, gaming entertainment, and health education. For example, it can be combined with technologies such as virtual reality and EMG collection to promote the development of immersive entertainment and education, and can be combined with technologies such as mechanical and electronic devices and exoskeletons to achieve the goals of reducing medical costs and promoting the development of medical health. This application does not limit the specific application scenarios of the signal collection circuit and the wearable device.

[0139] The beneficial effects of the embodiments of the present application include, but are not limited to, offsetting the parasitic capacitance in the signal acquisition circuit by installing a negative capacitance circuit, and further effectively increasing the input impedance of the entire signal acquisition circuit, ultimately significantly reducing the interference of the parasitic capacitance on the entire signal acquisition circuit, and improving the signal acquisition effectiveness of the signal acquisition circuit.

[0140] The achievable beneficial effects vary depending on the embodiment, and in different embodiments, the achievable beneficial effects may be any one or a combination of the above, or any other achievable beneficial effects.

[0141] Although the basic concepts have been described above, it will be apparent to those skilled in the art that the detailed disclosure above is merely illustrative and does not limit the present application. Although not expressly described herein, those skilled in the art may make various changes, improvements, and modifications to the present application. These changes, improvements, and modifications are intended to be suggested by the present application and therefore fall within the spirit and scope of the exemplary embodiments of the present application.

[0142] Furthermore, certain terms are used herein to describe embodiments of the present application. For example, "one embodiment," "one embodiment," and / or "some embodiments" refer to particular features, structures, or characteristics associated with at least one embodiment of the present application. Therefore, it is emphasized and understood that the appearances of "one embodiment" or "one embodiment" or "one alternative embodiment" more than once in various parts of this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.

[0143] Additionally, as will be appreciated by those skilled in the art, aspects of the present application may be illustrated and described in several patentable classes or contexts, including any new and useful process, machine, manufacture, or combination of matter, or any new and useful improvement thereto. Accordingly, aspects of the present application may be implemented entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or a combination of hardware and software. Such hardware or software may be referred to as a "data block," "module," "engine," "unit," "assembly," or "system." Additionally, aspects of the present application may take the form of a computer program product embodied in one or more computer-readable medium(s) containing computer-readable program code.

[0144] The computer storage medium may include a propagated data signal, propagated in baseband or as part of a carrier wave, for carrying computer program code. The propagated signal may take various forms, such as an electromagnetic signal, an optical signal, or a suitable combination. The computer storage medium may be any computer-readable medium other than a computer-readable storage medium, which can be coupled to an instruction execution system, device, or apparatus to achieve communication, propagation, or transmission of a program used therein. The program code on the computer storage medium may be propagated via any suitable medium, including wireless, cable, fiber optic cable, RF, or similar media, or any combination of the above media.

[0145] Furthermore, unless expressly stated in the claims, the enumerated order, use of alphanumeric characters, or use of other designations of processing elements or sequences described herein does not limit the order of the procedures and methods herein. While the above disclosure has set forth through various examples what are presently believed to be various useful embodiments of the invention, it should be understood that such details are merely illustrative, and that the appended claims are not limited to the disclosed embodiments, but rather are intended to cover all modifications and equivalent combinations within the spirit and scope of the embodiments herein. For example, the system assembly described above may be implemented by a hardware device, or may be implemented as a software-only solution, e.g., by installing the described system on an existing server or mobile device.

[0146] Similarly, in the foregoing description of embodiments of the present application, it should be understood that various features may be grouped together in a single embodiment, drawing, or description for the purpose of simplifying the application and facilitating an understanding of one or more embodiments of the present invention. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed subject matter requires more features than are recited in each claim. In fact, an embodiment may include fewer than all features of a single embodiment disclosed above.

[0147] In some embodiments, numbers describing the number of components and attributes are used; it should be understood that the numbers describing such embodiments are, in some instances, modified by the modifiers "about," "approximately," or "generally." Unless otherwise specified, "about," "approximately," or "generally" indicates that the number may vary by ±20%. Thus, in some embodiments, all numerical parameters used in the specification and claims are approximations that may vary depending on the specific characteristics of a particular embodiment. In some embodiments, numerical parameters should be used with the stated number of significant digits and ordinary rounding techniques should be applied. While in some embodiments, the numerical ranges and parameters used to determine ranges are approximations, in specific embodiments, such numerical values ​​are set as precisely as possible.

[0148] All patents, patent applications, published patent applications, and other materials, such as papers, books, specifications, publications, and documents, referenced in this application are incorporated herein by reference in their entirety, except for any prosecution history documents that are inconsistent or inconsistent with the content of this application and any documents that may have a limiting effect on the broadest scope of the claims of this application (now or later related to this application). Further, in the event that any explanation, definition, and / or term usage in the accompanying materials of this application is inconsistent or inconsistent with the content set forth in this application, the explanation, definition, and / or term usage in this application shall control.

[0149] Finally, it should be understood that the embodiments described herein are merely illustrative of the principles of the present embodiments. Other variations may be within the scope of the present application. Thus, by way of example, and not of limitation, alternative configurations of the present embodiments may be considered consistent with the teachings of the present application. Thus, the present embodiments are not limited to the embodiments expressly introduced and described herein. [Explanation of symbols]

[0150] 100 signal acquisition circuit 110 first electrode 120 Second electrode 130 Differential Amplifier L1 First lead L2 Second lead 200 Signal acquisition circuit 210 First electrode 220 Second electrode 230 Differential Amplifier C10 First negative capacitance circuit C20 Second negative capacitance circuit C30 Third negative capacitance circuit 410 first operational amplifier R1 First resistor R2 Second resistor C401 First capacitor 300 Signal acquisition circuit C40 Fourth negative capacitance circuit C402 1st Unit C404 2nd Unit G2 First Amplifier G3 Second Amplifier C46 Third negative feedback capacitor C48 Fourth negative feedback capacitor G1 Dual-Ended Differential Amplifier C42 First negative feedback capacitor C44 Second negative feedback capacitor 400 Signal Acquisition Circuit 501 Common Mode Power Frequency Source 530 Differential Amplifier R5, R6 resistance C5 and C6 capacitors L11 First lead L22 Second lead

Claims

1. a differential amplifier; a first electrode and a second electrode; a fourth negative capacitance circuit; Including, the first electrode is connected to a first input terminal of the fourth negative capacitance circuit via a first lead wire; the second electrode is connected to a second input terminal of the fourth negative capacitance circuit via a second lead wire; a first output terminal of the fourth negative capacitance circuit is connected to a first input terminal of the differential amplifier; a second output terminal of the fourth negative capacitance circuit is connected to a second input terminal of the differential amplifier; The signal acquisition circuit, wherein the fourth negative capacitance circuit has a negative capacitance effect.

2. the fourth negative capacitance circuit includes a double-ended differential amplifier, a first negative feedback capacitor, and a second negative feedback capacitor; 2. The signal acquisition circuit of claim 1, wherein the first negative feedback capacitor is connected between a first input terminal of the double-ended differential amplifier and a first output terminal of the double-ended differential amplifier, and the second negative feedback capacitor is connected between a second input terminal of the double-ended differential amplifier and a second output terminal of the double-ended differential amplifier.

3. 3. The signal acquisition circuit of claim 2, wherein the double-ended differential amplifier is a fixed gain amplifier.

4. the fourth negative capacitance circuit includes a first unit and a second unit, the first unit includes a first amplifier and a third negative feedback capacitor, and the second unit includes a second amplifier and a fourth negative feedback capacitor; 2. The signal acquisition circuit according to claim 1, wherein the third negative feedback capacitor is connected between the input terminal of the first amplifier and the output terminal of the first amplifier, and the fourth negative feedback capacitor is connected between the input terminal of the second amplifier and the output terminal of the second amplifier.

5. a relative error between the absolute value of the equivalent capacitance value of the first unit of the fourth negative capacitance circuit and the parasitic capacitance value of the first lead wire to ground is less than 50%; 5. The signal acquisition circuit according to claim 4, wherein a relative error between an absolute value of the equivalent capacitance value of the second unit of the fourth negative capacitance circuit and a parasitic capacitance value to ground of the second lead wire is less than 50%.

6. 2. The signal acquisition circuit of claim 1, further comprising a feedback control circuit that adjusts an equivalent capacitance value of the fourth negative capacitance circuit.

7. A wearable device comprising the signal collection circuit according to any one of claims 1 to 6.

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