High frequency amplifier

Abstract

To provide a high frequency amplifier capable of improving a high frequency characteristic.SOLUTION: A high frequency amplifier includes a capacitor including a part of a first wiring layer (wiring layer 123), a part of a second wiring layer (wiring layer 124), and a part of dielectric layers 131 to 136 provided between a driver amplifier 10, a carrier amplifier 20, and a peak amplifier 30 and a branch circuit and a phase adjustment circuit, thus signal interference between the driver amplifier, the carrier amplifier, and the peak amplifier, and the branch circuit and the phase adjustment circuit, is less likely to arise, and high frequency characteristic can be improved.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to high frequency amplifiers. [Background technology]

[0002] In recent years, mobile communication systems such as those for mobile phones have become increasingly wider in bandwidth. Therefore, power amplifiers used in base station equipment in these systems are expected to have high power efficiency across a wide frequency band. A known power amplifier for achieving this high power efficiency is the asymmetric Doherty amplifier, which has a carrier amplifier and a peaking amplifier. The carrier amplifier is sometimes called the main amplifier. The asymmetric Doherty amplifier is connected after the driver amplifier. Furthermore, a high-frequency amplifier has been proposed in which the driver amplifier, carrier amplifier, and peaking amplifier are three-dimensionally implemented. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-170703 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for improved high frequency characteristics for high frequency amplifiers.

[0005] An object of the present disclosure is to provide a high-frequency amplifier that can improve high-frequency characteristics. [Means for solving the problem]

[0006] A high-frequency amplifier according to the present disclosure is a high-frequency amplifier having a driver amplifier that amplifies an input high-frequency signal, and an asymmetric Doherty amplifier that amplifies a high-frequency signal output from the driver amplifier, the asymmetric Doherty amplifier having a first stacked structure, a second stacked structure stacked on the first stacked structure, and a third stacked structure stacked on the second stacked structure, the asymmetric Doherty amplifier including a carrier amplifier, a peak amplifier that starts an amplification operation when an output of the carrier amplifier reaches a saturation region and has a saturated output different from that of the carrier amplifier, a branch circuit to which the high-frequency signal output from the driver amplifier is input, a first signal path provided between the branch circuit and the carrier amplifier, a second signal path provided between the branch circuit and the peak amplifier, and a third signal path provided in at least one of the first signal path or the second signal path, the third signal path being configured to amplify a phase of an input signal to the carrier amplifier or a phase of an input signal to the peak amplifier. and a phase adjustment circuit that delays at least one phase of an input signal, wherein the branching circuit branches a high-frequency signal output from the driver amplifier into the first signal path and the second signal path and outputs the branched signal, the second laminated structure has a first wiring layer provided between the first laminated structure and the third laminated structure, a second wiring layer provided between the first wiring layer and the third laminated structure, a dielectric layer provided between the first wiring layer and the second wiring layer, and one or more capacitors including a part of the first wiring layer, a part of the second wiring layer, and a part of the dielectric layer, the driver amplifier, the carrier amplifier, and the peak amplifier are provided in the first laminated structure, and the branching circuit and the phase adjustment circuit are provided in the third laminated structure, and the capacitor is electrically connected to either the driver amplifier, the carrier amplifier, or the peak amplifier. [Effects of the Invention]

[0007] According to the present disclosure, high frequency characteristics can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a high-frequency amplifier according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing the configurations of a driver amplifier, an input matching circuit, an output matching circuit, and an output bias circuit. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of an asymmetric Doherty amplifier. [Figure 4] FIG. 4 is a cross-sectional view showing a high-frequency amplifier according to an embodiment. [Figure 5] FIG. 5 is a diagram (part 1) showing the layout of the wiring layer. [Figure 6] FIG. 6 is a diagram (part 2) showing the layout of the wiring layer. [Figure 7] FIG. 7 is a diagram (part 3) showing the layout of the wiring layer. [Figure 8] FIG. 8 is a diagram (part 4) showing the layout of the wiring layer. [Figure 9] FIG. 9 is a diagram (part 5) showing the layout of the wiring layer. [Figure 10] FIG. 10 is a diagram (part 6) showing the layout of the wiring layer. [Figure 11] FIG. 11 is a cross-sectional view (part 1) illustrating a method for manufacturing a high-frequency amplifier according to an embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 2) illustrating a method for manufacturing the high-frequency amplifier according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 3) illustrating a method for manufacturing the high-frequency amplifier according to the embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 4) illustrating a method for manufacturing the high-frequency amplifier according to the embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 5) illustrating a method for manufacturing a high-frequency amplifier according to an embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 6) illustrating a method for manufacturing a high-frequency amplifier according to an embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 7) illustrating a method for manufacturing a high-frequency amplifier according to an embodiment. [Figure 18] FIG. 18 is a diagram showing a layout in the first example. [Figure 19] FIG. 19 is a diagram showing a layout in the second example. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] [1] A high-frequency amplifier according to one aspect of the present disclosure includes a driver amplifier that amplifies an input high-frequency signal, and an asymmetric Doherty amplifier that amplifies a high-frequency signal output from the driver amplifier, the asymmetric Doherty amplifier including a first stacked structure, a second stacked structure stacked on the first stacked structure, and a third stacked structure stacked on the second stacked structure, the asymmetric Doherty amplifier including a carrier amplifier, a peak amplifier that starts an amplification operation when an output of the carrier amplifier reaches a saturation region and has a saturated output different from that of the carrier amplifier, a branch circuit to which the high-frequency signal output from the driver amplifier is input, a first signal path provided between the branch circuit and the carrier amplifier, a second signal path provided between the branch circuit and the peak amplifier, and a third signal path provided in at least one of the first signal path or the second signal path, the third signal path being configured to adjust the phase of an input signal of the carrier amplifier or the peak amplitude. and a phase adjustment circuit that delays at least one of the phases of an input signal to the driver amplifier, the branching circuit branches a high-frequency signal output from the driver amplifier into the first signal path and the second signal path and outputs the branched signal, the second laminated structure has a first wiring layer provided between the first laminated structure and the third laminated structure, a second wiring layer provided between the first wiring layer and the third laminated structure, a dielectric layer provided between the first wiring layer and the second wiring layer, and one or more capacitors including a part of the first wiring layer, a part of the second wiring layer, and a part of the dielectric layer, the driver amplifier, the carrier amplifier, and the peaking amplifier are provided in the first laminated structure, and the branching circuit and the phase adjustment circuit are provided in the third laminated structure, and the capacitor is electrically connected to either the driver amplifier, the carrier amplifier, or the peaking amplifier.

[0011] A capacitor including a part of the first wiring layer, a part of the second wiring layer, and a part of the dielectric layer is provided between the driver amplifier, carrier amplifier, and peak amplifier and the branch circuit and phase adjustment circuit, thereby reducing signal interference between the driver amplifier, carrier amplifier, and peak amplifier and the branch circuit and phase adjustment circuit, and improving high-frequency characteristics.

[0012] [2] In [1], a first input matching circuit may be provided, the first input matching circuit including the capacitor and connected to the input terminal of the driver amplifier. In this case, the number of surface-mounted components included in the first input matching circuit can be reduced.

[0013] [3] In [2], the first input matching circuit may be provided in the first stacked structure and the second stacked structure, and in this case, a part of the first wiring layer may be used as an electrode of a capacitor included in the first input matching circuit.

[0014] [4] In any one of [1] to [3], a second input matching circuit may be provided, which includes the capacitor and is connected to the input terminal of the carrier amplifier. In this case, the number of surface-mounted components included in the second input matching circuit can be reduced.

[0015] [5] In [4], the second input matching circuit may be provided in the first stacked structure and the second stacked structure. In this case, a part of the first wiring layer may be used as an electrode of a capacitor included in the second input matching circuit.

[0016] [6] In any one of [1] to [5], a third input matching circuit may be provided, which includes the capacitor and is connected to the input terminal of the peak amplifier. In this case, the number of surface-mounted components included in the third input matching circuit can be reduced.

[0017] [7] In [6], the third input matching circuit may be provided in the first stacked structure and the second stacked structure. In this case, a part of the first wiring layer may be used as an electrode of a capacitor included in the third input matching circuit.

[0018] [8] In any one of [1] to [7], the first wiring layer may have a ground area that overlaps, at least in a plan view, with a transmission line through which a high-frequency signal output from the carrier amplifier or the peak amplifier is transmitted. In particular, the high-frequency signal output from the carrier amplifier or the peak amplifier is susceptible to the influence of parasitic capacitance, and the provision of the ground area makes it easier to suppress degradation of the high-frequency signal due to the parasitic capacitance.

[0019] [9] In any of [1] to [8], when n is an integer equal to or greater than 0, the electrical length from the output terminal of the driver amplifier to the input terminal of the carrier amplifier may be in the range of (2n+1)×π-π / 2 to (2n+1)×π+π / 2 in terms of the phase of the high-frequency signal. In this case, even if the driver amplifier and carrier amplifier are close to each other, the electrical characteristics of the carrier amplifier can be easily stabilized.

[0020]

[10] In any of [1] to [9], when n is an integer equal to or greater than 0, the electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier may be within a range of (2n+1)×π-π / 2 or more and (2n+1)×π+π / 2 or less in terms of the phase of the high-frequency signal. In this case, even if the driver amplifier and the peak amplifier are close to each other, the electrical characteristics of the carrier amplifier can be easily stabilized.

[0021]

[11] In any one of [1] to

[10] , the saturated output of the peak amplifier may be greater than the saturated output of the carrier amplifier. The peak amplifier requires a greater amount of phase shift to obtain optimal matching than the carrier amplifier.

[0022] [Details of the embodiments of the present disclosure] The following describes in detail embodiments of the present disclosure, but the present disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the semiconductor device. When viewed from an arbitrary point, the +Z side may be referred to as the upper side, upper side, or top, and the -Z side may be referred to as the lower side, lower side, or bottom.

[0023] (High frequency amplifier circuit) First, the circuit of the high frequency amplifier according to the embodiment will be described. Fig. 1 is a block diagram showing the high frequency amplifier according to the embodiment.

[0024] A high-frequency amplifier 1 according to the embodiment is mounted on a communication device such as a base station device in a mobile communication system. The high-frequency amplifier 1 is used, for example, to amplify a transmission signal. The high-frequency amplifier 1 amplifies, for example, a high-frequency (radio frequency: RF) signal having a frequency of approximately 5 GHz or more and 6 GHz or less.

[0025] 1 , the high-frequency amplifier 1 includes an input terminal RFin, an output terminal RFout, a driver amplifier 10, and an asymmetric Doherty amplifier 40. The asymmetric Doherty amplifier 40 includes a branching circuit 41, a first signal path 41A, a second signal path 41B, a carrier amplifier 20, and a peaking amplifier 30. The high-frequency amplifier 1 further includes an input matching circuit 11, an output matching circuit 12, and an output bias circuit 14. The asymmetric Doherty amplifier 40 further includes a phase adjustment circuit 23, an input matching circuit 21, an output matching circuit 22, an input bias circuit 24, a phase adjustment circuit 33, an input matching circuit 31, an output matching circuit 32, an input bias circuit 34, and a Doherty network 42.

[0026] The input matching circuit 11 is connected to the input terminal RFin. The input matching circuit 11 also functions as an input bias circuit. The input matching circuit 11 is connected to an input terminal 18 of the driver amplifier 10, and the output matching circuit 12 and the output bias circuit 14 are connected to an output terminal 19 of the driver amplifier 10. An RF signal is input to the driver amplifier 10 from the input terminal RFin via the input matching circuit 11, and the driver amplifier 10 amplifies the input RF signal. The driver amplifier 10 amplifies the RF signal to a level that allows, for example, an asymmetric Doherty amplifier 40 to amplify it to a predetermined transmission power. The RF signal amplified by the driver amplifier 10 is output via the output matching circuit 12. The input matching circuit 11 is an example of a first input matching circuit.

[0027] The RF signal output via the output matching circuit 12 is input to the branch circuit 41. The first signal path 41A is provided between the branch circuit 41 and the carrier amplifier 20, and the second signal path 41B is provided between the branch circuit 41 and the peak amplifier 30. The branch circuit 41 branches the input RF signal into the first signal path 41A and the second signal path 41B and outputs the branched signal. For example, the branch circuit 41 is a Wilkinson type divider, and divides the RF signal amplified by the driver amplifier 10 equally into the first signal path 41A and the second signal path 41B and outputs the divided signal.

[0028] The first signal path 41A is provided with a phase adjustment circuit 23 and an input matching circuit 21. The input matching circuit 21 and the input bias circuit 24 are connected to an input terminal 28 of the carrier amplifier 20, and the output matching circuit 22 is connected to an output terminal 29 of the carrier amplifier 20. The phase adjustment circuit 23 delays the phase of the signal (input signal to the carrier amplifier 20) output from the branch circuit 41 to the first signal path 41A. An RF signal is input to the carrier amplifier 20 via the input matching circuit 21, and the carrier amplifier 20 amplifies the input RF signal. The RF signal amplified by the carrier amplifier 20 is output via the output matching circuit 22. The input matching circuit 21 is an example of a second input matching circuit.

[0029] The second signal path 41B is provided with a phase adjustment circuit 33 and an input matching circuit 31. The input matching circuit 31 and the input bias circuit 34 are connected to an input terminal 38 of the peak amplifier 30, and the output matching circuit 32 is connected to an output terminal 39 of the peak amplifier 30. The phase adjustment circuit 33 delays the phase of the signal (input signal to the peak amplifier 30) output from the branch circuit 41 to the second signal path 41B. An RF signal is input to the peak amplifier 30 via the input matching circuit 31, and the peak amplifier 30 amplifies the input RF signal. The peak amplifier 30 begins amplification when the output of the carrier amplifier 20 reaches a saturation region, and has a saturated output different from that of the carrier amplifier 20. The RF signal amplified by the peak amplifier 30 is output via the output matching circuit 32. The input matching circuit 31 is an example of a third input matching circuit.

[0030] The RF signal output via the output matching circuit 22 and the RF signal output via the output matching circuit 32 are input to the Doherty network 42 .

[0031] Next, a description will be given of the circuit configurations of driver amplifier 10, input matching circuit 11, output matching circuit 12, and output bias circuit 14. Fig. 2 is a circuit diagram showing the configurations of driver amplifier 10, input matching circuit 11, output matching circuit 12, and output bias circuit 14.

[0032] The input matching circuit 11 includes capacitors C2, C3, and C4, and inductors L1 and L2. The capacitor C3 and inductor L1 are connected in series to the input terminal RFin, in this order. The gate of the driver amplifier 10 is connected downstream of the inductor L1. The inductor L2 is connected in parallel with the capacitor C3. The capacitor C2 is connected between the node between the capacitor C3 and the inductor L1 and ground. The capacitor C4 is connected between the node between the inductor L1 and the gate of the driver amplifier 10 and ground.

[0033] The output matching circuit 12 includes a capacitor C8 and inductors L4, L5, L9, and L10. The capacitor C8, inductor L10, and inductor L9 are connected in series to the drain of the driver amplifier 10 in this order. The inductor L4 is connected between the node between the inductors L10 and L9 and ground. The inductor L5 is connected downstream of the inductor L9, between the inductor L9 and ground.

[0034] The output bias circuit 14 includes a capacitor C6 and an inductor L3. The inductor L3 is connected between a node to which a voltage Vd is input and the drain of the driver amplifier 10. The capacitor C6 is connected between the node to which the voltage Vd is input and ground. The voltage Vd is supplied as a drain bias for the driver amplifier 10 via the inductor L3. The capacitor C6 is a bypass capacitor for the voltage Vd.

[0035] Next, a description will be given of the asymmetric Doherty amplifier 40. The asymmetric Doherty amplifier 40 further amplifies the RF signal amplified by the driver amplifier 10 and outputs the amplified signal from the output terminal RFout. FIG. 3 is a circuit diagram showing the configuration of the asymmetric Doherty amplifier 40.

[0036] As described above, the asymmetric Doherty amplifier 40 includes the branch circuit 41, the first signal path 41A, the second signal path 41B, the carrier amplifier 20, the peak amplifier 30, the phase adjustment circuit 23, the input matching circuit 21, the output matching circuit 22, the input bias circuit 24, the phase adjustment circuit 33, the input matching circuit 31, the output matching circuit 32, the input bias circuit 34, and the Doherty network 42.

[0037] The branch circuit 41 includes capacitors C23, C24, and C29, inductors L11 and L12, and a resistor R3. The inductor L11 is connected between the output matching circuit 12 and the phase adjustment circuit 23. The inductor L12 is connected between the output matching circuit 12 and the phase adjustment circuit 33. The capacitor C23 is connected between a node between the output matching circuit 12 and the inductors L11 and L12 and ground. The capacitor C24 is connected downstream of the inductor L11 between the inductor L11 and ground. The capacitor C29 is connected downstream of the inductor L12 between the inductor L12 and ground. The resistor R3 is connected downstream of the capacitors C24 and C29 between the inductor L11 and inductor L12.

[0038] The phase adjustment circuit 23 includes a capacitor C30 and inductors L13 and L14. The inductors L13 and L14 are connected in series with the inductor L11 in this order. The capacitor C30 is connected between the node between the inductors L13 and L14 and ground.

[0039] The phase adjustment circuit 33 includes capacitors C32 and C1 and an inductor L15. The capacitors C32 and C1 are connected in series to the inductor L12 in this order. The inductor L15 is connected between the node between the capacitors C32 and C1 and ground.

[0040] The input matching circuit 21 includes capacitors C11, C12, and C7, and an inductor L17. The capacitor C11 and inductor L17 are connected in series with the inductor L14 in this order. The gate of the carrier amplifier 20 is connected downstream of the inductor L17. The capacitor C12 is connected between the node between the capacitor C11 and the inductor L17 and ground. The capacitor C7 is connected between the node between the inductor L17 and the gate of the carrier amplifier 20 and ground.

[0041] The input bias circuit 24 includes a capacitor C15, a resistor R4, and an inductor L6. The resistor R4 and the inductor L6 are connected in series, in this order, between a power supply Vg and the gate of the carrier amplifier 20. The capacitor C15 is connected between the node between the power supply Vg and the resistor R4 and ground. The gate bias of the carrier amplifier 20 is supplied from the power supply Vg via the inductor L6. The capacitor C15 is a bypass capacitor for the power supply Vg, and the resistor R4 is an adjustment resistor.

[0042] The input matching circuit 31 includes capacitors C10, C5, and C13, and an inductor L7. The capacitor C10 and the inductor L7 are connected in series to the capacitor C1 in this order. The gate of the peak amplifier 30 is connected downstream of the inductor L7. The capacitor C5 is connected between the node between the capacitor C10 and the inductor L7 and ground. The capacitor C13 is connected between the node between the inductor L17 and the gate of the carrier amplifier 20 and ground.

[0043] The input bias circuit 34 includes a capacitor C21, a resistor R5, and an inductor L8. The resistor R5 and the inductor L8 are connected in series in this order between a power supply Vg and the gate of the peak amplifier 30. The capacitor C21 is connected between the node between the power supply Vg and the resistor R5 and ground.

[0044] The output matching circuit 22 includes capacitors C9 and C26. Capacitor C26 is connected between the drain of the carrier amplifier 20 and the Doherty network 42. Capacitor C26 is a capacitor for blocking DC components. Capacitor C9 is connected between the node between capacitor C26 and the Doherty network 42 and ground. A voltage Vd is supplied as a drain bias for the carrier amplifier 20 from an external output bias circuit.

[0045] The output matching circuit 32 includes capacitors C28 and C16, and an inductor L16. The capacitor C28 and the inductor L16 are connected in series, in this order, between the drain of the peak amplifier 30 and the Doherty network 42. The capacitor C28 is a capacitor for blocking DC components. The capacitor C16 is connected between the node between the drain of the peak amplifier 30 and the capacitor C28 and ground. A voltage Vd is supplied from an external output bias circuit as a drain bias for the peak amplifier 30.

[0046] The Doherty network 42 includes a capacitor C25 connected between ground and a node between the capacitor C26 and the inductor L16 and the output terminal RFout.

[0047] (High-frequency amplifier structure) Next, the structure of the high-frequency amplifier 1 according to the embodiment will be described. Fig. 4 is a cross-sectional view showing the high-frequency amplifier according to the embodiment. Note that Fig. 4 shows a schematic cross-section of the high-frequency amplifier 1, and the arrangement of the driver amplifier 10, carrier amplifier 20, peak amplifier 30, surface-mounted components, transmission line patterns, and conductive vias does not correspond to the circuits shown in Figs. 1 to 3.

[0048] 4, the high-frequency amplifier 1 has a first laminate structure 111, a second laminate structure 112, and a third laminate structure 113. The second laminate structure 112 is provided on the first laminate structure 111, and the third laminate structure 113 is provided on the second laminate structure 112. The first laminate structure 111, the second laminate structure 112, and the third laminate structure 113 each have a square planar shape with each side measuring, for example, 6 mm.

[0049] The first laminated structure 111 includes a wiring layer 121, a dielectric layer 131, a wiring layer 122, a dielectric layer 132, a driver amplifier 10, a carrier amplifier 20, a peak amplifier 30, and a plurality of surface-mounted components 51.

[0050] The wiring layer 122 is provided on the lower surface of the dielectric layer 132. The thickness of the dielectric layer 132 is, for example, 0.1 mm or more and 0.2 mm or less. For example, the relative dielectric constant of the dielectric layer 132 is 3.0 or more and 3.7 or less, and the dielectric loss tangent is 0.002 or more and 0.007 or less. The thickness of the wiring layer 122 is, for example, 10 μm or more and 45 μm or less. The thickness of the wiring layer 122 may be 35 μm or more and 45 μm or less. The wiring layer 122 is, for example, a copper layer. As will be described in detail later, a transmission line pattern and a ground pattern are formed on the wiring layer 122. The conductivity of copper is 6.25×10 17 It is about S / m.

[0051] The driver amplifier 10 is mounted on the lower surface of the wiring layer 122. The driver amplifier 10 is, for example, an amplifier including a gallium nitride (GaN)-based high electron mobility transistor (HEMT). The driver amplifier 10 has a substrate and a semiconductor layer provided on the substrate. The driver amplifier 10 has a rectangular parallelepiped three-dimensional shape with a main surface 10a and a main surface 10b opposite to the main surface 10a. The main surface 10a is on the semiconductor layer, and the main surface 10b is on the substrate. An amplifier circuit including the semiconductor layer is formed on the main surface 10a. A gate pad is provided near one of two parallel sides of the main surface 10a, and a drain pad is provided near the other. In addition, source pads are provided on both sides of the gate pad, and the source pads are connected to electrodes provided on the main surface 10b. The main surface 10a faces upward, and the main surface 10b faces downward.

[0052] The carrier amplifier 20 is mounted on the lower surface of the wiring layer 122. The carrier amplifier 20 is, for example, an amplifier including a GaN-based HEMT. The carrier amplifier 20 has a substrate and a semiconductor layer provided on the substrate. The carrier amplifier 20 has a rectangular parallelepiped three-dimensional shape with a main surface 20a and a main surface 20b opposite to the main surface 20a. The main surface 20a is on the semiconductor layer, and the main surface 20b is on the substrate. An amplifier circuit including the semiconductor layer is formed on the main surface 20a. A gate pad is provided near one of two parallel sides of the main surface 20a, and a drain pad is provided near the other. In addition, source pads are provided on both sides of the gate pad, and the source pads are connected to electrodes provided on the main surface 20b. The main surface 20a faces upward, and the main surface 20b faces downward.

[0053] The peak amplifier 30 is mounted on the lower surface of the wiring layer 122. The peak amplifier 30 is, for example, an amplifier including a GaN-based HEMT. The peak amplifier 30 has a substrate and a semiconductor layer provided on the substrate. The peak amplifier 30 has a rectangular parallelepiped three-dimensional shape with a main surface 30a and a main surface 30b opposite to the main surface 30a. The main surface 30a is on the semiconductor layer, and the main surface 30b is on the substrate. An amplifier circuit including the semiconductor layer is formed on the main surface 30a. A gate pad is provided near one of two parallel sides of the main surface 30a, and a drain pad is provided near the other. In addition, source pads are provided on both sides of the gate pad, and the source pads are connected to electrodes provided on the main surface 30b. The main surface 30a faces upward, and the main surface 30b faces downward.

[0054] The surface-mounted components 51 are, for example, capacitors, inductors, or resistors, and are mounted on the lower surface of the wiring layer 122.

[0055] The dielectric layer 131 is provided below the dielectric layer 132. The dielectric layer 131 covers the wiring layer 122 and the surface-mounted components 51 from below. The dielectric layer 132 laterally covers the side surfaces of the driver amplifier 10, the carrier amplifier 20, and the peak amplifier 30. The main surface 10b of the driver amplifier 10, the main surface 20b of the carrier amplifier 20, and the main surface 30b of the peak amplifier 30 are not covered by the dielectric layer 132 and are exposed from the dielectric layer 132. The thickness of the dielectric layer 131 is, for example, 0.3 mm or more and 0.4 mm or less. The relative dielectric constant of the dielectric layer 131 is, for example, 3.0 or more and 3.7 or less, and the dielectric dissipation factor is 0.002 or more and 0.007 or less.

[0056] The wiring layer 121 is provided on the lower surface of the dielectric layer 131. The thickness of the wiring layer 121 is, for example, 10 μm or more and 120 μm or less. The thickness of the wiring layer 121 may be 80 μm or more and 120 μm or less. The wiring layer 121 is, for example, a copper layer. As will be described in detail later, a transmission line pattern and a ground pattern are formed on the wiring layer 121.

[0057] The second stacked structure 112 has a wiring layer 123, a dielectric layer 133, and a wiring layer 124. The wiring layer 123 is provided on the lower surface of the dielectric layer 133, and the wiring layer 124 is provided on the upper surface of the dielectric layer 133. The dielectric layer 133 is provided between the wiring layer 123 and the wiring layer 124.

[0058] The wiring layer 123 is provided on the dielectric layer 132. The thickness of the wiring layer 123 is, for example, 10 μm or more and 35 μm or less. The thickness of the wiring layer 123 may be 10 μm or more and 18 μm or less. The wiring layer 123 is, for example, a copper layer. As will be described in detail later, a capacitor electrode pattern and a ground pattern are formed on the wiring layer 123. The ground pattern is formed in a solid state away from the electrode pattern. The wiring layer 123 is an example of a first wiring layer.

[0059] The thickness of the dielectric layer 133 is, for example, 1 μm or more and 24 μm or less. For example, the relative dielectric constant of the dielectric layer 133 is 7.0 or more and 10.0 or less, and the dielectric loss tangent is 0.01 or more and 0.03 or less.

[0060] The thickness of the wiring layer 124 is, for example, not less than 10 μm and not more than 35 μm. The thickness of the wiring layer 124 may be not less than 10 μm and not more than 18 μm. The wiring layer 124 is, for example, a copper layer. As will be described in detail later, a ground pattern is formed in a solid state on the wiring layer 124. The wiring layer 124 is an example of a second wiring layer.

[0061] The third laminated structure 113 has a dielectric layer 134, a wiring layer 125, a dielectric layer 135, a wiring layer 126, a dielectric layer 136, and a plurality of surface-mounted components 52. The wiring layer 125 is provided on the lower surface of the dielectric layer 135, and the wiring layer 126 is provided on the upper surface of the dielectric layer 135. The dielectric layer 135 is provided between the wiring layer 125 and the wiring layer 126.

[0062] The thickness of the dielectric layer 135 is, for example, 0.1 mm or more and 0.2 mm or less. For example, the relative dielectric constant of the dielectric layer 135 is 3.0 or more and 3.7 or less, and the dielectric dissipation factor is 0.002 or more and 0.007 or less. The thickness of the wiring layer 125 is, for example, 10 μm or more and 35 μm or less. The thickness of the wiring layer 125 may be 20 μm or more and 35 μm or less. The thickness of the wiring layer 126 is, for example, 10 μm or more and 45 μm or less. The thickness of the wiring layer 126 may be 30 μm or more and 45 μm or less. The wiring layers 125 and 126 are, for example, copper layers. As will be described in detail later, a solid ground pattern is formed on the wiring layer 125, and a transmission line pattern and a ground pattern are formed on the wiring layer 126.

[0063] Dielectric layer 134 is provided between dielectric layer 133 and dielectric layer 135, and covers wiring layer 124 from above and wiring layer 125 from below. The thickness of dielectric layer 134 is, for example, 0.1 mm or more and 0.2 mm or less. For example, the relative dielectric constant of dielectric layer 134 is 3.0 or more and 3.7 or less, and the dielectric dissipation factor is 0.002 or more and 0.007 or less.

[0064] The surface-mounted components 52 are, for example, capacitors, inductors, or resistors, and are mounted on the upper surface of the wiring layer 126.

[0065] Dielectric layer 136 is provided on dielectric layer 135. Dielectric layer 136 covers wiring layer 126 and surface-mounted components 52 from above. The thickness of dielectric layer 136 is, for example, 0.4 mm or more and 1.0 mm or less. For example, the relative dielectric constant of dielectric layer 136 is 3.0 or more and 4.0 or less, and the dielectric dissipation factor is 0.002 or more and 0.012 or less.

[0066] Conductive vias 141 and 142 for signal transmission and conductive via 151 for grounding are provided on dielectric layer 131. Conductive vias 141, 142, and 151 each electrically connect a part of wiring layer 121 to a part of wiring layer 122. The part of wiring layer 121 connected to conductive via 141 is used as input terminal RFin, and the part of wiring layer 121 connected to conductive via 142 is used as output terminal RFout. The part of wiring layer 121 connected to conductive via 151 is used as a ground terminal to which a ground potential is applied.

[0067] A conductive via 143 for signal transmission is provided in the dielectric layer 132. The conductive via 143 electrically connects a part of the wiring layer 122 and a part of the wiring layer 123.

[0068] A grounding conductive via 153 is provided in the dielectric layer 133. The conductive via 153 electrically connects a part of the wiring layer 123 and a part of the wiring layer 124.

[0069] A grounding conductive via 155 is provided in the dielectric layer 135. The conductive via 155 electrically connects a part of the wiring layer 125 and a part of the wiring layer 126.

[0070] Grounding conductive vias 156 are provided in the dielectric layers 133, 134, and 135. The conductive vias 156 electrically connect a part of the wiring layer 123, a part of the wiring layer 124, a part of the wiring layer 125, and a part of the wiring layer 126.

[0071] Conductive via 144 for signal transmission and conductive via 157 for grounding are provided in dielectric layers 132, 133, 134, and 135. Conductive via 144 electrically connects a portion of wiring layer 122 to a portion of wiring layer 126. Conductive via 144 may also be electrically connected to a portion of wiring layer 123. Conductive via 157 electrically connects a portion of wiring layer 122 to a portion of wiring layer 123 to a portion of wiring layer 124 to a portion of wiring layer 125 to a portion of wiring layer 126.

[0072] A strip line is formed by the transmission line pattern formed on wiring layer 122, the ground pattern formed on wiring layer 123, and the portion of dielectric layer 132 therebetween. A strip line is also formed by the transmission line pattern formed on wiring layer 126, the ground pattern formed on wiring layer 125, and the portion of dielectric layer 135 therebetween. The ground pattern formed on wiring layer 123, 124, or 125 blocks the propagation of electromagnetic waves generated in first laminated structure 111 to third laminated structure 113, and blocks the propagation of electromagnetic waves generated in third laminated structure 113 to first laminated structure 111.

[0073] In the second laminated structure 112, the electrode pattern formed on the wiring layer 123 is not electrically connected to the wiring layer 124, and a thin film capacitor is formed by the electrode pattern formed on the wiring layer 123, the ground pattern formed on the wiring layer 124, and the portion of the dielectric layer 133 between them.

[0074] The high-frequency amplifier 1 is mounted on, for example, a printed circuit board 100 of a communication device. The printed circuit board 100 has a base material 101, a signal wiring 102 to which an input terminal RFin is connected, a signal wiring 103 to which an output terminal RFout is connected, and a ground wiring 104 to which a ground terminal is connected. The signal wiring 102, the signal wiring 103, and the ground wiring 104 are provided on the upper surface of the base material 101.

[0075] A portion of the transmission line pattern of the wiring layer 121, which is connected to the signal wiring 102 to which the input terminal RFin is connected, is connected to a portion of the transmission line pattern of the wiring layer 122 (the input of the input matching circuit 11) through a conductive via 141. Furthermore, a portion of the transmission line pattern of the wiring layer 121, which is connected to the signal wiring 103 to which the output terminal RFout is connected, is connected to a portion of the transmission line pattern of the wiring layer 122 (the output of the Doherty network 42) through a conductive via 142. Furthermore, the ground pattern of the wiring layer 121 is connected to the ground patterns of the wiring layers 122, 123, 124, 125, and 126 through conductive vias 153, 155, 156, and 157, etc. Conductive vias for grounding may be provided in the dielectric layer 132.

[0076] A portion of the transmission line pattern of the wiring layer 122 connected to the drain pad (output terminal 19) of the driver amplifier 10 is connected to a portion of the transmission line pattern of the wiring layer 126 (the input of the output matching circuit 12) through one conductive via 144 (conductive via 91 in FIGS. 5 and 9). A portion of the transmission line pattern of the wiring layer 126 connected to the output of the phase adjustment circuit 23 is connected to a portion of the transmission line pattern of the wiring layer 122 (the input of the input matching circuit 21) through one conductive via 144 (conductive via 92 in FIGS. 5 and 9). A portion of the transmission line pattern of the wiring layer 126 connected to the output of the phase adjustment circuit 33 is connected to a portion of the transmission line pattern of the wiring layer 122 (the input of the input matching circuit 31) through one conductive via 144 (conductive via 93 in FIGS. 5 and 9).

[0077] A part of the transmission line pattern of the wiring layer 122 is connected to a part of the electrode pattern of the wiring layer 123 through a conductive via 143 .

[0078] Next, the layout of each wiring layer will be described. Fig. 5 is a diagram showing the layout of wiring layer 126. Fig. 6 is a diagram showing the layout of wiring layer 125. Fig. 7 is a diagram showing the layout of wiring layer 124. Fig. 8 is a diagram showing the layout of wiring layer 123. Fig. 9 is a diagram showing the layout of wiring layer 122. Fig. 10 is a diagram showing the layout of wiring layer 121. In Figs. 5 to 10, the ground patterns are given a matte finish (a dotted pattern). Fig. 5 also shows surface-mounted components 51, and Fig. 10 also shows surface-mounted components 52, driver amplifier 10, carrier amplifier 20, and peak amplifier 30.

[0079] 5, the wiring layer 126 is formed with a ground pattern 126G, a transmission line pattern that constitutes the output bias circuit 14, and a transmission line pattern that constitutes the output matching circuit 12. The wiring layer 126 also is formed with a transmission line pattern that constitutes the branch circuit 41, a transmission line pattern that constitutes the phase adjustment circuit 23, and a transmission line pattern that constitutes the phase adjustment circuit 33. On the upper surface of the transmission line patterns of the wiring layer 126, surface-mounted components 52 are mounted capacitors C6, C8, C23, C24, C29, C30, C32, and C1, inductors L3, L10, L4, L9, L5, L11, L12, L13, L14, and L15, and a resistor R3.

[0080] 6, a ground pattern 125G is formed in a solid state on the wiring layer 125. The wiring layer 125 has openings formed therein through which the conductive vias 144 pass.

[0081] 7, a ground pattern 124G is formed in a solid state on the wiring layer 124. The wiring layer 124 has openings formed therein through which the conductive vias 144 pass.

[0082] 8, a ground pattern 123G is formed in a solid state on the wiring layer 123. The wiring layer 123 also has formed thereon an electrode pattern of the capacitor C2 or C4 of the input matching circuit 11, an electrode pattern of the capacitor C12 or C7 of the input matching circuit 21, and an electrode pattern of the capacitor C5 or C13 of the input matching circuit 31. The wiring layer 123 has formed therein an opening through which the conductive via 144 passes.

[0083] 9, the wiring layer 122 is formed with a ground pattern 122G, a transmission line pattern constituting the input matching circuit 11, and a transmission line pattern constituting the Doherty network 42. The wiring layer 122 is further formed with a transmission line pattern constituting the input matching circuit 21, a transmission line pattern constituting the input bias circuit 24, and a transmission line pattern constituting the output matching circuit 22. The wiring layer 122 is further formed with a transmission line pattern constituting the input matching circuit 31, a transmission line pattern constituting the input bias circuit 34, and a transmission line pattern constituting the output matching circuit 32. On the lower surface of the transmission line patterns of the wiring layer 122, surface-mounted components 51 are mounted capacitors C3, C11, C15, C9, C26, C10, C21, C28, C16, and C25, inductors L1, L2, L17, L6, L7, L8, and L16, and resistors R4 and R5.

[0084] As shown in FIG. 10, the wiring layer 121 is provided with a ground pattern 121G formed in a solid state.

[0085] The output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20 may be adjacent to each other. However, if the spatial distance between the output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20 is small and the phase difference between the RF signals at the output terminal 19 and the input terminal 28 is small (including the same phase), an electrically unstable state may occur. For example, oscillation may occur.

[0086] In contrast, if the phases of the RF signals are opposite between the output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20, an electrically unstable state is less likely to occur. For example, if the electrical length between the output terminal 19 of the driver amplifier 10 and the input terminal 28 of the carrier amplifier 20, converted into the phase of the wavelength λ of the RF signal input to the input terminal RFin, is within the range of (2n+1)×π-π / 2 or more and (2n+1)×π+π / 2 or less, the phases of the RF signals become close to opposite phases, making it less likely that an electrically unstable state will occur. In other words, even if the driver amplifier 10 and the carrier amplifier 20 are close to each other, the electrical characteristics of the carrier amplifier 20 can be stabilized easily. Here, n is an integer greater than or equal to 0.

[0087] Furthermore, the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peak amplifier 30 may be adjacent to each other. However, if the spatial distance between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peak amplifier 30 is small and the phase difference between the RF signals at the output terminal 19 and the input terminal 38 is small (including the same phase), an electrically unstable state may occur. For example, oscillation may occur.

[0088] In contrast, if the phases of the RF signals are opposite between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peak amplifier 30, an electrically unstable state is less likely to occur. For example, if the electrical length between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peak amplifier 30, converted into the phase of the wavelength λ of the RF signal input to the input terminal RFin, is within a range of not less than "(2n+1)×π-π / 2" and not more than "(2n+1)×π+π / 2", the phases of the RF signals become close to opposite phases, making it less likely that an electrically unstable state will occur. In other words, even if the driver amplifier 10 and the peak amplifier 30 are close to each other, it is easy to stabilize the electrical characteristics of the peak amplifier 30.

[0089] In this embodiment, the wiring layer 126 has the transmission line pattern shown in FIG. 5, so that the electrical length between the output terminal 19 of the driver amplifier 10 and the input terminal 38 of the peak amplifier 30 is within the range of not less than "(2n+1)×π-π / 2" and not more than "(2n+1)×π+π / 2". Specifically, for example, in FIG. 5, the transmission line pattern from the output terminal (drain output) of the driver amplifier 10 to the branch circuit 41 makes a large detour from the center to the right half. Furthermore, a phase adjustment circuit 23 is provided between the branch circuit 41 and the carrier amplifier 20, and a phase adjustment circuit 33 is provided between the branch circuit 41 and the peak amplifier 30. Furthermore, the transmission line pattern from the output of the branch circuit 41 to the conductive via 93 and the transmission line pattern from the output of the branch circuit 41 to the conductive via 93 are curved rather than linear.

[0090] Furthermore, heat generated in the driver amplifier 10 is transferred from the main surface 10b to the wiring layer 121, heat generated in the carrier amplifier 20 is transferred from the main surface 20b to the wiring layer 121, and heat generated in the peak amplifier 30 is transferred from the main surface 30b to the wiring layer 121. The heat transferred to the wiring layer 121 is then released to the outside via the ground wiring 104 of the printed circuit board 100.

[0091] (High frequency amplifier operation) Next, the operation of the high-frequency amplifier 1 will be described.

[0092] An RF signal input to input terminal RFin (part of wiring layer 121) via signal wiring 102 reaches wiring layer 122 via conductive via 141 and is input to driver amplifier 10 via input matching circuit 11 provided in wiring layer 122. The RF signal amplified by driver amplifier 10 travels toward wiring layer 126 via conductive via 91. Then, in wiring layer 126, the RF signal is transmitted to branch circuit 41 via output matching circuit 12, and branched by branch circuit 41 into a first signal path 41A and a second signal path 41B for output.

[0093] The RF signal output to the first signal path 41A is input to the phase adjustment circuit 23. The phase adjustment circuit 23 delays the phase of the input RF signal (input signal to the carrier amplifier 20) by a predetermined distributed constant and outputs the delayed signal. On the other hand, the RF signal output to the second signal path 41B is input to the phase adjustment circuit 33. The phase adjustment circuit 33 delays the phase of the input RF signal (input signal to the peak amplifier 30) by a predetermined distributed constant and outputs the delayed signal. The RF signal output from the phase adjustment circuit 23 travels through the conductive via 92 to the wiring layer 122 and is input to the carrier amplifier 20 via the input matching circuit 21. The RF signal output from the phase adjustment circuit 33 travels through the conductive via 93 to the wiring layer 122 and is input to the peak amplifier 30 via the input matching circuit 31.

[0094] In the asymmetric Doherty amplifier 40, the peak amplifier 30 and the carrier amplifier 20 exhibit different maximum output intensities in response to an input RF signal. For example, the peak amplifier 30 has a saturated output power (size) approximately twice that of the carrier amplifier 20, and the peak amplifier 30 begins amplifying when the output of the carrier amplifier 20 reaches the saturated region. Specifically, the carrier amplifier 20 operates in class AB or class B, and the peak amplifier 30 operates in class C. When the instantaneous power is small, the carrier amplifier 20 operates and the peak amplifier 30 does not, thereby improving power efficiency. When the instantaneous power is large, both the carrier amplifier 20 and the peak amplifier 30 operate, thereby increasing the saturated power while maintaining high power efficiency. When the saturated output power of the peak amplifier 30 is larger than that of the carrier amplifier 20, the peak amplifier 30 requires a larger phase shift amount to achieve optimal matching than the carrier amplifier 20.

[0095] For example, the driver amplifier 10 has a size sufficient for an output of 10 W, the carrier amplifier 20 has a size sufficient for an output of 15 W, and the peak amplifier 30 has a size sufficient for an output of 30 W. In this case, the current consumption or power consumption may increase in the order of the driver amplifier 10, the carrier amplifier 20, and the peak amplifier 30. The amount of heat generated during operation may also increase in the order of the driver amplifier 10, the carrier amplifier 20, and the peak amplifier 30.

[0096] The RF signal amplified by the carrier amplifier 20 is input to the Doherty network 42 via the output matching circuit 22, and the RF signal amplified by the peak amplifier 30 is input to the Doherty network 42 via the output matching circuit 32. The RF signal output from the Doherty network 42 then reaches the output terminal RFout (part of the wiring layer 121) via the conductive via 142 and is output via the signal wiring 103.

[0097] (Manufacturing method of high frequency amplifier) Next, a description will be given of a method for manufacturing the high-frequency amplifier 1. Figures 11 to 17 are cross-sectional views illustrating a method for manufacturing the high-frequency amplifier according to this embodiment.

[0098] 11, a laminate is fabricated in which wiring layer 125 is formed on the lower surface of dielectric layer 135, wiring layer 126 is formed on the upper surface, and conductive via 155 is formed inside. This laminate can be fabricated using, for example, a copper-clad laminate. At this stage, the portions of wiring layer 126 that overlap conductive vias 144, 156, or 157 are not formed.

[0099] 12, a second laminate structure 112 is fabricated, in which a wiring layer 123 is formed on the lower surface of the dielectric layer 133, a wiring layer 124 is formed on the upper surface thereof, and a conductive via 153 is formed inside. The second laminate structure 112 can be fabricated using, for example, a copper-clad laminate.

[0100] 13, a dielectric layer 132, a wiring layer 122, and a conductive via 143 are formed under the second stacked structure 112. At this point, the portions of the wiring layer 122 that overlap with the conductive vias 144, 156, or 157 are not formed.

[0101] Next, as shown in FIG. 14, the laminate shown in FIG. 11 is superimposed on the laminate shown in FIG. 13 with the dielectric layer 134 sandwiched therebetween.

[0102] 15, conductive vias 144, 156, and 157 are formed. At this time, portions of wiring layer 126 that overlap with conductive vias 144, 156, or 157, and portions of wiring layer 122 that overlap with conductive vias 144, 156, or 157 are also formed.

[0103] 16, surface-mounted components 52 are mounted on the upper surface of wiring layer 126, and surface-mounted components 51, driver amplifier 10, carrier amplifier 20, and peak amplifier 30 are mounted on the lower surface of wiring layer 122. Conductive vias 141 and 142 are provided on the lower surface of wiring layer 122. Copper material can be used for the conductive vias 141 and 142.

[0104] 17, dielectric layer 136 is formed on dielectric layer 135, dielectric layer 131 is formed under dielectric layer 132, and wiring layer 121 is formed under dielectric layer 131. When forming dielectric layer 131, the dielectric layer that will become dielectric layer 131 is formed thicker than dielectric layer 131, and then the dielectric layer is polished so that main surface 10b of driver amplifier 10, main surface 20b of carrier amplifier 20, and main surface 30b of peak amplifier 30 are exposed. In addition, wiring layer 121 includes a ground pattern in contact with main surface 10b of driver amplifier 10, main surface 20b of carrier amplifier 20, and main surface 30b of peak amplifier 30, a transmission line pattern in contact with conductive via 141, and a transmission line pattern in contact with conductive via 142.

[0105] In this manner, the high-frequency amplifier 1 according to the embodiment can be manufactured.

[0106] In the high-frequency amplifier 1, a second laminate structure 112 having a wiring layer 123, a dielectric layer 133, and a wiring layer 124 is provided between the driver amplifier 10, the carrier amplifier 20, and the peak amplifier 30 and the branch circuit 41, the phase adjustment circuit 23, and the phase adjustment circuit 33. Therefore, signal interference is less likely to occur between the driver amplifier 10, the carrier amplifier 20, and the peak amplifier 30 and the branch circuit 41, the phase adjustment circuit 23, and the phase adjustment circuit 33, improving the high-frequency characteristics.

[0107] Furthermore, the uniformity of the path lengths between the capacitors C2, C4, C7, C12, C5, and C13 and the inputs of the driver amplifier 10, the carrier amplifier 20, or the peak amplifier 30 can be increased, thereby improving the high frequency characteristics.

[0108] Here, the high-frequency characteristics of amplifiers in two examples with different capacitor configurations will be further described with reference to Figures 18 and 19. Figure 18 is a diagram showing the layout in the first example, and Figure 19 is a diagram showing the layout in the second example.

[0109] In the first example shown in FIG. 18, the amplifier 60 has gate terminals 211, 212, 213 and 214, source terminals 221 and 222, and drain terminals 231, 232, 233 and 234.

[0110] Gate terminals 211, 212, 213, and 214 are arranged in this order along the first axis. Gate terminals 211, 212, 213, and 214 are connected to wiring layer 61. Wiring layer 61 is connected to a capacitor through conductive via 71. This capacitor is provided in second laminated structure 112, just like in high-frequency amplifier 1.

[0111] Source terminals 221 and 222 are arranged in this order along the first axis. Source terminal 221 is on the positive side of the second axis perpendicular to the first axis relative to the row of gate terminals 211, 212, 213, and 214. Source terminal 221 is on the negative side of the first axis relative to gate terminal 211, and source terminal 221 is on the positive side of the first axis relative to gate terminal 214. Source terminals 221 and 222 are connected to wiring layer 62. Wiring layer 62 is grounded through conductive vias 721 and 722. Conductive via 721 is on the negative side of the second axis relative to amplifier 60, and conductive via 722 is on the positive side of the second axis relative to amplifier 60.

[0112] Drain terminals 231, 232, 233, and 234 are arranged in this order along the first axis. Drain terminals 231, 232, 233, and 234 are on the positive side of the second axis relative to the row of source terminals 221 and 222. Drain terminal 231 is on the positive side of the first axis relative to source terminal 221, and drain terminal 234 is on the negative side of the first axis relative to source terminal 222. Drain terminals 231, 232, 233, and 234 are connected to wiring layer 63.

[0113] An input signal to amplifier 60 is input to wiring layer 61. An output signal from amplifier 60 is output to wiring layer 63. In amplifier 60, a signal flows as shown by arrow 70. Driver amplifier 10, carrier amplifier 20, and peak amplifier 30 in high-frequency amplifier 1 can have the same structure as amplifier 60.

[0114] In the amplifier 60, the signal path length between the conductive via 71 and the gate terminal 211 can be made equal to the signal path length between the conductive via 71 and the gate terminal 214. Also, the signal path length between the conductive via 71 and the gate terminal 212 can be made equal to the signal path length between the conductive via 71 and the gate terminal 213.

[0115] 19, a wiring layer 64 is provided, and a capacitor of a surface-mounted component 80 is provided between a wiring layer 61 and a wiring layer 64. The wiring layer 64 is grounded through a conductive via 723. Other configurations of the second example are the same as those of the first example.

[0116] In the second example, the difference in signal path length between the capacitors and the gate terminals 211, 212, 213 and 214 is greater than in the first example.

[0117] In this way, in the first example, the difference in signal path length between each of the gate terminals 211, 212, 213, and 214 of the amplifier 60 and the capacitor is smaller than in the second example, and excellent high frequency characteristics are obtained.

[0118] Furthermore, since capacitors C2, C4, C7, C12, C5, and C13 are formed in the second laminate structure, surface-mounted components for these capacitors are not required, which allows for a reduction in the number of surface-mounted components compared to when surface-mounted components for these capacitors are used.

[0119] For example, by including capacitors C2 and C4 in input matching circuit 11, the number of surface-mounted components in input matching circuit 11 can be reduced. Furthermore, by including capacitors C7 and C12 in input matching circuit 21, the number of surface-mounted components in input matching circuit 21 can be reduced. Furthermore, by including capacitors C5 and C13 in input matching circuit 31, the number of surface-mounted components in input matching circuit 31 can be reduced.

[0120] The parasitic resistance and parasitic inductance of the capacitors C2, C4, C7, C12, C5, and C13 formed in the second laminate structure are smaller than when surface-mounted components such as laminated ceramic capacitors are used, making it possible to match RF signals (high-frequency matching) with low impedance.

[0121] Furthermore, because the ground pattern of the wiring layer 123 is formed in a solid shape, even if the dielectric layer 133 has a high dielectric constant, the influence of the dielectric layer 133 on the RF signal transmitted through the transmission line pattern of the wiring layer 122 can be suppressed. In particular, the output matching circuit 22, the output matching circuit 32, and the Doherty network 42 are susceptible to the influence of parasitic capacitance caused by the surrounding dielectric layers. If ground patterns (ground areas) are provided in the wiring layer 123 in a portion that overlaps with the transmission line pattern that constitutes the output matching circuit 22 in a planar view, a portion that overlaps with the transmission line pattern that constitutes the output matching circuit 32 in a planar view, and a portion that overlaps with the Doherty network 42 in a planar view, degradation of the RF signal in the output matching circuit 22, the output matching circuit 32, and the Doherty network 42 can be easily suppressed.

[0122] Note that if one of the phase adjustment circuits 23 and 33 is provided, the other does not have to be provided. For example, if the phase adjustment circuit 23 is provided, the phase adjustment circuit 33 does not have to be provided, and if the phase adjustment circuit 33 is provided, the phase adjustment circuit 23 does not have to be provided.

[0123] Furthermore, a base member made of metal such as copper may be used instead of the wiring layer 121. In this case, the main surface 10b of the driver amplifier 10, the main surface 20b of the carrier amplifier 20, and the main surface 30b of the peak amplifier 30 can be fixed to the base member using, for example, a sintered material of silver or copper, and electrically connected to the base member.

[0124] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0125] 1: High frequency amplifier 10: Driver amplifier 10a, 10b, 20a, 20b, 30a, 30b: Main surface 11, 21, 31: Input matching circuit 12, 22, 32: Output matching circuit 14: Output bias circuit 18, 28, 38: Input terminals 19, 29, 39: Output terminals 20: Carrier amplifier 23, 33: Phase adjustment circuit 24, 34: Input bias circuit 30: Peak amplifier 40: Asymmetric Doherty amplifier 41: Branch circuit 41A: First signal path 41B: Second signal path 42: Doherty Network 51, 52, 80: Surface mount components 60: Amplifier 61, 62, 63, 64, 121, 122, 123, 124, 125, 126: Wiring layer 70: Arrow 71, 91, 92, 93, 141, 142, 143, 144, 151, 153, 155, 156, 157, 721, 722, 723: Conductive vias 100: Printed circuit board 101: Base material 102, 103: Signal wiring 104: Ground wiring 111: First laminated structure 112: Second laminated structure 113: Third laminated structure 121G, 122G, 123G, 124G, 125G, 126G: Ground pattern 131, 132, 133, 134, 135, 136: Dielectric layers 211, 212, 213, 214: Gate terminals 221, 222: Source terminals 231, 232, 233, 234: Drain terminals C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C15, C16, C21, C23, C24, C25, C26, C28, C29, C30, C32: Capacitor L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15, L16, L17: Inductor R3, R4, R5: Resistor elements RFin: Input terminal RFout: Output terminal Vg: power supply λ: Wavelength

Claims

1. A driver amplifier that amplifies the input high-frequency signal; an asymmetric Doherty amplifier that amplifies the high-frequency signal output from the driver amplifier; A high frequency amplifier having a first laminated structure; a second laminated structure laminated on the first laminated structure; a third laminated structure laminated on the second laminated structure; and The asymmetric Doherty amplifier Carrier amplifier and a peak amplifier that starts amplifying when the output of the carrier amplifier reaches a saturation region and has a saturated output different from that of the carrier amplifier; a branch circuit to which the high-frequency signal output from the driver amplifier is input; a first signal path provided between the branch circuit and the carrier amplifier; a second signal path provided between the branch circuit and the peak amplifier; a phase adjustment circuit provided in at least one of the first signal path and the second signal path, which delays at least one of the phase of the input signal of the carrier amplifier and the phase of the input signal of the peak amplifier; and the branching circuit branches the high-frequency signal output from the driver amplifier into the first signal path and the second signal path, and outputs the branched signal; The second laminated structure is a first wiring layer provided between the first stacked structure and the third stacked structure; a second wiring layer provided between the first wiring layer and the third stacked structure; a dielectric layer provided between the first wiring layer and the second wiring layer; one or more capacitors each including a portion of the first wiring layer, a portion of the second wiring layer, and a portion of the dielectric layer; and the driver amplifier, the carrier amplifier, and the peak amplifier are provided in the first stacked structure; the branch circuit and the phase adjustment circuit are provided in the third stacked structure; and The capacitor is electrically connected to any one of the driver amplifier, the carrier amplifier, and the peak amplifier.

2. 2. The high-frequency amplifier according to claim 1, further comprising a first input matching circuit including the capacitor and connected to an input terminal of the driver amplifier.

3. 3. The high-frequency amplifier according to claim 2, wherein the first input matching circuit is provided in the first laminated structure and the second laminated structure.

4. 4. The high-frequency amplifier according to claim 1, further comprising a second input matching circuit including the capacitor and connected to an input terminal of the carrier amplifier.

5. 5. The high-frequency amplifier according to claim 4, wherein the second input matching circuit is provided in the first laminated structure and the second laminated structure.

6. 4. The high-frequency amplifier according to claim 1, further comprising a third input matching circuit including the capacitor and connected to the input terminal of the peak amplifier.

7. 7. The high-frequency amplifier according to claim 6, wherein the third input matching circuit is provided in the first laminated structure and the second laminated structure.

8. 4. The high-frequency amplifier according to claim 1, wherein the first wiring layer has a ground region that overlaps, at least in plan view, with a transmission line through which a high-frequency signal output from the carrier amplifier or the peak amplifier is transmitted.

9. 4. The high-frequency amplifier according to claim 1, wherein, when n is an integer equal to or greater than 0, an electrical length from the output terminal of the driver amplifier to the input terminal of the carrier amplifier is within a range of not less than "(2n+1)×π-π / 2" and not more than "(2n+1)×π+π / 2" in terms of the phase of the high-frequency signal.

10. 4. The high-frequency amplifier according to claim 1, wherein, when n is an integer equal to or greater than 0, an electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier is within a range of not less than "(2n+1)×π-π / 2" and not more than "(2n+1)×π+π / 2" in terms of the phase of the high-frequency signal.

11. 4. The high-frequency amplifier according to claim 1, wherein a saturated output of the peak amplifier is greater than a saturated output of the carrier amplifier.

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