Driving device

Abstract

To provide a driving device capable of suppressing an increase in a switching ripple generated in each of a plurality of driving units in a superimposed manner.SOLUTION: A driving device includes: a plurality of driving units each provided corresponding to each of a plurality of loads and to which an input current from a common input line is input, the plurality of driving units each having a switching element for outputting a driving current to the corresponding load based on a clock signal; and a phase adjusting unit configured to adjust a phase difference of each clock signal corresponding to each driving unit so as to reduce a switching ripple caused by switching of each switching element based on a command signal corresponding to each of the plurality of loads.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a drive device. [Background technology]

[0002] Conventionally, a configuration is known in which an input current is supplied from one power supply unit to multiple drive units (e.g., amplifiers) via a common input line. The drive units are provided with switching elements for outputting drive current, and the switching elements are switched so that the drive current corresponds to a command signal for the load to which each drive unit is connected.

[0003] In such a configuration, ripple currents (switching ripples) generated by switching the switching elements in each driver propagate to the input lines of each driver. Because the input lines of each driver are connected to a common input line, the propagated switching ripples may overlap and increase.

[0004] To solve this problem, for example, Patent Document 1 discloses a configuration in which the phases of the clock signals of the respective driving units are shifted for each driving unit, thereby canceling out the switching ripples. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-25784 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the configuration described in Patent Document 1, the amount of phase shift in the clock signal is fixed for each driver, so depending on the degree of fluctuation in the load power of each driver, the switching ripple may not be minimized, and there is room for improvement in the configuration to suppress an increase in the switching ripple.

[0007] An object of the present disclosure is to provide a drive device that can suppress the superposition and increase of switching ripples generated in each of a plurality of drive units. [Means for solving the problem]

[0008] The drive device according to the present disclosure comprises: a plurality of drive units provided corresponding to the plurality of loads, each of which receives an input current from a common input line, the drive units each having a switching element for outputting a drive current to the corresponding load based on a clock signal; a phase adjusting unit that adjusts a phase difference between clock signals corresponding to the respective driving units based on a command signal corresponding to each of the plurality of loads so as to reduce switching ripples caused by switching of each switching element; Equipped with. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to prevent switching ripples generated in each of a plurality of drive units from being superimposed and increasing. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram schematically illustrating a drive device according to an embodiment of the present invention. [Figure 2] 10A and 10B are diagrams showing the time change in input current for each driver when driven by clock signals with no phase difference. [Figure 3] 10A and 10B are diagrams showing the time change of input current for each driver when driven by a clock signal with an adjusted phase difference. [Figure 4] 10A and 10B are diagrams illustrating changes in a clock signal over time when adjusting from a reference clock signal to an adjusted clock signal. [Figure 5] 10 is a flowchart illustrating an example of an operation of phase adjustment control of the drive device. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. Fig. 1 is a diagram schematically illustrating a drive device 100 according to an embodiment of the present disclosure.

[0012] 1, the driving device 100 according to this embodiment is a device that receives an input current from one power supply unit 1 and can output a driving current to each of a plurality of loads 2. The driving device 100 has a plurality of driving sections 110 and a phase adjustment section 120.

[0013] The power supply unit 1 includes, for example, an AC / DC converter, is connected to an AC power supply 1A, and converts AC voltage supplied from the AC power supply 1A into DC voltage. The power supply unit 1 is configured to input an output current based on the converted DC voltage to each of the multiple driving units 110 via a common input line 1B.

[0014] The plurality of loads 2 are, for example, motor devices such as linear motors. Each of the plurality of loads 2 is connected to a respective one of the plurality of driving units 110, and is driven by being supplied with a driving current output from the connected driving unit 110. Each of the plurality of loads 2 is provided with a control circuit.

[0015] Each control circuit is configured to output a command signal to the drive device 100 so that the drive unit 110 corresponding to the load 2 outputs a desired drive current. The command signal is a signal for instructing the drive unit 110 to output the drive current required to drive the load 2, and is, for example, a voltage signal corresponding to the drive current (any pulse current, sine wave current, etc.) to be input to the load 2. The command signal is identified by the control circuit on the drive device 100 side, and a clock signal (described later) is set so that the drive current conforms to the command signal.

[0016] Each of the plurality of driving units 110 is, for example, a driving circuit such as an amplifier, and is provided corresponding to each of the plurality of loads 2. An input current output from the power supply unit 1 is input to each of the plurality of driving units 110 via a common input line 1B.

[0017] Each of the multiple drivers 110 has, for example, a full-bridge circuit including a switching element 111. The switching element 111 is switched on or off based on a clock signal input to the driver 110. As a result, the driver 110 outputs a drive current based on the command signal to the corresponding load 2.

[0018] The clock signal is a signal for, for example, PWM (pulse width modulation) driving the switching element 111. The clock signal is generated by a clock generation circuit provided inside or outside the driving device 100, and is input to the driving device 100.

[0019] The clock generation circuit may be a known circuit having, for example, an oscillator, a frequency divider, etc. In the clock generation circuit, the oscillator generates a pulse signal that serves as a source signal, and the frequency divider divides the frequency of the source signal to, for example, 1 / 8, which is output as a clock signal to the driver 110 (see, for example, the source signal and reference clock signal shown in FIG. 4).

[0020] The phase adjustment unit 120 includes a known logic circuit capable of adjusting the phase of the clock signal generated by the clock generation circuit. The phase adjustment unit 120 may also include a control circuit (not shown) having a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), and input / output circuits.

[0021] In the phase adjustment unit 120, a control circuit acquires command signals from each of the multiple loads 2, and adjusts the phase difference of the clock signals to each drive unit 110 based on the command signal corresponding to each load 2. The control circuit may be provided outside the phase adjustment unit 120 (drive device 100).

[0022] Incidentally, switching of the switching elements 111 may cause switching ripples generated in each driver 110 to propagate to the input side of the driver 110. Since an input current is input to each driver 110 via a common input line 1B, there is a risk that the switching ripples generated in each driver 110 may be superimposed on the common input line 1B and increase.

[0023] In this embodiment, the phase adjustment unit 120 adjusts the phase difference between the clock signals of the drive units 110 based on the command signal so as to reduce switching ripples caused by switching of the switching elements 111. Specifically, the phase adjustment unit 120 adjusts the phase difference between the clock signals so that the switching ripples generated in the plurality of drive units 110 cancel each other out on the common input line 1B.

[0024] More specifically, the phase adjustment unit 120 adjusts the phase difference of the clock signals based on the output power of each driver 110 based on the command signal. For example, the phase adjustment unit 120 sets the multiple clock signals to either a first clock signal or a second clock signal.

[0025] The first clock signal is a clock signal whose phase is shifted by 0 degrees from the initially set clock signal (a clock signal whose phase difference has not been adjusted).

[0026] The second clock signal is a clock signal whose phase is shifted, for example, by 180 degrees (a predetermined degree) from the first clock signal.

[0027] The phase adjustment unit 120 adjusts the phase difference of the clock signals so that the sum of the output powers of the drivers 110 set to the first clock signal is equal to the sum of the output powers of the drivers 110 set to the second clock signal. The maximum value of the switching ripple generated by each driver increases in proportion to the output power of the corresponding driver. Therefore, by making the sum of the output powers of the drivers 110 set to the first clock signal equal to the sum of the output powers of the drivers 110 set to the second clock signal, it is possible to cancel out the switching ripple propagating to the common input line 1B.

[0028] For example, suppose the plurality of driving units 110 are eight driving units: a first driving unit, a second driving unit, a third driving unit, a fourth driving unit, a fifth driving unit, a sixth driving unit, a seventh driving unit, and an eighth driving unit.

[0029] First, the phase adjustment unit 120 sets the clock signal of the first driving unit with the highest output power as the first clock signal, and then sets the clock signals of the second driving unit with the second highest output power and the third driving unit with the third highest output power as the second clock signal.

[0030] Then, phase adjustment unit 120 compares the output power of the first driver set to the first clock signal with the sum of the output powers of the second and third drivers set to the second clock signal, and sets the clock signal of the fourth driver having the fourth highest output power based on the comparison result. For example, if the output power of the first driver is greater than the sum of the output powers of the second and third drivers, phase adjustment unit 120 sets the clock signal of the fourth driver to the second clock signal. On the other hand, if the output power of the first driver is equal to or less than the sum of the output powers of the second and third drivers, phase adjustment unit 120 sets the clock signal of the fourth driver to the first clock signal.

[0031] Similarly, the phase adjustment unit 120 sets the clock signals of the fifth, sixth, seventh and eighth drive units in order according to the comparison result between the sum of the output power of the drive units set to the first clock signal and the sum of the output power of the drive units set to the second clock signal.

[0032] In this way, the phase adjustment unit 120 adjusts the phase difference of the clock signals so that the sum of the output power of the driving unit 110 set to the first clock signal approaches the sum of the output power of the driving unit 110 set to the second clock signal.

[0033] For example, suppose the output powers based on the command signals of the first, second, third, fourth, fifth, sixth, seventh, and eighth drive units are 80 W, 70 W, 60 W, 50 W, 40 W, 30 W, 20 W, and 10 W, respectively. Figure 2 shows the change over time in the input current for each drive unit when driven by clock signals with no phase difference.

[0034] As shown in Figure 2, when eight drive units are driven by the initial setting clock signal (clock signal with no phase difference), the timing at which the switching ripple reaches its maximum value is the same. Therefore, the maximum value of the switching ripple that propagates from each drive unit to the common input line 1B and is superimposed is the sum of the maximum values ​​of the switching ripple generated in each drive unit. In other words, when each drive unit is driven by a clock signal with no phase difference, the impact of the switching ripple generated in each drive unit becomes greater.

[0035] In contrast to this, in this embodiment, the phase difference of the clock signals is adjusted based on the output power of each driver 110 based on the command signal so that the switching ripples generated in each driver 110 cancel each other out.

[0036] For example, the clock signals of the first drive unit, the fourth drive unit, the fifth drive unit, and the eighth drive unit are set to the first clock signal, and the clock signals of the second drive unit, the third drive unit, the sixth drive unit, and the seventh drive unit are set to the second clock signal.

[0037] The output powers of the drivers set to the first clock signal are 80W, 50W, 40W, and 10W, totaling 180W. The output powers of the drivers set to the second clock signal are 70W, 60W, 30W, and 20W, totaling 180W. In other words, the sum of the output powers of the drivers set to the first clock signal is equal to the sum of the output powers of the drivers set to the second clock signal. Figure 3 shows the change over time in input current for each driver when driven by clock signals with adjusted phase differences.

[0038] As shown in Figure 3, the first clock signal and the second clock signal have a phase difference of 180 degrees, so the timing at which the input current to the drive unit based on one clock signal reaches its peak value (maximum value) on the positive side is equal to the timing at which the input current to the drive unit based on the other clock signal reaches its peak value (minimum value) on the negative side.

[0039] As a result, the sum of the maximum values ​​of switching ripples generated in the drive units set to the first clock signal becomes equal to the sum of the maximum values ​​of switching ripples generated in the drive units set to the second clock signal.

[0040] As a result, the switching ripples generated in the respective drive units cancel each other out on the common input line 1B, so that the switching ripples on the common input line 1B can be made zero or close to zero. It is possible to prevent the switching ripples generated in the respective drive units from superimposing and increasing.

[0041] Furthermore, when adjusting the clock signal to an adjusted clock signal that adjusts the phase of the reference clock signal by a predetermined degree, the phase adjustment unit 120 may change the adjusted clock signal so that the deviation from the reference clock signal gradually approaches the predetermined degree over time.

[0042] The reference clock signal may be, for example, a clock signal of a drive unit having the smallest phase shift from the initially set clock signal, or may be the initially set clock signal. Figure 4 shows an example in which the initially set clock signal obtained by dividing the source signal is used as the reference clock signal.

[0043] For example, it is assumed that the reference clock signal is the first clock signal described above, and the adjusted clock signal is the second clock signal described above that is 180 degrees out of phase with the first clock signal.

[0044] Here, suppose that when all the driving units are operating on the reference clock signal, the phase difference is adjusted based on the command signal. At this time, if the clock signal is suddenly changed by, for example, 180 degrees from the reference clock signal, a period will occur in which the duty ratio of the clock signal in the control of the switching element 111 fluctuates drastically, which may affect the operation of the load 2.

[0045] The phase adjustment unit 120 shifts the phase of the clock signal from the reference clock signal by, for example, 45 degrees (e.g., one cycle of the source signal). The phase adjustment unit 120 shifts the phase of the clock signal by 45 degrees at any timing, for example, one or two cycles after the source signal. Finally, the clock signal is adjusted to an adjusted clock signal that is 180 degrees out of phase with the reference clock signal.

[0046] This makes it possible to prevent the occurrence of a period in which the duty ratio of the clock signal fluctuates significantly when adjusting the phase difference, and thus to reduce the influence on the operation of the load 2.

[0047] An example of the operation of the driving device 100 configured as above will be described. Fig. 5 is a flowchart showing an example of the operation of the phase adjustment control of the driving device 100. The processing in Fig. 5 is executed as appropriate, for example, when a command to drive the driving device 100 is received.

[0048] 5, the driving device 100 acquires a command signal of each load 2 (step S101). After step S101, the driving device 100 determines whether or not it is necessary to adjust the phase difference of the clock signals based on each command signal (step S102).

[0049] If the determination result indicates that the phase difference needs to be adjusted (step S102, YES), the driving device 100 adjusts the phase difference between the clock signals (step S103). Specifically, the driving device 100 adjusts the phase difference so that the sum of the output powers of the driving units set to the first clock signal is equal to the sum of the output powers of the driving units set to the second clock signal.

[0050] After step S103, the driving device 100 outputs a driving current to the load 2 according to the set clock signal (step S104). Returning to the determination in step S102, if there is no need to adjust the phase difference (step S102, NO), the process proceeds to step S104. A case in which there is no need to adjust the phase difference may be a case in which it is possible to drive all of the driving units 110 with a clock signal having no phase difference. Furthermore, a case in which there is no need to adjust the phase difference may be a case in which there is no change in the driving status based on the command signal when the process returns to step S101 from step S106 described below.

[0051] After step S104, the driving device 100 determines whether a certain time has elapsed (step S105). The certain time is, for example, a time set so that the driving device 100 can adjust the phase difference at an appropriate timing, and is a time that can be set to an appropriate time.

[0052] If the result of the determination is that the certain time has not elapsed (step S105, NO), the process of step S105 is repeated. On the other hand, if the certain time has elapsed (step S105, YES), the driving device 100 determines whether or not the driving of the entire device has been completed (step S106).

[0053] If the determination result shows that the driving of the entire device has not been completed (step S106, NO), the process returns to step S101. On the other hand, if the driving of the entire device has been completed (step S106, YES), this control ends. Note that if a command to end the driving of the entire device is received before the fixed time in step S105 has elapsed, this control may end at that point.

[0054] According to the present embodiment configured as described above, the phase adjustment unit 120 adjusts the phase difference of each clock signal corresponding to each drive unit 110 based on each command signal so as to reduce switching ripple caused by switching of each switching element 111.

[0055] As a result, the sum of the switching ripples generated in each driving unit 110 and propagating to the common input line 1B can be reduced, thereby preventing the switching ripples generated in each of the multiple driving units 110 from overlapping and increasing.

[0056] Furthermore, if switching ripples are superimposed on the common input line 1B and increase, it becomes necessary to provide a capacitor with a capacitance that matches the maximum value of the switching ripples on the common input line 1B. However, in this embodiment, the switching ripples can be reduced, so the capacitance of the capacitor provided on the common input line 1B can be reduced.

[0057] Furthermore, if the switching ripples are superimposed on the common input line 1B and increase, there is a possibility that noise will be generated due to the increased switching ripples. However, in this embodiment, the switching ripples can be reduced, and therefore the generation of noise due to the switching ripples can be suppressed.

[0058] Furthermore, if the switching ripples are superimposed and increase on the common input line 1B, there is a possibility that the power loss in the entire device will increase. However, in this embodiment, the switching ripples can be reduced, and therefore the power loss caused by the switching ripples can be reduced.

[0059] Furthermore, the phase adjustment unit 120 adjusts the phase difference so that the switching ripples generated in each of the multiple driving units 110 cancel each other out on the common input line 1B. As a result, the switching ripple on the common input line 1B can be made zero or close to zero.

[0060] Furthermore, the phase adjustment unit 120 adjusts the phase difference based on the output power of each driver 110 based on the command signal. Specifically, the phase adjustment unit 120 adjusts the phase difference so that the sum of the output powers of the drivers set to the first clock signal is equal to the sum of the output powers of the drivers set to the second clock signal.

[0061] This makes it possible to set the phase difference of the clock signals of the driving sections 110 in various patterns according to the driving conditions of the loads 2. As a result, it is possible to reliably reduce switching ripples.

[0062] Furthermore, based on the adjustment of the phase difference, phase adjustment unit 120 gradually adjusts the adjusted clock signal over time so that the deviation from the reference clock signal becomes a predetermined degree. This makes it possible to prevent the occurrence of periods in which the duty ratio of the clock signal fluctuates significantly when adjusting the phase difference, thereby reducing the impact on the operation of load 2.

[0063] In the above embodiment, the phase difference is adjusted so that the sum of the output powers of the drive units set to the first clock signal is equal to the sum of the output powers of the drive units set to the second clock signal, but the present disclosure is not limited to this. For example, the phase adjustment unit 120 may adjust the phase difference of the clock signals by referring to a table that associates drive patterns based on the command signals of the drive units with phase difference variation patterns of the clock signals.

[0064] The table associating the drive patterns with the phase difference variation patterns is stored in a storage device (not shown). The storage device may be provided in the drive device 100 or in an external device that can communicate with the drive device 100.

[0065] The drive pattern and the phase difference variation pattern may be patterns that are set in advance through experiments, simulations, or the like.

[0066] Even with this configuration, the sum of the switching ripples generated in each driving unit 110 and propagating to the common input line 1B can be reduced, thereby preventing the switching ripples generated in each of the multiple driving units 110 from overlapping and increasing.

[0067] In the above embodiment, the clock signals of the multiple drivers are set to one of two clock signals (first clock signal and second clock signal), but the present disclosure is not limited to this. For example, the phase adjustment unit may set the clock signals of the multiple drivers to one of three or more clock signals.

[0068] Furthermore, when the clock signals of the multiple drive units are set to one of three or more clock signals, the phase shift of each clock signal does not have to be 180 degrees. For example, when the clock signals of the multiple drive units are set to one of three clock signals, the three clock signals may be signals with a phase shift of 120 degrees each. Furthermore, when the clock signals of the multiple drive units are set to one of four clock signals, the four clock signals may be signals with a phase shift of 90 degrees each.

[0069] Furthermore, the above-described embodiments are merely examples of specific embodiments for carrying out the present disclosure, and the technical scope of the present disclosure should not be interpreted as being limited by these embodiments. In other words, the present disclosure can be carried out in various forms without departing from its gist or main features. [Industrial Applicability]

[0070] The drive device of the present disclosure is useful as a drive device that can suppress the superposition and increase of switching ripples generated in each of a plurality of drive units. [Explanation of symbols]

[0071] 1 power supply unit 1A AC power supply 1B Common input line 2. Load 100 Drive unit 110 Drive unit 111 Switching element 120 Phase adjustment section

Claims

1. a plurality of drive units provided corresponding to the plurality of loads, each of which receives an input current from a common input line, the drive units each having a switching element for outputting a drive current to the corresponding load based on a clock signal; a phase adjusting unit that adjusts a phase difference between clock signals corresponding to the respective driving units based on a command signal corresponding to each of the plurality of loads so as to reduce switching ripples caused by switching of each switching element; A drive unit comprising:

2. the phase adjustment unit adjusts the phase difference so that switching ripples generated in the plurality of drive units cancel each other out on the common input line. The drive device according to claim 1 .

3. the phase adjustment unit adjusts the phase difference based on the output power of each driver based on the command signal. The drive device according to claim 2 .

4. The phase adjustment unit setting the clock signals of the plurality of driving units to at least one of a first clock signal and a second clock signal that is shifted in phase from the first clock signal by a predetermined degree; adjusting the phase difference so that a sum of output powers of the driving units set to the first clock signal is equal to a sum of output powers of the driving units set to the second clock signal; The drive device according to claim 3 .

5. the phase adjustment unit adjusts the phase difference by referring to a table that associates a drive pattern based on the command signal of each drive unit with a phase difference variation pattern of a clock signal. The drive device according to claim 3 .

6. the phase adjustment unit, when adjusting the clock signal to an adjusted clock signal that adjusts the phase of the reference clock signal by a predetermined degree, changes the adjusted clock signal so that the deviation from the reference clock signal gradually approaches the predetermined degree over time; The drive device according to claim 2 .

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