Semiconductor device, manufacturing method for semiconductor device, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device in which an amount of harmful defects in a gate insulating layer is reduced.SOLUTION: A semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer provided between the silicon carbide layer and the gate electrode and containing carbon (C), nitrogen (N), and hydrogen (H); and a region provided between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration of 1×1021 cm-3 or more. A concentration distribution of nitrogen in the silicon carbide layer, the silicon oxide layer, and the region has a peak in the region. A first concentration of nitrogen at a first position 10 nm away from the peak to the silicon oxide layer side is 1×1018 cm-3 or more, a second concentration of carbon at the first position is 1×1018 cm-3 or more, a third concentration of hydrogen at the first position is 1×1018 cm-3 or more. The second concentration is 80% or more and 120% or less of the first concentration, and the third concentration is 80% or more and 120% or less of the first concentration.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] For example, when forming a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) using silicon carbide, problems such as reduced carrier mobility and threshold voltage fluctuations occur. One of the causes of reduced carrier mobility and threshold voltage fluctuations is thought to be harmful defects present in the gate insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-153168 Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by the present invention is to provide a semiconductor device in which the amount of harmful defects in the gate insulating layer is reduced. [Means for solving the problem]

[0006] The semiconductor device of the embodiment includes a silicon carbide layer, a gate electrode, a silicon oxide layer provided between the silicon carbide layer and the gate electrode and containing carbon (C), nitrogen (N), and hydrogen (H), and a silicon oxide layer provided between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration of 1×10 21 cm -3 and a region, wherein a concentration distribution of nitrogen in the silicon carbide layer, the silicon oxide layer, and the region has a peak in the region, and a first concentration of nitrogen at a first position 10 nm away from the peak toward the silicon oxide layer is 1×10 18 cm -3 and the second concentration of carbon at the first location is 1×10 18 cm -3 and the third concentration of hydrogen at the first location is 1×10 18 cm -3 The second concentration is 80% or more and 120% or less of the first concentration, and the third concentration is 80% or more and 120% or less of the first concentration. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] A diagram showing the crystal structure of a SiC semiconductor. [Figure 3] FIG. 2 is a diagram showing the element concentration distribution of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a schematic diagram showing the bonding state of nitrogen atoms in the semiconductor device according to the first embodiment. [Figure 5] FIG. 2 is an explanatory view of a gate insulating layer of the semiconductor device according to the first embodiment. [Figure 6] FIG. 2 is a process flow diagram of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 8] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 9] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 10] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 11] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a diagram showing the element concentration distribution of the semiconductor device according to the second embodiment. [Figure 13] FIG. 10 is a schematic diagram of a drive device according to a third embodiment. [Figure 14] FIG. 10 is a schematic diagram of a vehicle according to a fourth embodiment. [Figure 15] FIG. 10 is a schematic diagram of a vehicle according to a fifth embodiment. [Figure 16] FIG. 10 is a schematic diagram of an elevator according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - and p + , p, p - When the notation is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type may be simply referred to as p-type. Unless otherwise specified, the impurity concentration of each region is represented by the value of the impurity concentration at the center of each region.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0011] The depth of the trench, the thickness of the insulating layer, etc. can be measured on an image obtained by, for example, SIMS or a Transmission Electron Microscope (TEM).

[0012] The bonding states of silicon atoms, carbon atoms, nitrogen atoms, oxygen atoms, or hydrogen atoms in the silicon carbide layer or gate insulating layer can be identified by, for example, X-ray photoelectron spectroscopy (XPS) or Fourier transform infrared spectroscopy (FT-IR). The concentrations of various bonding states and the magnitude relationship between the concentrations can be determined by, for example, X-ray photoelectron spectroscopy or Fourier transform infrared spectroscopy.

[0013] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer, a gate electrode, a silicon oxide layer provided between the silicon carbide layer and the gate electrode and containing carbon (C), nitrogen (N), and hydrogen (H), and a silicon oxide layer provided between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration of 1×10 21 cm -3 The silicon carbide layer, the silicon oxide layer, and the region have a nitrogen concentration distribution peak in the region, and a first concentration of nitrogen at a first position 10 nm away from the peak toward the silicon oxide layer is 1×10 18 cm -3 and the second concentration of carbon at the first location is greater than or equal to 1×10 18 cm -3 and a third concentration of hydrogen at the first location is greater than or equal to 1×10 18 cm -3The second concentration is 80% or more and 120% or less of the first concentration, and the third concentration is 80% or more and 120% or less of the first concentration.

[0014] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device is a MOSFET 100. The MOSFET 100 is a double implantation MOSFET (DIMOSFET) in which a p-well and a source region are formed by ion implantation. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0015] The MOSFET 100 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, and an interface termination region 40 (region).

[0016] The silicon carbide layer 10 includes a drain region 12 , a drift region 14 , a p-well region 16 , a source region 18 , and a p-well contact region 20 .

[0017] The silicon carbide layer 10 is, for example, a single crystal of 4H—SiC. The silicon carbide layer 10 is located between a source electrode 34 and a drain electrode 36.

[0018] Figure 2 is a diagram showing the crystal structure of SiC semiconductor. A typical crystal structure of SiC semiconductor is a hexagonal system like 4H-SiC. One of the faces (top faces of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (0001) face. A face equivalent to the (0001) face is called the silicon face (Si face) and is written as the {0001} face. Silicon atoms (Si) are arranged on the top surface of the silicon face.

[0019] The other surface (top surface of the hexagonal prism) normal to the c-axis along the axial direction of the hexagonal prism is the (000-1) surface. The surface equivalent to the (000-1) surface is called the carbon surface (C-surface) and is written as the {000-1} surface. Carbon atoms (C) are arranged on the outermost surface of the carbon surface.

[0020] On the other hand, the side surfaces of the hexagonal prism (cylindrical surfaces) are m-planes, i.e., {1-100} planes, which are equivalent to the (1-100) plane. Furthermore, the planes passing through pairs of non-adjacent ridges are a-planes, i.e., {11-20} planes, which are equivalent to the (11-20) plane. Both silicon atoms (Si) and carbon atoms (C) are arranged on the outermost surfaces of the m-plane and a-plane.

[0021] Hereinafter, an example will be described in which the front surface of silicon carbide layer 10 is inclined at an angle of 0 to 8 degrees relative to the silicon surface, and the back surface is inclined at an angle of 0 to 8 degrees relative to the carbon surface. The front surface of silicon carbide layer 10 has an off angle of 0 to 8 degrees relative to the silicon surface.

[0022] The drain region 12 is n + The drain region 12 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0023] The drift region 14 is provided on the drain region 12. The drift region 14 has an n - The drift region 14 is made of SiC of n-type. The drift region 14 contains, for example, nitrogen as an n-type impurity.

[0024] The n-type impurity concentration of the drift region 14 is lower than the n-type impurity concentration of the drain region 12. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The drift region 14 is, for example, an epitaxially grown layer of SiC formed on the drain region 12 by epitaxial growth.

[0025] The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0026] The p-well region 16 is provided on a part of the surface of the drift region 14. The p-well region 16 is made of p-type SiC. The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0027] The depth of the p-well region 16 is, for example, not less than 0.4 μm and not more than 0.8 μm. The p-well region 16 functions as a channel region of the MOSFET 100.

[0028] The source region 18 is provided on a part of the surface of the p-well region 16. The source region 18 is an n + The source region 18 is made of n-type SiC. The source region 18 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 18 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 It is less than cm.

[0029] The depth of the source region 18 is shallower than the depth of the p-well region 16. The depth of the source region 18 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0030] The p-well contact region 20 is provided on a part of the surface of the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18. The p-well contact region 20 is provided on the p + It is a type of SiC.

[0031] The p-well contact region 20 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the p-well contact region 20 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0032] The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16. The depth of the p-well contact region 20 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0033] The gate insulating layer 28 is provided between the silicon carbide layer 10 and the gate electrode 30. The gate insulating layer 28 is provided between the drift region 14 and the p-well region 16 and the gate electrode 30. The gate insulating layer 28 is provided on the drift region 14 and the p-well region 16. The gate insulating layer 28 is continuously formed on the surfaces of the drift region 14 and the p-well region 16.

[0034] The gate insulating layer 28 is silicon oxide. The gate insulating layer 28 is, for example, silicon dioxide. The gate insulating layer 28 is an example of a silicon oxide layer.

[0035] The gate insulating layer 28 contains nitrogen (N), carbon (C), and hydrogen (H).

[0036] The thickness of the gate insulating layer 28 is, for example, not less than 30 nm and not more than 100 nm. The gate insulating layer 28 functions as a gate insulating layer of the MOSFET 100. The thickness of the gate insulating layer 28 is, for example, not less than 40 nm and not more than 50 nm.

[0037] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains nitrogen (N) as a terminating element that terminates dangling bonds in the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0038] The nitrogen concentration in the interface termination region 40 is 1×10 21 cm -3 That's all.

[0039] 3 is a diagram showing the element concentration distribution in the semiconductor device of the first embodiment, in gate insulating layer 28, interface termination region 40, and silicon carbide layer 10.

[0040] Figure 3 shows the concentration distributions of nitrogen (N), carbon (C), and hydrogen (H). In Figure 3, the solid line shows the concentration distribution of nitrogen, the dotted line shows the concentration distribution of carbon, and the dashed-dotted line shows the concentration distribution of hydrogen.

[0041] The nitrogen concentration distribution has a peak in the interface termination region 40. The peak nitrogen concentration is, for example, 1×10 21 cm -3 That is all. The full width at half maximum of the peak of the nitrogen concentration distribution is, for example, 1 nm or less. Nitrogen segregates at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0042] The nitrogen concentration at the peak of the nitrogen concentration distribution is, for example, 1×10 21 cm -3 Over 4×10 23 cm -3 To ensure termination, the peak nitrogen concentration must be 1×10 22 cm -3 On the other hand, if there is excess nitrogen, it will become a charge trap, so the peak nitrogen concentration should be 1×10 23 cm -3 Typically, 5.0 x 10 22 cm -3 degree, i.e., 5.0 x 10 22 cm -3 When the peak nitrogen concentration is within the above range, the capacitor formed by the gate electrode 30, the gate insulating layer 28, and the silicon carbide layer 10 exhibits good characteristics without charge traps. The surface density of nitrogen at the interface is 1×10 14 cm -2 Over 2.5 x 10 15 cm -2 It is preferable that the density is 1.4×10 or less. Typically, it is 1.4×10 15 cm -2 degree, i.e., 1.4 x 10 15 cm -2 When the surface density of nitrogen is within the above range, the capacitor formed by the gate electrode 30, the gate insulating layer 28, and the silicon carbide layer 10 exhibits good characteristics with little charge trapping.

[0043] 4A and 4B are schematic diagrams showing the bonding state of nitrogen atoms in the semiconductor device of the first embodiment, where Fig. 4A shows the case where the nitrogen atoms are tricoordinated, and Fig. 4B shows the case where the nitrogen atoms are tetracoordinated.

[0044] In the case of three-coordinated structure shown in Figure 4(a), the nitrogen atom bonds to three silicon atoms, while in the case of four-coordinated structure shown in Figure 4(b), the nitrogen atom bonds to four silicon atoms.

[0045] In interfacial termination region 40, the amount of nitrogen atoms bonded to three silicon atoms is greater than the amount of nitrogen atoms bonded to four silicon atoms. In other words, in interfacial termination region 40, the amount of nitrogen atoms with a three-coordinate bond is greater than the amount of nitrogen atoms with a four-coordinate bond.

[0046] For example, 90% or more of the nitrogen atoms present in the interface termination region 40 are tricoordinated nitrogen atoms. The concentration of tricoordinated nitrogen atoms is, for example, 1×10 22 cm -3 That's all.

[0047] The three-coordinated nitrogen atoms present in interface termination region 40 terminate dangling bonds on the surface of silicon carbide layer 10 .

[0048] The nitrogen atoms replace carbon atoms in the bilayer that constitutes the uppermost layer of the silicon carbide layer 10. Excess silicon atoms and carbon atoms are released toward the gate insulating layer 28, and the terminating element is ultimately bonded to the silicon carbide layer 10 in a three-coordinated manner. The nitrogen atoms are located at the positions of carbon atoms in the crystal structure of silicon carbide. Some of the silicon atoms on the uppermost surface are absorbed into the gate insulating layer 28, and the nitrogen atoms form a three-coordinated manner with the silicon atoms of the silicon carbide layer 10.

[0049] As shown in FIG. 3, the first concentration of nitrogen at a first position 10 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 (C1 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3The second concentration of carbon at the first position (C2 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3 The third concentration of hydrogen at the first position (C3 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0050] For example, the first concentration C1 is 1×10 19 cm -3 More than 1×10 20 cm -3 and the second concentration C2 is 1×10 19 cm -3 More than 1×10 20 cm -3 and the third concentration C3 is 1 x 10 19 cm -3 More than 1×10 20 cm -3 The following is the result.

[0051] The second concentration C2 is 80% or more and 120% or less of the first concentration C1, and the third concentration C3 is 80% or more and 120% or less of the first concentration C1.

[0052] For example, the second concentration C2 is 90% or more and 110% or less of the first concentration C1, and the third concentration C3 is 90% or more and 110% or less of the first concentration C1.

[0053] As shown in FIG. 3, for example, a fourth concentration of nitrogen (C4 in FIG. 3) at a second position 20 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 side is 1×10 18 cm -3 More than 1×10 21 cm -3 For example, the fifth concentration of carbon at the second position (C5 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3For example, the sixth concentration of hydrogen at the second position (C6 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0054] For example, the fifth concentration C5 is 80% or more and 120% or less of the fourth concentration C4, and the sixth concentration C6 is 80% or more and 120% or less of the fourth concentration C4.

[0055] For example, the fifth concentration C5 is 90% or more and 110% or less of the fourth concentration C4, and the sixth concentration C6 is 90% or more and 110% or less of the fourth concentration C4.

[0056] As shown in FIG. 3, for example, the seventh concentration of nitrogen at a third position (C7 in FIG. 3) 30 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 side is 1×10 18 cm -3 For example, the eighth concentration of carbon at the third position (C8 in FIG. 3) is less than 1×10 18 cm -3 The ninth concentration of hydrogen at the third position (C9 in FIG. 3) is less than 1×10 18 cm -3 is less than.

[0057] In SIMS measurements, the measurement limit for nitrogen, carbon, and hydrogen is approximately 1×10 18 cm -3 In the SIMS measurement, it is preferable that the measurable amount of the concentration of each element at the third position is less than the measurement limit. In this case, charge traps in the insulating film have almost no effect on the device characteristics.

[0058] For example, the eighth concentration C8 is 80% or more and 120% or less of the seventh concentration C7, and the ninth concentration C9 is 80% or more and 120% or less of the seventh concentration C7.

[0059] For example, the eighth concentration C8 is 90% or more and 110% or less of the seventh concentration C7, and the ninth concentration C9 is 90% or more and 110% or less of the seventh concentration C7.

[0060] The semiconductor device manufacturing method of the first embodiment, which will be described later, allows the concentrations of nitrogen, carbon, and hydrogen to be closely matched. If precise concentration measurement below the measurement limit of SIMS is required, it is effective to use HAXPES (Hard X-ray photoelectron spectroscopy) measurement or the like.

[0061] Fig. 5 is an explanatory diagram of the gate insulating layer of the semiconductor device of the first embodiment. Fig. 5 shows a complex composed of carbon atoms, oxygen atoms, nitrogen atoms, and hydrogen atoms contained in the gate insulating layer 28. Hereinafter, the complex composed of carbon atoms, oxygen atoms, nitrogen atoms, and hydrogen atoms shown in Fig. 5 will be referred to as a CONH complex.

[0062] As shown in Figure 5, in the CONH complex, carbon atoms, oxygen atoms, nitrogen atoms, and hydrogen atoms are in close proximity to form a complex in silicon oxide. In the CONH complex, carbon atoms and oxygen atoms, oxygen atoms and nitrogen atoms, and nitrogen atoms and hydrogen atoms are bonded, respectively.

[0063] In the CONH complex, carbon atoms and nitrogen atoms each substitute for silicon atoms in silicon dioxide. In other words, in the CONH complex, carbon atoms and nitrogen atoms each reside at the silicon sites of silicon dioxide. In the CONH complex, an oxygen atom resides between the carbon atoms and nitrogen atoms. The carbon atoms and oxygen atoms, and the nitrogen atoms and oxygen atoms, are each bonded by a single bond. The carbon atoms that make up the CONH complex are four-coordinated.

[0064] For example, most of the carbon atoms, nitrogen atoms, and hydrogen atoms present in a region 10 nm or more away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 constitute the CONH complex. Therefore, for example, as shown in FIG. 3, the distribution of carbon atoms, the distribution of nitrogen atoms, and the distribution of hydrogen atoms overlap in a region 10 nm or more away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28.

[0065] For example, the amount of CONH complexes decreases with distance from the peak of the nitrogen concentration distribution in the gate insulating layer 28. Therefore, as shown in FIG. 3, the concentrations of carbon, nitrogen, and hydrogen decrease with distance from the peak of the nitrogen concentration distribution in the gate insulating layer 28.

[0066] Furthermore, since most of the hydrogen atoms in the gate insulating layer 28 form CONH complexes, the amount of hydrogen atoms bonded to nitrogen atoms in the gate insulating layer 28 is greater than the amount of hydrogen atoms bonded to silicon atoms.

[0067] The gate electrode 30 is provided on the gate insulating layer 28. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the silicon carbide layer 10. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the drift region 14. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the p-well region 16.

[0068] The gate electrode 30 is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0069] The interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0070] The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16.

[0071] The source electrode 34 is formed, for example, by laminating a Ni (nickel) barrier metal layer and an aluminum metal layer on the barrier metal layer. The nickel barrier metal layer and the silicon carbide layer may react to form nickel silicide (NiSi, NiSi, etc.). The nickel barrier metal layer and the aluminum metal layer may react to form an alloy.

[0072] The drain electrode 36 is provided on the opposite side of the silicon carbide layer 10 to the source electrode 34, i.e., on the back surface side. The drain electrode 36 is made of, for example, nickel. Nickel may react with the drain region 12 to form nickel silicide (NiSi, NiSi, etc.).

[0073] In the first embodiment, the n-type impurity is, for example, nitrogen or phosphorus. Arsenic (As) or antimony (Sb) can also be used as the n-type impurity.

[0074] In the first embodiment, the p-type impurity is, for example, aluminum. Boron (B), gallium (Ga), and indium (In) can also be used as the p-type impurity.

[0075] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0076] The method for manufacturing a semiconductor device of the first embodiment includes forming a silicon oxide film on the surface of a silicon carbide layer, performing a first heat treatment at a temperature of 1100°C or more and 1300°C or less in an atmosphere containing nitrogen oxide gas after the formation of the silicon oxide film, performing a second heat treatment at a temperature of 100°C or more and 600°C or less in an atmosphere containing oxygen gas after the first heat treatment, performing a third heat treatment at a temperature of 100°C or more and 600°C or less in an atmosphere containing hydrogen gas after the second heat treatment, and forming a gate electrode on the silicon oxide film after the third heat treatment.

[0077] FIG. 6 is a process flow diagram of the method for manufacturing the semiconductor device of the first embodiment.

[0078] As shown in FIG. 6, the method for manufacturing the semiconductor device of the first embodiment includes silicon carbide layer preparation (step S100), p-type impurity ion implantation (step S101), n-type impurity ion implantation (step S102), p-type impurity ion implantation (step S103), silicon oxide film formation (step S104), first heat treatment (step S105), second heat treatment (step S106), third heat treatment (step S107), fourth heat treatment (step S108), gate electrode formation (step S109), interlayer insulating film formation (step S110), source electrode formation (step S111), and drain electrode formation (step S112).

[0079] In step S100, a silicon carbide layer 10 is prepared. The silicon carbide layer 10 has an n + type drain region 12 and n - The semiconductor device includes a drift region 14. The drift region 14 is formed on the drain region 12 by, for example, epitaxial growth.

[0080] The drain region 12 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0081] The drift region 14 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0082] In step S101, a first mask material is formed by patterning using photolithography and etching. Then, using the first mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14. The ion implantation forms a p-well region 16.

[0083] In step S102, first, a second mask material is formed by patterning using photolithography and etching. Then, using the second mask material as an ion implantation mask, phosphorus, which is an n-type impurity, is ion-implanted into the drift region 14 to form the source region 18.

[0084] In step S103, a third mask material is formed by patterning using photolithography and etching. Using the third mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14 to form the p-well contact region 20.

[0085] In step S104, a silicon oxide film is formed on the silicon carbide layer 10. The silicon oxide film will eventually become the gate insulating layer .

[0086] The silicon oxide film is formed by, for example, vapor phase growth. The silicon oxide film is formed by, for example, a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method). The silicon oxide film is a deposited film. The thickness of the silicon oxide film is, for example, 30 nm or more and 100 nm or less. The thickness of the silicon oxide film is, for example, 40 nm or more and 50 nm or less.

[0087] The silicon oxide film is formed by a CVD method using, for example, tetraethyl orthosilicate (TEOS) as a source gas, or by a CVD method using, for example, dichlorosilane gas (SiH2Cl2) and dinitrogen monoxide gas (N2O) as source gas.

[0088] In step S105, a first heat treatment is performed. The first heat treatment is performed in an atmosphere containing nitrogen oxide gas (NOx). The nitrogen oxide gas is, for example, nitric oxide gas (NO). The nitrogen oxide gas is, for example, dinitrogen monoxide gas (NO).

[0089] For example, nitrogen oxide gas (NOx) is supplied to a reactor in which the silicon carbide layer 10 is placed, and heat treatment is performed.

[0090] The temperature of the first heat treatment is 1100°C or higher and 1300°C or lower.

[0091] The first heat treatment forms interface termination region 40 at the interface between silicon carbide layer 10 and the silicon oxide film.

[0092] The first heat treatment also functions as a densifying anneal for the silicon oxide film, and the silicon oxide film becomes a high-density film through the first heat treatment.

[0093] The first heat treatment oxidizes the surface of silicon carbide layer 10, and excess carbon diffuses into the silicon oxide film.

[0094] In step S106, a second heat treatment is performed in an atmosphere containing oxygen gas (O2), which is diluted with, for example, nitrogen gas (N2) or argon gas (Ar).

[0095] For example, oxygen gas (O2) diluted with nitrogen gas (N2) is supplied to a reactor containing the silicon carbide layer 10 to perform the heat treatment.

[0096] The temperature of the second heat treatment is 100°C or higher and 600°C or lower.

[0097] The second heat treatment fills oxygen vacancies in the silicon oxide film, forming a silicon oxide film with reduced oxygen vacancies.

[0098] In step S107, a third heat treatment is performed in an atmosphere containing hydrogen gas (H2). The hydrogen gas (H2) may be diluted with, for example, nitrogen gas (N2) or argon gas (Ar).

[0099] For example, hydrogen gas (H 2 ) diluted with nitrogen gas (N 2 ) is supplied to a reactor containing the silicon carbide layer 10 to perform the heat treatment.

[0100] The partial pressure of hydrogen gas (H2) in the atmosphere for the third heat treatment is, for example, 5% or more and 20% or less.

[0101] The temperature of the third heat treatment is 100° C. or higher and 600° C. or lower. The temperature of the third heat treatment is, for example, equal to or lower than the temperature of the second heat treatment.

[0102] The third heat treatment forms a CONH complex in the silicon oxide film.

[0103] In step S108, a fourth heat treatment is performed in an atmosphere having a lower partial pressure of hydrogen gas than the atmosphere of the third heat treatment. The partial pressure of hydrogen gas in the fourth heat treatment is, for example, less than 5%.

[0104] The fourth heat treatment is performed, for example, in an atmosphere containing nitrogen gas (N2). The fourth heat treatment is performed, for example, in a nitrogen gas atmosphere.

[0105] The fourth heat treatment is performed, for example, in an atmosphere containing argon gas (Ar).The fourth heat treatment is performed, for example, in an argon gas atmosphere.

[0106] For example, nitrogen gas (N2) is supplied to a reactor containing the silicon carbide layer 10 to perform the heat treatment.

[0107] The temperature of the fourth heat treatment is 100° C. or higher and 600° C. or lower. The temperature of the fourth heat treatment is, for example, lower than the temperature of the second heat treatment or lower than the temperature of the third heat treatment.

[0108] The fourth heat treatment reduces interstitial hydrogen in the silicon oxide film.

[0109] In step S109, the gate electrode 30 is formed on the gate insulating layer 28. The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0110] In step S110, the interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0111] In step S111, the source electrode 34 is formed. The source electrode 34 is formed on the source region 18 and the p-well contact region 20. The source electrode 34 is formed by, for example, sputtering nickel (Ni) and aluminum (Al).

[0112] In step S112, the drain electrode 36 is formed. The drain electrode 36 is formed on the back surface side of the silicon carbide layer 10. The drain electrode 36 is formed by, for example, sputtering nickel.

[0113] By the above manufacturing method, the MOSFET 100 shown in FIG. 1 is formed.

[0114] Next, the functions and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0115] When forming a MOSFET using silicon carbide, there is a problem of reduced carrier mobility. One factor that reduces carrier mobility is thought to be the intersurface state between the silicon carbide layer and the gate insulating layer. The interface state is thought to be caused by dangling bonds present on the surface of the silicon carbide layer.

[0116] The MOSFET 100 of the first embodiment includes an interface termination region 40 in which nitrogen is segregated between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 reduces dangling bonds, thereby realizing a MOSFET 100 in which a decrease in carrier mobility is suppressed.

[0117] Furthermore, when silicon carbide is used to form MOSFETs, problems such as reduced carrier mobility and threshold voltage fluctuations occur. Other problems include increased leakage current in the gate insulating layer and reduced reliability of the gate insulating layer. One of the causes of these problems is thought to be harmful defects present in the gate insulating layer.

[0118] The harmful defects present in the gate insulating layer are thought to be, for example, oxygen vacancies in silicon oxide and defects caused by carbon or nitrogen contained in silicon oxide. The defects present in the gate insulating layer are thought to be a cause of the above problems by forming trap levels in the gate insulating layer.

[0119] The MOSFET 100 of the first embodiment has a reduced amount of harmful defects in the gate insulating layer 28. This reduces the carrier mobility, the threshold voltage fluctuation, the increase in leakage current in the gate insulating layer, and the degradation of the reliability of the gate insulating layer, which are caused by harmful defects. This will be described in detail below.

[0120] 7 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. Fig. 7 shows an oxygen vacancy in silicon oxide. The oxygen vacancy in silicon oxide is accompanied by a dangling bond of a silicon atom.

[0121] Dangling bonds of silicon atoms form trap states in the gate insulating layer. For example, charge trapping in the trap states can reduce carrier mobility, shift the threshold voltage, or increase leakage current in the gate insulating layer. Therefore, it is desirable to reduce the amount of oxygen vacancies in the gate insulating layer.

[0122] 8 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. Fig. 8 shows a structure in which a hydrogen atom is bonded to a dangling bond of a silicon atom generated by an oxygen vacancy in silicon oxide. Hereinafter, the structure in which a hydrogen atom is bonded to a dangling bond of a silicon atom generated by an oxygen vacancy is referred to as a SiH complex.

[0123] For example, heat treatment of silicon oxide in a hydrogen-containing atmosphere forms SiH complexes, eliminating dangling silicon bonds. However, there is a high possibility that hydrogen atoms may be removed from the SiH complexes in the gate insulating layer during MOSFET operation, causing dangling silicon bonds to be reformed. Therefore, it is desirable to minimize the amount of oxygen vacancies in the gate insulating layer of a MOSFET.

[0124] The amount of oxygen vacancies in silicon oxide increases with increasing temperature of the heat treatment applied to silicon oxide, because the entropy increases with increasing temperature of the heat treatment.

[0125] In the method for manufacturing a semiconductor device according to the first embodiment, interface termination region 40 is formed at the interface between silicon carbide layer 10 and a silicon oxide film by a first heat treatment performed in an atmosphere containing nitrogen oxide gas (NOx). The first heat treatment is performed at a high temperature of 1100°C or higher and 1300°C or lower. Therefore, an increase in entropy causes a large number of oxygen vacancies to be formed in the silicon oxide film.

[0126] In the method for manufacturing a semiconductor device according to the first embodiment, a second heat treatment is performed after the first heat treatment. The second heat treatment is performed in an atmosphere containing oxygen gas (O2). The second heat treatment fills oxygen vacancies, reducing the amount of oxygen vacancies in the silicon oxide film. The reduction in the amount of oxygen vacancies in the silicon oxide film prevents the formation of SiH complexes, even if a heat treatment is performed in an atmosphere containing hydrogen after the second heat treatment.

[0127] The second heat treatment is performed at a temperature of 100° C. to 600° C. The second heat treatment is performed at 600° C. or less, which suppresses oxidation of the surface of silicon carbide layer 10. This suppresses new diffusion of carbon into the silicon oxide film.

[0128] The temperature of the second heat treatment is preferably 200°C or higher and 500°C or lower, and more preferably 300°C or higher and 400°C or lower. When the above lower limit is satisfied, the amount of oxygen vacancies decreases. When the above upper limit is satisfied, oxidation of the surface of the silicon carbide layer 10 can be suppressed.

[0129] 9 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. FIG. 9 shows defects caused by carbon and nitrogen in silicon oxide. Carbon atoms, oxygen atoms, and nitrogen atoms are close to each other in silicon oxide to form a complex. Hereinafter, this complex will be referred to as a CON complex.

[0130] In the CON complex, carbon and nitrogen atoms each substitute for a silicon atom in silicon dioxide. In other words, in the CON complex, carbon and nitrogen atoms each exist at the silicon site of silicon dioxide. An oxygen atom exists between the carbon and nitrogen atoms. The nitrogen and oxygen atoms are bonded by a double bond. The carbon and nitrogen atoms each have a dangling bond. The carbon atoms that make up the CON complex are three-coordinated.

[0131] 10 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and is a band diagram of silicon dioxide.

[0132] As shown in Figure 10, CON complexes form trap levels in the energy bands of silicon dioxide. For example, CON complexes release electrons and become fixed positive charges. This can lead to, for example, a decrease in the threshold voltage of a MOSFET. Furthermore, charges trapped in trap levels during MOSFET operation can cause fluctuations in the MOSFET's threshold voltage. Furthermore, the presence of trap levels can lead to, for example, a decrease in carrier mobility and an increase in leakage current in the gate insulating layer. Therefore, it is desirable to reduce the amount of CON complexes, which are harmful defects in the gate insulating layer.

[0133] In the method for manufacturing a semiconductor device according to the first embodiment, the surface of the silicon carbide layer 10 is oxidized by the first heat treatment performed in an atmosphere containing nitrogen oxide gas (NOx), and carbon is released into the silicon oxide film. The carbon released into the silicon oxide film combines with nitrogen in the nitrogen oxide gas to form a CON complex.

[0134] In the first heat treatment (nitrogen oxide heat treatment), nitrogen is introduced into the silicon oxide film, where it interacts with excess carbon to form and stabilize a CON complex. At this time, both carbon and nitrogen enter the silicon sites in the silicon oxide film. Once the CON complex is formed, the carbon and nitrogen are in the silicon sites and cannot be removed by the second heat treatment (treatment involving oxygen gas).

[0135] These CON complexes trap charges, which leads to a degradation of the mobility at the MOS interface and a decrease in the reliability of the insulating film. To introduce a sufficient amount of nitrogen into the interface, a first heat treatment is required, which is performed at a high temperature and for a long time. However, when the first heat treatment is performed at a high temperature and for a long time, a large amount of carbon is released into the silicon oxide film, which generates a large amount of CON complexes in the insulating film. This results in a degradation of the mobility at the MOS interface and a decrease in the reliability of the insulating film.

[0136] On the other hand, if only nitrogen is present in the silicon oxide film and no carbon is present, the nitrogen will occupy oxygen sites in the silicon oxide film. Therefore, it can be removed from the silicon oxide film by oxidation using the first heat treatment (nitrogen oxide heat treatment) or the second heat treatment (treatment containing oxygen gas). This condition also holds true when the amount of nitrogen is greater than the amount of carbon. In other words, a CON structure is formed with the same amount of nitrogen as the amount of carbon, and the amount of nitrogen in excess of the amount of carbon occupies oxygen sites in the silicon oxide film. Therefore, the amount of nitrogen that has entered in excess of the amount of carbon can be removed from the insulating film by oxidation using the first heat treatment (nitrogen oxide heat treatment) or the second heat treatment (treatment containing oxygen gas).

[0137] Furthermore, if only carbon is present and no nitrogen is present, the carbon will occupy oxygen sites in the silicon oxide film. Therefore, the carbon can be removed from the silicon oxide film by oxidation through the second heat treatment (treatment containing oxygen gas). This condition also holds true when the amount of carbon is greater than the amount of nitrogen. In other words, a CON structure is formed with the same amount of carbon as the amount of nitrogen, and the amount of carbon in excess of the nitrogen occupies oxygen sites in the silicon oxide film. Therefore, the amount of carbon that has entered in excess of the amount of nitrogen can be removed from the insulating film by oxidation through the second heat treatment (treatment containing oxygen gas).

[0138] That is, the first heat treatment oxidizes the surface of the silicon carbide layer 10, causing excess carbon to diffuse into the silicon oxide film and interact with the nitrogen introduced into the silicon oxide film by the first heat treatment to form a CON complex in the silicon oxide film. If excess nitrogen or carbon exists at oxygen positions in the silicon oxide film, it is removed from the silicon oxide film by the second heat treatment. Thus, the CON complex is distributed in a gradually decreasing amount from the interface between the silicon carbide layer and the insulating film toward the interface between the insulating film and the electrode.

[0139] In the method for manufacturing a semiconductor device according to the first embodiment, a third heat treatment is performed after the first and second heat treatments. The third heat treatment is performed in an atmosphere containing hydrogen gas (H). The third heat treatment causes hydrogen atoms derived from the hydrogen gas to bond to nitrogen atoms in the CON complex, converting the CON complex into a CONH complex as shown in FIG. 5.

[0140] As shown in Figure 10, the CON complex and interstitial hydrogen each form a trap level in the energy band of silicon dioxide. However, the inventors' investigations have revealed that when interstitial hydrogen binds to the CON complex to form a CONH complex, the trap level in the energy band disappears.

[0141] The CONH complex in silicon oxide is energetically more stable than the combination of the CON complex and interstitial hydrogen. The energy difference between the CONH complex and the combination of the CON complex and interstitial hydrogen is 12.0 eV, which is extremely large.

[0142] The inventors' investigations have revealed that among the structures that carbon atoms, oxygen atoms, nitrogen atoms, and hydrogen atoms can assume in close proximity in silicon oxide, the CONH complex is the most stable. Therefore, once the CONH complex is formed in the gate insulating layer 28, it is unlikely to decompose, even during operation of the MOSFET, for example.

[0143] In the method for manufacturing a semiconductor device according to the first embodiment, the CON complex in the gate insulating layer 28 is converted into a CONH complex by the third heat treatment, and the amount of the CON complex in the gate insulating layer 28 can be reduced.

[0144] The temperature of the third heat treatment is 100°C or higher and 600°C or lower. The temperature of the third heat treatment is preferably 200°C or higher and 500°C or lower, and more preferably 300°C or higher and 400°C or lower. By satisfying the above lower limit, the conversion of the CON complex to the CONH complex is promoted. By satisfying the above lower limit, an increase in entropy can be suppressed, thereby suppressing an increase in oxygen vacancies in the gate insulating layer 28.

[0145] From the viewpoint of suppressing an increase in oxygen vacancies in the gate insulating layer 28, the temperature of the third heat treatment is preferably equal to or lower than the temperature of the second heat treatment.

[0146] The third heat treatment must be performed after the second heat treatment, or in other words, the second heat treatment must be performed before the third heat treatment.

[0147] If the third heat treatment in an atmosphere containing hydrogen gas (H2) were performed before the second heat treatment, the oxygen vacancies in the gate insulating layer 28 would be converted to SiH complexes. Even if the second heat treatment in an atmosphere containing oxygen gas (O2) were performed after the conversion to SiH complexes, the oxygen vacancies would not be filled. Therefore, the SiH complexes would remain in the gate insulating layer even after the MOSFET is fabricated. If the SiH complexes remain, there is a high possibility that hydrogen atoms will be detached from the SiH complexes in the gate insulating layer during MOSFET operation, and dangling bonds of silicon atoms will be reformed, as described above.

[0148] As shown in Figure 10, interstitial hydrogen forms trap levels in the energy band of silicon dioxide. Therefore, if interstitial hydrogen remains in the gate insulating layer 28 after the third heat treatment performed in an atmosphere containing hydrogen gas (H), for example, charges are trapped in the trap levels, resulting in a decrease in carrier mobility, a shift in threshold voltage, or an increase in leakage current in the gate insulating layer. Therefore, it is desirable to reduce the amount of interstitial hydrogen in the gate insulating layer.

[0149] In the method for manufacturing a semiconductor device according to the first embodiment, the fourth heat treatment is performed in an atmosphere having a lower partial pressure of hydrogen gas than the partial pressure of the atmosphere for the third heat treatment. The fourth heat treatment causes outward diffusion of interstitial hydrogen in the gate insulating layer 28, thereby reducing the amount of interstitial hydrogen in the gate insulating layer 28.

[0150] The partial pressure of hydrogen gas in the fourth heat treatment is preferably less than 5% from the viewpoint of promoting outward diffusion of interstitial hydrogen in the gate insulating layer 28. From the viewpoint of promoting outward diffusion of interstitial hydrogen in the gate insulating layer 28, the fourth heat treatment is preferably performed in a nitrogen gas atmosphere or an argon gas atmosphere.

[0151] From the viewpoint of suppressing an increase in oxygen vacancies in the gate insulating layer 28, the temperature of the fourth heat treatment is preferably equal to or lower than the temperature of the second heat treatment and equal to or lower than the temperature of the third heat treatment.

[0152] It should be noted that, for example, if there is little interstitial hydrogen in the gate insulating layer 28 after the third heat treatment, it is possible to omit the fourth heat treatment.

[0153] The method for manufacturing a semiconductor device according to the first embodiment makes it possible to reduce harmful defects, namely, oxygen vacancies, CON complexes, and interstitial hydrogen, that cause a decrease in carrier mobility and a shift in threshold voltage of the MOSFET in the gate insulating layer 28. Therefore, the amount of harmful defects in the gate insulating layer 28 of the MOSFET 100 can be reduced, and the decrease in carrier mobility and the shift in threshold voltage can be suppressed.

[0154] In the MOSFET 100 of the first embodiment, the gate insulating layer 28 is a silicon oxide layer containing carbon (C), nitrogen (N), and hydrogen (H).

[0155] As shown in FIG. 3, the MOSFET 100 of the first embodiment has a first concentration of nitrogen (C1 in FIG. 3) of 1×10 at a first position 10 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28. 18 cm -3 More than 1×10 21 cm-3 The second concentration of carbon at the first position (C2 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3 The third concentration of hydrogen at the first position (C3 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0156] The second concentration C2 is 80% or more and 120% or less of the first concentration C1, and the third concentration C3 is 80% or more and 120% or less of the first concentration C1.

[0157] As shown in FIG. 3, for example, a fourth concentration of nitrogen (C4 in FIG. 3) at a second position 20 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 side is 1×10 18 cm -3 More than 1×10 21 cm -3 For example, the fifth concentration of carbon at the second position (C5 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3 For example, the sixth concentration of hydrogen at the second position (C6 in FIG. 3) is 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0158] For example, the fifth concentration C5 is 80% or more and 120% or less of the fourth concentration C4, and the sixth concentration C6 is 80% or more and 120% or less of the fourth concentration C4.

[0159] As shown in FIG. 3, for example, the seventh concentration of nitrogen at a third position (C7 in FIG. 3) 30 nm away from the peak of the nitrogen concentration distribution toward the gate insulating layer 28 side is 1×10 18 cm -3For example, the eighth concentration of carbon at the third position (C8 in FIG. 3) is less than 1×10 18 cm -3 The ninth concentration of hydrogen at the third position (C9 in FIG. 3) is less than 1×10 18 cm -3 is less than.

[0160] For example, the eighth concentration C8 is 80% or more and 120% or less of the seventh concentration C7, and the ninth concentration C9 is 80% or more and 120% or less of the seventh concentration C7.

[0161] In the MOSFET 100 of the first embodiment, most of the carbon atoms, nitrogen atoms, and hydrogen atoms contained in the gate insulating layer 28 are fixed as CONH complexes. Therefore, as shown in FIG. 3 , the distribution of carbon atoms, the distribution of nitrogen atoms, and the distribution of hydrogen atoms in the gate insulating layer 28 overlap.

[0162] The carbon in gate insulating layer 28 is carbon that is released and diffused from the surface of silicon carbide layer 10 by the first heat treatment. Therefore, for example, the carbon concentration decreases in gate insulating layer 28 with increasing distance from silicon carbide layer 10, as shown in FIG.

[0163] In the MOSFET 100 of the first embodiment, most of the carbon atoms, nitrogen atoms, and hydrogen atoms contained in the gate insulating layer 28 are fixed as CON-H complexes, which are defects that are harmless to the characteristics of the MOSFET 100. In other words, the gate insulating layer 28 of the MOSFET 100 contains extremely small amounts of oxygen vacancies, CON bonds, and interstitial hydrogen, which are defects that are harmful to the characteristics of the MOSFET 100. In the MOSFET 100, the reduction in the amount of harmful defects in the gate insulating layer 28 can suppress a decrease in carrier mobility and a variation in threshold voltage.

[0164] As described above, according to the first embodiment, a semiconductor device and a method for manufacturing the semiconductor device in which the amount of harmful defects in the gate insulating layer is reduced are realized.

[0165] (Second embodiment) The semiconductor device of the second embodiment differs from the first embodiment in that it is a trench-gate MOSFET having a gate electrode in a trench. It also differs from the first embodiment in that the surface of the silicon carbide layer facing the gate electrode is a plane inclined at an angle of 0 to 8 degrees with respect to the {1-100} plane, or a plane inclined at an angle of 0 to 8 degrees with respect to the {11-20} plane. Hereinafter, some of the details overlapping with those of the first embodiment will be omitted.

[0166] 11 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a MOSFET 200. The MOSFET 200 is a trench-gate MOSFET having a gate electrode in a trench. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0167] The MOSFET 200 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, an interface termination region 40 (region), and a trench 50.

[0168] The silicon carbide layer 10 includes a drain region 12 , a drift region 14 , a p-well region 16 , a source region 18 , and a p-well contact region 20 .

[0169] The trench 50 penetrates the source region 18 and the p-well region 16 and reaches the drift region 14. The bottom surface of the trench 50 is located in the drift region 14.

[0170] A gate insulating layer 28 and a gate electrode 30 are provided in the trench 50. The side surface of the trench 50 is, for example, a plane having an off angle of 0 to 8 degrees with respect to the m-plane, or a plane having an off angle of 0 to 8 degrees with respect to the a-plane.

[0171] On the side surface of trench 50, the surface of silicon carbide layer 10 facing gate electrode 30 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the {1-100} plane, or a surface inclined at an angle of 0 to 8 degrees relative to the {11-20} plane.

[0172] 12 is a diagram showing the element concentration distribution in the semiconductor device of the second embodiment, in gate insulating layer 28 on the side surface of trench 50, interface termination region 40, and silicon carbide layer 10.

[0173] Fig. 12 shows the concentration distributions of nitrogen (N), carbon (C), and hydrogen (H). In Fig. 12, the solid line shows the concentration distribution of nitrogen, the dotted line shows the concentration distribution of carbon, and the dashed-dotted line shows the concentration distribution of hydrogen.

[0174] The nitrogen concentration distribution has a peak in the interface termination region 40. The peak nitrogen concentration is, for example, 1×10 21 Over 4×10 23 cm -3 The full width at half maximum of the peak of the nitrogen concentration distribution is, for example, 1 nm or less. Nitrogen segregates at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0175] The hydrogen concentration distribution has a peak in the interface termination region 40. The peak hydrogen concentration is, for example, 1×10 21 cm -3 More than 1×10 23 cm -3 The full width at half maximum of the hydrogen concentration distribution peak is, for example, 1 nm or less. Hydrogen segregates at the interface between silicon carbide layer 10 and gate insulating layer 28. Note that hydrogen atoms present in interface termination region 40 are bonded to carbon atoms.

[0176] According to the MOSFET 200 of the second embodiment, similarly to the MOSFET 100 of the first embodiment, the amount of harmful defects in the gate insulating layer 28 is reduced, and a decrease in carrier mobility and a variation in threshold voltage can be suppressed.

[0177] When forming a MOSFET with a trench gate structure using silicon carbide, there is a problem of threshold voltage fluctuation due to AC stress. One factor is thought to be the interface states between the silicon carbide layer and the gate insulating layer. The interface states are thought to be generated, in particular, by dangling carbon bonds present on the inner surface of the trench. It is thought that applying AC stress traps charges injected into the interface between the silicon carbide layer and the gate insulating layer, resulting in threshold voltage fluctuation.

[0178] For example, when the inner surface of the trench is an m-plane or an a-plane, dangling bonds of carbon atoms exist on the outermost surface, unlike an Si-plane.

[0179] The method for manufacturing the MOSFET 200 of the second embodiment includes a third heat treatment performed in an atmosphere containing hydrogen gas (H2). By performing the third heat treatment, dangling bonds of carbon atoms are terminated with hydrogen atoms. In the MOSFET 200 of the second embodiment, the dangling bonds of carbon atoms are terminated with hydrogen atoms, and thus a peak of the hydrogen concentration distribution exists in the interfacial termination region 40. In the MOSFET 200, the dangling bonds of carbon atoms on the surface of the silicon carbide layer are reduced, and fluctuations in the threshold voltage of the MOSFET 200 due to AC stress can be suppressed.

[0180] As described above, according to the second embodiment, a semiconductor device and a method for manufacturing the semiconductor device in which the amount of harmful defects in the gate insulating layer is reduced are realized.

[0181] (Third embodiment) The inverter circuit and the drive device of the third embodiment are an inverter circuit and a drive device that include the semiconductor device of the first embodiment.

[0182] 13 is a schematic diagram of a driving device according to the third embodiment. The driving device 700 includes a motor 140 and an inverter circuit 150.

[0183] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140.

[0184] According to the third embodiment, the inverter circuit 150 and the driving device 700 are provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the inverter circuit 150 and the driving device 700.

[0185] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0186] 14 is a schematic diagram of a vehicle according to the fourth embodiment. The vehicle 800 according to the fourth embodiment is a railcar. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0187] The inverter circuit 150 is composed of three semiconductor modules that use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 800 are rotated by the motor 140.

[0188] According to the fourth embodiment, the vehicle 800 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 800.

[0189] (Fifth embodiment) The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0190] 15 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 900 according to the fifth embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0191] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0192] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 900.

[0193] According to the fifth embodiment, the vehicle 900 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 900.

[0194] (Sixth embodiment) The elevator of the sixth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0195] 16 is a schematic diagram of an elevator according to a sixth embodiment. The elevator 1000 according to the sixth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0196] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0197] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoisting machine 616, causing the car 610 to rise and fall.

[0198] According to the sixth embodiment, the elevator 1000 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the elevator 1000.

[0199] In the above, the first and second embodiments have been described using an example in which the silicon carbide crystal structure is 4H—SiC, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0200] The oxidation rate of a silicon carbide layer depends on the plane orientation. In the first or second embodiment, it is preferable to optimize the temperature of the first heat treatment depending on the plane orientation.

[0201] The present invention can also be applied to an n-channel IGBT (Insulated Gate Bipolar Transistor).

[0202] Furthermore, the present invention is not limited to an n-channel type, but can also be applied to a p-channel type MOSFET or IGBT.

[0203] Furthermore, in the third to sixth embodiments, the semiconductor device of the present invention has been described as being applied to vehicles and elevators, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0204] Furthermore, in the third to sixth embodiments, the semiconductor device of the first embodiment is applied, but it is also possible to apply, for example, the semiconductor device of the second embodiment.

[0205] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0206] 10 Silicon carbide layer 28 Gate insulating layer (silicon oxide layer) 30 gate electrode 40 Interface termination area (area) 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) 700 Drive Unit 800 vehicles 900 vehicles 1000 elevators C1 First concentration C2 Second concentration C3 Third concentration C4 Fourth concentration C5 Fifth concentration C6 6th concentration C7 Seventh concentration C8 8th concentration C9 9th concentration

Claims

1. a silicon carbide layer; a gate electrode; a silicon oxide layer provided between the silicon carbide layer and the gate electrode and containing carbon (C), nitrogen (N), and hydrogen (H); a silicon carbide layer and a silicon oxide layer, the silicon carbide layer and the silicon oxide layer being provided therebetween, and the concentration of nitrogen is 1×10 ２１ cm －３ The above areas, a nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has a peak in the region; The first concentration of nitrogen at a first position 10 nm away from the peak toward the silicon oxide layer is 1×10 １８ cm －３ That's all, The second concentration of carbon at the first location is 1×10 １８ cm －３ That's all, The third concentration of hydrogen at the first location is 1×10 １８ cm －３ That's all, the second concentration is 80% or more and 120% or less of the first concentration, The third concentration is 80% or more and 120% or less of the first concentration.

2. 2. The semiconductor device according to claim 1, wherein in said silicon oxide layer, hydrogen atoms are bonded to nitrogen atoms.

3. 2. The semiconductor device according to claim 1, wherein the number of hydrogen atoms bonded to nitrogen atoms in said silicon oxide layer is greater than the number of hydrogen atoms bonded to silicon atoms.

4. The first concentration is 1×10 １９ cm －３ That's all, The second concentration is 1×10 １９ cm －３ That's all, The third concentration is 1×10 １９ cm －３ 2. The semiconductor device according to claim 1, wherein:

5. A fourth concentration of nitrogen at a second position 20 nm away from the peak toward the silicon oxide layer is 1×10 １８ cm －３ That's all, a fifth concentration of carbon at the second location of 1×10 １８ cm －３ That's all, The sixth concentration of hydrogen at the second location is 1×10 １８ cm －３ That's all, the fifth concentration is 80% or more and 120% or less of the fourth concentration, 2. The semiconductor device according to claim 1, wherein said sixth concentration is 80% or more and 120% or less of said fourth concentration.

6. A seventh concentration of nitrogen at a third position 30 nm away from the peak toward the silicon oxide layer is 1×10 １８ cm －３ is less than an eighth concentration of carbon at the third location of 1×10 １８ cm －３ is less than The ninth concentration of hydrogen at the third location is 1×10 １８ cm －３ The semiconductor device according to claim 1 , wherein the thickness is less than 100 nm.

7. 2. The semiconductor device according to claim 1, wherein a surface of the silicon carbide layer facing the gate electrode is a surface inclined at an angle of 0 to 8 degrees with respect to a {1-100} plane, or a surface inclined at an angle of 0 to 8 degrees with respect to a {11-20} plane.

8. The concentration of hydrogen in the region is 1×10 ２１ cm －３ 8. The semiconductor device according to claim 7, wherein:

9. An inverter circuit comprising the semiconductor device according to claim 1.

10. A driving device comprising the semiconductor device according to claim 1.

11. A vehicle comprising the semiconductor device according to claim 1.

12. An elevator comprising the semiconductor device according to claim 1.

13. forming a silicon oxide film on the surface of the silicon carbide layer; After forming the silicon oxide film, a first heat treatment is performed at a temperature of 1100° C. or more and 1300° C. or less in an atmosphere containing nitrogen oxide gas; After the first heat treatment, a second heat treatment is performed in an atmosphere containing oxygen gas at a temperature of 100° C. or more and 600° C. or less; After the second heat treatment, a third heat treatment is performed in an atmosphere containing hydrogen gas at a temperature of 100° C. or more and 600° C. or less; a gate electrode formed on the silicon oxide film after the third heat treatment;

14. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the atmosphere for the third heat treatment contains nitrogen gas.

15. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the temperature of the third heat treatment is equal to or lower than the temperature of the second heat treatment.

16. 14. The method for manufacturing a semiconductor device according to claim 13, further comprising the steps of: after the third heat treatment, and before forming the gate electrode, performing a fourth heat treatment at a temperature of 100° C. or more and 600° C. or less in an atmosphere having a lower partial pressure of hydrogen gas than the atmosphere in the third heat treatment.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the temperature of the fourth heat treatment is equal to or lower than the temperature of the third heat treatment.

18. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the silicon oxide film is formed by vapor phase growth.

19. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the silicon oxide film has a thickness of 30 nm or more and 100 nm or less.

20. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the surface is a surface inclined at an angle of 0 to 8 degrees relative to the {1-100} plane, or a surface inclined at an angle of 0 to 8 degrees relative to the {11-20} plane.

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