Semiconductor device

Abstract

To provide a novel and nonvolatile latch circuit and a semiconductor device using the latch circuit.SOLUTION: A semiconductor device comprises: a latch part having a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element; and a data holding part for holding data, and the latch part and the data holding part compose a nonvolatile latch circuit. In the data holding part, a transistor which uses an oxide semiconductor as a semiconductor material for composing a channel formation region is used as a switching element. The semiconductor device further comprises an inverter electrically connected to a source electrode or a drain electrode of the transistor. By using the above-described transistor, data held by the latch part can be written in gate capacitance of the inverter or in separately prepared capacitance.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention is a nonvolatile logic circuit and a logic circuit that retains its stored logic state even when the power is turned off. In particular, the present invention relates to a nonvolatile latch circuit and a semiconductor device using the same. Relating to the body apparatus. [Background technology]

[0002] Non-volatile logic is a logic circuit that incorporates the property of "non-volatility," meaning that memory does not disappear even when the power is turned off. For example, a nonvolatile integrated circuit using a ferroelectric element has been proposed. A latch circuit has been proposed as a nonvolatile logic (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2003 / 044953 Summary of the Invention [Problem to be solved by the invention]

[0004] However, nonvolatile latch circuits using ferroelectric elements have limitations in terms of reliability in terms of the number of rewrites and low voltage operation. Furthermore, ferroelectric elements are polarized by the electric field applied to the element, and this polarization However, if this residual polarization is small, the effect of variations is large. This may result in a larger signal and require a highly accurate readout circuit.

[0005] In view of such a problem, one aspect of the present invention is a novel nonvolatile latch circuit and An object of the present invention is to provide a semiconductor device. [Means for solving the problem]

[0006] In one aspect of the present invention, an output of a first element is electrically connected to an input of a second element, and the second element a latch section having a loop structure in which an output of the first element is electrically connected to an input of the second element; The data holding unit holds the data of the latch unit. A volatile latch circuit is configured. The data holding section configures the channel forming region. A transistor using an oxide semiconductor as a semiconductor material is used as a switching element. In addition, an insulator electrically connected to the source electrode or the drain electrode of this transistor is The data held in the latch section is read using the transistor. It can be written to the gate capacitance of the inverter or to a separately prepared capacitance. Using a transistor, the data written to the gate capacitance of the inverter or a separately prepared capacitance The data can be stored.

[0007] That is, one aspect of the present invention is a latch unit, a data holding unit that holds data of the latch unit, The data holding unit has a transistor and an inverter. The channel formation region includes an oxide semiconductor layer, and the source electrode and the drain electrode of the transistor are formed by the oxide semiconductor layer. One of the electrodes is electrically connected to a wiring to which an output signal is given, and the other is the source electrode of the transistor. The other of the drain electrodes is electrically connected to the input of the inverter, and the output of the inverter is A nonvolatile latch circuit is formed by electrically connecting the transistor to a wiring to which an input signal is applied. It is something that is accomplished.

[0008] In the above, the data holding unit may have a capacitance in addition to the transistor and inverter. The capacitance can be used to write and hold data held in the latch section. One electrode of the capacitor is connected to the other of the source and drain electrodes of the transistor. It can be electrically connected and used.

[0009] In the above, the latch unit has a first element and a second element, and the output of the first element is a second element. The input of the second element is electrically connected to the input of the first element, and the output of the second element is electrically connected to the input of the first element. The input of the first element is connected to a circuit to which an input signal is given. The output of the first element is electrically connected to a wiring to which an output signal is provided. For example, an inverter is used as the first element and a For example, a NAND may be used as the first element and an inverter may be used as the second element. A clocked inverter can be used as element 2.

[0010] In the above, the transistor transfers the data held in the latch unit to the input of the data holding unit. It has the function of writing to the inverter gate capacitance or a separately prepared capacitance. The transistor is written to the gate capacitance of the inverter in the data storage section or to a separately prepared capacitance. It has the function of retaining the data stored in it.

[0011] In the above, an oxide semiconductor layer formed of an oxide semiconductor material is provided in a channel formation region. The transistor used has a channel width W of 1×10 4 μm and channel length 3 μm Even for devices with an off-state current of 1×10 -13 Below A, subthreshold The S value is approximately 0.1V / dec. (gate insulating film thickness 100nm). Therefore, the off-state current when the voltage between the gate and source electrodes is almost zero, i.e. The leakage current is significantly smaller than that of silicon-based transistors. A transistor using an oxide semiconductor layer in a capacitor formation region is used as a switching element. Even after the supply of power voltage to the latch circuit is stopped, the data stored in the capacitance of the data holding section remains. The charge can be kept stored in the data storage section. In addition, the supply of power supply voltage to the latch circuit is restarted. After the data is read, the data stored in the data storage unit can be read. It is possible to restore the logic state before the supply of power voltage was stopped. Even at high temperatures, the off-current is sufficiently low and the on-current is sufficiently high. The Vg-Id characteristics of the transistor are in the range of -25℃ to 150℃. Data has been obtained showing that the temperature dependence of the flow, mobility, and S value is small. One type of light has a wide temperature operating range, operates stably even at high temperatures, and retains its memory even when the power is turned off. The present invention provides a nonvolatile latch circuit whose logic state does not disappear.

[0012] In the above, various logic circuits can be provided by using a nonvolatile latch circuit. In addition, various semiconductor devices using the logic circuit can be provided. For example, among a plurality of block circuits included in a logic circuit, one or more unused blocks may be The supply of power supply voltage to the latch circuit can be stopped. This allows the logic state of the block circuit to be recorded even after the supply of power voltage to the block circuit is stopped. Furthermore, after the supply of power supply voltage to the block circuit is restarted, This allows the stored logic state to be read out immediately after the supply of power supply voltage is stopped. The previous logical state can be restored.

[0013] In the above, the oxide semiconductor layer may be an In-Ga-Zn-O based, an In-Sn-O based, an In- Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z nO series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn -O-based, In-O-based, Sn-O-based, and Zn-O-based materials can be used. The compound semiconductor layer may contain indium, gallium, and zinc. The hydrogen concentration in the oxide semiconductor layer was 5×10 19 / cm 3 Below 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 Less than or equal to 1×10 16 / cm 3 Less than or equal to 1×10 16 / cm 3 It can be less than 100%. The carrier concentration of the compound semiconductor layer is 1×10 14 / cm 3 Less than 1×10 12 / cm 3 Less than 1×10 11 / cm 3 It can be less than 10 ... The off-state current of the MOSFET at room temperature is 1×10 -13 It can be A or less.

[0014] In the above, the transistor including an oxide semiconductor may be a bottom-gate transistor. It may be a top gate type. It may also be a bottom contact type. The bottom gate transistor may be a contact type. a gate electrode, a gate insulating film on the gate electrode, and a gate insulating film overlapping the gate electrode and an oxide semiconductor layer serving as a channel formation region. an oxide semiconductor layer serving as a channel formation region on at least an insulating surface; and a gate electrode that is on the gate insulating film and overlaps with the oxide semiconductor layer. In a bottom-contact transistor, a channel is formed on the source and drain electrodes. The top-contact transistor has an oxide semiconductor layer that serves as a channel forming region. A source electrode and a drain electrode are provided over the oxide semiconductor layer that serves as a region.

[0015] In this specification, terms such as "above" and "below" refer to the positional relationship of a component "directly above" For example, the term "gate insulating layer on a gate insulating layer" does not necessarily mean "directly under" the gate insulating layer. If the expression "electrode" is used, it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation, and Except where otherwise applicable, this also includes cases where the top and bottom are reversed.

[0016] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0017] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.

[0018] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0019] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also transistors. Switching elements such as transistors, resistive elements, inductors, capacitors, and other various devices This includes elements that have functions such as: [Effects of the Invention]

[0020] According to one embodiment of the present invention, an oxide semiconductor is used as a semiconductor material for forming a channel formation region. By using the transistor as a switching element in the data storage section, It operates stably over a wide range even at high temperatures, and is non-volatile, retaining its stored logic state even when the power is turned off. A latch circuit that is self-refreshing or a latch that has a built-in data holding section with a sufficiently long refresh period The circuit can be realized by switching the transistors to write data. In addition, the write voltage is controlled by the transistor For example, the operating voltage can be set to about 1 V. Or, it can be made smaller. Since the data is stored as it is, there is less variation compared to when the residual polarization component is used as data. It is less susceptible to damage and data can be easily read.

[0021] By using the nonvolatile latch circuit described above, it is possible to realize various logic circuits. For example, in a logic circuit using a nonvolatile latch circuit, the power supply for an unused block By turning off the power, power consumption can be reduced. This allows the system to start up when the power is turned on and when the power is turned off. This allows the system to be shut down quickly and with low power consumption. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Figure 2] FIG. 1 is a diagram showing an example of the configuration of a portion of a nonvolatile latch circuit. [Figure 3] 1A and 1B are diagrams showing an example of a cross section and a plan view of an element included in a nonvolatile latch circuit; [Figure 4] 1A to 1C illustrate an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 5] 1A to 1C illustrate an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 6] 1A to 1C illustrate an example of a manufacturing method of an element included in a nonvolatile latch circuit. [Figure 7] FIG. 10 is a diagram illustrating an example of a cross-sectional structure of an inverted staggered transistor including an oxide semiconductor. [Figure 8] Energy band diagram (schematic diagram) at the A-A' cross section in Figure 7. [Figure 9](A) shows the state in which a positive potential (+VG) is applied to the gate (GE1), and (B) shows the state in which a negative potential (-VG) is applied to the gate (GE1). [Figure 10] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 11] FIG. 1 is a diagram showing the energy required for hot carrier injection in silicon (Si). [Figure 12] This is a diagram showing the energy required for hot carrier injection in an In-Ga-Zn-O oxide semiconductor (IGZO). [Figure 13] FIG. 1 is a diagram showing the energy required for hot carrier injection in silicon carbide (4H—SiC). [Figure 14] FIG. 10 is a diagram showing the results of a device simulation regarding short channel effects. [Figure 15] FIG. 10 is a diagram showing the results of a device simulation regarding short channel effects. [Figure 16] FIG. [Figure 17] A graph showing the relationship between Vg and (1 / C)2. [Figure 18] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Figure 19] FIG. 1 is a diagram showing an example of the configuration and operation of a nonvolatile latch circuit. [Figure 20] FIG. 1 is a diagram showing an example of the configuration and operation of a nonvolatile latch circuit; [Figure 21] FIG. 1 is a diagram showing an example of the configuration and operation of a nonvolatile latch circuit. [Figure 22] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Figure 23] 1A and 1B are diagrams showing examples of a semiconductor device using a nonvolatile latch circuit. [Figure 24] FIG. 1 is a diagram showing an example of the configuration of a nonvolatile latch circuit. [Figure 25] FIG. 10 is a diagram showing an example of an evaluation result of a nonvolatile latch circuit. DETAILED DESCRIPTION OF THE INVENTION

[0023] The following describes embodiments and examples of the present invention with reference to the drawings. The present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following description of the embodiments and examples. It should be noted that the present invention is not limited to the above. The same reference numerals are used in common between different drawings.

[0024] The size, layer thickness, or area of ​​each component shown in the drawings of each embodiment may differ from the actual size, layer thickness, or area of ​​each component shown in the drawings of each embodiment. The figures may be exaggerated for clarity. Not limited.

[0025] In this specification, terms using ordinal numbers such as first, second, and third refer to components. The numbers are added for the convenience of identification and are not intended to limit the number.

[0026] (Embodiment 1) This embodiment will describe a configuration, an operation, and a nonvolatile latch circuit according to one embodiment of the disclosed invention. Regarding the manufacturing method of the elements included in the volatile latch circuit, FIGS. 7 to 17.

[0027] <Configuration and operation of nonvolatile latch circuit> FIG. 1A shows a latch unit 411 and a data holding unit 401 that holds data from the latch unit. FIG. 1B shows the configuration of a nonvolatile latch circuit 400 having a data holding unit 4. The figure shows the configuration of 01.

[0028] In the nonvolatile latch circuit 400 shown in FIG. 1A, the output of the first element (D1) 412 is The output of the second element (D2) 413 is electrically connected to the input of the second element (D3) 413. A latch unit 41 having a loop structure electrically connected to the input of the first element (D1) 412 1 and a data holding unit 401 that holds data from the latch unit.

[0029] The input of the first element (D1) 412 is connected to a wiring 414 to which an input signal of the latch circuit is applied. The output of the first element (D1) 412 is electrically connected to the output of the latch circuit. The wiring 415 is electrically connected to the wiring 415.

[0030] If the first element (D1) 412 has a plurality of inputs, one of them is used as the input signal of the latch circuit. The second element (D2) 413 can be electrically connected to a wiring 414 to which a signal is applied. If there are multiple inputs, one of them is electrically connected to the output of the first element (D1) 412. It can continue.

[0031] The first element (D1) 412 uses an element that outputs an inverted version of the input signal. For example, the first element (D1) 412 may include an inverter, a NAND (NAND gate), ), NOR, clocked inverter, etc. can be used. (D2) 413 can be an element in which the inverted input signal is output. For example, the second element (D2) 413 may include an inverter, a NAND, a NOR, (NOR), a clocked inverter, etc. can be used.

[0032] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistor 402 is used as a switching element. One of the source electrode and the drain electrode is electrically connected to a wiring 415 to which an output signal is applied. The data storage unit 401 is connected to the source electrode of the transistor 402 and The capacitor 404 and the inverter 403 are electrically connected to the other of the drain electrodes. That is, the other of the source electrode and the drain electrode of the transistor 402 is connected to a capacitor 404. One of the electrodes is electrically connected to the input (input terminal) of the inverter 403. One of the electrodes of the capacitor 404, the input of the inverter 403, the source electrode of the transistor 402, and The node at which the other of the drain electrodes is electrically connected is referred to as node S. The other electrode of the capacitor 404 is applied with a potential Vc.

[0033] The output of the inverter 403 is electrically connected to a wiring 414 to which an input signal is applied. The inverter 403 includes a transistor 420 and a transistor 421. The source electrode of the transistor 420 is electrically connected to a high-level power supply voltage VDD. The source electrode of the transistor 421 is electrically connected to the low-level power supply voltage VSS. There are.

[0034] The inverter 403 is not limited to the configuration shown in FIG. 1(B), but may be, for example, a configuration as shown in FIG. , an N-channel transistor 420, and an N-channel transistor 421. Alternatively, a buffer may be provided at the output. For example, a differential amplifier circuit as shown in FIG. 2(B) may be used. A differential amplifier circuit as shown in FIG. 2B may be an N-channel A P-channel transistor 421, N-channel transistors 501 and 502, and a P-channel transistor In either case, the input (input terminal) is floating. It is important that the signal is in a high impedance state.

[0035] The transistor 402 using this oxide semiconductor is The data is written to the capacitance 404 of the data holding unit 401 and the gate capacitance of the inverter 403. The transistor 402 has a capacitance 404 and an inductor 405 of the data storage unit 401. It has the function of holding the data written in the gate capacitance of the inverter 403 .

[0036] The data held in the latch unit 411 is written to, held in, and read from the data holding unit 401. First, the gate electrode of the transistor 402 is connected to the transistor 403. A potential that turns on the transistor 402 is supplied to turn the transistor 402 on. This allows the data held in the latch section, i.e., the wire 4 to which the output signal is given, to be The potential of 15 is applied to one electrode of the capacitor 404 and the input terminal of the inverter 403. As a result, one electrode of the capacitor 404 and the gate capacitor of the inverter 403 are connected to the wiring 415 A charge corresponding to the potential is stored (written). The potential of the transistor 402 is set to a potential at which the transistor 402 is turned off. By setting the capacitor 404 in this state, the charge is accumulated in one electrode of the capacitor 404 and the gate capacitance of the inverter 403. The charge stored in the capacitor 404 is held (retained). By reading out the potential of the input terminal, data can be read out (read ) Data can be rewritten in the same manner as the data writing and storage described above.

[0037] The oxide semiconductor layer of the transistor 402 is made of an In—Ga—Zn—O-based material or an In—Sn-based material. O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series, A l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series It is desirable to use Al-Zn-O, In-O, Sn-O, or Zn-O based materials. stomach.

[0038] The oxide semiconductor layer is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19 / cm 3 Below, wish Preferably 5 x 10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 Below, more hope Preferably 1 x 10 16 / cm 3 Less than or equal to 1×10 16 / cm 3 Less than. The carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 Less than 1×10 12 / cm 3 Less than 1×10 11 / cm 3 It can be less than The oxide semiconductor layer, which has been highly purified by sufficiently reducing the hydrogen concentration, is a typical silicon wafer. Carrier in silicon wafers (silicon wafers doped with trace amounts of impurity elements such as phosphorus and boron) concentration (1×10 14 / cm 3The carrier concentration is sufficiently small compared to the .

[0039] In this way, the hydrogen concentration is sufficiently reduced to achieve high purity, and the carrier concentration is sufficiently low, i By using an oxide semiconductor that is doped or substantially i-type, extremely excellent off-current characteristics can be achieved. For example, a transistor 402 having a channel width W of 1×10 4 In μm Even if the channel length L is 3 μm, the drain voltage Vd applied to the drain electrode is + When the gate voltage Vg applied to the gate electrode is 1V or +10V, In the range of -20V, the off-state current at room temperature is 1×10 -13 A or less. Also, the temperature In terms of characteristics, it is possible to obtain a transistor with a sufficiently low off-state current and a sufficiently high on-state current even at high temperatures. For example, the Vg-Id characteristics of the transistor 402 can be measured in the range of -25°C to 150°C. In this case, data was obtained showing that the temperature dependence of the off-current, on-current, mobility, and S value is small. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). The measurements were made using International Ion Mass Spectroscopy (Ion Mass Spectroscopy). do.

[0040] The oxide semiconductor forming the oxide semiconductor layer is not particularly limited as long as it has a non-single-crystal structure. For example, amorphous structure, microcrystalline (microcrystal, nanocrystal, etc.) structure, polycrystalline Crystalline structure, structure containing microcrystals or polycrystals in amorphous, microcrystals or polycrystals on the surface of amorphous structure Various structures can be applied, such as a structure in which crystals are formed.

[0041] In this way, the hydrogen concentration is sufficiently reduced to achieve high purity, and the carrier concentration is sufficiently low, i The transistor 402 using an oxide semiconductor that is doped or substantially i-type is By using it as a latch element, the device can continue to operate even after the supply of power supply voltage to the latch circuit 400 is stopped. The charge stored in the capacitor 404 of the data holding unit 401 and the gate capacitor of the inverter 403 is polarized. That is, the data can be written to the data storage unit 401 and can be stored for a long time. The latch circuit 4 can hold the data stored in it for an extremely long time. After the supply of power supply voltage to 00 is restarted, the data held in the data holding unit 401 This allows the logic state before the power supply voltage was stopped to be restored. In this way, the hydrogen concentration is sufficiently reduced to achieve high purity, and the carrier concentration is Transistor 40 using an i-type or substantially i-type oxide semiconductor with sufficiently low conductivity By using 2 as a switching element, the temperature operating range is wide and it operates stably even at high temperatures. To realize a novel nonvolatile latch circuit that retains its stored logic state even when the power is turned off. It is possible.

[0042] The elements included in the nonvolatile latch circuit 400 other than the transistor 402 are semiconductors. Materials other than oxide semiconductors can be used as the conductive material. As the material, single crystal silicon, crystalline silicon, etc. can be used. The elements other than the resistor 402 can be provided on a substrate including a semiconductor material. The substrates include silicon wafers, SOI (Silicon on Insulator) r) Substrates, silicon films on insulating surfaces, etc. can be used. Materials other than oxide semiconductors By using this, high speed operation becomes possible.

[0043] Among the elements included in the nonvolatile latch circuit 400, the elements other than the transistor 402 are Alternatively, an oxide semiconductor may be used as the semiconductor material.

[0044] <Plane and cross-sectional configurations of elements in a nonvolatile latch circuit> FIG. 3 shows a transistor 402 included in the nonvolatile latch circuit. Here, the element other than the transistor 402 is a data The transistor 421 included in the inverter 403 of the holding unit 401 will be taken as an example. The other elements other than the transistor 402 are configured to be the same as or similar to the transistor 421. The capacitor 404 and other elements can be connected to the transistor 402 or other elements. It can be formed using the film that constitutes the element. Figure 3(A) shows a cross section, and Figure 3(B) 3(A) shows the planes of the line A1-A2 and the line B in FIG. As shown in Figures 3(A) and 3(B), the bottom of the A transistor 421 using a material other than an oxide semiconductor is provided, and a transistor 422 using an oxide semiconductor is provided in the upper portion. A transistor 402 is provided.

[0045] The transistor 421 has a channel formation region 11 formed in a substrate 100 containing a semiconductor material. 6, and the impurity region 114 and the high concentration impurity region 115 provided so as to sandwich the channel forming region 116. The pure region 120 (collectively referred to as the impurity region) and the channel forming region 11 6, and a gate insulating layer 108a provided on the gate insulating layer 108a. The electrode 110a and the source or drain electrode 111 electrically connected to the impurity region 114 are 30a, and has a source or drain electrode 130b.

[0046] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in plan view, A high concentration impurity region 120 is present, and a metal compound region 124 is formed on the high concentration impurity region 120. In addition, an element isolation insulating layer 1 is formed on the substrate 100 so as to surround the transistor 421. 06 is provided, and the interlayer insulating layer 126 and the interlayer insulating layer 127 are provided to cover the transistor 421. An insulating layer 128 is provided. A source or drain electrode 130a, a source or drain electrode 130b, a The drain electrode 130b is formed in an opening formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. The metal compound region 124 is electrically connected to the source electrode or The source or drain electrode 130a is formed by the metal compound region 1 24, which is electrically connected to the high concentration impurity region 120 and the impurity region 114. The gate electrode 110a is connected to a source electrode or drain electrode 130a or a source electrode Alternatively, an electrode 130c provided similarly to the drain electrode 130b is electrically connected .

[0047] The transistor 402 includes a gate electrode 136d provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the electrode 136d, and a gate insulating layer 138 is provided on the gate insulating layer 138. an oxide semiconductor layer 140; and a metal oxide film provided on the oxide semiconductor layer 140. The source or drain electrode 142a is electrically connected to the source or drain electrode 142b. and an inner electrode 142b.

[0048] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, the source electrode or drain electrode The electrode 136a is in contact with the source or drain electrode 130b. An electrode 136b is formed in contact with the electrode 130c, and an electrode 136c is formed in contact with the electrode 130c.

[0049] In addition, a protective film is formed on the transistor 402 so as to be in contact with part of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. An opening is provided that reaches the source electrode 142a and the source or drain electrode 142b. Through the openings, the electrodes 150d and 150e are connected to the source and drain electrodes. The electrode 142a is formed in contact with the source electrode or the drain electrode 142b. At the same time as forming the electrode 150d and the electrode 150e, the gate insulating layer 138, the protective insulating layer 144, and the layer The electrodes 136a, 136b, and 136c are electrically connected to each other through openings provided in the interlayer insulating layer 146. Electrodes 150a, 150b, and 150c are formed in contact with the substrate.

[0050] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 / cm 3 Below 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 Less than or equal to 1×1016 / cm 3 Less than or equal to 1×10 16 / cm 3 The carrier concentration of the oxide semiconductor layer 140 is less than 1×10 14 / cm 3 Less than 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Not yet In addition, the hydrogen concentration in the oxide semiconductor is sufficiently reduced and the oxide semiconductor is highly purified. The layer 140 is a typical silicon wafer (doped with trace amounts of impurity elements such as phosphorus and boron). The carrier concentration (1×10 14 / cm 3 Compared to the degree In this way, the hydrogen concentration is sufficiently reduced and high purity is achieved. and an oxide semiconductor that is made i-type or substantially i-type and has a sufficiently low carrier concentration. By using the above, the transistor 402 can have excellent off-state current characteristics. For example, the channel width W is 1×10 4 Even if the device has a channel length L of 3 μm, the drain When the drain voltage Vd applied to the electrode is +1V or +10V, When the applied gate voltage Vg is in the range of -5V to -20V, the off-state current at room temperature is 1× 10 -13 The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry. (SIMS: Secondary Ion Mass Spectroscopy) This has been determined.

[0051] An insulating layer 152 is provided on the interlayer insulating layer 146, and a buried insulating layer 152 is provided on the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so that the electrodes are embedded in the Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150a. b, electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 54d is in contact with electrode 150e.

[0052] That is, in the element included in the nonvolatile latch circuit shown in FIG. The gate electrode 110a and the source or drain electrode 142a of the transistor 402 via electrodes 130c, 136c, 150c, 154c and 150d. are electrically connected to each other.

[0053] <Method for manufacturing elements included in nonvolatile latch circuit> Next, an example of a method for manufacturing an element included in the nonvolatile latch circuit will be described. First, a method for manufacturing the lower transistor 421 will be described with reference to FIG. Then, a method for manufacturing the upper transistor 402 will be described with reference to FIGS. 5 and 6. .

[0054] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 4(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate in which silicon semiconductor is formed on an insulating surface. It refers to a substrate having a structure in which a conductor layer is provided, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. The concept also includes substrates having semiconductor layers made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is configured such that a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This also includes the following.

[0055] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 4(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of a material such as silicon nitride oxide can be used. In order to control the threshold voltage of the transistor, an impurity that gives n-type conductivity is added. An element or an impurity element that imparts p-type conductivity may be added to the substrate 100. In the case of a capacitor, impurities that give it n-type conductivity include, for example, phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Umium, gallium, etc. can be used.

[0056] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 4(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0057] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer can be removed by polishing such as CMP or etching. After the semiconductor region 104 is formed or after the element isolation insulating film is formed, After the layer 106 is formed, the protective layer 102 is removed.

[0058] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0059] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. By oxidizing or nitriding the surface of the semiconductor region 104 through plasma treatment or thermal oxidation treatment, The insulating layer may be formed by the high density plasma treatment, for example, using He, Ar, Kr, or X. It is performed using a mixture of rare gases such as e, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. m or less.

[0060] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment mode, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0061] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. a) A gate electrode 110a is formed (see FIG. 4(C)).

[0062] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 4(C)). The semiconductor region 104 is doped with phosphorus (P) or arsenic (As) to form a shallow junction impurity. A region 114 is formed (see FIG. 4(C)). Note that an n-type transistor is formed here. To achieve this, phosphorus or arsenic is added, but when forming a p-type transistor, boron (B) The impurity element such as silicon dioxide (Si) or aluminum (Al) may be added to the impurity region 114. As a result of this formation, a channel forming region 11 is formed below the gate insulating layer 108a of the semiconductor region 104. 6 is formed (see FIG. 4(C)). Here, the concentration of the added impurity can be appropriately set. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In this case, the step of forming the impurity region 114 after forming the insulating layer 112 is performed. However, the process of forming the insulating layer 112 after forming the impurity region 114 is also used. good.

[0063] Next, a sidewall insulating layer 118 is formed (see FIG. 4(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110a and the impurity region 110b. It is advisable to expose the top surface of 114.

[0064] Next, a layer is formed so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed in a region in contact with the impurity region 114 by ion implantation of phosphorus (P) or arsenic (Ar). (As) or the like is added to form a high concentration impurity region 120. After that, the insulating layer is removed. Then, the gate electrode 110a, the sidewall insulating layer 118, the high concentration impurity region 120, etc. are removed. A metal layer 122 is formed to cover the metal layer 122 (see FIG. 4(E)). It can be formed by various film forming methods such as a method for forming a thin film, a sputtering method, a spin coating method, etc. The metal layer 122 reacts with the semiconductor material that makes up the semiconductor region 104 to form a low-resistance metallization. It is desirable to form the wiring board using a metallic material that can be used as a composite material. For example, titanium, tantalum, tungsten, nickel, cobalt, platinum, etc.

[0065] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 4(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of Oa that comes into contact with the metal layer 122.

[0066] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short time of heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0067] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. It is also possible to form the insulating layer using an organic insulating material such as acrylic. Although the structure has a two-layer structure of the edge layer 126 and the interlayer insulating layer 128, the structure of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, the surface is not subjected to a CMP or etching process. Therefore, it is desirable to flatten it.

[0068] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 4(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. can be formed by removing

[0069] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. Removes unnecessary tungsten, titanium, titanium nitride, etc. and improves the flatness of the surface. In this way, the source electrode or drain electrode 130a, the source electrode Alternatively, by planarizing the surface including the drain electrode 130b, it is possible to improve the quality of the surface in a later process. It becomes possible to form favorable electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0070] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, Electrodes in contact with the port electrode 110a (for example, electrode 130c in FIG. 3(A)) The source or drain electrode 130a, the source or drain electrode 130b, and the There is no particular limitation on the material that can be used for the drain electrode 130b. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as stainless steel, aluminum, copper, neodymium, and scandium can be used. Cut.

[0071] In this manner, the transistor 421 is formed using the substrate 100 containing a semiconductor material. After the above steps, electrodes, wiring, insulating layers, etc. may be further formed. In addition, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, Therefore, it is possible to provide a highly integrated semiconductor device.

[0072] <How to make the upper transistor> Next, referring to FIGS. 5 and 6, a process for forming a transistor 402 on the interlayer insulating layer 128 will be described. 5 and 6 show various electrodes and transistors on the interlayer insulating layer 128. Since the figure shows the manufacturing process of the transistor 402, the transistor 402 is located below the transistor 402. The transistor 421 and other components that are connected to it are omitted.

[0073] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 132 is formed on the drain electrode 130b and the electrode 130c (see FIG. 5(A)). The edge layer 132 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The insulating film 10 can be formed using a material containing an inorganic insulating material such as silica.

[0074] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 132 are Openings are formed that reach the drain electrode 130b and the electrode 130c. An opening is also formed in the region where the gate electrode 136d is to be formed. A conductive layer 134 is formed to fill the opening (see FIG. 5B). The mask can be formed by a method such as etching using a photomask. It can be formed by exposure or other methods. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnS, and scandium, as well as alloys and compounds thereof (e.g., nitrides), are examples of such materials. can be done.

[0075] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has a boundary. The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, a function of reducing contact resistance with the source or drain electrodes 130b, 130c, etc. In addition, the titanium nitride film formed thereafter has a burr-like property that suppresses the diffusion of the conductive material. In addition, after forming a barrier film using titanium or titanium nitride, plating is performed. Alternatively, a copper film may be formed by a method.

[0076] After the conductive layer 134 is formed, the conductive layer 134 is removed by etching or CMP. 34 is removed to expose the insulating layer 132, and the electrodes 136a, 136b, and 136c are formed. 36c and a gate electrode 136d are formed (see FIG. 5(C)). Parts are removed to form electrodes 136a, 136b, 136c, and gate electrode 136d. When doing so, it is desirable to process the insulating layer 13 so that the surface is flat. 2. Planarizing the surfaces of the electrodes 136a, 136b, 136c, and gate electrode 136d This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc. in subsequent processes. This becomes possible.

[0077] Next, the insulating layer 132, the electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d The gate insulating layer 138 is formed to cover the gate insulating layer 138 (see FIG. 5(D)). The gate insulating layer can be formed by using a CVD method, a sputtering method, or the like. 138 is silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide It is preferable to form the gate insulating film so as to contain hafnium, tantalum oxide, etc. The layer 138 may have a single layer structure or a multilayer structure. Silicon oxynitride was produced by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited. However, it can be, for example, 10 nm or more and 500 nm or less. For example, a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a first gate insulating layer It is preferable to laminate a second gate insulating layer having a thickness of 5 nm to 300 nm on the layer.

[0078] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high-quality oxide semiconductor layer. Quality will be required.

[0079] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made into a good one.

[0080] Of course, any purified acid can be used as long as it can form a good insulating layer as a gate insulating layer. Even when a nitride semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, the film quality of the gate insulating layer 138 is good. At the same time, the interface state density with the oxide semiconductor layer is reduced, and a good interface can be formed. Just form it.

[0081] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bonds between the main component of the compound are broken by a strong electric field (B: bias) and high temperature (T: temperature), The resulting dangling bonds induce a drift in the threshold voltage (Vth).

[0082] In response to this, impurities in the oxide semiconductor, especially hydrogen and water, are eliminated as much as possible, and the gate electrode is By improving the interface characteristics with the base insulating layer, a stable transistor is produced even during BT tests. It is possible to obtain data.

[0083] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 5(E)).

[0084] The oxide semiconductor layer includes In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn—O-based oxide semiconductor layer. An amorphous oxide was formed using an In-Ga-Zn-O metal oxide target as the conductor layer. The semiconductor layer is formed by a sputtering method. By adding silicon, the crystallization can be suppressed. For example, SiO2 The oxide semiconductor layer may be formed using a target containing 2 wt % to 10 wt % of the oxide semiconductor.

[0085] Examples of targets for forming an oxide semiconductor layer by sputtering include oxide A target of a metal oxide containing zinc as the main component can be used. and a metal oxide target containing Zn (composition ratio: In2O3:Ga2O3:Zn O=1:1:1 [molar ratio] can also be used. In, Ga, and Zn As a metal oxide target containing In2O3:Ga2O3:ZnO=1:1:2[m mol ratio], or the composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [mol ratio] The filling rate of the metal oxide target is 90% or more. 0% or less, preferably 95% or more (for example, 99.9%). By using a target, a dense oxide semiconductor layer is formed.

[0086] The oxide semiconductor layer is formed in a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is preferable to use a mixed atmosphere of rare gas (typically argon) and oxygen. In practice, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of several ppm or less (desirably It is preferable to use a high purity gas in which the concentration has been reduced to a few ppb or less.

[0087] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating, the impurity concentration in the oxide semiconductor layer can be reduced. Damage caused by sputtering can also be reduced. The residual moisture in the metal oxide layer is removed, and a sputtering gas from which hydrogen and water have been removed is introduced. The oxide semiconductor layer is formed using a target of It is preferable to use an adsorption type vacuum pump. For example, a cryopump or an ion pump A titanium sublimation pump can be used. A cryopump with a cold trap may be used. In the deposition chamber, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) Preferably, compounds containing carbon atoms are also exhausted, so that oxides formed in the film-forming chamber are The concentration of impurities contained in the compound semiconductor layer can be reduced.

[0088] The formation conditions are, for example, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%), The following conditions can be applied. If a pulsed direct current (DC) power supply is used, the dust The thickness of the oxide semiconductor layer is preferably 2 nm or less. The thickness is set to 200 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the conductor material, so the thickness should be selected appropriately depending on the material used. good.

[0089] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the sputtering Instead of bombarding the target with ions, the target is bombarded with ions, which are then bombarded with the surface to be treated. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. It is also possible to use nitrogen, helium, oxygen, etc. instead of the argon atmosphere. good.

[0090] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable etching, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The etching time, temperature, etc. are set appropriately.

[0091] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( CCl4) and other gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride). Fluorine (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C HF3), hydrogen bromide (HBr), oxygen (O2), and helium (He) in these gases Alternatively, a gas containing a rare gas such as argon (Ar) may be used.

[0092] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0093] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide (a mixture of ammonia, water, and hydrogen peroxide) can be used. Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0094] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. The temperature of the first heat treatment is The temperature is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and lower than the strain point of the substrate. For example, The substrate is placed in an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heated in a nitrogen atmosphere. Heat treatment is performed at 450° C. in air for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the air. No touching is required to prevent recontamination with water or hydrogen.

[0095] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may also be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0096] For example, as the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is removed from the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Because it is a heat treatment, it can be applied even at temperatures exceeding the distortion point of the substrate.

[0097] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0098] In addition, when an electric furnace is used for the first heat treatment, the atmosphere may be changed when the temperature is lowered during the heat treatment. For example, the atmosphere during the heat treatment can be an inert gas such as nitrogen, or helium, neon, or the like. The atmosphere is changed to an oxygen-containing atmosphere when the temperature is lowered. The oxygen-containing atmosphere can be oxygen gas or oxygen gas and nitrogen gas. When using an atmosphere containing oxygen, the atmosphere It is preferable that the oxygen gas and nitrogen gas used do not contain water, hydrogen, etc. The degree is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, ( That is, it is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less.

[0099] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. For example, the crystallinity may be 90% or more, or 80% or more. % or more of a microcrystalline oxide semiconductor layer. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also cases where this is the case.

[0100] In addition, microcrystals (grain size of 1 nm or less) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). The oxide semiconductor layer is a mixture of the upper 20 nm or less (typically 2 nm to 4 nm). There are cases like this.

[0101] In addition, the electrical characteristics of the oxide semiconductor layer can be changed by arranging microcrystals in the amorphous state. For example, it is possible to use an In-Ga-Zn-O metal oxide target. When forming a ZnO semiconductor layer, the crystal grains of In2Ga2ZnO7 with electrical anisotropy are By forming a microcrystalline portion in which the crystals are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. can.

[0102] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in this direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystalline portion has a function of suppressing the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0103] The oxide semiconductor layer having the above-described microcrystalline portion is formed by GRTA treatment. It can be formed by surface heating. Also, the content of Zn is higher than the content of In or Ga. A more suitable formation can be achieved by using a smaller sputtering target.

[0104] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment can be performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0105] The heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Such dehydration treatment, dehydrogenation treatment, etc. The process is carried out by forming a source electrode or a drain electrode on the oxide semiconductor layer 140 after forming the oxide semiconductor layer. After laminating electrodes, forming a protective insulating layer on the source electrode or drain electrode, etc. In addition, such dehydration treatment and dehydrogenation treatment can be carried out at the timing of The treatment may be carried out not only once but also multiple times.

[0106] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 5(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. It can be formed.

[0107] The conductive layer is formed by PVD (Physical Vapor Deposition) methods such as sputtering. sition method and CVD (Chemical Vapor Deposition) method such as plasma CVD method. The conductive layer can be formed by using a deposition method. , aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten The above-mentioned elements and alloys containing the above-mentioned elements can be used. Instead, manganese, magnesium, zirconium, beryllium, thorium, and yttrium Alternatively, a material selected from one or more of the above may be used. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. A material containing one or more of the elements may be used. For example, aluminum containing silicon may be used. Single-layer structure of film, two-layer structure with titanium film laminated on aluminum film, titanium film and aluminum film Examples include a three-layer structure in which an In-Ga-Zn- O series, In-Sn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system , Sn-Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O oxides In this case, a conductive film can be used. It is preferable to use a material having high conductivity or low resistivity for the oxide conductive film. The conductivity of a conductive film can be increased by increasing the carrier concentration. The carrier concentration can be increased by increasing the hydrogen concentration. The carrier concentration can be increased by increasing the oxygen vacancy.

[0108] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF Preferably, a laser beam is used.

[0109] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the , is determined by the distance between the lower end of the source electrode or drain electrode 142b. When performing exposure so that the channel length (L) is less than 25 nm, the channel length is set to a value of several nm to several tens of nm. and extremely short wavelength extreme ultraviolet light. Exposure using extreme ultraviolet light provides high resolution and a large depth of focus. The channel length (L) of the transistor to be formed later is designed to be less than 25 nm. In other words, the channel length (L) can be set to 10 nm or more and 1000 nm or less. Furthermore, the off-state current is extremely small, so power consumption is low. This prevents power consumption from increasing.

[0110] When etching the conductive layer, the oxide semiconductor layer 140 is not removed. The materials and etching conditions are adjusted appropriately. In this step, a part of the oxide semiconductor layer 140 is etched to form a groove (a recess ) may be formed as an oxide semiconductor layer.

[0111] In addition, between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, An oxide conductive layer is formed between the conductive layer 140 and the source or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or the source or drain electrode 142b may be The conductive layer for forming the drain electrode 142b is formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region. This allows the transistor to operate at high speed.

[0112] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. A resist mask is formed using a multi-tone mask, which is a mask, and an etching process is performed using this. The resist mask formed using the multi-tone mask has a plurality of thicknesses. This can be further deformed by ashing, resulting in a different shape. It can be used in multiple etching processes to process into patterns. The mask forms resist masks corresponding to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography The number of graphic processes can also be reduced, simplifying the process.

[0113] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adhered water and other substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0114] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 5(G)).

[0115] The protective insulating layer 144 is formed by a method such as sputtering, which does not mix impurities such as water or hydrogen into the protective insulating layer 144. The thickness of the film should be at least 1 nm. The protective insulating layer 144 can be formed of a material such as silicon oxide, silicon nitride, or the like. Silicon oxynitride, silicon nitride oxide, etc. The structure may be a single layer structure, The substrate temperature when the protective insulating layer 144 is formed is equal to or higher than room temperature and equal to or higher than 300° C. The atmosphere is preferably a rare gas (typically argon) atmosphere or an oxygen atmosphere. Alternatively, a mixed atmosphere of a rare gas (typically argon) and oxygen is preferably used.

[0116] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or the oxide semiconductor layer may be damaged by the hydrogen. The oxygen in the oxide semiconductor layer is extracted, and the back channel side of the oxide semiconductor layer is Therefore, the resistance of the protective insulating layer 14 may be reduced, and a parasitic channel may be formed. It is important to avoid using hydrogen in the formation method so that 4 contains as little hydrogen as possible. be.

[0117] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The oxide semiconductor layer 140 and the protective insulating layer 144 are preferably formed so as not to contain hydrogen, hydroxyl groups, or moisture. This is to make it possible.

[0118] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O), etc., are removed, so that the compounds formed in the film formation chamber The concentration of impurities contained in the protective insulating layer 144 can be reduced.

[0119] The sputtering gas used when forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or Impurities such as hydrides are reduced to concentrations of a few ppm or less (preferably, a few ppb or less). It is preferable to use high purity gases that have been removed.

[0120] Then, a second heat treatment (preferably 20 It is desirable to carry out the heating at a temperature of 0°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistors.

[0121] In addition, even if heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours, This heat treatment may be carried out by maintaining a constant heating temperature, or by increasing the temperature from room temperature to 100°C or higher. The temperature was increased to 200°C and then decreased to room temperature several times. This heat treatment may be carried out under reduced pressure before the formation of the protective insulating layer. By carrying out the heat treatment in the above-mentioned second method, the heating time can be shortened. This may be carried out in place of the heat treatment, or may be carried out before or after the second heat treatment.

[0122] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 6(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as silica. After that, it is desirable to flatten the surface by a method such as CMP or etching. It's nice.

[0123] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, electrode 136c, source or drain electrode 142a, source An opening is formed so as to reach the electrode or drain electrode 142b, and a conductive layer is formed so as to be embedded in the opening. A conductive layer 148 is formed (see FIG. 6B). The opening is formed by etching using a mask or the like. The mask can be formed by a method such as exposure using a photomask. The etching can be wet etching or dry etching. However, from the viewpoint of fine processing, it is recommended to use dry etching. The conductive layer 148 is preferably formed by a film forming method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, and the like. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. Examples include any conductive material, their alloys, and compounds (e.g., nitrides).

[0124] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method has a thickness of 1000 nm at the interface. The oxide film is reduced, and the lower electrodes (here, the electrodes 136a, 136b, 136c, and The connection between the source or drain electrode 142a and the source or drain electrode 142b The titanium nitride film formed afterwards has the function of reducing contact resistance. It has a barrier function that suppresses the diffusion of materials. It also has a barrier film made of titanium or titanium nitride. After forming the insulating film, a copper film may be formed by plating.

[0125] After the conductive layer 148 is formed, the conductive layer 148 is removed by a method such as etching or CMP. 150a, 150b, and 150c are removed to expose the interlayer insulating layer 146. Then, the conductive layer 50c, the electrode 150d, and the electrode 150e are formed (see FIG. 6(C)). A part of 148 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming the pole 150e, it is desirable to process it so that the surface is flat. As shown, the interlayer insulating layer 146, the electrode 150a, the electrode 150b, the electrode 150c, the electrode 150d, By planarizing the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form an insulating layer, a semiconductor layer, etc.

[0126] Furthermore, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the insulating layer 150 is embedded in the opening. After forming the conductive layer as shown above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a and the like. So I will omit the details.

[0127] When the transistor 402 is manufactured by the above method, the hydrogen concentration in the oxide semiconductor layer 140 is Degrees are 5 x 10 19 atoms / cm 3 At room temperature of the transistor 402, The off-state current is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced. By using the highly purified oxide semiconductor layer 140, the transistor 40 with excellent characteristics can be obtained. In addition, a transistor 42 using a material other than an oxide semiconductor in the lower part can be obtained. 1 and a transistor 402 using an oxide semiconductor therein. A device can be fabricated.

[0128] In addition, examples of semiconductor materials that can be compared with oxide semiconductors include silicon carbide (e.g., 4H Oxide semiconductors and 4H-SiC have several things in common. The rear density is one example. According to the Fermi-Dirac distribution, the minority Carrier is 10 -7 / cm 3 This is estimated to be about 6.7% for 4H-SiC. x10 -11 / cm 3 This is an extremely low value, similar to the intrinsic carrier density of silicon (1. 4×10 10 / cm 3 If you compare it to the level of Cut.

[0129] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. In this respect, oxide semiconductors and silicon carbide have in common.

[0130] On the other hand, there is a significant difference between oxide semiconductors and silicon carbide. The semiconductor process using silicon carbide is generally performed at a temperature of 1500 to 2000°C. Because heat treatment is required, it is difficult to form a laminated structure with semiconductor elements made of other semiconductor materials. This is because such high temperatures can destroy semiconductor substrates and semiconductor elements. On the other hand, oxide semiconductors can be grown at temperatures between 300 and 500°C (below the glass transition temperature, up to about 700°C). It can be fabricated by heat treatment at 4000K (degrees Celsius), and integrated circuits can be fabricated using other semiconductor materials. Therefore, it is possible to form a semiconductor element using an oxide semiconductor.

[0131] In addition, unlike silicon carbide, it is possible to use a substrate with low heat resistance, such as a glass substrate. Furthermore, compared to silicon carbide, it has the advantage that it does not require high-temperature heat treatment. This has the advantage that the energy cost can be sufficiently reduced.

[0132] In oxide semiconductors, the density of state (DOS) and other physical properties are Although many studies have been conducted, these studies have not been based on the idea of ​​sufficiently reducing DOS itself. In one embodiment of the disclosed invention, water and hydrogen, which may cause an increase in DOS, are not included in the oxide semiconductor. By removing the oxide from the conductor, a highly purified oxide semiconductor is produced. This is based on the idea of ​​reducing the amount of things we use. This will enable the production of industrial products.

[0133] Furthermore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and oxygen vacancies are eliminated. By reducing the DOS, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen is formed in close contact with the channel forming region, By supplying oxygen from the oxide film, it is possible to reduce DOS due to oxygen defects.

[0134] Defects in oxide semiconductors are caused by excess hydrogen at a level of 0.1 to 0.2 eV below the conduction band, or by oxygen. These defects are thought to be caused by deep levels due to deficiencies. We believe that the technical concept of thoroughly removing hydrogen and providing sufficient oxygen is correct. can be obtained.

[0135] In addition, although oxide semiconductors are generally n-type, in one embodiment of the disclosed invention, In particular, the i-type is achieved by removing water and hydrogen. Rather than being made into an i-type by adding impurities, it can be said to involve a technological concept that has never been seen before.

[0136] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 7 to 10. In the following explanation, an ideal situation is assumed for ease of understanding. Not all of the information reflects reality. The following explanation is merely a consideration. It should be noted that this is merely a modification and does not affect the validity of the invention.

[0137] Figure 7 shows a cross section of an inverted staggered transistor (thin-film transistor) made of an oxide semiconductor. An oxide semiconductor layer (O S) is provided on which a source electrode (S) and a drain electrode (D) are provided. An insulating layer is provided so as to cover the source electrode (S) and the drain electrode (D).

[0138] FIG. 8 shows an energy band diagram (schematic diagram) in the cross section A-A' of FIG. The black circles (●) in 8 represent electrons, and the white circles (○) represent holes, each with a charge (-q, +q ) and a positive voltage (V D >0), the dashed line indicates the gate voltage When no voltage is applied to the electrode (V G =0), the solid line indicates a positive voltage (V G >0) When no voltage is applied to the gate electrode, the high potential barrier This indicates an off state in which no carriers (electrons) are injected from the electrode to the oxide semiconductor, and no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, and the on-state in which current flows is established. Indicates the state.

[0139] FIG. 9 shows an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. FIG. 9(A) shows the gate electrode (GE1) with a positive voltage (V G >0) is a given state, This shows the on-state where carriers (electrons) flow between the source electrode and the drain electrode. FIG. 9(B) shows a case where a negative voltage (V G <0) is applied. This shows the case where the transistor is in the off state (a state in which minority carriers do not flow).

[0140] Figure 10 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0141] At room temperature, electrons in a metal are degenerate, and the Fermi level is located within the conduction band.

[0142] On the other hand, conventional oxide semiconductors are n-type, and their Fermi level (E F ) is the band gap The central intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that part of hydrogen in oxide semiconductors acts as a donor and is one of the factors that makes them n-type. It is being done.

[0143] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that contains as few impurity elements as possible, other than the main components of the oxide semiconductor. By purifying it to such a high level, it becomes genuine (type i) or is intended to become genuine. .

[0144] That is, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. This is characterized by the fact that it produces a highly purified i-type (intrinsic semiconductor) or something close to it. This results in the Fermi level (E F ) is the intrinsic Fermi level (E i ) It is possible.

[0145] The band gap (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is The electron affinity (χ) of the oxide semiconductor is approximately equal to that of the metal-oxide semiconductor. In this case, no Schottky barrier is formed for electrons.

[0146] At this time, the electrons are transported between the gate insulating layer and the highly purified oxide semiconductor layer as shown in FIG. The electrons move near the interface with the oxide semiconductor (the lowest energetically stable part of the oxide semiconductor).

[0147] Also, as shown in FIG. 9B, when a negative potential is applied to the gate electrode (GE1), Since the number of holes, which are carriers, is essentially zero, the current is close to zero. do.

[0148] In this way, high purity oxide semiconductors are used to minimize the inclusion of elements (impurity elements) other than the main components of the oxide semiconductor. By this, the device becomes intrinsic (i-type) or substantially intrinsic, so the boundary with the gate insulating layer Therefore, the gate insulating layer must have a good interface with the oxide semiconductor. Specifically, for example, it is necessary to have a power supply frequency in the VHF to microwave bands. The insulating layer is produced by the CVD method using high density plasma generated by the sputtering method. It is preferable to use an insulating layer manufactured by

[0149] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width W of a transistor is 1×10 4 μm, channel length L In the case of 3 μm, 10 -13 Off-state current of less than A, subthreshold voltage of 0.1V / dec. A high swing value (S value) (gate insulating layer thickness: 100 nm) can be achieved.

[0150] In this way, the oxide semiconductor is highly oxidized so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0151] <Hot-carrier degradation resistance of oxide semiconductor transistors> Next, the resistance to hot carrier degradation of a transistor including an oxide semiconductor will be described with reference to FIGS. The following explanation will be given with reference to Figure 13. In the following explanation, an ideal situation is assumed for ease of understanding. The following explanation is based on the actual situation and may not reflect all of the information. I would like to add that this is merely one consideration.

[0152] The main cause of hot carrier degradation is channel hot electron injection (CHE injection). and drain avalanche hot carrier injection (DAHC injection). For simplicity, only electrons are considered.

[0153] CHE injection is an injection into the semiconductor layer that has energy greater than or equal to the barrier of the gate insulating layer. This refers to the phenomenon in which electrons that have become electrons are injected into the gate insulating layer, etc. This is achieved by accelerating electrons through a low electric field.

[0154] DAHC injection is a method in which new electrons generated by the collision of electrons accelerated by a high electric field are injected into the gate. The difference between DAHC injection and CHE injection is that the impact ions The question is whether or not avalanche breakdown occurs due to the breakdown of the semiconductor. Electrons with kinetic energy greater than the band gap are required.

[0155] Figures 11 and 12 show the structure of silicon (Si) and In-Ga-Zn-O oxide semiconductor (I The energy required for various hot carrier injections estimated from the band structure of GZO is shown. In Figures 11 and 12, the left side represents CHE injection and the right side represents DAHC injection.

[0156] In silicon, the degradation caused by DAHC implantation is more severe than that caused by CHE implantation. In the electron, only a small number of carriers (e.g., electrons) are accelerated without collisions. This is because silicon has a small band gap and is prone to avalanche breakdown. The number of electrons that can cross the barrier of the gate insulating layer due to avalanche breakdown increases, and the CHE This easily outweighs the probability of injection.

[0157] In the case of In-Ga-Zn-O oxide semiconductors, the energy required for CHE injection is silicon This is not significantly different from the case of DAHC injection, and the probability is low. The required energy is about the same as that required for CHE injection due to the wide band gap. do.

[0158] In other words, the probability of CHE injection and DAHC injection is low, and the hot chip is smaller than that of silicon. High resistance to carrier degradation.

[0159] By the way, the band gap of In-Ga-Zn-O oxide semiconductors is This is comparable to the notable silicon carbide (SiC). The energy required for various hot carrier injections is shown below. For CHE injection, In-Ga -Zn-O based oxide semiconductors have a slightly higher threshold and are therefore advantageous.

[0160] As mentioned above, the In-Ga-Zn-O oxide semiconductor has a lower hot carrier degradation rate than silicon. It can be seen that the resistance to carbonization and source-drain breakdown is very high. It can be said that the breakdown voltage is comparable to that of silicon.

[0161] <Short-channel effect in oxide semiconductor transistors> Next, regarding the short-channel effect in a transistor using an oxide semiconductor, FIGS. 14 and 15 15 will be used for the following explanation. In the following explanation, an ideal situation will be assumed for ease of understanding. The following explanation is based on the actual situation and may not reflect all of the information. I would like to add that this is merely one consideration.

[0162] The short channel effect becomes apparent as transistors become smaller (reduced channel length (L)). The short channel effect is a degradation of electrical characteristics caused by the drain effect extending to the source. Specific examples of short channel effects include a decrease in threshold voltage and an S value. Increased current and leakage current.

[0163] Here, a device simulation is used to determine a structure that can suppress short channel effects. Specifically, we investigated the structure of the oxide semiconductor layer by varying the carrier concentration and the thickness of the oxide semiconductor layer. Four types of models were prepared to confirm the relationship between channel length (L) and threshold voltage (Vth). A bottom-gate transistor was used as the model, and the oxide semiconductor capacitance Rear density 1.7×10 -8 / cm 3 , or 1.0 × 10 15 / cm 3 Either The thickness of the oxide semiconductor layer was set to either 1 μm or 30 nm. The substrate is an In-Ga-Zn-O oxide semiconductor, and the gate insulating layer is a 100 nm thick silicon dioxide film. The band gap of the oxide semiconductor is 3.15 eV, and the electron affinity is 1.0 eV. The sum force is 4.3 eV, the relative dielectric constant is 15, and the electron mobility is 10 cm 2 / Vs. Nitric oxide The relative dielectric constant of the silicon dioxide film was assumed to be 4.0. The software "Atlas" was used.

[0164] There is no significant difference in the calculation results between the top gate structure and the bottom gate structure.

[0165] The calculation results are shown in Figures 14 and 15. Figure 14 shows the results for a carrier concentration of 1.7 × 10 -8 / c m 3 In the case of , Figure 15 shows that the carrier concentration is 1.0 × 10 15 / cm 3 This is the case in Figure 14. In addition, in FIG. 15, a transistor with a channel length (L) of 10 μm is used as a reference. The change in threshold voltage (Vth) (Δ As shown in Figure 14, when the carrier concentration of the oxide semiconductor is 1.7 × 1 0 -8 / cm 3 When the thickness of the oxide semiconductor layer is 1 μm, the change in threshold voltage is In addition, as shown in FIG. 14, the carrier density of the oxide semiconductor The concentration of α is 1.7×10 -8 / cm 3 When the thickness of the oxide semiconductor layer is 30 nm, The change in threshold voltage (ΔVth) was −0.2 V. As shown in FIG. The carrier concentration of the oxide semiconductor is 1.0×10 15 / cm 3 and the thickness of the oxide semiconductor layer When the thickness is 1 μm, the change in threshold voltage (ΔVth) is -3.6 V. As shown in Figure 15, when the carrier concentration of the oxide semiconductor is 1.0 × 10 15 / cm 3 and acid When the thickness of the nitride semiconductor layer is 30 nm, the change in threshold voltage (ΔVth) is -0.2 V. This result indicates that the oxide semiconductor layer This shows that the short channel effect can be suppressed by reducing the thickness of the When the channel length (L) is about 1 μm, the oxide semiconductor layer has a sufficiently high carrier concentration. However, it is reasonable to assume that the short channel effect can be sufficiently suppressed if the thickness is set to about 30 nm. It is understood.

[0166] <Carrier concentration> The technical idea of ​​the disclosed invention is to sufficiently reduce the carrier concentration in the oxide semiconductor layer, The aim is to get as close to intrinsic (i-type) as possible. Below is how to calculate the carrier concentration: The actually measured carrier concentration will be described with reference to FIGS. 16 and 17. FIG.

[0167] First, we will briefly explain how to calculate the carrier concentration. The results of CV measurements of the MOS capacitor (CV characteristics) were evaluated. It is possible to do this.

[0168] More specifically, the relationship between the gate voltage Vg and capacitance C of a MOS capacitor is plotted as C -V characteristics are obtained, and the gate voltage Vg and (1 / C) are calculated from the CV characteristics. 2 A graph showing the relationship between Obtain a rough graph and calculate (1 / C) in the weak inversion region. 2 Calculate the differential value of By substituting the value of the carrier concentration N d The magnitude of is calculated. In (1), e is the elementary charge, ε0 is the dielectric constant of a vacuum, and ε is the relative dielectric constant of the oxide semiconductor. do.

[0169]

number

[0170] Next, we will explain the carrier concentration actually measured using the above method. A titanium film was formed on the glass substrate to a thickness of 300 nm, and a titanium nitride film was then formed on the titanium film to a thickness of 100 nm. The titanium nitride film is formed to a thickness of 1000 nm, and an In-Ga-Zn-O oxide semiconductor is used on the titanium nitride film. An oxide semiconductor layer was formed to a thickness of 2 μm, and a silicon oxynitride film was formed on the oxide semiconductor layer to a thickness of 300 μm. A sample (MOS crystal) was formed with a thickness of 100 nm, and a silver film was formed with a thickness of 300 nm on the silicon oxynitride film. The oxide semiconductor layer was made of a metal oxide containing In, Ga, and Zn. Sputtering using a metal target (In:Ga:Zn=1:1:0.5[atom%]) The oxide semiconductor layer was formed by a deposition method in a mixed atmosphere of argon and oxygen. The atmosphere was set to Ar:O2=30 (sccm):15 (sccm)).

[0171] Figure 16 shows the CV characteristics, and Figure 17 shows the relationship between Vg and (1 / C) 2 The relationship between these is shown in the figure. (1 / C) in the weak inversion region of 17 2 The carrier obtained from the differential value of The concentration is 6.0 x 10 10 / cm 3 It was.

[0172] In this way, an oxide semiconductor that has been made i-type or substantially i-type (for example, a semiconductor having a carrier concentration of 1×10 12 / cm 3 Less than 1×10 11 / cm 3 By using It is possible to obtain a transistor with extremely excellent off-state current characteristics.

[0173] The nonvolatile latch circuit according to the present embodiment is used to store the semiconductor material constituting the channel forming region. A transistor using an oxide semiconductor as a material is used as a switching element for a data storage portion. By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers the setting even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data circuit whose refresh period is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewriting is done by switching the The input voltage is about the same as the threshold voltage of the transistor, so it can operate at low voltage. For example, the operating voltage can be reduced to 1 V or less. Since the data is stored as is, it is less susceptible to variations and the data is easy to read. It is easy to make the overflow.

[0174] By using the nonvolatile latch circuit described above, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible to do this.

[0175] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0176] (Embodiment 2) This embodiment describes a configuration of a nonvolatile latch circuit which is one embodiment of the disclosed invention. An example different from that shown in FIG. 1 will be described with reference to FIG. 18. FIG. 18(A) shows a latch unit 411 and a latch A nonvolatile latch circuit 400 having a data holding section 401 for holding data in the latch section. 18B shows the configuration of the data holding unit 401.

[0177] FIG. 18 shows an example in which the configuration of the data holding unit 401 is different from that shown in FIG. This is an example in which the capacitor of the holding unit 401 (the capacitor 404 in FIG. 1) is not provided. The other configurations are the same as those in FIG. The configuration of the transistor 402 is the same as that of the first embodiment. .

[0178] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistor 402 is used as a switching element. 403 electrically connected to the other of the source electrode and drain electrode of the MOSFET. are.

[0179] One of the source and drain electrodes of the transistor 402 is connected to a The output of the inverter 403 is electrically connected to the wiring 415. The inverter 403 is electrically connected to a wiring 414 that is connected to a transistor 420. and transistor 421. The source electrode of transistor 420 is connected to a high level The source electrode of transistor 421 is electrically connected to the power supply voltage VDD. This pin is electrically connected to the power supply voltage VSS of the

[0180] This embodiment is configured without a capacitance connected to node S. In this case, Charge is accumulated in the gate capacitance of the transistor constituting the capacitor 403. The gate capacitance of the transistor 421 in the inverter 403 is The gate capacitance of the transistor 420 can be larger than that of the transistor 420. The dimensions are the channel length L, channel width W, gate insulating film thickness, dielectric constant, etc. of the transistor. By doing so, the transistor 420 and the transistor The ratio of the capacitance between VSS and node S to the gate capacitance of 421 increases, The potential of the gate electrodes of the transistors 420 and 421 is affected by the fluctuation of VDD. This is preferable because it makes it less likely to break down.

[0181] The inverter 403 is not limited to the configuration shown in FIG. 18(B), but may be, for example, as shown in FIG. It may be configured with an N-channel transistor, or may be configured with a buffer at the output. Also, a sense amplifier circuit may be used instead of the inverter 403. For example, in FIG. A differential amplifier circuit as shown in (B) may also be used. It is important that the input terminals are in a floating state (high impedance state). In the circuit shown in FIG. 2A, the input charge is accumulated in the gate capacitance of the transistor 421. In addition, in the circuit shown in FIG. 2B, the input charge is transferred to the gate capacitance of the transistor 421. In the circuits shown in Figures 2(A) and 2(B), these gate capacitances are mainly Since it is configured between VSS and node S, the potential of the input terminal is not affected by fluctuations in VDD. This is preferable because it makes it less likely to get dirty.

[0182] The transistor 402 using this oxide semiconductor is The data is written to the gate capacitance of the inverter 403 of the data holding unit 401. The transistor 402 is connected to the gate capacitance of the inverter 403 of the data holding unit 401. It has the function of retaining written data.

[0183] The data held in the latch unit 411 is written to, held in, and read from the data holding unit 401. First, the gate electrode of the transistor 402 is connected to the transistor 403. A potential that turns on the transistor 402 is supplied to turn the transistor 402 on. This allows the data held in the latch section, i.e., the wire 4 to which the output signal is given, to be The potential of 15 is applied to the input terminal of the inverter 403. As a result, A charge corresponding to the potential of the wiring 415 is stored in the gate capacitance (write). The potential of the gate electrode of the transistor 402 is set to a potential at which the transistor 402 is turned off. By turning off the transistor 402, the voltage stored in the gate capacitance of the inverter 403 is The accumulated charge is held (held). The potential of the input terminal of the inverter 403 is read out. The data can be read (read) by the above. This can be done in the same way as writing and retaining data.

[0184] The nonvolatile latch circuit according to the present embodiment is used to store the semiconductor material constituting the channel forming region. A transistor using an oxide semiconductor as a material is used as a switching element for a data storage portion. By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers the setting even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data circuit whose refresh period is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewriting is done by switching the The input voltage is about the same as the threshold voltage of the transistor, so it can operate at low voltage. For example, the operating voltage can be reduced to 1 V or less. Since the data is stored as is, it is less susceptible to variations and the data is easy to read. It is easy to make the overflow.

[0185] By using the nonvolatile latch circuit described above, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible to do this.

[0186] This embodiment mode can be freely combined with other embodiment modes.

[0187] (Embodiment 3) This embodiment describes a configuration and operation of a nonvolatile latch circuit which is one embodiment of the disclosed invention. This will be described with reference to FIG. 19 and FIG.

[0188] FIG. 19A shows a latch unit 411 and a data holding unit 401 that holds data from the latch unit. FIG. 19(B) shows the configuration of a nonvolatile latch circuit 400 having a nonvolatile 1 shows an example of a timing chart of the latch circuit 400.

[0189] FIG. 19A is a specific example of the configuration of the latch unit 411 in FIG. 1A. (A) shows the configuration of the latch unit 411 in FIG. 1(A) with an inverter as the first element. The transistor 402 is configured as follows: This is the same as the first embodiment.

[0190] The latch unit 411 includes an inverter 412 and an inverter 413. The output of the inverter 412 is electrically connected to the input of the inverter 413, and the output of the inverter 413 is The latch section 41 has a loop structure electrically connected to the input of the inverter 412. 1 has a switch 431 and a switch 432, and an inverter is connected via the switch 432. The output of the inverter 413 is electrically connected to the input of the inverter 412 .

[0191] The input of the inverter 412 is given the input signal of the latch circuit via the switch 431. The output of the inverter 412 is electrically connected to a wiring 414. The signal is electrically connected to a wiring 415 to which the signal is given.

[0192] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistor 402 is used as a switching element. A capacitor 404 electrically connected to the other of the source electrode and drain electrode of O2 and an inverter 403 and

[0193] One of the source and drain electrodes of the transistor 402 is connected to a The output of the inverter 403 is electrically connected to the wiring 415. 414 to which an input signal is applied.

[0194] The transistor 402 using this oxide semiconductor is The data is written to the capacitance 404 of the data holding unit 401 and the gate capacitance of the inverter 403. The transistor 402 has a capacitance 404 and an inductor 405 of the data storage unit 401. It has the function of holding the data written in the gate capacitance of the inverter 403 .

[0195] The potential of the input signal IN is applied to the wiring 414 from the previous circuit. The switch 431 receives the power of the clock signal φ1 as an output signal OUT. When a high level potential is applied to the clock signal φ1, the switch 431 The potential of the clock signal φ2 is applied to the switch 432. When a high-level potential is applied to φ2, the switch 432 is turned on. The potential of the control signal ST is applied to the gate of O2. The control signal ST is a high-level potential. When the voltage Vcc is applied, the transistor 402 has a potential to be turned on. When a high level potential is given to the control signal LD, the During normal operation, the clock signal φ2 has a potential at which the switch 405 is turned on. The control signal and clock signal φ1 are inverted. An example in which a transistor or switch is turned on when the voltage is at a certain level is shown below.

[0196] The inverter 403 included in the data holding unit 401 and the inverter included in the latch unit 411 412 and inverter 413 are supplied with a high-level power supply voltage VDD and a low-level A power supply voltage VSS is applied.

[0197] Next, in FIG. 19(B), the nonvolatile latch circuit 400 is in an active state (operating period) and in a stopped state. During the stop state (non-operating period), the input signal IN, the output signal OUT, the control signal ST, An example of a timing chart of the potentials of the control signal LD, clock signal φ1, and clock signal φ2 is shown below. The potentials of the node S of the data storage unit 401 and the power supply voltage VDD are also shown. S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, the ground potential is applied. There are.

[0198] In FIG. 19(B), periods a, b, d, and e are operating periods, and period c is non-operating period. Periods a and e are normal operation periods, during which the clock signal φ1 and the clock The signal φ2 is alternately given a high level or a low level potential. Period b is a preparation period before the power supply voltage VDD. Period b is also called the fall period. This is the preparation period after the power is turned on until the normal operation period begins. Period d is also called the start-up period. say.

[0199] During the normal operation period (period a), the clock signal φ1 is at a high level, and the clock signal φ2 When a low level potential is applied to the At the same time, the switch 431 is turned on, and the potential of the input signal is input to the inverter 412. The potential of the input signal is inverted by the inverter 412 and output as the output signal OUT to the subsequent stage. When a high-level potential is applied to the clock signal φ1, the input signal If the potential of the clock is high, an output signal having a low potential is obtained. When a high-level potential is applied to the signal φ1, if the potential of the input signal is low, When the clock signal φ1 is at a low level, an output signal having a high level potential is obtained. When a high level potential is applied to the clock signal φ2, the switch 431 is turned off and The switch 432 is turned on to form an inverter loop, and the potential of the output signal OUT is maintained. During normal operation, the control signal ST has a transition The potential at node S is not applied to turn on the node 402. Here, it is set to an indefinite value.

[0200] Next, in a preparation period (period b) before the non-operating period, the control signal ST is applied to the transistor 40 When a potential that turns on transistor 402 is applied, the potential of the output signal is applied to node S (write). If the potential of the output signal is high, After that, the control signal ST is turned on, and the potential of the transistor 402 is turned off. The transistor 402 is turned off, and the potential of the node S is floating. As a result, the potential written to the node S is maintained as it is (retained). The clock signals φ2 and φ1 may be maintained at the potentials at the end of the period a. Fix the clock signal φ2 at high level and the clock signal φ1 at low level. At the end of period a The control signal ST is supplied to the transistor 40 after the start of the period b. Alternatively, a potential may be applied to turn on the transistor 402 at the same time as the start of the period b. Alternatively, a potential may be applied such that

[0201] Next, during the non-operating period (period c), the power supply is stopped and the power supply voltage VDD drops. Clock signal φ1, clock signal φ2, input signal IN, and output signal OUT are VDD-VS Any value can be taken between S. During this time, the potentials of the control signals ST and LD are During the non-operating period (period c), the signal is held at a low level, for example, at ground potential. Therefore, the potential of node S is floating, so the charge stored in node S is When the power supply voltage VDD drops, the potential of node S is It may fluctuate slightly due to the effect of capacitive coupling with the power supply potential. The charge is retained, so when the power supply voltage VDD is supplied again, the original potential is restored. .

[0202] Next, after the power supply voltage VDD is turned on, during the preparation period (period d) before the normal operation period begins, In this case, the clock signals φ2 and φ1 are fixed to a low level, and the control signal When a potential that turns on the switch 405 is applied to the signal LD, the switch 405 turns on. The potential held at the node S is inverted by the inverter 403 and applied to the latch unit 411. Then, after a potential that turns on the switch 405 is given to the control signal LD, The potential at the end of the period a is applied to the lock signal φ2 and the clock signal φ1. The logic state of the period d can be returned to the logic state before the non-operating period. The voltage may be set to low level before the end of the period d, or the voltage at which the switch 405 is turned on may be set to low level before the end of the period d. You may keep your position.

[0203] Next, during the normal operation period (period e), the clock signals φ1 and φ2 are During the normal operation period (period At the start of the normal operation period ( It may start from the same potential as at the end of period a) or from the next state of the potential at the end of period a). It is okay to start from there.

[0204] The potential of the node S is then increased when a potential is applied to the control signal ST such that the transistor 402 is turned on. Therefore, the transistor 402 is turned on by the control signal ST. The potential of the node S is maintained as it is until a potential is applied that satisfies the condition.

[0205] During the period d, the potential Vc of the other electrode of the capacitor 404 is a value between VDD and VSS. As a result, a potential that takes into account the increment of the potential Vc is applied to the node S, and the read This makes it possible to perform the discharge operation more stably.

[0206] The nonvolatile latch circuit according to the present embodiment is used to store the semiconductor material constituting the channel forming region. A transistor using an oxide semiconductor as a material is used as a switching element for a data storage portion. By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers the setting even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data circuit whose refresh period is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewriting is done by switching the The input voltage is about the same as the threshold voltage of the transistor, so it can operate at low voltage. For example, the operating voltage can be reduced to 1 V or less. Since the data is stored as is, it is less susceptible to variations and the data is easy to read. It is easy to make the overflow.

[0207] By using the nonvolatile latch circuit described above, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible to do this.

[0208] This embodiment mode can be freely combined with other embodiment modes.

[0209] (Fourth embodiment) This embodiment describes a configuration and operation of a nonvolatile latch circuit which is one embodiment of the disclosed invention. An example different from that shown in FIG. 19 will be described with reference to FIG. 20 and FIG. 18. FIG. 20(A) shows a wrapper. The nonvolatile latch has a latch unit 411 and a data holding unit 401 that holds data of the latch unit. 20(B) shows the configuration of the nonvolatile latch circuit 400. 1 shows an example of a timing chart.

[0210] FIG. 20 shows an example in which the configuration of the data holding unit 401 is different from that shown in FIG. This is an example in which a capacitance (capacitor 404 in FIG. 19) of the data holding section is not particularly provided. Since this is the same as the above, the explanation will be omitted.

[0211] FIG. 20A is a specific example of the configuration of the latch section 411 in FIG. 18A. FIG. 20A shows the latch section 411 of FIG. 18A, in which an inverting resistor is used as the first element. This is an example in which a first element is an inverter and a second element is an inverter. The structure of the transistor 402 will be described with reference to FIG. The same is true.

[0212] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The transistor 402 is used as a switching element. 403 electrically connected to the other of the source electrode and drain electrode of the MOSFET. are.

[0213] One of the source and drain electrodes of the transistor 402 is connected to a The output of the inverter 403 is electrically connected to the wiring 415. The inverter 403 is electrically connected to a wiring 414 to which an input signal is applied via a The configuration is as shown in FIG. 18B. The inverter 403 includes a transistor 420 and a The source electrode of the transistor 420 is connected to a high level voltage. The source electrode of transistor 421 is electrically connected to the power supply voltage VDD. It is electrically connected to the power supply voltage VSS.

[0214] This embodiment is configured without a capacitance connected to node S. In this case, Charge is accumulated in the gate capacitance of the transistor connected to the input of the transistor 403. Preferably, the gate capacitance of the transistor 421 in the inverter 403 is The gate capacitance of the transistor 420 is larger than that of the transistor 420. The length depends on the transistor channel length L, channel width W, gate insulating film thickness, dielectric constant, etc. This allows the input capacitance of the inverter 403 to be controlled mainly by the It consists of a capacitor between VDD and VSS, and the potential of the input terminal is less susceptible to fluctuations in VDD. This is preferable because

[0215] The inverter 403 is not limited to the configuration shown in FIG. 18(B), but may be, for example, as shown in FIG. It may be configured with an N-channel transistor, or may be configured with a buffer at the output. Also, a sense amplifier circuit may be used instead of the inverter 403. For example, in FIG. A differential amplifier circuit as shown in (B) may also be used. It is important that the input terminals are in a floating state (high impedance state). In the circuit shown in FIG. 2A, the input charge is accumulated in the gate capacitance of the transistor 421. In addition, in the circuit shown in FIG. 2B, the input charge is transferred to the gate capacitance of the transistor 421. In the circuits shown in Figures 2(A) and 2(B), these gate capacitances are mainly Since it is configured between VSS and node S, the potential of the input terminal is not affected by fluctuations in VDD. This is preferable because it makes it less likely to get dirty.

[0216] The transistor 402 using this oxide semiconductor is The data is written to the gate capacitance of the inverter 403. 402 has a function of holding data written in the gate capacitance of the inverter 403. There are.

[0217] FIG. 20B shows an example of a timing chart of the nonvolatile latch circuit 400. The timing chart in (B) is almost the same as the timing chart in FIG. 19(B). So, I will omit the explanation.

[0218] The nonvolatile latch circuit according to the present embodiment is used to store the semiconductor material constituting the channel forming region. A transistor using an oxide semiconductor as a material is used as a switching element for a data storage portion. By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers the setting even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data circuit whose refresh period is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewriting is done by switching the The input voltage is about the same as the threshold voltage of the transistor, so it can operate at low voltage. For example, the operating voltage can be reduced to 1 V or less. Since the data is stored as is, it is less susceptible to variations and the data is easy to read. It is easy to make the overflow.

[0219] By using the nonvolatile latch circuit described above, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible to do this.

[0220] This embodiment mode can be freely combined with other embodiment modes.

[0221] (Embodiment 5) This embodiment describes a configuration and operation of a nonvolatile latch circuit which is one embodiment of the disclosed invention. An example different from that shown in FIG. 19 will be described with reference to FIG. 21. FIG. 21(A) shows a non-volatile The configuration of the nonvolatile latch circuit 400 is shown in FIG. 21B is a timing chart of the nonvolatile latch circuit 400. An example is shown.

[0222] In the timing chart shown in FIG. 21(B), after the power supply voltage VDD is supplied again, In the period d, a potential that turns on the transistor 402 is applied to the control signal ST. The timing at which the control signal ST rises to high level is determined by the timing at which the control signal LD ​​rises to high level. It is sufficient if the timing is after the control signal ST falls from low to high. The timing is when the clock signals φ1 and φ2 reach the same potential as at the end of the period a. In the period d, the control signal ST is By applying an on potential, the potential of node S can be refreshed. do.

[0223] In the timing chart of FIG. 21(B), the timings other than the control signal ST are the same as those in FIG. Since this is the same as B), the explanation will be omitted.

[0224] The nonvolatile latch circuit according to the present embodiment is used to store the semiconductor material constituting the channel forming region. A transistor using an oxide semiconductor as a material is used as a switching element for a data storage portion. By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers the setting even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data circuit whose refresh period is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewriting is done by switching the The input voltage is about the same as the threshold voltage of the transistor, so it can operate at low voltage. For example, the operating voltage can be reduced to 1 V or less. Since the data is stored as is, it is less susceptible to variations and the data is easy to read. It is easy to make the overflow.

[0225] By using the nonvolatile latch circuit described above, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible to do this.

[0226] This embodiment mode can be freely combined with other embodiment modes.

[0227] (Sixth embodiment) This embodiment describes a logic circuit including a plurality of nonvolatile latch circuits, which is one embodiment of the disclosed invention. The circuit configuration will be described with reference to FIG.

[0228] FIG. 22 shows a configuration of a latch unit 411 and a data holding unit 401 that holds data from the latch unit. 4 shows the configuration of a logic circuit having two nonvolatile latch circuits 400.

[0229] The configuration of the data holding unit 401 is the same as that shown in FIG. 1(A) or FIG. 18(A). The first configuration is the same as that of the latch unit 411 shown in FIG. 1(A) or FIG. 18(A), except that the first element This is an example in which a NAND is used as the first element and a clocked inverter is used as the second element.

[0230] The latch unit 411 includes a NAND 412 and a clocked inverter 413. The output of the ND412 is electrically connected to the input of the clocked inverter 413, The output of the inverter 413 is electrically connected to the input of the NAND 412. The latch unit 411 also has an analog switch 431.

[0231] One of the inputs of the NAND 412 is connected to the latch circuit 400 via an analog switch 431. The NAND 412 is electrically connected to a wiring 414 to which an input signal is applied. The NAN is electrically connected to a wiring 415 to which an output signal from the latch circuit 400 is supplied. Another input of D412 is electrically connected to the wiring that carries the RSTB signal. do.

[0232] The logic circuit shown in FIG. 22 is a nonvolatile latch circuit 400. The nonvolatile latch circuit 400a includes a nonvolatile latch circuit 400b. 00a is electrically connected to a wiring 414 to which the potential of an input signal is applied from the previous circuit. The wiring 415 to which the potential of the output signal of the nonvolatile latch circuit 400a is applied is The latch circuit 400b is electrically connected to a wiring 414 to which a potential of an input signal is applied. The nonvolatile latch circuit 400b is connected to a wiring 4 through which the potential of an output signal is applied to a circuit at a subsequent stage. In the nonvolatile latch circuit 400a, the analog switch The clock signal φ1 and the inverted signal of the clock signal φ1 are applied to the switch 431. The inverter 413 is supplied with the clock signal φ2 and an inverted signal of the clock signal φ2. In the nonvolatile latch circuit 400b, the analog switch 431 receives a clock signal φ 2 and the inverted signal of clock signal φ2 are given to clocked inverter 413. The signal φ1 and the inverted signal of the clock signal φ1 are applied.

[0233] The nonvolatile latch circuit according to the present embodiment is used to store the semiconductor material constituting the channel forming region. A transistor using an oxide semiconductor as a material is used as a switching element for a data storage portion. By using this, the temperature operating range is wide, it operates stably even at high temperatures, and it remembers the setting even when the power is turned off. A non-volatile latch circuit whose logic state does not disappear or a data circuit whose refresh period is long enough It is possible to realize a latch circuit with a built-in holding section. Since the rewriting is done by switching the The input voltage is about the same as the threshold voltage of the transistor, so it can operate at low voltage. For example, the operating voltage can be reduced to 1 V or less. Since the data is stored as is, it is less susceptible to variations and the data is easy to read. It is easy to make the overflow.

[0234] By using the nonvolatile latch circuit described above, it is possible to realize various logic circuits. For example, power consumption can be reduced by turning off unused blocks. In addition, since the logic state is remembered even when the power is turned off, the This allows the system to start up quickly and with low power consumption when the power is turned off, and to shut down quickly when the power is turned off. It is possible to do this.

[0235] This embodiment mode can be freely combined with other embodiment modes.

[0236] (Embodiment 7) In this embodiment, a semiconductor device using the nonvolatile latch circuit obtained in the previous embodiment is An example of an electronic device incorporating the above-described embodiment will be described with reference to FIG. Electronic devices incorporating semiconductor devices using volatile latch circuits have excellent characteristics not found in conventional devices. Therefore, a new semiconductor device using the nonvolatile latch circuit can be used. It is possible to provide an electronic device with a new configuration. The semiconductor device using the latch circuit is integrated and mounted on a circuit board or the like, and is used in various electronic devices. It will be installed inside the

[0237] FIG. 23A shows a semiconductor device using the nonvolatile latch circuit according to the previous embodiment. It is a notebook-sized personal computer, and includes a main body 301, a housing 302, a display unit 303, a keyboard 304, and a keyboard 306. The semiconductor device according to the present invention is a notebook type. By applying this technology to personal computers, it is possible to develop notebook personal computers with excellent performance. A computer can be provided.

[0238] FIG. 23B shows a semiconductor device using the nonvolatile latch circuit according to the previous embodiment. It is a personal digital assistant (PDA), and the main body 311 has a display unit 313 and an external interface 315 and operation buttons 314. A stylus is also provided as an accessory for operation. 312. The semiconductor device according to the disclosed invention can be applied to a personal digital assistant (PDA). This makes it possible to provide a personal digital assistant (PDA) with excellent performance.

[0239] FIG. 23C shows a semiconductor device using the nonvolatile latch circuit according to the previous embodiment. As an example of electronic paper, an electronic book 320 is shown. The electronic book 320 includes a housing 321 and The housing 321 and the housing 323 are made up of two housings, a shaft portion 3 The opening and closing operations can be performed around the shaft portion 337. With this configuration, the electronic book 320 can be used like a paper book.

[0240] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, The text is displayed on the right display unit (display unit 325 in FIG. 23(C)), and the text is displayed on the left display unit (display unit 325 in FIG. 23(C)). In (C), an image can be displayed on the display unit 327).

[0241] FIG. 23C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, etc. You can turn the page by pressing the arrow 333. In addition, there is a keyboard and a pointer on the same surface as the display unit of the housing. The back and sides of the housing may be provided with an external Connection terminals (earphone jack, USB terminal, AC adapter and USB cable, etc.) terminals that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary.

[0242] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0243] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to the display of various cards such as credit cards. To provide electronic paper with excellent performance by applying a semiconductor device to the electronic paper. can be done.

[0244] FIG. 23D shows a semiconductor device using the nonvolatile latch circuit according to the previous embodiment. This mobile phone is composed of two housings, housing 340 and housing 341. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, and a 4. Pointing device 346, camera lens 347, external connection terminal 348, etc. The housing 340 also includes a solar cell 349 for charging the mobile phone, an external The device is also provided with an internal memory slot 350. The antenna is built into the housing 341. are.

[0245] The display panel 342 has a touch panel function, and in FIG. 23(D) an image is displayed. The multiple operation keys 345 are shown by dotted lines. A boost circuit is implemented to boost the voltage output by 9 to the voltage required for each circuit. In addition to the above configuration, it may be configured to incorporate a contactless IC chip, a small recording device, etc. It is also possible.

[0246] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid, and as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it possible to make it compact and portable. It is Noh.

[0247] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. The external memory slot 350 can store a recording medium. It can insert and store and move larger amounts of data. In addition to the above functions, The device may also have an infrared communication function, a television receiving function, etc. By applying the semiconductor device to a mobile phone, it is possible to provide a mobile phone with excellent performance. Cut.

[0248] FIG. 23(E) shows a semiconductor device using the nonvolatile latch circuit according to the previous embodiment. The digital camera is a camera body 361, a display unit (A) 367, an eyepiece, and a 363, an operation switch 364, a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the disclosed invention to a digital camera, an excellent It is possible to provide a digital camera with excellent performance.

[0249] FIG. 23(F) shows a semiconductor device using the nonvolatile latch circuit according to the previous embodiment. The television device 370 has a display unit 373 mounted on a housing 371. The display unit 373 can display images. 3 shows a configuration in which a housing 371 is supported by a stand 375.

[0250] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying the information may be provided.

[0251] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). By applying the semiconductor device according to the disclosed invention to a television set, A television device with excellent performance can be provided.

[0252] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination [Example]

[0253] In this example, the results of evaluating the operation of a nonvolatile latch circuit according to one embodiment of the disclosed invention are shown. Shows.

[0254] The configuration of the nonvolatile latch circuit used for the evaluation is shown in Figure 24. The latch circuit 400 includes a latch unit 411 and a data holding unit 401 that holds data from the latch unit. It has.

[0255] The latch unit 411 is composed of an inverter 412, an inverter 413, and a transistor. The switch 431 is made up of a resistor and the switch 432 is made up of a transistor.

[0256] The data storage unit 401 uses an oxide semiconductor as a semiconductor material for forming a channel formation region. The circuit is composed of a transistor 402, a capacitor 404, an inverter 403, and a transistor. The node S is connected to one electrode of the capacitor 404 and the switch 405. 4 shows the potential of the input terminal of inverter 403.

[0257] The transistor 402 was fabricated according to the procedures shown in FIGS. 5(A) to 5(G) and 6(A) to 6(D). The transistor 402 has the same structure as that shown in (D). A transistor using a highly purified oxide semiconductor with a channel length L=3 μm and a channel width W=5 μm was fabricated. It is a transistor.

[0258] The inverter 412, the inverter 413, the inverter 403, and the transistor switch 431, a switch 432, and a The switch 405 was formed of a silicon transistor.

[0259] The potential of the input signal IN is applied to the wiring 414 from the previous circuit. The potential of the signal φ1 is applied to the switch 431. The potential of the signal φ2 is applied to the switch 432. The potential of the control signal ST is applied to the switch 405. The potential of the control signal LD ​​is applied to the switch 406. can be.

[0260] 25(A) and (B) show the evaluation results of the nonvolatile latch circuit 400. During the write operation, the power supply voltage VDD, the input signal IN, the control signal ST, and the output signal O The potential of UT measured with an oscilloscope is shown in Figure 25(B). In this case, the potentials of the power supply voltage VDD, input signal IN, control signal LD, and output signal OUT are oscillated. The results of measurements using a spectroscopic instrument are shown below. The power supply voltages during power supply were VDD=5V and VSS=0V.

[0261] First, the potential of the output signal OUT is written to the node S and held (see FIG. 25(A)). )). The potential of the output signal OUT during writing was set to 5V, and the potential of the input signal IN was set to 0V. A potential (here, a potential of 5 V) that turns on the transistor 402 is applied to the control signal ST. The transistor 402 is turned on, and the potential of the output signal OUT (here, a potential of 5 V) is connected to the node S. The period during which transistor 402 is turned on is 200 microseconds. It was decided.

[0262] After that, the control signal ST is set to a potential (here, a potential of 0 V) ​​that turns off the transistor 402. This turns off the transistor 402, causing the potential of the node S to float ( retention).

[0263] During writing and holding, the control signal LD ​​is set to a potential (here, 0 A potential of 100 V was applied.

[0264] During the write and hold periods, the signals φ2 and φ1 are at the potentials before the write operation (here, the signals Signal φ2 was held at a low level (0 V), and signal φ1 was held at a high level (5 V).

[0265] Next, the power supply is stopped (also called turning off the power), and the non-volatile memory is stored at room temperature for 10 minutes. The latch circuit 400 was left alone. During this time, the potential of the control signal ST and the control signal LD ​​are set to 0V. Retained.

[0266] Then, the power supply is restarted (also called turning the power on) and the potential of the power supply voltage VDD is set to 5V. I did.

[0267] Next, the potential of the node S was read (see FIG. 25(B)). The potentials of the signals φ2 and φ1 are set to a low level (0 V), and the switches 432 and 431 In this state, the control signal LD ​​is set to a potential at which the switch 405 is turned on (here, A potential of 5 V was applied to the switch 405, and the switch 405 was turned on. A potential of 5 V was output as the potential of the output signal OUT (readout).

[0268] The potential of the output signal OUT is determined by the potential of the node S passing through the inverter 403 and the inverter 412. Therefore, from Fig. 25(B), it can be seen that the node The potential written to S is maintained even after the power supply is stopped, and is used as the potential of the output signal OUT. In other words, by using the nonvolatile latch circuit 400, It was confirmed that the logic state before the power supply was stopped could be restored immediately after the power supply was resumed. [Explanation of symbols]

[0269] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108a Gate insulating layer 110a gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a drain electrode 130b drain electrode 130c electrode 132 Insulating layer 134 Conductive Layer 136a electrode 136b Electrode 136c electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Drain electrode 142b Drain electrode 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device 400 Latch Circuit 400a latch circuit 400b latch circuit 401 Data storage unit 402 transistor 403 Inverter 404 capacity 405 Switch 411 Latch section 412 First Element 413 Second Element 414 Wiring 415 Wiring 420 transistors 421 Transistor 431 Switch 432 Switch 501 N-channel transistor 502 N-channel transistor 503 P-channel transistor 504 P-channel transistor 505 P-channel transistor 506 P-channel transistor

Claims

[Claim 1] a first circuit, a second circuit, a first transistor, a second transistor, a third transistor, a capacitance, a first wiring, and a second wiring; an output of the first circuit electrically connected to an input of the second circuit; an output of the second circuit electrically connected to an input of the first circuit; an input of the first circuit electrically connected to the first wiring; an output of the first circuit is electrically connected to the second wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to an electrode of the capacitor, a gate of the second transistor, and a gate of the third transistor; one of a source or a drain of the second transistor and one of a source or a drain of the third transistor are electrically connected to the first wiring; the first transistor includes an oxide semiconductor; The second transistor and the third transistor are semiconductor devices having silicon.

Images