Semiconductor Devices

Abstract

To suppress characteristic deterioration of a transistor in a driver circuit.SOLUTION: An embodiment includes: a first transistor; a second transistor to which a second signal is inputted to a gate and one of a source and a drain; a third transistor whose gate is electrically connected to the other of the source or the drain of the first transistor, for controlling whether or not to set a voltage state of an output signal by turning on or off; and a fourth transistor whose gate is electrically connected to the other of the source or the drain of the second transistor, for controlling whether or not to set a voltage state of the output signal by turning on or off.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] Semiconductor device, display device, liquid crystal display device, light-emitting device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a display device, a liquid crystal display device, a light emitting device, or a driving method thereof, or a semiconductor device The present invention relates to an electronic device having the light-emitting device, the display device, the liquid crystal display device, or the light-emitting device. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single-crystal semiconductors are used to form a pixel portion. The technology of configuring drive circuits such as gate drivers on the board is expected to significantly reduce costs and improve reliability. Development is underway actively to contribute significantly to the

[0003] A transistor made of a non-single-crystal semiconductor has a fluctuation in threshold voltage or a decrease in mobility. As this transistor degradation progresses, the drive circuit becomes difficult to operate, Therefore, there is a problem that the image cannot be displayed. Patent Document 1 describes a function of maintaining the output signal of a flip-flop at a low level, or A transistor that has the function of lowering a signal to a low level (hereinafter referred to as a pull-down transistor) These documents disclose shift registers that can suppress the deterioration of the Two pull-down transistors are used. , the output terminal of the flip-flop and the low power supply voltage (also called voltage Vss or negative power supply) are supplied The pull-down transistor is connected to the wiring connected to the other pull-down transistor. The down transistor and the down transistor are alternately turned on (also called the on state). , the time that each pull-down transistor is on is reduced, This makes it possible to suppress the deterioration of the transistor characteristics. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-50502 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-24350 [Non-patent literature]

[0005] [Non-Patent Document 1] Yong Ho Jang, et al., “Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure”, Proceedings of The 11th International Display Workshops 2004, pp.333-336 Summary of the Invention [Problem to be solved by the invention]

[0006] In the configuration of the conventional technology, a transistor (hereinafter referred to as The voltage at the gate of the pull-up transistor is the positive supply voltage or the clock signal. The voltage at the high level may be higher than the voltage at the high level. A large voltage may be applied to the gate of the pull-up transistor. A large voltage may be applied to the transistor being used, or the transistor may be degraded. However, if the channel width of the transistor is increased so that the shift register can operate, Alternatively, when the channel width of a transistor becomes larger, the distance between the gate and the This may cause a short circuit between the source or drain of the transistor. As the channel width increases, the parasitic capacitance of each transistor that makes up the shift register increases. This may happen.

[0007] An object of one embodiment of the present invention is to suppress deterioration of transistor characteristics. An object of one embodiment of the present invention is to reduce the channel width of a transistor. One aspect is to suppress deterioration of the characteristics of the pull-up transistor or to reduce the channel width. Another object of one embodiment of the present invention is to increase the amplitude of an output signal. Another object of one embodiment of the present invention is to increase the on-time of a transistor included in a pixel. Another object of one embodiment of the present invention is to improve insufficient writing to pixels. Another object of one embodiment of the present invention is to shorten the fall time of an output signal. An object of one embodiment of the present invention is to shorten the rise time of an output signal. In one aspect of the invention, a video signal for pixels in one row is written to a pixel in another row. Another object of one embodiment of the present invention is to prevent the output signal of a driver circuit from being transmitted. Another object of one embodiment of the present invention is to reduce variations in fall time. Another object of the present invention is to make the influence of feedthrough on the element constant. Another object of the present invention is to reduce crosstalk. Another object of one embodiment of the present invention is to narrow the frame of a display device. Another object of one embodiment of the present invention is to provide a display device with high resolution. Another object of one embodiment of the present invention is to increase yield. Another object of one embodiment of the present invention is to reduce the distortion of an output signal. Another object of the present invention is to reduce the delay of an output signal. Another object of one embodiment of the present invention is to reduce power consumption. An object of one embodiment of the present invention is to reduce the current supply capability of an external circuit. One aspect of the present invention is to reduce the size of an external circuit or the size of a display device having the external circuit. The description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not necessarily solve all of these problems. [Means for solving the problem]

[0008] One aspect of the present invention is a digital signal processing device that receives a first input signal and a second input signal and outputs an output signal. It has a drive circuit and a liquid crystal element, and the voltage applied to the liquid crystal element is set according to the output signal. a pixel, and the driving circuit has a gate, a source, and a drain, a first transistor to which a first signal is input at one of its gate and drain; and a drain, and a second signal is input to the gate and one of the source and drain. a second transistor having a gate, a source, and a drain, the gate of which is connected to the first transistor; The other of the source and drain of the transistor is electrically connected to the other of the source and drain of the transistor, and is turned on or off. a third transistor that controls whether to set the voltage state of the output signal; and a drain, the gate of which is electrically connected to the other of the source and drain of the second transistor. It is connected to the output terminal and controls whether it sets the voltage state of the output signal by being on or off. and a fourth transistor that controls the first transistor.

[0009] One aspect of the present invention is a digital signal processing apparatus in which a first input signal, a second input signal, and a third input signal are input; A driving circuit for outputting an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in accordance with the output signal. a pixel to which a voltage corresponding to the first input signal is set, and the driving circuit a second wiring to which a second input signal is input; and a third wiring to which a third input signal is input. a line, a gate, a source, and a drain, and one of the gate and the source and the drain is a first transistor electrically connected to a first wiring; a second transistor whose gate and one of the source and drain are electrically connected to a second wiring; a transistor having a gate, a source, and a drain, the gate being a first transistor the other of the source and drain of the first transistor, and the other of the source and drain of the second transistor is electrically connected to a third transistor. a third transistor electrically connected to the line, the third transistor having a gate, a source, and a drain; The gate is electrically connected to the other of the source and drain of the second transistor, and the source and a fourth transistor having one of its drain and drain electrically connected to a third wiring; the other of the source and drain of the first transistor and the source and drain of the fourth transistor and a fourth wiring electrically connected to the other end, the voltage of which becomes the voltage of the output signal. It is a liquid crystal display device.

[0010] One aspect of the present invention is a method for generating a first input signal, a second input signal, a third input signal, and a fourth input signal. A driving circuit receives an input signal and outputs an output signal, and the liquid crystal element is provided, and the liquid crystal element changes in accordance with the output signal. a pixel in which a voltage applied to a liquid crystal element is set, and a driving circuit receives a first input signal. a first wiring to which a second input signal is input, a second wiring to which a third input signal is input, and a third wiring to which a fourth input signal is input, a fourth wiring to which a fourth input signal is input, and a gate, a source, and a and a drain, and the gate and one of the source and drain are electrically connected to the first wiring. a first transistor having a gate, a source, and a drain, a second transistor, one of whose source and drain are electrically connected to a second wiring; a gate connected to the source and drain of the first transistor, a second transistor electrically connected to the first wiring and one of the source and drain of the second transistor electrically connected to the third wiring; a third transistor having a gate, a source, and a drain, the gate of which is connected to the second transistor; the other of the source and drain of the fourth a fourth transistor electrically connected to the wiring; and a source and drain of the third transistor. the other of the source and drain of the fourth transistor. and a fifth wiring to which a voltage applied becomes a voltage of an output signal.

[0011] One aspect of the present invention is a digital signal processing device that receives a first input signal and a second input signal and outputs an output signal. The device has a drive circuit and a liquid crystal element, and the voltage applied to the liquid crystal element is set according to the output signal. a pixel, and the driving circuit includes a first wiring to which a first input signal is input and a second wiring to which a second input signal is input. A second wiring to which a signal is input, a gate, a source, and a drain, a first transistor having one of a source and a drain electrically connected to a first wiring; , a source, and a drain, and the gate and one of the source and the drain are connected to a second wiring. a second transistor electrically connected to the gate electrode; a second transistor having a gate, a source, and a drain; and one of the source and drain of the first transistor is connected to the other of the source and drain of the second transistor. a third transistor electrically connected to the gate electrode; and one of the source and drain of the second transistor is connected to the other of the source and drain of the second transistor. a fourth transistor electrically connected to the source and drain of the third transistor; and the other of the source and drain of the fourth transistor, and a third wiring through which the voltage applied thereto becomes the voltage of the output signal.

[0012] In one embodiment of the present invention, the channel width of the third transistor is set to be equal to that of the fourth transistor. It can also be made equal to the channel width of

[0013] In one embodiment of the present invention, the channel width of the first transistor is The channel width of the second transistor can be made smaller than that of the first transistor. The channel width of the transistor can be made smaller than that of the transistor of 4.

[0014] One aspect of the present invention is a digital signal processing device that receives a first input signal and a second input signal and outputs an output signal. a pixel in which a voltage to be applied to a liquid crystal element is set in accordance with an output signal; The driving circuit has a first wiring to which a first input signal is input and a second wiring to which a second input signal is input. 2 wiring, a gate, a source, and a drain, and the gate and the source and drain A first transistor, one of which is electrically connected to a first wiring, and a gate, a source, and a drain The gate and one of the source and drain are electrically connected to a second wiring. a second transistor having a positive electrode and a negative electrode, the positive electrode of which is connected to the source and negative electrodes of the first transistor; a first diode electrically connected to the other of the drains; and a first diode having a positive electrode and a negative electrode, the positive electrode being a second diode electrically connected to the other of the source and drain of the second transistor; and a negative terminal of the first diode and a negative terminal of the second diode are electrically connected to each other. and a third wiring through which the voltage applied thereto becomes the voltage of an output signal.

[0015] In one embodiment of the present invention, the channel width of the first transistor is It can also be made equal to the channel width of

[0016] One aspect of the present invention is a liquid crystal display device according to any one of the above aspects, and a display device of the liquid crystal display device. and an operation switch for controlling the electronic device.

[0017] One aspect of the present invention is a semiconductor device having a gate, a source, and a drain. a first transistor having a first signal input to one input thereof; a second transistor having a gate and one of a source and a drain to which a second signal is input; a transistor and a switch connected in parallel with each other, one of the switches being a first Sets the voltage state of the output signal by turning it on or off depending on the input signal. The other switch is turned on or off according to a second input signal to control the output. Controls whether to set the voltage state of the signal, and when one switch is on, the other switch is off. The first switch is off when the other switch is on. The first switch and the second switch.

[0018] The switch can be of various types. For example, There are switches and mechanical switches. In other words, anything that can control the flow of current. For example, a transistor (e.g., a barrier) may be used as a switch. bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator or Metal) diode, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc. Alternatively, a logic circuit that combines these can be used as a switch.

[0019] Examples of mechanical switches include digital micromirror devices (DMDs), There are switches that use MEMS (microelectromechanical systems) technology. The switch has an electrode that can be mechanically moved, and the movement of the electrode The transistor operates by controlling conduction and non-conduction.

[0020] In addition, CMOS transistors are used to implement both N-channel and P-channel transistors. A switch of the type may be used as the switch.

[0021] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are functionally connected, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) , wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, a predetermined connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may include connection relationships other than those shown in the drawings or text. This also includes other things.

[0022] For example, if A and B are electrically connected, the electrical connection between A and B can be The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more electrodes (such as a diode) may be connected between A and B. Alternatively, A and B may In the case of functional connection, a circuit that allows the functional connection between A and B (e.g. , logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits circuits, AD conversion circuits, gamma correction circuits, etc.), voltage level conversion circuits (power supply circuits (boosting circuits, voltage source, current source, Switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential differential amplifier circuits, source follower circuits, buffer circuits, signal generation circuits, memory circuits, control One or more circuits may be connected between A and B. For example, Even if there is another circuit between them, if the signal output from A is transmitted to B, A and B are considered to be functional. It is assumed that the devices are actively connected.

[0023] In addition, when it is explicitly stated that A and B are electrically connected, it means that A and B are electrically When A and B are directly connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is another When A and B are connected functionally across a circuit, and when A and B are connected directly ( (i.e., when A and B are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. is the same as if it were expressly stated only that the

[0024] Note that the term "display element," "display device having a display element," "light-emitting element," and "device having a light-emitting element" may be used interchangeably. The light emitting device can have a variety of forms and can have a variety of elements. For example, the display element, display device, light-emitting element, or light-emitting device may be an EL (electroluminescent) luminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), L ED (white LED, red LED, green LED, blue LED, etc.), transistor (current transistors that emit light in response to light), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices, Grating light valve (GLV), digital micromirror device (DMD), Carbon nanotubes, etc., have electromagnetic effects that improve contrast, brightness, reflectivity, and transparency. The display device may have a display medium that changes transmittance, etc. The display may be a ray or piezoelectric ceramic display. Electroluminescent displays are examples of such devices, and field Field Emission Displays (FEDs) and Single Emission Display (SED) flat panel displays rface-conduction Electron-emitter Displa y), and liquid crystal displays (transmissive liquid crystal displays) are examples of display devices that use liquid crystal elements. Spray, transflective LCD, reflective LCD, direct view LCD (1) Projection type liquid crystal display), and display devices using electronic ink or electrophoretic elements. There is electronic paper.

[0025] The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. It is composed of a pair of electrodes and liquid crystal. The optical modulation effect of the liquid crystal is controlled by an electric field (including a transverse electric field, a longitudinal electric field, or an oblique electric field) applied to the The liquid crystal elements include nematic liquid crystal, cholesteric liquid crystal, and smectic liquid crystal. Crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals, low molecular weight liquid crystals, high Molecular liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side Examples include chain-type polymer liquid crystals, plasma-addressed liquid crystals (PALC), and banana-shaped liquid crystals. The LCD driving method is TN (Twisted Nematic) mode. , STN (Super Twisted Nematic) mode, IPS (In-Pl Fringe-Switching mode, FFS (Fringe Field Switching) hing mode, MVA (Multi-domain Vertical Alignment ment) mode, PVA (Patterned Vertical Alignment) t) mode, ASV (Advanced Super View) mode, ASM (Ax ally Symmetric aligned Micro-cell) mode, O CB (Optically Compensated Birefringence) Electrically Controlled Birefring (ECB) ence) mode, FLC (Ferroelectric Liquid Crystal l) Mode, AFLC (AntiFerroelectric Liquid Crys) tal) mode, PDLC (Polymer Dispersed Liquid Crystal Galaxy mode, guest host mode, Blue Phase mode, etc. However, there are other liquid crystal elements that are not limited to these. It is possible.

[0026] Note that transistors with various structures can be used as the transistors. There is no limitation on the type of transistor used. For example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, Crystalline (also called microcrystalline, nanocrystalline, or semi-amorphous) silicon, etc. It is possible to use thin film transistors (TFTs) having non-single crystal semiconductor films, such as can.

[0027] When producing polycrystalline silicon, a catalyst (such as nickel) is used to This further improves the crystallinity, making it possible to manufacture a transistor with good electrical characteristics. When producing microcrystalline silicon, the crystallinity can be improved by using a catalyst (such as nickel). This further improves the electrical characteristics of the transistors, making it possible to manufacture transistors with good electrical characteristics. It is possible to produce polycrystalline silicon and microcrystalline silicon without using a catalyst (such as nickel). It is Noh.

[0028] In addition, improving the crystallinity of silicon to polycrystalline or microcrystalline can improve the overall panel performance. It is desirable to perform this process, but it is not limited to this. The crystallinity of the silicon may be improved.

[0029] Or ZnO, a-InGaZnO, SiGe, GaAs, IZO (indium zinc oxide) (Indium Tin Oxide), ITO (Indium Tin Oxide), SnO, TiO, AlZnSnO (AZTO), etc. Transistors having any compound semiconductor or oxide semiconductor, and further, A thin film transistor made of a conductor or an oxide semiconductor can be used. By simply using these compound semiconductors or oxide semiconductors in the channel portion of a transistor, For example, these compound semiconductors or oxides can be used for other purposes. The semiconductor can be used as a resistor element, a pixel electrode, or a light-transmitting electrode. These can be deposited or formed simultaneously with the transistors, thereby reducing costs.

[0030] Alternatively, a transistor formed by inkjet or printing can be used. .

[0031] Alternatively, a transistor having an organic semiconductor or a carbon nanotube may be used. These features make it possible to form transistors on a flexible substrate. A semiconductor device using such a substrate can be made resistant to shocks.

[0032] Furthermore, transistors of various structures can be used. For example, MOS transistors The use of transistors such as junction transistors and bipolar transistors as transistors can be done.

[0033] In addition, MOS transistors, bipolar transistors, etc. can be mixed and formed on a single substrate. It may be done.

[0034] Note that the transistor can be formed using various substrates. The substrate is not limited to, for example, a semiconductor substrate (e.g., a single crystal Substrates (e.g., silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic substrates , metal substrate, stainless steel substrate, substrate with stainless steel foil, Tungsten substrates, substrates with tungsten foil, flexible substrates, etc. can be used. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Examples of flexible substrates include polyethylene terephthalate (PET), poly Plastics such as ethylene naphthalate (PEN) and polyethersulfone (PES) There are also other materials such as adhesive films, such as plastic sticks, or flexible synthetic resins such as acrylic. Film (polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.) , paper containing fibrous materials, base film (polyester, polyamide, polyimide, inorganic There are also other types of substrates (such as metallized films and paper). After that, the transistor may be transferred to another substrate and the transistor may be disposed on the other substrate. The substrates on which transistors are transferred include single crystal substrates, SOI substrates, glass substrates, and quartz substrates. Board, plastic substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, cloth substrate (natural fiber Fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers Fiber (including acetate, cupro, rayon, recycled polyester), leather substrate, rubber The substrates used are aluminum substrates, stainless steel substrates, and substrates with stainless steel foil. Alternatively, a transistor can be formed using a substrate, and the substrate can be polished to a thin film. The substrate to be polished may be a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, or the like. Plate, plastic substrate, stainless steel substrate, stainless steel foil By using these substrates, transistors with good characteristics can be manufactured. Formation of transistors with low power consumption, fabrication of durable devices, and heat resistance This allows for a reduction in weight or thickness.

[0035] The structure of the transistor is not limited to a specific structure. For example, a transistor having two or more gate electrodes may be used. The above multi-gate structure can be applied.

[0036] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. In addition, by using a structure in which gate electrodes are arranged above and below the channel, multiple transistors can be This results in a circuit configuration equivalent to that of transistors connected in parallel.

[0037] A structure in which a gate electrode is placed above a channel region, and a structure in which a gate electrode is placed below a channel region Structures in which the channel region is divided into multiple regions, such as a positive staggered structure, a reverse staggered structure, and a A structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series are also suitable. Furthermore, the source electrode and drain electrode can be overlapped on the channel region (or a part of it). The structure can also be applied.

[0038] Note that the transistor can be formed using various substrates. To achieve the desired function, all of the necessary circuits may be formed on the same substrate. For example, all the circuits required to realize a given function can be mounted on the same glass substrate or plastic. It can also be formed using various substrates such as a solid substrate, a single crystal substrate, or an SOI substrate. Alternatively, a part of the circuit required to realize a predetermined function is formed on a certain substrate, It is also possible to form another part of the circuitry required to achieve a given function on a different substrate. In other words, all of the circuits required to realize a given function are formed using the same substrate. For example, some of the circuits required to realize a given function may not be The circuitry required to realize a specific function is formed by transistors on a glass substrate. Another part is formed on a single crystal substrate and is composed of transistors formed using the single crystal substrate. The IC chip is connected to the glass substrate by COG (Chip On Glass). It is also possible to place the IC chip on a glass substrate. Glass using TAB (Tape Automated Bonding) or printed circuit boards It is also possible to connect it to a substrate.

[0039] The transistor has at least three terminals including a gate, a drain, and a source. It is also possible to use a device having a channel between the drain and source regions. The semiconductor device has a channel region and allows current to flow through the drain region, the channel region, and the source region. Here, the source and drain can be determined depending on the structure and operating conditions of the transistor. Since the voltage changes depending on the source and drain, it is difficult to determine which is the source and which is the drain. In the case where the regions that function as source and drain are not called source or drain, In that case, for example, they may be written as the first terminal and the second terminal, respectively. Alternatively, they may be referred to as the first electrode and the second electrode, respectively. Alternatively, the source and drain may be referred to as a first region. The gate may also be referred to as the third terminal or the third electrode. be.

[0040] The transistor also has at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector may be connected to the first terminal and the second terminal. It may be written as a terminal. The base can also be written as a gate. Therefore, the notations "gate," "first terminal," and "second terminal" refer to the base, emitter, and collector, respectively. This can be rephrased as one of the emitter and collector, and the other of the emitter and collector.

[0041] Note that it is not possible to explicitly say that B is formed on A, or that B is formed on A. When describing, it is not limited to forming B on A in direct contact with it. This also includes cases where there is no object between A and B, i.e., there is another object between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0042] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When the layer is placed on top of the substrate, there are cases where layer B is formed directly on top of layer A, and cases where layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed adjacent to it, and layer B is formed directly on top of it. It should be noted that other layers (such as layer C and layer D) may be formed separately. It may be a single layer or multiple layers.

[0043] Furthermore, the same applies when it is explicitly stated that B is formed above A. This is not limited to B being directly on top of A, but also includes the presence of another object between A and B. For example, if layer B is formed above layer A, In this case, there are two cases: when layer B is formed directly on top of layer A, and when layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be single layers. Alternatively, it may be multi-layered.

[0044] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that "B" is formed, this also includes the case where B is formed diagonally above. .

[0045] The same applies to the case where B is below A, or B is below A.

[0046] In addition, when something is explicitly stated as singular, it is preferable that it be singular. However, it is not limited to this, and plural numbers are also possible. It is preferable that the items listed are plural. However, this is not limited to this. , it is also possible that it is singular.

[0047] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0048] The diagrams are merely diagrams showing ideal examples, and are not limited to the shapes or values ​​shown in the diagrams. For example, variations in shape due to manufacturing technology, variations in shape due to errors, and noise Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Alternatively, it is possible to include variations in current.

[0049] Note that technical terms may be used to describe specific embodiments or examples. Many, but not limited to:

[0050] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It can be used as a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. The terms defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0051] It should be noted that the terms first, second, third, etc., refer to various elements, members, regions, layers, and sections as distinct from one another. Therefore, the words "first," "second," "third," etc. are used to distinguish between elements, parts, etc. It is not intended to limit the number of materials, regions, layers, areas, etc. It is possible to replace "second" or "third" etc.

[0052] In addition, "up," "upward," "downward," "downward," "sideways," "right," "left," Spatial arrangement such as "diagonally," "in the back," "in front," "inside," "outside," or "inside" The location phrases should be used to easily illustrate the relationship of one element or feature to another. However, it is not limited to this and is often used to indicate the spatial arrangement of these. The phrase "above A" can include other directions in addition to the direction shown in the drawing. For example, When explicitly indicated as B, B is not limited to being above A. can be flipped or rotated 180 degrees, so it can include B being below A. In this way, the word "upon" can be used to refer to the direction of "up" as well as the direction of "down." The devices shown may include, but are not limited to, various orientations. Since it is possible to rotate the word "on" in addition to the directions "on" and "under" "Sideways", "Right", "Left", "Diagonally", "Back", "Front", "Inside", "Outside" Other directions such as "into" or "into" may be included.

[0053] One embodiment of the present invention is a semiconductor device including a first transistor and a second transistor. The first terminal of the first transistor is electrically connected to the first wiring, and the second terminal of the first transistor is is electrically connected to the second wiring, and the gate of the first transistor is electrically connected to the third wiring. a first terminal of the second transistor electrically connected to the first wiring; The second terminal of the second transistor is electrically connected to the second wiring. The gate is electrically connected to the fourth wiring.

[0054] One aspect of the present invention is a method for detecting a voltage having a first period and a second period, the first period being divided into a first sub-period and a second sub-period. a second sub-period, the second period having a third sub-period and a fourth sub-period, In one sub-period, the first transistor is turned on and the second transistor is turned off. In the second sub-period, the first transistor is turned off and the second transistor is turned on. In the third sub-period, the first transistor is turned off, and in the third sub-period, the first transistor is turned off, and During the fourth sub-period, the second transistor is turned on, and during the fourth sub-period, the first transistor is turned off. The first transistor is turned off and the second transistor is turned off.

[0055] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. and a fourth transistor, the first terminal of the first transistor being connected to the first wiring. a second terminal of the first transistor electrically connected to the second wiring; The first terminal of the second transistor is electrically connected to the first wiring. The second terminal of the third transistor is electrically connected to the second wiring, and the first terminal of the third transistor is The second terminal of the third transistor is electrically connected to the third wiring. The gate of the third transistor is electrically connected to the third wiring. The first terminal of the fourth transistor is electrically connected to the fourth wiring. The second terminal of the transistor is electrically connected to the gate of the second transistor, and the fourth terminal of the transistor is electrically connected to the gate of the fourth transistor. The gate of the transistor is electrically connected to the fourth wiring, and the gate of the third transistor is electrically connected to the fifth wiring, and the gate of the fourth transistor is electrically connected to the fifth wiring. It is connected to the network.

[0056] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first circuit. The first terminal of the first transistor is electrically connected to the first wiring. The second terminal of the second transistor is electrically connected to the second wiring, and the first terminal of the second transistor is The second terminal of the second transistor is electrically connected to the first wiring, and the second terminal of the second transistor is electrically connected to the second wiring. The first circuit is electrically connected to the first transistor such that the first signal is in a first voltage state. and a function of turning on the second transistor when the second signal is in a first voltage state. It has the function of connecting the

[0057] Note that one embodiment of the present invention includes a second circuit, and the second circuit outputs a first transistor for a certain period. a function of maintaining the voltage of the gate of the first transistor at a second voltage state; a function of maintaining the voltage of the second wiring in a second voltage state; The function may be the same as above.

[0058] Note that one embodiment of the present invention includes a third circuit, and the third circuit is a gate of the first transistor. a function of setting the voltage of the gate of the second transistor to a second voltage state; and a function of causing the voltage of the second wiring to be in a second voltage state. It may also be something. [Effects of the Invention]

[0059] According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. This embodiment allows the channel width of the transistor to be reduced. It is possible to suppress the deterioration of the transistor characteristics or reduce the channel width. According to one aspect of the present invention, the amplitude of a signal can be increased. Alternatively, one embodiment of the present invention can be realized by increasing the on-time of a transistor. Alternatively, one embodiment of the present invention can improve the fall time of a signal. Alternatively, one aspect of the present invention is to shorten the rise time of a signal. Or, the video signal for the pixels in one row can be written to the pixels in another row. Alternatively, the variation in the fall time of the signal can be reduced. Or, the influence of feedthrough on the pixel can be made constant. Alternatively, one embodiment of the present invention can reduce the layout area. Alternatively, according to one embodiment of the present invention, the frame of a display device can be narrowed. Alternatively, according to one embodiment of the present invention, a display device can have high resolution. Alternatively, one embodiment of the present invention can reduce costs. Alternatively, one embodiment of the present invention can reduce the distortion of a signal. According to one embodiment of the present invention, signal delay can be reduced. Alternatively, one embodiment of the present invention can reduce the current supply capability of an external circuit. Alternatively, one embodiment of the present invention is to provide a device having a size of an external circuit or a semiconductor device having the external circuit. This allows the size of the display device to be reduced. [Brief explanation of the drawings]

[0060] [Figure 1] 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] 2 is an example of a timing chart for explaining the operation of the semiconductor device of FIG. 1. [Figure 3] FIG. 2 is a schematic diagram illustrating an example of the operation of the semiconductor device of FIG. 1. [Figure 4] FIG. 2 is a schematic diagram illustrating an example of the operation of the semiconductor device of FIG. 1. [Figure 5] 2 is an example of a timing chart for explaining the operation of the semiconductor device of FIG. 1. [Figure 6] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 7] 7 is an example of a schematic diagram for explaining the operation of the semiconductor device of FIG. 6. [Figure 8] 7 is an example of a schematic diagram for explaining the operation of the semiconductor device of FIG. 6. [Figure 9] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 14] 10A and 10B are an example of a circuit diagram of a semiconductor device according to a second embodiment and an example of a timing chart for explaining the operation thereof. [Figure 15] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 16] 10A and 10B are an example of a circuit diagram of a semiconductor device according to a third embodiment and an example of a timing chart for explaining the operation thereof. [Figure 17] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 18] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 19] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 20] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 21] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 22] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 23] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 24] 1 is an example of a circuit diagram of a semiconductor device according to a first embodiment. [Figure 25] 25 is an example of a timing chart for explaining the operation of the semiconductor device of FIG. 24. [Figure 26] FIG. 11 is an example of a block diagram of a display device according to a fourth embodiment. [Figure 27] FIG. 13 is an example of a circuit diagram of a shift register according to the fourth embodiment. [Figure 28] 28 is an example of a timing chart for explaining the operation of the shift register of FIG. 27. [Figure 29] FIG. 13 is an example of a circuit diagram of a signal line driving circuit according to a fifth embodiment. [Figure 30] 13A and 13B are an example of a circuit diagram of a pixel according to the sixth embodiment and an example of a timing chart for explaining the operation thereof. [Figure 31] FIG. 22 is an example of a circuit diagram of a pixel according to the sixth embodiment. [Figure 32] FIG. 13 is an example of a cross-sectional view of a transistor according to a seventh embodiment. [Figure 33] 13A and 13B are an example of a top view of a display device according to Embodiment 8 and an example of a cross-sectional view of the display device. [Figure 34] 10A to 10C are examples of cross-sectional views illustrating a manufacturing process of a transistor in Embodiment 9. [Figure 35] FIG. 23 is an example of a layout diagram of a semiconductor device according to a tenth embodiment. [Figure 36] FIG. 22 is a diagram illustrating an example of an electronic device according to an eleventh embodiment. [Figure 37] FIG. 22 is a diagram illustrating an example of an electronic device according to an eleventh embodiment. [Figure 38] 13 is an example of a schematic diagram for explaining the operation of the semiconductor device of FIG. 12. [Figure 39] 13 is a schematic diagram illustrating an example of the operation of the semiconductor device of FIG. 12. [Figure 40] 17A and 17B are schematic diagrams illustrating an example of the operation of the semiconductor device of FIG. 16. [Figure 41]17A and 17B are schematic diagrams illustrating an example of the operation of the semiconductor device of FIG. 16. [Figure 42] 17A and 17B are schematic diagrams illustrating an example of the operation of the semiconductor device of FIG. 16. [Figure 43] 17A and 17B are schematic diagrams illustrating an example of the operation of the semiconductor device of FIG. 16. [Figure 44] 24 is an example of a schematic diagram illustrating the operation of the semiconductor device of FIG. 23. [Figure 45] 24 is an example of a schematic diagram illustrating the operation of the semiconductor device of FIG. 23. [Figure 46] 24 is an example of a schematic diagram illustrating the operation of the semiconductor device of FIG. 23. [Figure 47] 24 is an example of a schematic diagram illustrating the operation of the semiconductor device of FIG. 23. [Figure 48] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 49] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 50] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 51] 11 is a timing chart showing calculation results for the semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0061] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily understood by those skilled in the art that various modifications can be made to the design and details of the present embodiment. It should not be construed as being limited to the contents of the description below. The same reference numerals are used in different drawings to indicate the same parts or parts with similar functions. A detailed description of the portion having the symbol will be omitted.

[0062] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Another content (which may be part of the content) described in a certain state, and / or application, combination, or replacement For the content (which may be part of the content) described in a certain form, it is assumed that one aspect can be constituted by performing operations such as For example, active elements (such as transistors and diodes), wirings, passive elements (such as capacitor elements and resistor elements) , conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, substrates, modules, devices, solids , liquids, gases, operation methods, manufacturing methods, etc., in a single or plural number described in drawings (such as cross-sectional views, plan views , circuit diagrams, block diagrams, flowcharts, process diagrams, perspective views, elevation views, layout diagrams, timing charts , structure diagrams, schematic diagrams, graphs, tables, optical path diagrams, vector diagrams, state diagrams, waveform diagrams, photographs , chemical formulas, etc.) or texts, it is assumed that one aspect of the invention can be constituted by extracting a part thereof. As an example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), M (M is an integer and M < N) circuit elements (such as transistors and capacitor elements) can be extracted to constitute one aspect of the invention. It is possible. As another example, from a cross-sectional view composed of N layers, M layers can be extracted to constitute one aspect of the invention. As another example, from a flowchart composed of N elements , M elements can be extracted to constitute one aspect of the invention. It is possible.

[0063] (Embodiment 1) In this embodiment, an example of a semiconductor device which is one aspect of the present invention will be described. In this embodiment The semiconductor device of this form is, as an example, a shift register, a gate driver, or a source driver The semiconductor device of this embodiment can be used in various driver circuits such as a driver circuit. It may also be referred to as a driver circuit or a circuit.

[0064] First, a circuit configuration of a semiconductor device of this embodiment mode will be described with reference to FIG. The semiconductor device in FIG. 1A includes a circuit 100 (also referred to as a second control circuit) and a circuit 200 ( The circuit 100 includes transistors 101_1 to 101_2. It has multiple transistors, numbered 2.

[0065] It is assumed that the transistors 101_1 and 101_2 are N-channel transistors, for example. In an N-channel transistor, the potential difference (Vgs) between the gate and source is equal to the threshold voltage. However, it is not limited to this and may be turned on when the voltage exceeds the threshold voltage (Vth). The transistor 101_1 and / or the transistor 101_2 are P-channel type. A P-channel transistor has a potential difference (Vgs) between the gate and source. It turns on when the voltage drops below the threshold voltage (Vth).

[0066] Next, the connection relationship of the semiconductor device in FIG. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 111. A first terminal of the transistor 101_2 is connected to a wiring 112. The second terminal of the first terminal 101_2 is connected to the wiring 111. ), the wiring 113, the wiring 114, the wiring 115_1 to 115_2, the wiring 116_ 1 to 116_2, wiring 117, wiring 118, the gate of transistor 101_1, transistor 101_2 and the wiring 111. However, the present invention is not limited to this. The wiring connected to the semiconductor device shown in FIG. 1(A) is an example. Therefore, it is possible to increase the number of wirings connected to the semiconductor device. For example, the circuit 200 may be configured to use various wirings depending on its configuration. Alternatively, the circuit 200 may be connected to the wiring described above. It is possible that the IF signal is not connected to either the IF signal or the IF signal.

[0067] In FIG. 1A, the connection point between the gate of the transistor 101_1 and the circuit 200 is referred to as node 11, and the connection point between the gate of the transistor 101_2 and the circuit 200 is referred to as node It is shown as Do12.

[0068] Next, the voltages or signals input to or output from each wiring will be described.

[0069] As an example, a signal OUT is output from the wiring 111. The voltage state is set according to the signal input to the conductor device. It can be a signal having a first voltage state and a second voltage state, for example, a signal OUT is often a digital signal that has two voltage states: high and low. The wiring 111 can function as an output signal of the semiconductor device. , signal line, or output signal line. However, this is not limited to this. For example, the wiring 111 can be arranged so as to extend to the pixel portion. Therefore, the wiring 111 can be connected to the pixel. For example, in the case of a liquid crystal display device, The wiring 111 is connected to a pixel having a liquid crystal element, and a voltage is applied to the liquid crystal element according to the voltage of the wiring 111. Alternatively, the wiring 111 may be configured to set a voltage to be applied to a transistor of the pixel. connected to the gate of a transistor (e.g., a selection transistor or a switching transistor) Therefore, the wiring 111 can be used as a gate signal line (hereinafter also referred to as a gate line). In this case, the signal OUT can function as a gate signal or a scanning signal.

[0070] As an example, a signal CK1 is input to the wiring 112. The signal CK1 is, for example, For example, the signal CK may be a signal having a first voltage state and a second voltage state. 1 may be a digital signal that alternates between two voltage states: high and low. Therefore, the wiring 112 can function as a signal line. signal line or clock signal line (hereinafter also referred to as clock line or clock supply line) However, the wiring 112 may have a function of supplying a voltage. Therefore, the wiring 112 can function as a power supply line. is.

[0071] As an example, a signal CK2 is input to the wiring 113. The signal CK2 is, for example, For example, the signal CK may be a signal having a first voltage state and a second voltage state. 2 may be a digital signal that alternates between two voltage states: high and low. In many cases, the signal CK2 can function as an inverted clock signal. It is an inverted signal of signal CK1 or a signal whose phase is shifted by approximately 180° from signal CK1. Therefore, the wiring 113 is a signal line or an inverted clock signal line (hereinafter referred to as an inverted clock signal line). It is possible for the line to function as a clock line or an inverted clock supply line.

[0072] As an example, a voltage V2 is supplied to the wiring 114. The voltage V2 is a high level It is often approximately equal to the signal of the power supply voltage, reference voltage, or positive power supply voltage. Therefore, the wiring 114 can function as a power supply line. It is possible to do this.

[0073] As an example, a signal SP1 is input to the wiring 115_1. For example, the signal may have a first voltage state and a second voltage state. SP1 is often a digital signal that goes high and low, and is used as a start signal. Therefore, the wiring 115_1 can function as a signal line. However, it is not limited to this. For example, it is possible to have a plurality of semiconductor devices. When the devices are connected in cascade, the wiring 115_1 is connected to the wiring 111 of another stage (for example, the previous stage), or The wiring 115_1 can be connected to other wirings. It is possible for the signal line to function as a gate signal line or a scanning line. Signal SP1 can function as a transfer signal, a gate signal, or a scanning signal. do.

[0074] As an example, a signal SP2 is input to the wiring 115_2. For example, the signal may have a first voltage state and a second voltage state. SP2 is often a digital signal and may function as a start signal. Therefore, the wiring 115_2 can function as a signal line. However, this is not limiting. For example, when a plurality of semiconductor devices are connected in series, the wiring 1 15_2 may be connected to the wiring 111 of another stage (for example, the previous stage) or other wiring. Therefore, the wiring 115_2 can be used as an output signal line, a gate signal line, or a scanning line. In this case, the signal SP2 can have the functions of a transfer signal, a gate signal, and the like. It is possible for the signal to function as a signal or a scanning signal.

[0075] For example, a signal SEL1 is input to the wiring 116_1. may be, for example, a signal having a first voltage state and a second voltage state. The signal SEL1 changes between a high level and a low level every certain period (for example, every frame period). It is often a digital signal that alternates between two voltage states, and is used as a control signal or clock signal. Therefore, the wiring 116_1 can function as a signal line, a control line, Alternatively, it can have a function as a clock signal line.

[0076] As an example, the signal SEL2 is input to the wiring 116_2. may be, for example, a signal having a first voltage state and a second voltage state. The signal SEL2 changes between a high level and a low level every certain period (for example, every frame period). In many cases, the signal SEL2 is a digital signal that alternates between two states. It is often an inverted signal of EL1 or a signal that is 180° out of phase with signal SEL1. It can function as a control signal or an inverted clock signal. It can function as a line, a control line, or an inverted clock signal line.

[0077] For example, a signal RE is input to the wiring 117. The signal RE is, for example, It can be a signal having one voltage state and a second voltage state. For example, the signal RE can be It is often a digital signal and can function as a reset signal. Therefore, the wiring 117 can function as a signal line. For example, when a plurality of semiconductor devices are connected in series, the wiring 117 may be connected to another stage. It is possible to connect to the wiring 111 (for example, in the next stage) or other wiring. The wiring 117 may function as an output signal line, a gate signal line, or a scanning line. In such a case, the signal RE may be used as a transfer signal, a gate signal, or a scanning signal. It is possible to have the following functions.

[0078] As an example, a voltage V1 is supplied to the wiring 118. The voltage V1 is a low level. It is often roughly equal to the signal in the Therefore, the wiring 118 can function as a power supply line, Alternatively, it can have a function as a ground.

[0079] However, the present invention is not limited to this, and may include wiring 111, wiring 112, wiring 113, wiring 114, wiring 1 15_1, wiring 115_2, wiring 116_1, wiring 116_2, wiring 117, and wiring 1 Various signals or voltages can be input to the 18. Wiring can have many other functions and does not have to have all of the above functions. There's no need.

[0080] The term "generally" refers to errors due to noise, process variations, and the manufacturing process of the element. This includes various errors such as errors due to variations in process and / or measurement errors.

[0081] Generally, voltage refers to the potential difference between two points, and potential refers to the The electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a point In an electronic circuit, the potential at a certain point is referred to as a reference. Since the difference between the potential (for example, ground potential) and the voltage at a certain point is often expressed as the voltage at that point, Unless otherwise specified, when referring to a voltage at a certain point, it refers to the potential at that point. It indicates the difference from the reference potential.

[0082] As an example, the first voltage state, i.e., the voltage of the low-level signal, is V1, and the second voltage state is V2. The voltage state of this signal, that is, the voltage of the high level signal, is V2. And, V2>V1. Therefore, when the voltage V1 is written, the voltage V1 is approximately equal to the low level of the signal. On the other hand, when describing voltage V2, voltage V2 is the high level of the signal. However, it is not limited to this and may be a low-level signal. The voltage at V1 can be lower than V2 or higher than V3. Alternatively, the voltage of the high level signal can be lower than V2, or For example, depending on the circuit configuration, Even if V2 is higher than V1, the voltage may be lower than V2 or higher than V2. Depending on the circuit configuration, even if it is described as a low-level signal, its voltage may be lower than V1. Sometimes it may be higher than V1.

[0083] It should be noted that the signal CK1 and / or the signal CK2 can be balanced or unbalanced. Balanced means that only a few pulses in one cycle are at a high level. The non-equilibrium state means that the period when the signal is at a high level is roughly equal to the period when the signal is at a low level. This means that the period during which the signal is at a high level is different from the period during which the signal is at a low level. It is assumed to be outside the range of cases where they are approximately equal.

[0084] When the signals CK1 and CK2 are unbalanced, the signal CK2 is the inverse of the signal CK1. In this case, the period when the signal CK1 is at a high level and the period when the signal CK The length of the period when 2 is at a high level and the length of This is not limited to this.

[0085] Next, the functions of each circuit and each transistor will be described.

[0086] For example, the circuit 100 changes the voltage state of the signal OUT in accordance with the signal input from the circuit 200. Alternatively, the circuit 100 may have a function of setting the voltage of the node 11 and / or the The transistor 112 has a function of controlling the conduction state between the wiring 112 and the wiring 111 in accordance with the voltage of the node 12 . Alternatively, the circuit 100 may have a function of controlling the timing at which the voltage of the wiring 112 is supplied to the wiring 111. For example, a voltage such as a voltage V2 or a signal such as a signal CK1 is applied to the wiring 112. When supplied, the circuit 100 transfers the voltage or signal supplied to the wiring 112 to the wiring 11 The circuit 100 has a function of controlling the timing of supplying a high-level signal to the The timing at which a signal (for example, signal CK1) is supplied to the wiring 111 is controlled. The circuit 100 has a function of controlling the timing of raising the voltage of the wiring 111 to, for example, V2. Alternatively, the circuit 100 may transmit a low-level signal (for example, the signal CK1) to the wiring 111. Alternatively, the circuit 100 has a function of controlling the timing at which the voltage of the wiring 111 is supplied to the Alternatively, the circuit 100 may have a function of controlling the timing at which the voltage V is reduced to, for example, V1. The circuit 100 has a function of maintaining the voltage of the line 111. Alternatively, the circuit 100 may be configured to / or raising the voltage at node 12 above V2 by bootstrapping As described above, the circuit 100 includes a control circuit, a buffer, and a It can have the function of a circuit, a switch, etc. However, it is not limited to this. In addition, the circuit 100 can have various other functions. , it is not necessary to have all of the above functions.

[0087] As an example, the circuit 200 receives at least two signals and selectively outputs the input signals. Alternatively, the circuit 200 has a function of outputting an input signal or voltage (signal CK2, signal SP1, signal SP2, signal RE, the voltage at node 11, the voltage at node 12, and / or , signal OUT, etc.), the voltage at node 11, the voltage at node 12, and / or the wiring Alternatively, the circuit 200 may have a function of controlling the voltage of the node 11 and / or The node 12 has a function of controlling the timing of supplying a high-level signal or voltage V2. Alternatively, the circuit 200 may apply a low-level signal to the node 11 and / or the node 12. Alternatively, the circuit 200 may have a function of controlling the timing of supplying the voltage V1. It has a function of not supplying a signal or voltage to the node 11 and / or the node 12. The circuit 200 has a function of making the node 11 and / or the node 12 floating. Alternatively, the circuit 200 may supply a low-level signal or voltage V1 to the wiring 111. Alternatively, the circuit 200 may reduce the voltage of the wiring 111 to, for example, V1. Alternatively, the circuit 200 has a function of controlling the timing at which the voltage of the wiring 111 is maintained. As described above, the circuit 200 has a function as a control circuit. However, the circuit 200 is not limited to this and may have various other functions. It is possible to implement the following. Note that the circuit 200 does not necessarily have all of the above functions.

[0088] For example, the transistor 101_1 is connected to the wiring 112 in response to the voltage of the node 11. The transistor 101_1 has a function of controlling electrical continuity between the wiring 111 and the transistor 101_2. The timing at which the voltage of the wiring 111 is supplied to the wiring 112 is controlled. When a voltage such as voltage V2 or a signal such as signal CK1 is applied to transistor 12, The terminal 101_1 supplies a voltage or a signal supplied to the wiring 112 to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of a high-level signal. The timing at which a signal (for example, a signal CK1) is supplied to the wiring 111 is controlled. The transistor 101_1 has a function of controlling the timing of increasing the voltage of the wiring 111. Alternatively, the transistor 101_1 may output a low-level signal (for example, a signal CK1). The transistor 101 has a function of controlling the timing of supplying the signal to the wiring 111. 1 controls the timing of reducing the voltage on line 111 to, for example, V1, i.e., V1 The transistor 101_1 has a function of controlling the setting of the voltage of the wiring 111 to the The transistor 101_1 has a function of maintaining the voltage of the wiring 111. Alternatively, the transistor 101_1 has a function of performing a strap operation. It has the function of raising the pressure to, for example, V2 or above by bootstrap operation, or Transistor 101_1 sets the voltage state of signal OUT by being turned on or off. As described above, the transistor 101_1 has a function of controlling whether or not the buffer It is possible for the device to have functions such as a power supply circuit or a switch. However, this is not limited to this. The transistor 101_1 may have various other functions. The transistor 101_1 does not need to have all of the above functions.

[0089] For example, the transistor 101_2 is connected to the wiring 112 in response to the voltage of the node 12. The transistor 101_2 has a function of controlling electrical continuity between the wiring 111 and the transistor 101_3. The timing at which the voltage of the wiring 111 is supplied to the wiring 112 is controlled. When a voltage such as voltage V2 or a signal such as signal CK1 is applied to transistor 12, The terminal 101_2 supplies a voltage or a signal supplied to the wiring 112 to the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the timing of a high-level signal. The timing at which a signal (for example, a signal CK1) is supplied to the wiring 111 is controlled. The transistor 101_2 determines the timing to raise the voltage of the wiring 111 to, for example, V2. Alternatively, the transistor 101_2 has a function of controlling a low-level signal (for example, a signal The transistor 111 has a function of controlling the timing of supplying a signal CK1 to the wiring 111. The starter 101_2 controls the timing of reducing the voltage of the wiring 111 to, for example, V1. That is, it has a function of controlling the setting of the voltage of the wiring 111 to V1. The transistor 101_2 has a function of maintaining the voltage of the wiring 111. The transistor 101_2 has a function of performing a bootstrap operation. It has a function to raise the voltage of the board 12 to, for example, V2 or higher by bootstrap operation. Alternatively, the transistor 101_2 is turned on or off to control the output of the signal OUT. As described above, the transistor 101 has a function of controlling whether or not to set the voltage state. _2 can function as a buffer circuit, a switch, etc. However, the transistor 101_2 is not limited to this, and may have various other functions. It should be noted that the transistor 101_2 does not necessarily have all of the above functions.

[0090] Next, the operation of the semiconductor device of FIG. 1A will be described with reference to a timing chart of FIG. The timing chart of FIG. 2 shows signals SEL1, SEL2, CK1, and Signal CK2, signal SP1, signal SP2, signal RE, voltage at node 11 (Va1), voltage at node 1 2 (Va2), and the signal OUT. It is not limited to the timing chart and can be controlled by various timings. do.

[0091] The timing chart in FIG. 2 shows a plurality of periods (hereinafter, a period is also called a frame period). Each period has a plurality of sub-periods (hereinafter, a sub-period is referred to as one gate selection period). For example, the timing chart in FIG. 2 includes a period T1 and a period T2. The period T1 includes a period A1, a period B1, a period C1, a period D1, and a period The period T2 has a plurality of sub-periods, namely, period E1, period A2, period B2, period C2, period However, the present invention is not limited to this. For example, For example, the timing chart of FIG. 2 may have a period other than the period T1 and the period T2. It is possible to omit either the period T1 or the period T2. 1 can have various periods other than the periods A1 to E1, and the periods A1 to E1 Alternatively, the period T2 may be extended to include various periods other than the periods A2 to E2. It is possible to have various periods, and it is possible to omit any of the periods A2 to E2. is.

[0092] As an example, the periods T1 and T2 are alternately arranged. However, the order of the periods T1 and T2 is not limited to this, and the periods T1 and T2 can be arranged in various orders.

[0093] As an example, in the period T1, the period A1, the period B1, and the period C1 are arranged in this order. After this, the period D1 and the period E1 continue until the end of the period T1 (or until the beginning of the period T2). However, the present invention is not limited to this, and the periods A1 to E1 may be arranged in various orders. For example, from the beginning of period T1 to the beginning of period A1 The period may include a period D1 and / or a period E1.

[0094] As an example, in the period T2, the period A2, the period B2, and the period C2 are arranged in this order. After this, until the end of period T2 (or until the beginning of period T1), periods D2 and E2 However, the present invention is not limited to this, and the periods A2 to E2 may be arranged in various orders. For example, the period from the beginning of period T2 to the beginning of period A2 can be arranged as follows: It is possible to place a period D2 and / or a period E2 in between.

[0095] First, the operation in the period T1 will be described. In the period T1, the signal SP1 is The signal SP2 is at a high level during the period A1 to B2, and at a low level during the period B1 to E1. The signal SEL1 goes to a high level during the period E1. L2 goes to low level.

[0096] During the period A1, as shown in FIG. 3(A), the signal SP1 becomes high level, so that the circuit 200 supplies voltage V2, or a high level signal, to node 11. At this time, the signal SP2 goes low, so the circuit 200 , a voltage V1 or a low level signal is supplied to node 12. Therefore, the voltage of node 12 is , V1. Alternatively, the circuit 200 does not provide a voltage or signal to the node 12, and the circuit 2 00 and node 12 are in a non-conductive state. Therefore, if the initial value of the voltage of node 12 is V1, Then, the voltage of the node 12 is maintained at V1. As a result, the transistor 101_2 is turned on. After that, the voltage at node 11 continues to rise. The voltage of node 11 is V1+Vth101_1 (Vth101_1: transistor 101_ When the voltage Vx reaches the threshold voltage (Vth) of the transistor 101_1+Vx, the transistor 101_1 turns on. The Vx is a value greater than 0. Therefore, the wiring 112 and the wiring 111 are connected to the transistor 1. Since the signal CK1 is in a conductive state through the wiring 112, the signal CK1 at a low level is transmitted to the wiring 112. As a result, the signal OUT is supplied to the wiring 111 through the low level transistor 101_1. After that, the voltage at node 11 rises further. Eventually, the circuit 200 The supply of voltage or signal to node 11 is stopped, so that circuit 200 and node 11 are in a non-conductive state. As a result, the node 11 is in a floating state, and the voltage of the node 11 is V1+Vth1 For example, the circuit 200 may be configured to maintain a voltage V It is possible to continue supplying a voltage of 1+Vth101_1+Vx to node 11.

[0097] Note that during the period A1, the circuit 200 supplies the voltage V1 or a low-level signal to the wiring 111. Alternatively, the circuit 200 can supply a voltage, a signal, or the like to the wiring 111. It is possible not to.

[0098] Next, during period B1, as shown in FIG. 3(B), signal SP1 goes low. Therefore, the circuit 200 does not provide any voltage or signal to the node 11. The voltage at node 11 is left floating and the voltage at node 11 is V1 + Vth101_1 + Vx That is, the transistor 101_1 remains on, so the wiring 112 and The signal S Since P2 remains low, the circuit 200 applies voltage V1 or a low signal to node Alternatively, the circuit 200 may be configured to supply a voltage or signal to the node 12 without supplying a voltage or signal to the node 12. Path 200 and node 12 are in a non-conductive state. Therefore, the voltage at node 12 becomes V1. As a result, the transistor 101_2 remains off. As the signal CK1 rises from low level to high level, the voltage on the wiring 111 begins to rise. Then, since node 11 is left floating, the voltage at node 11 is This rises due to the parasitic capacitance between the gate of O1_1 and the second terminal. Thus, the voltage at node 11 becomes V2+Vth101_1+Vx. This allows the voltage on the line 111 to rise to a value greater than V2. In this way, the signal OUT goes high.

[0099] Note that during the period B1, the circuit 200 does not supply a voltage, a signal, or the like to the wiring 111. However, the circuit 200 is not limited to this. It is possible to supply a signal or the like to the wiring 111.

[0100] Next, in a period C1, as shown in FIG. 3(C), the signal RE becomes high level, The circuit 200 supplies a voltage V1 or a low level signal to the node 11, the node 12, and / or The voltage at the node 11, the voltage at the node 12, and / or the voltage at the wiring 111 are supplied to the wiring 111. The voltage of the line 111 becomes V1. Therefore, the transistor 101_1 and the transistor 1 Since the signal 01_2 is turned off, the wiring 112 and the wiring 111 are in a non-conductive state. The signal OUT goes low.

[0101] In the period C1, the signal CK1 becomes higher than the timing at which the voltage of the node 11 decreases. In other words, the timing when the transistor 101_1 becomes low may be earlier. Before turning off, the signal CK1 may become low level. When CK1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_1, In such a case, the channel width of the transistor 101_1 is, for example, When a signal OUP has a channel width larger than that of other transistors, Therefore, in the period C1, the fall time of the circuit 200 When the signal or voltage V1 is supplied to the wiring 111, the signal or voltage V2 is supplied to the wiring 112. When a low-level signal is supplied to the wiring 111 via the resistor 101_1, A signal or voltage V1 of a low level to a low level is supplied to the wiring 111, and a transistor is supplied from the wiring 112. There is a case where a low level signal is supplied to the wiring 111 via the transistor 101_1.

[0102] Next, in the periods D1 and E1, as shown in FIG. 3D, the circuit 200 V1 or a low-level signal is supplied to the node 11, the node 12, and / or the wiring 111. Then, the voltage of the node 11, the voltage of the node 12, and / or the voltage of the wiring 111 are as follows: Therefore, the transistor 101_1 and the transistor 101_2 are turned on. Therefore, the wiring 112 and the wiring 111 remain in a non-conductive state. The signal OUT remains at a low level.

[0103] In addition, during one of the periods D1 and E1, the circuit 200 supplies the voltage V1 or The signal of the bell is supplied to the node 11, the node 12, and / or the wiring 111, and during the other period, In this case, the circuit 200 supplies a voltage V1 or a low level signal to the nodes 11, 12, and Alternatively, it is possible not to supply the wiring 111 .

[0104] Next, the operation during the period T2 will be described. During the period T2, the signal SP1 is The signal SP2 goes to a low level during period A2 and goes to a high level during period B. The signal SEL1 goes low and the signal SEL2 goes low. Become a high level.

[0105] During the period A2, as shown in FIG. 4(A), the signal SP2 becomes high level, so that the circuit 200 supplies voltage V2, or a high level signal, to node 12. At this time, the signal SP1 goes low, so the circuit 200 , a voltage V1 or a low level signal is supplied to node 11. Therefore, the voltage of node 11 is , V1. Alternatively, the circuit 200 may be configured to operate without supplying a voltage or signal to the node 11. 200 and node 11 are in a non-conductive state. Therefore, let us assume that the initial value of node 11 is V1. As a result, the voltage at node 11 is maintained at V1, and transistor 101_1 is turned off. After that, the voltage at node 12 continues to rise. Eventually, the voltage at node 12 reaches V1+ Vth101_2 (Vth101_2: threshold voltage of transistor 101_2) + Vx At this time, Vx is greater than 0, and Therefore, the wiring 112 and the wiring 111 are electrically connected to each other through the transistor 101_2. Therefore, the low-level signal CK1 is transmitted from the wiring 112 through the transistor 101_2. As a result, the signal OUT becomes low level. The voltage at node 12 continues to rise. Eventually, circuit 200 detects the voltage or signal at node 12. By removing the supply, the circuit 200 is in a non-conductive state with respect to node 12. 2 is floating and the voltage at node 12 is maintained at V1 + Vth101_2 + Vx. However, the present invention is not limited to this. For example, the circuit 200 may be configured as follows: V1+Vth101_2+V The voltage at x can continue to be applied to node 12.

[0106] Note that during the period A2, the circuit 200 supplies the voltage V1 or a low-level signal to the wiring 111. Alternatively, the circuit 200 can supply a voltage, a signal, or the like to the wiring 111. It is possible not to.

[0107] Next, during period B2, as shown in FIG. 4(B), signal SP2 goes low. , the circuit 200 remains without supplying any voltage or signal to the node 12. Node 12 is left floating and the voltage at node 12 is V1 + Vth101_2 + Vx That is, the transistor 101_2 remains on, so the wiring 112 and The signal S Since P1 remains low, the circuit 200 applies voltage V1 or a low signal to node Alternatively, the circuit 200 may not supply a voltage or signal to the node 11. The path 200 and the node 11 are in a non-conductive state. Therefore, the voltage at the node 11 becomes V1. As a result, the transistor 101_1 remains off. As the signal CK1 rises from low level to high level, the voltage on the wiring 111 begins to rise. Then, since node 12 is left floating, the voltage at node 12 is This rises due to the parasitic capacitance between the gate of O1_2 and the second terminal. Thus, the voltage at node 12 becomes V2 + Vth101_2 + Vx. By increasing the voltage on the wiring 111 to a value greater than V2, Thus, the signal OUT goes high.

[0108] Note that during the period B2, the circuit 200 does not supply a voltage, a signal, or the like to the wiring 111. However, the circuit 200 is not limited to this. A signal can be provided on line 111.

[0109] Next, in a period C2, as shown in FIG. 4(C), the signal RE becomes high level, The circuit 200 supplies a voltage V1 or a low level signal to the node 11, the node 12, and / or The voltage at the node 11, the voltage at the node 12, and / or the voltage at the wiring 111 are supplied to the wiring 111. The voltage of the line 111 becomes V1. Therefore, the transistor 101_1 and the transistor 1 Since the signal 01_2 is turned off, the wiring 112 and the wiring 111 are in a non-conductive state. The signal OUT goes low.

[0110] In the period C2, the signal CK1 becomes low before the node 12 decreases. In other words, the timing when the transistor 101_2 turns off may be earlier. Therefore, the signal CK1 may become low before the may be supplied from the wiring 112 to the wiring 111 through the transistor 101_2. In such a case, the channel width of the transistor 101_2 is set to, for example, When the transistor has a channel width larger than that of other transistors, the signal OUT Therefore, during the period C2, the voltage is output from the circuit 200. When a high-level signal or voltage V1 is supplied to the wiring 111, a transistor is connected to the wiring 112. When a low-level signal is supplied to the wiring 111 via the first gate 101_2, and when a low-level signal is supplied to the wiring 111 via the first gate 101_3, a A low level signal or voltage V1 is supplied to the wiring 111 from the In some cases, a low-level signal is supplied to the wiring 111 via the resistor 101_2.

[0111] Next, in the period D2 and the period E2, as shown in FIG. 4D, the circuit 200 V1 or a low-level signal is supplied to the node 11, the node 12, and / or the wiring 111. Then, the voltage of the node 11, the voltage of the node 12, and / or the voltage of the wiring 111 are as follows: Therefore, the transistor 101_1 and the transistor 101_2 are turned on. Therefore, the wiring 112 and the wiring 111 remain in a non-conductive state. The signal OUT remains at a low level.

[0112] Note that the circuit 200 only applies the voltage V1 or the voltage V2 during either the period D2 or the period E2. A high-level signal can be supplied to the node 11, the node 12, and / or the wiring 111. It is Noh.

[0113] As described above, in the period T1, the transistor 101_2 is turned off, and in the period T2, Therefore, the transistor 101_1 can be turned off. The number of times that transistors 101_1 and 101_2 are turned on, respectively, or the number of times that transistor 1 The time that the transistors 01_1 and 101_2 are turned on can be reduced. Therefore, the deterioration of the characteristics of the transistors 101_1 and 101_2 can be suppressed. It is possible.

[0114] Alternatively, various benefits can be obtained by suppressing the deterioration of transistor characteristics. For example, when the wiring 111 functions as a gate signal line or a scan line, When the wiring 111 is connected to the pixel, the video signal held by the pixel has a waveform similar to that of the signal OUT. For example, the high-level voltage of the OUT signal may not rise to V2. In this case, the transistors (e.g., selection transistors or switching transistors) included in the pixels This results in insufficient video signal being written to the pixel. This may result in a drop in display quality. If the rise time is long, the pixels belonging to the selected row will not be biased to pixels belonging to another row. This may result in a decrease in display quality. If the fall time of the signal OUT varies, the feed to the video signal held by the pixel The effect of through may vary, resulting in uneven display such as crosstalk. It ends up happening.

[0115] However, the semiconductor device of this embodiment can suppress the deterioration of the transistor characteristics. Therefore, the high level voltage of the signal OUT can be increased to V2. This allows the transistor in the pixel to be turned on for a longer period of time. This allows for a sufficient time for writing video signals, improving display quality. Alternatively, the fall time and rise time of the signal OUT can be shortened. Therefore, the video signal for the pixels in a selected row is written to the pixels in another row. As a result, the display quality can be improved. Or, since the variation in the fall time of the signal OUT can be suppressed, the pixel is maintained. This reduces the variation in the effect of feedthrough on the video signal being held. Display unevenness can be suppressed.

[0116] Alternatively, in the semiconductor device of this embodiment, the polarity of all the transistors is set to N-channel type or P-channel type. By making the polarity of all the transistors the same, Compared to CMOS circuits, it reduces the number of processes, improves yield, improves reliability, or reduces costs. In particular, all transistors, including those in the pixel section, are N-channel. In the case of the quartz type, the semiconductor layer of the transistor is made of amorphous semiconductor, microcrystalline semiconductor, or organic semiconductor. However, it is possible to use a semiconductor such as a silicon dioxide semiconductor or an oxide semiconductor. Transistors are often prone to deterioration. However, the semiconductor device of this embodiment This can suppress deterioration of the star.

[0117] Alternatively, the transistor may be degraded so that the semiconductor device can continue to operate. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of this embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0118] In the period T1, the transistor 101_1 is turned on (period A1 and period The period B1) is called the first period or the first sub-period, during which the transistor 101_1 is turned off. Calling the periods (period C1, period D1, and period E1) second periods or second sub-periods Similarly, in the period T2, the period when the transistor 101_2 is turned on ( The period A2 and the period B2 are called the third period or the third sub-period, and the transistor 101 The periods during which _2 is off (periods C2, D2, and E2) are called the fourth period or the fourth subperiod. This can be called a sub-period.

[0119] It should be noted that the periods (periods A1 and B1) during which the transistor 101_1 is turned on are In many cases, this is shorter than the period (period C1 to E1) during which the resistor 101_1 is turned off. During the periods (periods A2 and B2) when the transistor 101_2 is turned on, This is often shorter than the period during which O1_2 is off (period C2 to E2). The period during which the transistor 101_1 is on and the period during which the transistor 101_2 is on are roughly In most cases, the breasts are of equal length, but this is not the only option.

[0120] In the period T1, the period B1 functions as a selection period, and the periods A1 and C 1, period D1, and period E1 can function as non-selection periods. In the period T2, the period B2 functions as a selection period, and the periods A2 and C2 , period D2, and period E2 can function as non-selection periods.

[0121] In addition, Period A1 and Period A2 function as a set period or a start period. The period B1 and the period B2 can function as a selection period. Alternatively, the periods C1 and C2 may function as reset periods. do.

[0122] Note that the period T1 and the period T2 can function as a frame period. It is preferable that the frame frequency is approximately 60 Hz (or 50 Hz). However, this is not limiting. For example, the frame frequency can be increased to more than 60 Hz. Therefore, blurring of moving images or afterimages can be improved. However, if the frame frequency is high, If it is too high, the drive frequency will be high, which will increase the power consumption. To suppress this increase, the frame frequency must be between 60Hz and 360Hz. It is preferable that the frequency is 60 Hz or more and 240 Hz or less. Preferably, the frame frequency is between 60 Hz and 120 Hz. By keeping the frequency below 60 Hz, the external circuitry can be simplified. Also, power consumption can be reduced. However, if the frame frequency is too slow, the pixel storage capacitance will increase, Therefore, in order to prevent the decrease in the aperture ratio, the frame frequency The frequency is preferably 15 Hz or more and 60 Hz or less. It is preferable that the frequency is 0 Hz or less.

[0123] The periods A1 to E1 and the periods A2 to E2 are sub-periods or one gate selection period. It is possible to have the following functions.

[0124] Note that a period or sub-period can be referred to as a step, a process, or an operation. For example, a first period may refer to a first step, a first process, or a first action. It can be rephrased as "creation."

[0125] In the period T1, the period D1 and the period E1 are alternately arranged before the period A1. In the period T2, when the period D2 and the period E2 are alternately arranged before the period A2, The time from the start time of T1 to the start time of period A1 is the time from the start time of period T2 to the start time of period A1. It is preferable that the time is roughly equal to the start time of A2. However, this is not limited to this. stomach.

[0126] Note that the signals CK1 and CK2 can be unbalanced. For example, the period during which the signal is at a high level is shorter than the period during which the signal is at a low level in one cycle. In this way, in the period C1 or the period C2, Therefore, it becomes possible to supply a low-level signal CK1 to the wiring 111. In particular, the line 111 is formed to extend to the pixel portion. When this is done, it is possible to prevent the writing of incorrect video signals to the pixels. However, the period in one cycle when the signal is at a high level is longer than the period when the signal is at a low level. It is possible to do this.

[0127] It is possible to use a multiphase clock signal in a semiconductor device. The device can use an n-phase clock signal (n is a natural number equal to or greater than 2). The clock signal is a set of n clock signals, each with a 1 / n period difference. FIG. 5B shows an example of a timing diagram when a three-phase clock signal is used in a semiconductor device. The timing charts shown are, but are not limited to,

[0128] The larger n is, the lower the clock frequency becomes, which can reduce power consumption. However, if n is too large, the number of signals increases, which increases the layout area. Therefore, n<8 is required. It is preferable that n<6. It is even more preferable that n=4. Alternatively, n=3 is preferred, but the present invention is not limited to this.

[0129] The transistor 101_1 and the transistor 101_2 may be turned on at the same time. In this case, for example, the circuit 200 applies a voltage V It is possible to provide a 2 or high level signal.

[0130] The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the degree of deterioration of the selected transistors can be made roughly equal. Even if the signal is switched, the waveform of the signal OUT can be made roughly the same. Therefore, the channel length of the transistor 101_1 and the channel length of the transistor 101_2 are It is preferable that the values ​​of the transistors 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 1 The channel width of transistor 101_1 and the channel width of transistor 101_2 can be different. Alternatively, the channel length of the transistor 101_1 and the channel length of the transistor 101_2 It is possible that the above may be different.

[0131] When describing the channel width of a transistor, it is expressed as W / L (W is the channel It can be rephrased as:

[0132] The transistors 101_1 and 101_2 are connected to large circuits such as gate signal lines. Since the transistor 101_1 drives a large load, the channel width of the transistor 101_1 and the The channel width of transistor _2 is preferably larger than the channel width of other transistors. For example, The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are 1 It is preferable that the thickness is 2000 μm to 30000 μm. It is more preferable that the thickness is 3000 μm to 8000 μm, or It is preferable that the thickness is 10,000 μm to 18,000 μm. However, it is not limited to this. .

[0133] As shown in FIG. 1B, the circuit 100 includes transistors 101_1 to 101_N ( It is possible to have multiple transistors (N is a natural number greater than or equal to 2). The first terminals of the transistors 101_1 to 101_N are connected to the wiring 112. The second terminals of the transistors 101_1 to 101_N are connected to the wiring 111. The gates of the transistors 101_1 to 101_N are connected to the circuit 200. The connection points between the gates of the transistors .gtoreq.N and the circuit 200 are denoted as nodes 11 to 1N, respectively.

[0134] Note that a large N reduces the number of times each transistor is turned on, or This reduces the time that each transistor is on. However, if N is too large, The number of transistors increases too much, and the circuit scale becomes large. Therefore, N is It is preferably 6 or less, more preferably 4 or less, and even more preferably It is more preferable that N=2 or N=3.

[0135] As in FIG. 1B, the circuit 100 in the configuration described in FIG. 1A also includes a transistor. It is possible to have a plurality of transistors 101_1 to 101_N.

[0136] As shown in FIG. 1C, the first terminal of the transistor 101_1 and the second terminal of the transistor 10 The first terminals of the first and second terminals 1_2 can be connected to separate wirings. In this case, the wiring 112 is divided into a plurality of wirings 112A to 112B. The first terminal of the transistor 101_1 is connected to the wiring 112A, and the second terminal of the transistor 101_2 is connected to the wiring 112B. The first terminal is connected to the wiring 112B. However, this is not limitative. The first terminal of the transistor 101_1 and the first terminal of the transistor 101_2 are connected to various wirings or various The wirings 112A to 112B can be connected to the wiring 112. Therefore, the wirings 112A to 112B are connected to the signal CK 1 can be input. However, the present invention is not limited to this, and the wiring 112A to Various signals, voltages, or currents can be input to 112B. Alternatively, different voltages or different signals may be supplied to the wiring 112A and the wiring 112B. It is possible.

[0137] As in FIG. 1C, in the configuration described in FIGS. 1A to 1B, the circuit 100 Transistors (for example, transistors 101_1 to 101_2, or transistor 1 The first terminals of the first electrodes 01_1 to 101_N can be connected to separate wirings.

[0138] As shown in FIG. 1D, a capacitance is formed between the gate and the second terminal of the transistor 101_1. A capacitance element 102_1 is connected between the gate and the second terminal of the transistor 101_2. By doing so, the bootstrap operation can be During operation, the voltage at node 11 or the voltage at node 12 tends to rise. Since the Vgs of the transistors 101_1 and 101_2 can be increased, Therefore, the channel width of these transistors can be reduced. The fall time or rise time can be shortened. However, it is not limited to this. , one of the capacitor 102_1 and the capacitor 102_2 can be omitted. As the capacitance element, for example, an MIS capacitance can be used.

[0139] Note that the material of one electrode of the capacitor 102_1 and the capacitor 102_2 is the same as that of the transistor. It is preferable that the gate of the transistor 101_1 and the gate of the transistor 101_2 are made of the same material. The other electrodes of the capacitors 102_1 and 102_2 are made of the same material as that of the transistor 1. 01_1 and the source or drain of the transistor 101_2. This is preferable. By doing so, the layout area can be reduced. However, the capacitance value can be increased. Various materials can be used as the material of one electrode and the other electrode of the capacitor 102_2. It is possible to use.

[0140] The capacitance value of the capacitor 102_1 and the capacitance value of the capacitor 102_2 are approximately equal. Alternatively, it is preferable that the area where one electrode and the other electrode of the capacitor 102_1 overlap with each other is The area where one electrode of the capacitor 102_2 overlaps with the other electrode is approximately equal to By doing so, even when the transistors are switched, the transistor The Vgs of the transistor 101_1 and the Vgs of the transistor 101_2 can be made approximately equal. Therefore, the waveform of the signal OUT can be made roughly the same. However, this is not limited to this. The capacitance value of the capacitor 102_1 and the capacitance value of the capacitor 102_2 are different from each other. Alternatively, the area where one electrode and the other electrode of the capacitor 102_1 overlap with each other and The area where one electrode and the other electrode of the capacitor 102_2 overlap can be different. be.

[0141] As in FIG. 1(D), in the configurations described in FIGS. 1(A) to 1(C), the transistor (For example, transistors 101_1 to 101_2 or transistors 101_1 to 101_ A capacitive element can be connected between the gate of N) and the second terminal.

[0142] As shown in FIG. 1E, the transistor 101_1 is connected to one terminal (hereinafter referred to as the positive terminal). The negative terminal of the positive electrode 11 is connected to the node 11, and the negative terminal of the negative electrode 11 is connected to the wiring 111. Similarly, the transistor 101_2, one terminal (hereinafter also referred to as the positive terminal) is connected to the node 12, and the other terminal (hereinafter also referred to as the negative electrode) is replaced with the diode 101a_2 connected to the wiring 111. However, this is not limiting. For example, as shown in FIG. 1(F), The first terminal of the transistor 101_1 is connected to the node 11, 101_1 can be configured as a diode. The first terminal of the transistor 101_2 is connected to the node 12, can be configured as a diode-connected.

[0143] As in the configurations shown in FIGS. 1(E) to 1(F), the transistor Transistors (for example, transistors 101_1 to 101_2, or transistors 101_1 to 101_N) can be replaced with a diode, and a transistor (e.g. Transistors 101_1 to 101_2 or transistors 101_1 to 101_N) as diodes. It is possible to connect the card.

[0144] As shown in FIG. 24(A), a signal for transfer can be generated separately from the signal OUT. For example, suppose multiple semiconductor devices are connected in series. In this case, the signal for transfer is The signal is not input to the gate signal line, but is input to the semiconductor device in the next stage as a start signal. Therefore, the delay or distortion of the signal for transfer is smaller than that of the signal OUT. Therefore, it is necessary to drive the semiconductor device using a signal with little delay or distortion. Therefore, the delay of the output signal of the semiconductor device can be reduced. Since the timing of inputting a signal to node 11 or node 12 can be advanced, the operating range can be shortened. In addition, in the operation of the semiconductor device shown in FIG. The waveforms of the signals between these are as shown in FIG.

[0145] To this end, the semiconductor device may include a circuit 700. The circuit 700 includes a transistor The transistor 70 has a plurality of transistors 701_1 to 701_2. 1_1 to 701_2 preferably have the same polarity as the transistors 101_1 to 101_2. Preferably, the transistor 70 is an N-channel type. However, it is not limited to this. 1_1 to 701_2 can be of the P-channel type.

[0146] A first terminal of the transistor 701_1 is connected to the wiring 112. The second terminal of the transistor 701_1 is connected to a wiring 711_1. A first terminal of the transistor 701_2 is connected to the wiring 112. The second terminal of the transistor 701_2 is connected to the wiring 711_2. The gate of the semiconductor device is connected to the node 12. The wiring 711_1 is connected to the wiring 115_1 of the semiconductor device in the next stage, for example. For example, the wiring 711_2 may be connected to the wiring 115_ of the semiconductor device in the next stage. In this case, the wiring 111 is formed to extend to the pixel portion. Alternatively, the transistors (for example, switching transistors) included in the pixels can be It is possible to connect the gate of the gate of the transistor (select transistor). Not limited.

[0147] A signal SOUT1 is output from the wiring 711_1. In many cases, the output signal of the semiconductor device is a digital signal having high and low levels. Therefore, the wiring 711_1 can function as a signal line. A signal SOUT2 is output from the wiring 711_2. When the signal SOUT2 is a digital signal having a high level and a low level, Therefore, the wiring 7 can function as an output signal for the semiconductor device. 11_2 can function as a signal line.

[0148] For example, the circuit 700 may be configured to change the voltage between the wiring 112 and the wiring 711_1 in response to the voltage of the node 11. and / or the function of controlling the conduction state of the wiring 112 and the wiring 113 depending on the voltage of the node 12. Alternatively, the circuit 700 has a function of controlling the electrical continuity between the wiring 112 and the wiring 711_2. A function of controlling the timing of supplying pressure to the wiring 711_1 and / or the wiring 711_2. For example, a voltage such as a voltage V2 or a signal such as a signal CK1 is supplied to the wiring 112. When the voltage or signal supplied to the wiring 112 is supplied to the circuit 700, the circuit 700 may transmit the voltage or signal supplied to the wiring 711. 711_1 and / or the timing of supplying the signal to the wiring 711_2. , the circuit 700 transmits a high-level signal (for example, a signal CK1) to the wiring 711_1 and / or The circuit 700 has a function of controlling the timing at which the signal is supplied to the wiring 711_2. Controlling the timing for increasing the voltage of the wiring 711_1 and / or the wiring 711_2 Alternatively, the circuit 700 may transmit a low-level signal (for example, the signal CK1) to the wiring 71. 1_1 and / or the timing of supplying the signal to the wiring 711_2. The circuit 700 may set the voltage of the wiring 711_1 and / or the wiring 711_2 to, for example, V1. Alternatively, the circuit 700 has a function of controlling the timing of the decrease. And / or the circuit 700 has a function of maintaining the voltage of the wiring 711_2. The voltage at node 11 and / or the voltage at node 12 are set to, for example, V As described above, the circuit 700 has a function of increasing the input voltage to 2 or more. It is possible for the circuit to have functions such as a path or a switch. However, it is not limited to these. The circuit 700 can also have various other functions. It is not necessary to have all of the above functions.

[0149] For example, the transistor 701_1 is connected to the wiring 112 in response to the voltage of the node 11. The transistor 701_1 has a function of controlling the conduction state between the transistor 701_1 and the transistor 711_1. The timing at which the voltage of the wiring 112 is supplied to the wiring 711_1 is controlled. For example, when a voltage such as voltage V2 or a signal such as signal CK1 is supplied to the wiring 112, The transistor 701_1 transmits a voltage or a signal supplied to the wiring 112 to a wiring 711_1. Alternatively, the transistor 701_1 has a function of controlling the timing of supplying the high A function for controlling the timing of supplying a signal of a certain level (for example, a signal CK1) to the wiring 711_1. Alternatively, the transistor 701_1 has a function of increasing the voltage of the wiring 711_1. Alternatively, the transistor 701_1 has a function of controlling the low-level signal ( For example, it has a function of controlling the timing of supplying a signal CK1 to the wiring 711_1. The transistor 701_1 reduces the voltage of the wiring 711_1 to, for example, V1. Alternatively, the transistor 701_1 has a function of controlling the voltage of the wiring 711_1. Alternatively, the transistor 701_1 may perform a bootstrap operation. Alternatively, the transistor 701_1 may be configured to bootstrap the voltage of the node 11. The transistor has the function of increasing the voltage to, for example, V2 or higher by the flip-flop operation. 701_1 can function as a buffer circuit, a switch, etc. However, the transistor 701_1 is not limited to this, and may have various other functions. It is possible to implement the following. It is not necessary for the transistor 701_1 to have all of the above functions. do not have.

[0150] For example, the transistor 701_2 is connected to the wiring 112 in response to the voltage of the node 12. The transistor 701_2 has a function of controlling the conduction state between the transistor 701_2 and the transistor 711_2. The timing at which the voltage of the line 112 is supplied to the wiring 711_2 is controlled. When a voltage such as a voltage V2 or a signal such as a signal CK1 is supplied to the wiring 112, The transistor 701_2 transmits a voltage or a signal supplied to the wiring 112 to the wiring 711_2. Alternatively, the transistor 701_2 has a function of controlling the timing of supplying the high-level A function of controlling the timing of supplying a bell signal (for example, signal CK1) to the wiring 711_2. Alternatively, the transistor 701_2 may increase the voltage of the wiring 711_2 at a timing Alternatively, the transistor 701_2 has a function of controlling the switching of the For example, it has a function of controlling the timing of supplying a signal CK1 to the wiring 711_2. The transistor 701_2 reduces the voltage of the wiring 711_2 to, for example, V1. Alternatively, the transistor 701_2 has a function of controlling the voltage of the wiring 711_2. Alternatively, the transistor 701_2 performs a bootstrap operation. Alternatively, the transistor 701_2 may function as a bootstrap As described above, the transistor 7 has a function of increasing the voltage to, for example, V2 or higher. 01_2 can have a function as a buffer circuit, a switch, or the like. However, the transistor 701_2 is not limited to this, and may have various other functions. It is possible to implement the following. It is not necessary for the transistor 701_2 to have all of the above functions. stomach.

[0151] When the signals SOUT1 and SOUT2 are used as transfer signals, The load of the wiring 711_1 and the load of the wiring 711_2 may be smaller than the load of the wiring 111. Therefore, the channel width of the transistor 701_1 is Similarly, the channel width of the transistor 701_2 is preferably smaller than the channel width of the transistor 701_3. It is preferable that the channel width of the transistor 101_2 is smaller than that of the transistor 101_2. However, this is not a limitation. It will not be done.

[0152] The channel length of the transistor 701_1 is the same as that of the transistor 101_1. Alternatively, the channel length of the transistor 701_2 can be set to be approximately equal to It can be approximately equal to the channel length of the transistor 101_2. The channel length of the transistor 701_1 is not limited to the channel length of the transistor 101_1. The channel length of the transistor 701_2 can be different from that of the transistor 701_1. The channel length of the data bus 101_1 may be different from that of the data bus 101_2.

[0153] The channel width of the transistor 701_1 and the channel width of the transistor 701_2 are The thickness is preferably 100 μm to 5000 μm. More preferably, it is 300 μm to 2 000 μm, and more preferably 500 μm to 1000 μm. However, the present invention is not limited to this.

[0154] The channel width of the transistor 701_1 and the channel width of the transistor 701_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the degree of deterioration of the signal SOUT1 and the signal SOUT2 can be made approximately equal. For the same reason, the waveform of the transformer signal SOUT1 can be made roughly the same as that of the transformer signal SOUT2. The channel length of the transistor 701_1 and the channel length of the transistor 701_2 are approximately However, it is not limited to this, and the channel of the transistor 701_1 is preferably equal to The width and the channel width of transistor 701_2 can be different.

[0155] As shown in FIG. 24B, the circuit 700 includes a transistor 7 It is possible to have multiple transistors 01_1 to 701_N. The first terminals of the transistors 701_1 to 701_N are connected to the wiring 112. The second terminals of the transistors _1 to 701_N are connected to the wirings 711_1 to 711_N, respectively. The gates of the transistors 701_1 to 701_N are connected to the nodes 11 to 1N, respectively.

[0156] As in FIG. 24B, in the configuration described in FIG. 24A, the circuit 700 It is possible to have a plurality of transistors called transistors 701_1 to 701_N. .

[0157] As shown in FIG. 24C, similarly to FIG. 1C, the first The terminal and the first terminal of the transistor 701_2 can be connected to different wirings. In the example of FIG. 1(C), the wiring 112 is divided into a plurality of wirings 112C to 112D. The first terminal of the transistor 701_1 is connected to the wiring 112C. The first terminal of the resistor 701_2 is connected to the wiring 112D. However, the present invention is not limited to this. , the first terminal of the transistor 701_1 and the first terminal of the transistor 701_2 are The wirings 112C to 112D can be connected to various wirings or various nodes. The wiring 112C to 11D can have the same function as the wiring 112. Signals such as signal CK1 can be input to 2D. However, this is not limited to this. First, various signals, various voltages, or various currents are input to the wirings 112C to 112D. It is possible.

[0158] As in the case of FIG. 24(C), in the configuration described in FIGS. 24(A) to 24(B), the circuit 70 0 (for example, transistors 701_1 to 701_2, or transistor The first terminals of the terminals 701_1 to 701_N can be connected to separate wirings.

[0159] As shown in FIG. 24(D), similarly to FIG. 1(D), the gate of the transistor 701_1 A capacitor 702_1 is connected between the gate and the second terminal of the transistor 701_2. A capacitor 702_2 can be connected between the second terminal and the capacitor 702_2.

[0160] As in FIG. 24(D), in the configurations described in FIGS. 24(A) to 24(C), the transistor transistors 701_1 to 701_2, or transistors 701_1 to 70 1_N) and the second terminal.

[0161] As shown in FIG. 24E, the transistor 701_1 is connected to the One terminal (hereinafter also referred to as the positive terminal) is connected to the node 11, and the other terminal (hereinafter also referred to as the negative terminal) is connected to the node 12. ) can be substituted for the diode 701a_1 connected to the wiring 711_1. Similarly, one terminal (hereinafter also referred to as a positive terminal) of the transistor 701_2 is connected to the node 12, and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 711_2. However, it is not limited to this. For example, For example, as shown in FIG. 24(F), similarly to FIG. 1(F), the first terminal of the transistor 701_1 By connecting the transistor 701_1 to node 11, the transistor 701_1 is diode-connected. Similarly, the first terminal of the transistor 701_2 can be connected to the node 12. By this, the transistor 701_2 can be diode-connected. .

[0162] As in the configurations shown in FIGS. 24(E) to 24(F), Transistors (for example, transistors 701_1 to 701_2, or transistors 701_ 1 to 701_N) by a diode or by a transistor (e.g., 701_1 to 701_2 or 701_1 to 701_N) are diode-connected. It is possible to configure the system so that the two components are connected in series.

[0163] (Embodiment 2) In this embodiment, a specific example of the circuit 200 described in the first embodiment will be described. The circuit 200 can be referred to as a semiconductor device or a driver circuit. The contents to be described in this embodiment are the same as those in the first embodiment. It can be freely combined with the contents described in

[0164] First, an example of the circuit 200 will be described with reference to FIG. 6A. The circuit 200 includes a circuit 300. The circuit 300 shows a part of the circuit 200. 300 can include, by way of example, one or more transistors. It is preferable that this transistor has the same polarity as the transistors 101_1 and 101_2. However, this is not limited to this.

[0165] The circuit 300 includes, for example, a wiring 115_1, a wiring 115_2, a node 11, and a node 12. However, the circuit 300 is not limited to this, and may be connected to other can be connected to various wires, various nodes, or various terminals. When the circuit 300 requires a power supply voltage, the circuit 300 is connected to the wiring 114 and and / or may be connected to the wiring 118. Alternatively, the circuit 300 may need other signals. If necessary, the circuit 300 includes the wiring 112, the wiring 113, the wiring 116_1, the wiring 116_2, the wiring 116_3, the wiring 116_4, the wiring 116_5, the wiring 116_6, the wiring 116_7, the wiring 116_8, the wiring 116_9, the wiring 116_10, the wiring 116_11, the wiring 2, can be connected to wiring 117 and / or wiring 111.

[0166] The circuit 300 may, for example, receive an input signal or voltage (e.g., signal SP1 and signal SP 2, etc.) Alternatively, the circuit 300 may provide a high level signal or The circuit 300 has a function of controlling the timing of supplying the voltage V2. 1 and / or 12, the timing of supplying a low level signal or voltage V1 Alternatively, the circuit 300 may provide a function to control the node 11 and / or the node 12. The circuit 300 has a function of selectively not supplying a signal or voltage. , and / or have the function of making the node 12 floating. However, it is not limited to this. The circuit 300 can have various other functions. It is not necessary to have all of the functions of the above.

[0167] Next, an example of the operation of the circuit 300 in FIG. 6A will be described with reference to the timing chart in FIG. and explain.

[0168] During the period A1, the signal SP1 goes high, so that the circuit 300 supplies the voltage V2 or A high-level signal is supplied to node 11. After that, the voltage of node 11 becomes V1+Vth1 When the voltage Vx reaches 01_1+Vx, the circuit 300 stops supplying the voltage or signal to the node 11. On the other hand, since the signal SP2 is at a low level, the circuit 300 does not receive the voltage V1 or the low level. Alternatively, circuit 300 may provide a signal at node 12. It is possible to supply no voltage or signal to the

[0169] During period B1, the circuit 300 remains without supplying any voltage or signal to the node 11. On the other hand, the circuit 300 supplies a voltage V1 or a low level signal to the node 12. Alternatively, the circuit 300 may not provide a voltage or signal to the node 12. It is possible.

[0170] During the period C1 to the period E1, the circuit 300 supplies a voltage V1 or a low-level signal to the node 1. Alternatively, the circuit 300 may provide a voltage or signal to the node 11. On the other hand, the circuit 300 can supply the voltage V1 or a low-level signal. Alternatively, circuit 300 may provide a voltage or signal to node 12. It is possible not to provide a number etc.

[0171] During the period A2, the signal SP1 is at a low level, so the circuit 300 receives the voltage V1 or Alternatively, circuit 300 may provide a low level signal to node 11. On the other hand, it is possible to supply no voltage or signal to the signal SP2. Therefore, circuit 300 provides voltage V2, or a high level signal, to node 12. Then, when the voltage at node 12 becomes V1+Vth101_2+Vx, the circuit 30 0 turns off the voltage or signal to node 12.

[0172] In the period B2, the circuit 300 supplies the voltage V1 or a low-level signal to the node 11. Alternatively, the circuit 300 may not provide a voltage or signal to the node 11. On the other hand, the circuit 300 does not provide a voltage or signal to the node 12. It will remain the same.

[0173] During the period C2 to the period E2, the circuit 300 supplies the voltage V1 or a low-level signal to the node 1. Alternatively, the circuit 300 may provide a voltage or signal to the node 11. On the other hand, the circuit 300 can supply the voltage V1 or a low-level signal. Alternatively, circuit 300 may provide a voltage or signal to node 12. It is possible not to provide a number etc.

[0174] Next, a specific example of the circuit 300 will be described with reference to FIG. The transistor 3 has a plurality of transistors 301_1 to 301_2. 01_1 to 301_2 must have the same polarity as transistors 101_1 to 101_2. Preferably, the transistor is an N-channel type, but is not limited to this. 01_1 to 301_2 can be of the P-channel type.

[0175] A first terminal of the transistor 301_1 is connected to the wiring 115_1. The second terminal of the transistor 301_1 is connected to the node 11. The gate of the transistor 301_1 is connected to the wiring 1. A first terminal of the transistor 301_2 is connected to the wiring 115_2. The second terminal of the transistor 301_2 is connected to the node 12, and the second terminal of the transistor 301_3 is connected to the node 12. The gate of _2 is connected to the wiring 115_2.

[0176] For example, the transistor 301_1 controls electrical continuity between the wiring 115_1 and the node 11. Alternatively, the transistor 301_1 has a function of controlling the voltage of the wiring 115_1 to the node For example, the wiring 115_1 has a function of controlling the timing at which the voltage V When a voltage such as voltage V1 or voltage V2 or a signal such as signal SP1 is supplied, the transistor The node 301_1 supplies a voltage or a signal supplied to the wiring 115_1 to the node 11. Alternatively, the transistor 301_1 has a function of controlling the timing at which the high level control the timing of supplying a signal (for example, signal SP1) or voltage V2 to node 11. Alternatively, the transistor 301_1 may be configured to increase the voltage of the node 11. Alternatively, the transistor 301_1 has a function of controlling a signal or a voltage. Alternatively, the transistor 301_1 has a function of not supplying a voltage to the node 11. As described above, the transistor 301_1 has a function of setting the transistor 301_1 in a free state. functions as a rectifying element such as a diode-connected transistor. Without being limited thereto, the transistor 301_1 can have various other functions. It should be noted that the transistor 301_1 does not need to have all of the above functions.

[0177] For example, the transistor 301_2 controls electrical continuity between the wiring 115_2 and the node 12. Alternatively, the transistor 301_2 has a function of controlling the voltage of the wiring 115_2 to the node For example, the wiring 115_2 has a function of controlling the timing at which the voltage V When a voltage such as voltage V1 or voltage V2, or a signal such as signal SP2 is supplied, the transistor The node 301_2 supplies the voltage or signal supplied to the wiring 115_2 to the node 12. Alternatively, the transistor 301_2 has a function of controlling the timing at which the high level control the timing of supplying a signal (e.g., signal SP2) or voltage V2 to node 12. Alternatively, the transistor 301_2 may be configured to increase the voltage of the node 12. Alternatively, the transistor 301_2 has a function of controlling a signal or a voltage. Alternatively, the transistor 301_2 has a function of not supplying a voltage to the node 12. As described above, the transistor 301_2 has a function of setting the transistor 301_2 in a free state. functions as a rectifying element such as a diode-connected transistor. Without being limited thereto, the transistor 301_2 can have various other functions. It should be noted that the transistor 301_2 does not need to have all of the above functions.

[0178] Next, an example of the operation of the circuit 300 in FIG. 6B will be described with reference to the timing chart in FIG. Note that a schematic diagram of the operation of the semiconductor device in the period A1 is shown in FIG. FIG. 7B shows a schematic diagram of the operation of the semiconductor device in the period B1. FIG. 7C shows a schematic diagram of the operation of the semiconductor device in the periods D1 and E1. A schematic diagram of the operation is shown in FIG. 7D. Note that a schematic diagram of the operation of the semiconductor device in the period A2 is shown in 8A, a schematic diagram of the operation of the semiconductor device in the period B2 is shown in FIG. 8B, and FIG. 8C shows a schematic diagram of the operation of the semiconductor device during the period C2. A schematic diagram of the operation of the semiconductor device is shown in FIG.

[0179] During the period A1, the signal SP1 is at a high level, so that the transistor 301_1 is turned on. Therefore, the wiring 115_1 and the node 11 are connected through the transistor 301_1. Since the signal SP1 is turned on, the high-level signal SP1 is transmitted from the wiring 115_1 to the transistor 301 This causes the voltage at node 11 to rise. , the voltage of the node 11 is equal to the voltage of the gate of the transistor 301_1 (the high level of the signal SP1) The threshold voltage (Vth301_1) of the transistor 301_1 is subtracted from the voltage (V2) of the transistor 301_1. When the voltage rises above the value (V2-Vth301_1), the transistor 301_1 turns off. Therefore, the wiring 115_1 and the node 11 are not electrically connected, and the node 11 is floating. On the other hand, since the signal SP2 is at a low level, the transistor 301_2 is in a free state. Therefore, the wiring 115_2 and the node 12 are not electrically connected to each other.

[0180] During the period B1 to E1, the signal SP1 is at a low level, so that the transistor 301_1 Therefore, the wiring 115_1 and the node 11 are not electrically connected. Since the signal SP2 is at a low level, the transistor 301_2 is turned off. 115_2 and node 12 are in a non-conductive state.

[0181] During the period A2, the signal SP1 is at a low level, so that the transistor 301_1 is turned off. Therefore, the wiring 115_1 and the node 11 are not electrically connected. 2 is at a high level, the transistor 301_2 is turned on. _2 and node 12 are in a conductive state through the transistor 301_2, so that The signal SP2 of the line 115_2 is supplied to the node 12 through the transistor 301_2. As a result, the voltage at node 12 rises. The voltage at the gate of the transistor 301_2 (the high-level voltage (V2) of the signal SP2) The value obtained by subtracting the threshold voltage (Vth301_2) of the resistor 301_2 (V2-Vth301_2 ), the transistor 301_2 is turned off. 2 and node 12 are in a non-conductive state, so node 12 is in a floating state.

[0182] During the period B2 to E2, the signal SP1 is at a low level, so that the transistor 301_1 Therefore, the wiring 115_1 and the node 11 are not electrically connected. Since the signal SP2 is at a low level, the transistor 301_2 is turned off. 115_2 and node 12 are in a non-conductive state.

[0183] As described above, the signal (for example, SP1) supplied to the wiring 115_1 and the signal (for example, SP2) supplied to the wiring 115_2 are In this way, the transistor 101_1 and the transistor 101_2 are turned on. Select whether to turn on the transistor 101_1 or the transistor 101_2. However, this is not limited to this. For example, both the signal supplied to the wiring 115_1 and the signal supplied to the wiring 115_2 may be In this case, the transistor 101_1 and the transistor Since both the wiring 112 and the wiring 111 are turned on, the wiring 112 and the wiring 111 are turned on. Therefore, the signal OU is turned on through the transistor 101_1 and the transistor 101_2 in parallel. The fall time or rise time of T can be shortened.

[0184] Since the transistors 301_1 and 301_2 have the same function, The channel width of the transistor 301_1 and the channel width of the transistor 301_2 are It is preferable that the transistor sizes are roughly equal. By doing so, the current supply capacity can be made roughly equal. Therefore, the voltage at node 11 and the voltage at node 12 can be made approximately equal. The voltage can be roughly equalized, so the waveform of the signal OUT can be roughly equalized. For the same reason, the channel length of the transistor 301_1 and the It is preferable that the channel length of the first stanza 301_1 and the channel length of the second stanza 301_2 are approximately equal. The channel width of the transistor 301_1 and the channel width of the transistor 301_2 are Alternatively, the channel length of the transistor 301_1 and the channel length of the transistor 301_2 may be different. The channel length of the register 301_1 can be different from that of the register 301_2.

[0185] The load of the transistor 301_1 (for example, node 11) is Since the load of the transistor 301_1 is smaller than the load of the other transistor (for example, the wiring 111), The channel width is preferably smaller than the channel width of the transistor 101_1. The load of transistor 301_2 (for example, node 12) is the load of transistor 101_2. Since the load (for example, the wiring 112) is often smaller than the channel of the transistor 301_2, The channel width of the transistor 101_2 is preferably smaller than the channel width of the transistor 101_3. However, the channel width of the transistor 301_1 is not limited to the above. Alternatively, the channel width of the transistor 301_2 can be larger than , can be larger than the channel width of the transistor 101_2.

[0186] The channel width of the transistor 301_1 and the channel width of the transistor 301_2 are The thickness is preferably 500 μm to 3000 μm. More preferably, it is 800 μm to 2 It is preferably 500 μm, and more preferably 1000 μm to 2000 μm. However, the present invention is not limited to this.

[0187] As shown in FIG. 9A, the gate of the transistor 301_1 and the gate of the transistor 3 The gate of 01_2 can be connected to the wiring 113. In this case, If the signal CK2 is input to the input terminal 113, the signal C Since K2 is at a high level, the transistors 301_1 and 301_2 Therefore, in the period A1, the high-level signal SP1 is supplied from the wiring 115_1 to the The low-level signal SP2 is supplied to the node 11 via the transistor 301_1. The signal is supplied from the wiring 115_2 to the node 12 through the transistor 301_2. In the period A2, the low-level signal SP1 is supplied from the wiring 115_1 to the transistor 301 _1 to the node 11, and the high level signal SP2 is transmitted from the wiring 115_2. is supplied to the node 12 via the transistor 301_2. Therefore, the voltage of node 11 or the voltage of node 12 can be fixed, which makes it resistant to noise. However, the present invention is not limited to this.

[0188] For example, the gate of the transistor 301_1 and the gate of the transistor 301_2 are arranged It is possible to connect to various wirings other than the line 113. For example, the transistor 30 The gate of transistor 301_1 and the gate of transistor 301_2 are connected to the gate of transistor 301_2 during period A1 and / or period A2, a wiring to which a high-level signal or voltage V2 is supplied (for example, wiring 114, The wiring 116_1, wiring 116_2, etc. can be connected to the wiring 116_2.

[0189] As another example, as shown in FIG. 9(B), the wiring 113 may be divided into multiple wirings 113A to 113B. The gate of the transistor 301_1 is connected to the wiring 113A. and the gate of the transistor 301_2 is connected to the wiring 113B.

[0190] As another example, as shown in FIG. 9C, the gate of the transistor 301_1 is connected to the wiring 11. The gate of the transistor 301_2 is connected to the wiring 116_2. However, the present invention is not limited to this. For example, the gate of the transistor 301_1 may be The wire to which a high-level signal or voltage V2 is supplied during the period A1 (for example, the wire 113, wiring 114, wiring 115_1, wiring 116_1, etc.) Similarly, the gate of the transistor 301_2 is set to a high level during the period A2. Wiring to which a signal or voltage V2 is supplied (for example, wiring 113, wiring 114, wiring 115_2 , or wiring 116_2, etc.).

[0191] As shown in FIG. 9D, the first terminal of the transistor 301_1 is connected to the wiring 114. The second terminal of the transistor 301_1 is connected to the node 11, and the second terminal of the transistor 301_2 is connected to the node 12. The gate of transistor 01_1 can be connected to wiring 115_1. The first terminal of the transistor 301_2 is connected to the wiring 114, and the second terminal of the transistor 301_2 is connected to the wiring 114. The gate of the transistor 301_2 is connected to a node 12, and the gate of the transistor 301_2 is connected to a wiring 115_2. In this case, during the period A1, the signal SP1 is at a high level. When the voltage V2 is applied to the wiring 114, the transistor 301_1 is turned on. If the voltage V2 is supplied from the wiring 114 to the node On the other hand, during the period A2, when the signal SP2 becomes high level, the transistor Therefore, the voltage V2 is applied from the wiring 114 to the transistor 301_2. 01_2 to node 12. However, the present invention is not limited to this.

[0192] For example, the first terminal of the transistor 301_1 and the first terminal of the transistor 301_2 are , can be connected to various wirings other than the wiring 114. For example, The first terminal of the transistor 301_1 and the transistor 301_2 are connected to each other during the period A1 and / or the period A 2, a wiring (for example, wiring 113, wiring In this case, the wiring 116_1 or the wiring 116_2 can be connected. A reverse bias can be applied to the transistor, suppressing deterioration of the transistor's characteristics. It is possible.

[0193] As another example, as shown in FIG. 9(E), the wiring 114 may be divided into multiple wirings 114A to 114B. The first terminal of the transistor 301_1 is connected to the wiring 11. 4A, and a first terminal of the transistor 301_2 is connected to the wiring 114B.

[0194] As another example, as shown in FIG. 9F, the first terminal of the transistor 301_1 may be connected to the wiring 11. 6_1, and a first terminal of the transistor 301_2 is connected to the wiring 116_2. In this case, a reverse bias can be applied to the transistor. This can suppress the deterioration of the transistor characteristics. However, this is not limited to this. For example, the first terminal of the transistor 301_1 receives a high-level signal or The wiring to which the voltage V2 is supplied (for example, the wiring 113, the wiring 114, the wiring 115_1, or the wiring Similarly, the transistor 301_2 can be connected to the line 116_1. The first terminal is connected to a wiring (for example, For example, the wiring 113, the wiring 114, the wiring 115_2, the wiring 116_2, etc. It is possible.

[0195] As shown in FIG. 1B, the circuit 100 includes transistors 101_1 to 101_N. When the circuit 300 has a plurality of transistors, the transistors are arranged as shown in FIG. It is possible to have a plurality of transistors 301_1 to 301_N. The first terminals of the transistors 301_1 to 301_N are connected to the wirings 115_1 to 115_N, respectively. The second terminals of the transistors 301_1 to 301_N are connected to the nodes 11 to 1N, respectively. The gates of the transistors 301_1 to 301_N are connected to the wiring 115_1. Connected to ~115_N.

[0196] 10(A), in the configurations described in FIGS. 9(A) to 9(F), the circuit 300 may have multiple transistors 301_1 to 301_N. FIG. 10B shows an example in which the circuit 300 in FIG. 9A is replaced with a transistor. 1 shows a configuration in which a plurality of transistors 301_1 to 301_N are included.

[0197] As shown in FIG. 10C, the wiring 115_1 and the wiring 115_2 may be shared. The second terminal and the gate of the transistor 301_2 are connected to the wiring 115_1. However, the present invention is not limited to this. For example, the second terminal and the gate of the transistor 301_1 The second terminal and the gate of the transistor 301_2 are connected to a wiring different from the wiring 115_1. It is possible to connect to the wiring that shares the same wiring. This means that two elements connected to the same wiring are connected to the same wiring. This means connecting an element connected to one wiring to the other wiring.

[0198] As in FIG. 10(C), the same applies to the cases described in FIGS. 9(A) to 9(F) and 10(A) to 10(B). In the configuration, the wiring 115_1 and the wiring 115_2 can be shared. In FIG. 10(A) to (B), the wirings 115_1 to 115_N can be shared. FIG. 10D shows an example of the wiring 115_1 and the wiring 115_2 in FIG. This shows the configuration when sharing 15_2.

[0199] As shown in FIG. 11A, the circuit 300 includes transistors 302_1 to 302_2 It is possible to have a plurality of transistors such as transistors 302_1 to 302_2. _2 preferably has the same polarity as the transistors 301_1 to 301_2, and However, the present invention is not limited to this, and the transistors 302_1 to 302_2 are also usable. _2 can be of the P-channel type.

[0200] For example, the transistor 302_1 has a function of putting the node 11 into a floating state. Alternatively, the transistor 302_1 has a function of preventing leakage of charge from the node 11. Alternatively, the transistor 302_1 has a function of preventing the voltage of the node 11 from decreasing. In this way, the transistor 302_1 is, for example, a diode or a diode-connected It functions as a rectifying element such as a transistor. However, it is not limited to this. The transistor 302_1 can have various other functions. 302_1 does not need to have all of the above functions.

[0201] Note that the transistor 302_2 has a function of putting the node 12 into a floating state, for example. Alternatively, the transistor 302_2 has a function of preventing charge leakage from the node 12. Alternatively, the transistor 302_2 has a function of preventing the voltage of the node 12 from decreasing. In this way, the transistor 302_2 is a diode or a diode-connected transistor. However, it is not limited to this and functions as a rectifying element such as a transistor. The transistor 302_2 can have various other functions. _2 does not need to have all of the above functions.

[0202] The transistor 302_1 is connected between the second terminal of the transistor 301_1 and the node 11. The transistor 302_2 is connected between the second terminal of the transistor 301_2 and the node The first terminal of the transistor 302_1 is connected between the transistor 301_1 and the The second terminal of transistor 302_1 is connected to node 11. The gate of the transistor 302_1 is connected to the second terminal of the transistor 301_1. The first terminal of the transistor 302_2 is connected to the second terminal of the transistor 301_2. , the second terminal of the transistor 302_2 is connected to the node 12, and the The gate of the transistor 301_2 is connected to the second terminal of the transistor 301_2. I can't.

[0203] As in FIG. 11(A), the same applies to the cases described in FIGS. 9(A) to 9(F) and 10(A) to 10(D). In terms of configuration, the circuit 300 includes a plurality of transistors 302_1 to 302_2. As an example, FIG. 11(B) shows the same as FIG. 9(A). The circuit 300 has a plurality of transistors 302_1 to 302_2. 11C shows an example of a configuration in which the circuit 300 in FIG. The configuration in which the transistor 302_1 to the transistor 302_2 is show.

[0204] Note that as shown in FIG. 11D, the gate of the transistor 302_1 is connected to the wiring 115_1. Alternatively, the gate of the transistor 302_2 can be connected to the wiring 115_2. However, the present invention is not limited to this, and the transistor 302_1 can be connected to the The gate of the transistor 302_1 and the gate of the transistor 302_2 are connected to various wirings or various terminals. For example, the gate of the transistor 302_1 can be connected to the gate of the transistor 302_2. Alternatively, the first terminal or gate of the transistor 302 may be connected to the first terminal or gate of the transistor 302. The gate of transistor 301_2 may be connected to the first terminal or gate of transistor 301_2. is.

[0205] 11(D), FIGS. 9(A) to 9(F), 10(A) to 10(D), and 11 In the configurations described in (A) to (C), the gate of the transistor 302_1 is The first terminal and gate of the transistor 301_1 are connected to the first terminal and gate of the transistor 302_2. It can be connected to the first terminal and gate of the transistor 301_1. As an example, in the configuration described in FIG. 11C, The gate of the transistor 302_1 is connected to the wiring 114. The configuration when this is the case is shown below.

[0206] As shown in FIG. 11F, the transistor 302_1 is The second terminal side of the transistor 301_1 is not limited to the second terminal side of the transistor 301_2, but may be connected to the first terminal side of the transistor 301_1. Alternatively, the transistor 302_2 can be connected only to the second terminal side of the transistor 301_2. It is possible to connect the first terminal of the transistor 301_2 to the first terminal side of the transistor 301_2. , the transistor 302_1 is connected between the first terminal of the transistor 301_1 and the wiring 115_1. Alternatively, the transistor 302_2 can be connected to the transistor 301_ The transistor 30 can be connected between the first terminal of the transistor 30 and the wiring 115_2. A first terminal of the transistor 302_1 is connected to the wiring 115_1, and a second terminal of the transistor 302_1 is connected to the wiring 115_1. , connected to the first terminal of the transistor 301_1, and the gate of the transistor 302_1 is The first terminal of the transistor 302_2 is connected to the wiring 115_1. The second terminal of the transistor 302_2 is connected to the first terminal of the transistor 301_2. The gate of the transistor 302_2 is connected to the wiring 115_2. This is not limited to this.

[0207] 11(F), FIGS. 9(A) to 9(F), FIGS. 10(A) to 10(D), and FIG. 11 In the configurations described in (A) to (E), the transistor 302_1 is the same as the transistor 30 1_1, and may be connected to the first terminal side of the transistor 301_1. Alternatively, the transistor 302_2 may be connected to the second terminal of the transistor 301_2. The first terminal side of the transistor 301_1 is not limited to this, and may be connected to the first terminal side of the transistor 301_2. FIG. 11(G) shows an example of a transistor 30 in the configuration shown in FIG. 11(C). 2_1 is connected between the first terminal of the transistor 301_1 and the wiring 114, and the transistor When the transistor 302_2 is connected between the first terminal of the transistor 301_2 and the wiring 114, A first terminal of the transistor 302_1 is connected to the wiring 114. The second terminal of the transistor 302_1 is connected to the first terminal of the transistor 301_1. The gate of the transistor 302_1 is connected to the wiring 114. The first terminal of the transistor 302_2 is connected to the wiring 114, and the second terminal of the transistor 302_3 is connected to the wiring 114. The gate of the transistor 302_2 is connected to the first terminal of the transistor 302_3 and the wiring 114. can be.

[0208] As shown in FIG. 12A, the circuit 300 includes transistors 303_1 to 303_2. It is possible to have a plurality of transistors such as transistors 303_1 to 303_3. _2 preferably has the same polarity as the transistors 301_1 to 301_2, and However, the present invention is not limited to this, and the transistors 303_1 to 303_3 are also of the same type. _2 can be of the P-channel type.

[0209] For example, the transistor 303_1 is connected between the wiring 118 and the node 1 in response to the signal SEL1. 2. Alternatively, the transistor 303_1 has a function of controlling electrical continuity between the wiring 118 and the The wiring 118 has a function of controlling the timing at which the voltage is supplied to the node 12. When a signal such as a voltage V1 or a signal is supplied to the 118 to control the timing of supplying the voltage or signal to the node 12. Alternatively, the transistor 303_1 may be configured to supply the voltage V1 to the node 12. Alternatively, the transistor 303_1 has a function of controlling the switching of the transistor 303_2. For example, signal SP1, signal SP2, signal SEL1, or signal SEL2) to node 12. The transistor 303_1 has a function of controlling the timing of supplying the voltage. The timing for reducing the voltage of the transformer 12 to, for example, V1 is controlled. The transistor 303_1 has a function of maintaining the voltage of the node 12. The register 303_1 can function as a switch. Without being limited thereto, the transistor 303_1 can have various other functions. It should be noted that the transistor 303_1 does not need to have all of the above functions.

[0210] For example, the transistor 303_2 is connected between the wiring 118 and the node 1 in response to the signal SEL2. Alternatively, the transistor 303_2 has a function of controlling electrical continuity between the wiring 118 and the transistor 303_2. The wiring 118 has a function of controlling the timing at which the voltage is supplied to the node 11. When a signal such as a voltage V1 or a signal is supplied to the A function for controlling the timing of supplying a voltage or signal supplied to 118 to node 11. Alternatively, the transistor 303_2 may be configured to supply the voltage V1 to the node 11. Alternatively, the transistor 303_2 has a function of controlling the switching of the For example, signal SP1, signal SP2, signal SEL1, or signal SEL2) to node 11. The transistor 303_2 has a function of controlling the timing of supplying the voltage. The timing for reducing the voltage of the transformer 11 to, for example, V1 is controlled. The transistor 303_2 has a function of maintaining the voltage of the node 11. The resistor 303_2 can function as a switch. Without being limited thereto, the transistor 303_2 can have various other functions. It should be noted that the transistor 303_2 does not need to have all of the above functions.

[0211] A first terminal of the transistor 303_1 is connected to the wiring 118. The second terminal of the transistor 303_1 is connected to the node 12, and the gate of the transistor 303_1 is connected to the wiring 116. A first terminal of the transistor 303_2 is connected to the wiring 118. The second terminal of the transistor 303_2 is connected to the node 11. The port is connected to the wiring 116_2, but is not limited to this.

[0212] The operation of the semiconductor device of FIG. 12A will be described with reference to the timing chart of FIG. Note that a schematic diagram of the operation of the semiconductor device in the period A1 is shown in FIG. 38B is a schematic diagram of the operation of the semiconductor device in the period C1. 38C is a schematic diagram of the operation of the semiconductor device in the periods D1 and E1. 38D is a schematic diagram of the operation of the semiconductor device in the period A2. 39(A) is a schematic diagram of the operation of the semiconductor device in the period B2, and FIG. 39(B) is a schematic diagram of the operation of the semiconductor device in the period B3. FIG. 39C shows a schematic diagram of the operation of the semiconductor device during the period C2. A schematic diagram of the operation of the semiconductor device in 2 is shown in FIG. 39(D). 6B and the semiconductor device of FIG. 12A are combined. A schematic diagram is shown.

[0213] During the period A1 to E1, the signal SEL1 is at a high level, so that the transistors 303_ Therefore, the wiring 118 and the node 12 are connected via the transistor 303_1. Since the transistor 303_1 is turned on, the voltage V1 is supplied from the wiring 118 to the node 303_2 through the transistor 303_1. This causes the voltage at node 12 to be maintained at V1. On the other hand, since the signal SEL2 becomes low level, the transistor 303_2 is turned off. Therefore, the wiring 118 and the node 11 are brought out of conduction.

[0214] During the periods A2 to E2, the signal SEL1 is at a low level, so that the transistors 303_ 1 is turned off, and therefore, there is no electrical continuity between the wiring 118 and the node 12. Since SEL2 is at a high level, the transistor 303_2 is turned on. 118 and node 11 are in a conducting state through transistor 303_2, so that the voltage V 1 is supplied to the node 11 from the wiring 118 through the transistor 303_2. As a result, the voltage at node 11 is maintained at V1.

[0215] In this way, even when the transistor 301_1 is off, the transistor 303_2 By turning on, the voltage at node 11 can be fixed. Even if the transistor 301_2 is off, the transistor 303_1 is turned on. , the voltage at node 12 can be fixed. Since the voltage of 12 can be fixed, a semiconductor device that is resistant to noise can be obtained.

[0216] 12(A), FIGS. 9(A) to 9(F), 10(A) to 10(D), and 11 In the configurations described in (A) to (G), the circuit 300 also includes transistors 303_1 to 303_3. 3_2. In the configuration shown in FIG. 9A, the circuit 300 includes transistors 303_1 to 303_3. FIG. 12C shows an example of a structure having a plurality of transistors, each of which is designated by . In the configuration described in FIG. 9D, the circuit 300 includes transistors 303_1 to 303_2. 12(D) shows an example of a structure having a plurality of transistors. In the configuration described in FIG. 11B, the circuit 300 includes transistors 303_1 to 303_2. 12(E) shows an example of a structure having a plurality of transistors. In the configuration described in FIG. 11C, the circuit 300 includes transistors 303_1 to 303_2. 13A shows a configuration in which a plurality of transistors, each of which has a length of 2, are included. In the configuration described in FIG. 11(F), the circuit 300 includes transistors 303_1 to 303_2. 2 shows a configuration having a plurality of transistors.

[0217] As shown in FIG. 13B, the second terminal of the transistor 303_1 is connected to the second terminal of the transistor 303_2. 301_2 and the first terminal of the transistor 302_2. Alternatively, the second terminal of the transistor 303_2 may be connected to the first terminal of the transistor 301_1. The second terminal and the first terminal of the transistor 302_1 can be connected to each other. However, the second terminal of the transistor 303_1 is not limited to this, and may be connected to various wirings or Alternatively, the second terminal of the transistor 303_2 may be connected to various nodes. , can be connected to various wirings or various nodes. For example, transistor 3 The second terminal of the transistor 303_1 is connected to the second terminal of the transistor 301_2 and the second terminal of the transistor 302_2. The connection point with the first terminal, or the connection point between the first terminal of transistor 301_2 and the second terminal of transistor 302_ 2, etc., can be connected. Or, the second terminal of transistor 3 03_2 is the connection point between the second terminal of transistor 301_1 and the first terminal of transistor 302_1 The connection point with the first terminal, or the connection point between the first terminal of transistor 301_2 and the second terminal of transistor 302_ 1, etc., can be connected.

[0218] In addition, similar to FIG. 13(B), in the configurations described in FIGS. 9(A) to (F), FIGS. 10(A) to (D), FIGS. 11(A ) to (G), FIGS. 12(A) to (E), and FIG. 13(A), the second terminal of transistor 303_1 is also the connection point between the second terminal of transistor 301_2 and the first terminal of transistor 30 2_2, or the connection point between the first terminal of transistor 301_2 and the second terminal of transistor 30 2_2, etc., can be connected. Or, the second terminal of transistor 303_2 is the connection point between the second terminal of transistor 301_1 and the first terminal of transistor 30 2_1, or the connection point between the first terminal of transistor 301_1 and the second terminal of transistor 30 2_1, etc., can be connected. 302_1, etc., can be connected.

[0219] In addition, as shown in FIG. 13(C), the first terminal of transistor 303_1 and the first terminal of transistor 3 03_2 can be connected to separate wirings. In one example of FIG. 13(C), wiring 118 is divided into a plurality of wirings such as wiring 118A to 118B. And the first terminal of transistor 303_1 is connected to wiring 118A, and the first terminal of transistor 303 _2 is connected to wiring 118B. However, it is not limited to this, and the transistor is not limited to this. The first terminal of the transistor 303_1 and the first terminal of the transistor 303_2 are connected to various wires or It is possible to connect to various nodes. Therefore, the wirings 118A to 118B can have the same function as the wirings 118A to 118B. However, the present invention is not limited to this, and a signal such as a signal CK1 can be input via the wiring 11. Various signals, various voltages, or various currents can be input to 8A and 8B.

[0220] As in FIG. 13(C), FIGS. 9(A) to (F), 10(A) to (D), and 11(A) 12(A) to (E), and the configurations described in FIGS. 13(A) to (B). The first terminal of the transistor 303_1 and the first terminal of the transistor 303_2 are separate. It is possible to connect with the wiring.

[0221] As shown in FIG. 13D, the first terminal of the transistor 303_1 is connected to the wiring 116_ Alternatively, the first terminal of the transistor 303_2 can be connected to the wiring 1. 16_1. By doing so, the transistor 303_ During the period when 1 is off, a high-level signal can be supplied to the first terminal. Similarly, during the period when the transistor 303_2 is turned off, a high level is applied to the first terminal. Therefore, a reverse bias is applied to the transistor. Therefore, the deterioration of the transistor characteristics can be alleviated.

[0222] As in FIG. 13(D), FIGS. 9(A) to (F), 10(A) to (D), and 11(A) 12(A) to (E), and the configurations described in FIGS. 13(A) to (C). , a first terminal of the transistor 303_1 can be connected to the wiring 116_2. Alternatively, the first terminal of the transistor 303_2 can be connected to the wiring 116_1. is.

[0223] As shown in FIG. 13(E), the transistor 301_1 is connected to one terminal (hereinafter referred to as the positive terminal) of the The other terminal (hereinafter also referred to as the negative terminal) is connected to the wiring 116_ 1. Alternatively, the transistor 303a_1 may be replaced with a diode 303a_2 connected to the transistor 303a_1. One terminal (hereinafter also referred to as the positive terminal) of the stator 301_2 is connected to the node 11, and the other terminal A diode 303a_2 whose terminal (hereinafter also referred to as a negative electrode) is connected to the wiring 116_2. However, it is not limited to this. For example, as shown in FIG. In this way, the first terminal of the transistor 303_1 is connected to the node 12, The transistor 303_1 can be configured to be diode-connected. The first terminal of the transistor 303_2 is connected to the node 11, 303_2 can be configured to be diode-connected.

[0224] 13(E) to (F), as well as Figs. 9(A) to (F), Figs. 10(A) to (D), Figs. 11(A) to (G), 12(A) to (E), and 13(A) to (D). In this case, the transistors (for example, the transistors 303_1 to 303_2) are used as diodes. By replacing or duplicating the transistors (for example, the transistors 303_1 to 303_2), It is possible to use a diode-connected configuration.

[0225] As shown in FIG. 11(H), the transistors 302_1 and 302_2 are connected to the resistor element 3 04_1 to 304_2. Or, as shown in FIG. 12(F), , the transistors 302_1 and 302_2 are replaced with diodes 305_1 and 305_2. However, it is not limited to this.

[0226] 11(H) or 12(F), FIGS. 9(A) to 9(F) and 10(A) to 10(F) D), Figs. 11(A) to (G), Figs. 12(A) to (E), and Figs. 13(A) to (F). In this configuration, the transistors can be replaced with resistors or diodes. do.

[0227] As shown in FIG. 14(A), a P-channel transistor is used as the transistor. The transistors 101p_1 and 101p_2 can be 1_1 to 101_2, and are P-channel type. p_2 corresponds to the transistors 301_1 to 301_2 and is a P-channel type. As shown in FIG. 14B, when the polarity of the transistor is a P-channel type, A voltage V1 is supplied to the wiring 118, a voltage V2 is supplied to the wiring 119, and signals CK1, CK2, signal SP1, signal SP2, signal SEL1, signal SEL2, signal RE, the voltage of node 11, The voltage at node 12 and the signal OUT are inverted compared to the timing diagram of FIG. It should be noted that

[0228] As in FIG. 14(A), FIGS. 9(A) to (F), 10(A) to (D), and 11(A) 12(A) to (F), and the configurations described in FIGS. 13(A) to (F). As the transistor, a P-channel transistor can be used.

[0229] (Embodiment 3) In this embodiment, a specific example of the circuit 200 different from that in the second embodiment will be described. The contents described in the first and second embodiments will not be described here. The contents described in this embodiment can be appropriately combined with the contents described in the first and second embodiments. can.

[0230] First, an example of the circuit 200 will be described with reference to FIG. In the example, the circuit 200 includes a circuit 400. The circuit 400 shows a portion of the circuit 200. The circuit 400 can include, by way of example, one or more transistors. These transistors preferably have the same polarity as the transistors 101_1 and 101_2. However, it is not limited to this.

[0231] As shown in FIG. 15B, the circuit 200 includes the circuit 400 and the circuit 100 described in the second embodiment. The circuit 300 and the circuit 400 may be the same as the circuit 300. Some or all of it can be shared.

[0232] The circuit 400 includes, for example, a wiring 114, a wiring 118, a node 11, a node 12, and a wiring The circuit 400 is connected to the line 111. However, the circuit 400 is not limited to this, and may be configured as follows depending on the configuration: In addition, it is possible to connect to various wirings, various nodes, or various terminals. For example, when the circuit 400 needs a signal, the circuit 400 needs a signal via the wiring 112, the wiring 113, the wiring 114, the wiring 115, the wiring 116, the wiring 117, the wiring 118, the wiring 119, the wiring 120, the wiring 121, the wiring 122, the wiring 123, the wiring 124, the wiring 125, the wiring 12 Wire 115_1, wire 115_2, wire 116_1, wire 116_2, and / or wire 1 17.

[0233] For example, the circuit 400 may be configured to detect the voltage at node 11, the voltage at node 12, and / or the voltage at wiring 1. Depending on the voltage at node 11, the voltage at node 12 and / or the voltage at line 111 Alternatively, the circuit 400 may have a function of controlling the voltage at the nodes 11, 12, and / or has a function of controlling the timing of supplying a low-level signal or voltage V1 to the wiring 111. Alternatively, the circuit 400 may include a floating node 11, a floating node 12, and / or a floating wire 111. Alternatively, the circuit 400 has a function of turning on the wiring 111 and the node 11. Alternatively, the circuit 400 has a function of controlling the electrical continuity between the wiring 111 and the node 12. However, the circuit 400 is not limited to this, and may also have various other functions. It should be noted that the circuit 400 does not necessarily have all of the above functions. .

[0234] Next, an example of the operation of the circuit 400 in FIG. 15A will be described with reference to the timing chart in FIG. This will be explained in light of the above.

[0235] During the period A1, the circuit 400 often does not supply a signal or voltage to the node 11. On the other hand, the circuit 400 may apply a voltage V1 or a low level signal to the node 12 and / or Alternatively, the circuit 400 may supply a voltage or a signal to the wiring 111. It is possible that the voltage is not supplied to the node 12 and / or the wiring 111 .

[0236] In the period B1, the circuit 400 outputs a signal or a voltage to the node 11 and / or the wiring 1 On the other hand, the circuit 400 does not supply the voltage V1 or a low level signal. Alternatively, the circuit 400 may provide a voltage or signal to the node 12. It is possible not to supply the power to the node 12.

[0237] During the periods C1 to E1, the circuit 400 supplies a voltage V1 or a low-level signal to the node 11, The signal can be supplied to the node 12 and / or the wiring 111. Alternatively, the circuit 400 can be , voltage or signal is not supplied to the node 11, the node 12, and / or the wiring 111. It is possible to do this.

[0238] During the period A2, the circuit 400 often does not supply a signal or voltage to the node 12. On the other hand, the circuit 400 may apply a voltage V1 or a low level signal to the node 11 and / or Alternatively, the circuit 400 may supply a voltage or a signal to the wiring 111. It is possible that the voltage is not supplied to the node 11 and / or the wiring 111.

[0239] In the period B2, the circuit 400 outputs a signal or a voltage to the node 12 and / or the wiring 1. On the other hand, the circuit 400 does not supply the voltage V1 or a low level signal. Alternatively, the circuit 400 may provide a voltage or signal to the node 11. It is possible not to supply the power to the node 11.

[0240] During the periods C2 to E2, the circuit 400 supplies the voltage V1 or a low-level signal to the node 11, The signal can be supplied to the node 12 and / or the wiring 111. Alternatively, the circuit 400 can be , voltage or signal is not supplied to the node 11, the node 12, and / or the wiring 111. It is possible to do this.

[0241] Next, a specific example of the circuit 400 will be described with reference to FIG. The circuit 500 includes a plurality of transistors 401_1 to 401_2 and a transistor The transistor 402 has a plurality of transistors 401_1 to 401_2. The transistor 402 has the same polarity as the transistors 101_1 and 101_2. It is preferable that the transistor is an N-channel type, but is not limited to this. For example, , any one of the transistors 401_1 to 401_2 and the transistor 402 is omitted. Alternatively, a plurality of transistors 401_1 to 401_2 may be used. The transistor 402 may be a P-channel type.

[0242] A first terminal of the transistor 401_1 is connected to the wiring 118. A second terminal of the transistor 401_2 is connected to the node 11. A first terminal of the transistor 401_3 is connected to the wiring 1. The second terminal of the transistor 401_2 is connected to the node 18, and the second terminal of the transistor 401_3 is connected to the node 12. A first terminal of the transistor 402 is connected to the wiring 118, and a second terminal of the transistor 402 is connected to the wiring 118. , and the wiring 111. The circuit 500 includes the wiring 118, the wiring 114, the node 11, and the The gate 12, the wiring 111, the gate of the transistor 401_1, the gate of the transistor 401_2 and / or the gate of the transistor 402. Depending on the configuration, the circuit 500 may be connected to various wires or various nodes. It is possible.

[0243] The connection point between the gate of the transistor 401_1 and the circuit 500 is indicated as a node 21. The connection point between the gate of the transistor 401_2 and the circuit 500 is designated as a node 22. The connection point between the gate of the resistor 402 and the circuit 500 is indicated as node 31 .

[0244] The transistor 401_1 controls electrical continuity between the wiring 118 and the node 11, for example. Alternatively, the transistor 401_1 may supply the voltage of the wiring 118 to the node 11. For example, the wiring 118 has a function of controlling the timing at which a voltage such as voltage V1 is supplied. When a signal such as the signal CK1 or the signal CK2 is supplied, the transistor 401_1 is connected to the wiring 118 The timing of supplying a voltage or signal to the node 11 is controlled by the As described above, the transistor 401_1 can function as a switch. However, the transistor 401_1 is not limited to this, and may have various other functions. It should be noted that the transistor 401_1 can have all of the above functions. There is no need to do so.

[0245] The transistor 401_2 controls electrical continuity between the wiring 118 and the node 12, for example. Alternatively, the transistor 401_2 supplies the voltage of the wiring 118 to the node 12. For example, the wiring 118 has a function of controlling the timing at which a voltage such as voltage V1 is supplied. When a signal such as the signal CK1 or the signal CK2 is supplied, the transistor 401_2 is connected to the wiring 118 The timing of supplying a voltage or signal to the node 12 is controlled by the As described above, the transistor 401_2 has a function as a switch. However, the transistor 401_2 is not limited to this, and may have various other functions. It should be noted that the transistor 401_2 can have all of the above functions. There is no need to do so.

[0246] The transistor 402 has a function of controlling electrical continuity between the wiring 118 and the wiring 111, for example. Alternatively, the transistor 402 may be a transistor that supplies the voltage of the wiring 118 to the wiring 111. For example, the wiring 118 may be connected to a voltage such as a voltage V1 or a signal When a signal such as signal CK2 is supplied, the transistor 402 is turned on. The wiring 111 has a function of controlling the timing of supplying a voltage, a signal, or the like to the wiring 111. Thus, the transistor 402 can function as a switch. However, the transistor 402 can have various other functions. It should be noted that the transistor 402 does not necessarily have all of the above functions.

[0247] For example, the circuit 500 may be configured to detect the voltage at node 11, the voltage at node 12, and / or the voltage at wiring 1. 11, the voltage at node 21, the voltage at node 22, and / or the voltage at node 31. The circuit 500 has a function of controlling the timing of the control. 22 and / or node 31, a high level signal, a low level signal, a voltage V1, or has the function of controlling the timing of supplying voltages such as voltage V2. The circuit 500 has a function as a control circuit. However, the circuit 500 is not limited to this. It should be noted that the circuit 500 may have any of the above functions. There is no need to have a hand.

[0248] Next, regarding an example of the operation of the circuit 400 of FIG. 16(A), the timing chart of FIG. 16(B) will be explained. The operation of the semiconductor device during the period A1 will be described with reference to FIG. 40B is a schematic diagram of the operation of the semiconductor device during the period C1. FIG. 41A is a schematic diagram of the operation of the semiconductor device in the period D1 and the period E1. A schematic diagram of the operation of the semiconductor device is shown in FIG. 42A is a schematic diagram of the operation of the semiconductor device in the period B1. 42(B), and a schematic diagram of the operation of the semiconductor device during the period C2 is shown in FIG. 43(A). A schematic diagram of the operation of the semiconductor device in the periods D2 and E2 is shown in FIG. 40 to 43, the semiconductor device of FIG. 6B is used as the circuit 300, and the semiconductor device of FIG. 16A. The semiconductor device of FIG. 16A is used in the configuration shown in FIG.

[0249] During the period A1, the signal SP1 goes high, causing the voltage at the node 11 to rise. Therefore, the circuit 500 provides a low level signal or voltage V1 to the node 21. Since the transistor 401_1 is turned off, the wiring 118 and the node 11 are not electrically connected to each other. Since the signal SP2 goes low, the node 12 is maintained at approximately V1. Thus, circuit 500 provides a high level signal or voltage V2 to node 22. Then, the transistor 401_2 is turned on, and the wiring 118 and the node 12 are connected to each other. Therefore, the voltage V1 is applied to the transistor 401_ 2 to the node 12. A low-level signal CK1 is supplied to the wiring 111. Therefore, the voltage of the wiring 111 becomes V1. supplies voltage V2 to node 31. This turns on transistor 402, so that The line 118 and the wiring 111 are electrically connected via the transistor 402. Therefore, the voltage V 1 is supplied to the wiring 111 through the transistor 402. However, this is not limiting. For example, in the period A1, the circuit 500 applies a low-level signal or voltage V1 to the node 2 In this case, the transistor 401_2 is turned off, so that The wiring 118 and the node 12 can be in a non-conductive state. In FIG. 1, the circuit 500 supplies a low level signal or voltage V1 to the node 31. In this case, the transistor 402 is turned off, and the wiring 118 and the wiring 11 1 can be in a non-conducting state.

[0250] During the period B1, the voltage at the node 11 rises due to the bootstrap operation, so that Circuit 500 provides a low level signal or voltage V1 to node 21. Since the resistor 401_1 is turned off, the wiring 118 and the node 11 are not electrically connected. The voltage on board 12 is maintained at approximately V1, so that circuit 500 A signal or voltage V2 is applied to node 22. Then, transistor 401_2 is turned on. Therefore, the wiring 118 and the node 12 are brought into electrical continuity through the transistor 401_2. Therefore, the voltage V1 is supplied to the node 12 through the transistor 401_2. Since a high level signal CK1 is supplied to 11, the voltage of the wiring 111 becomes V2. Therefore, the circuit 500 provides a low level signal or voltage V1 to the node 31. Since the transistor 402 is turned off, the wiring 118 and the wiring 111 are not electrically connected. However, this is not limiting. For example, in the period B1, the circuit 500 A signal or voltage V1 can be applied to node 22. In this case, the transistor Since 401_2 is turned off, the wiring 118 and the node 12 can be in a non-conductive state. is.

[0251] During the period C1 to the period E1, the voltage of the node 11 becomes approximately V1. provides a high level signal or voltage V2 to node 21. Thus, transistor 40 1_1 is turned on, the wiring 118 and the node 11 are connected via the transistor 401_1. Then, the voltage V1 is supplied from the wiring 118 to the node 401_1 through the transistor 401_1. The voltage at node 12 is approximately V1, so the circuit 500 is Therefore, the transistor 401_2 supplies a high-level signal or voltage V2 to the node 22. is turned on, so that the wiring 118 and the node 12 are electrically connected via the transistor 401_2. Then, the voltage V1 is supplied from the wiring 118 to the node 1 through the transistor 401_2. 2. Since the voltage of the wiring 111 is approximately V1, the circuit 500 is This provides a signal or voltage V2 to node 31, thus turning on transistor 402. Therefore, the wiring 118 and the wiring 111 are brought into electrical continuity via the transistor 402. The voltage V1 is supplied from the wiring 118 to the wiring 111 through the transistor 402. However, the present invention is not limited to this. For example, in one of the periods D1 and E1, the circuit 500 applies a low level signal or voltage V1 to node 21, node 22, and / or node 31. Therefore, the transistor 401_1, the transistor 401_ 2 and / or transistor 402 can be turned off. 8 and node 11, the wiring 118 and node 12, and / or the wiring 118 and wiring 111 are not connected to each other. It is possible to be in a conductive state.

[0252] During the period A2, the signal SP1 goes low, so the node 11 is maintained at approximately V1. Therefore, the circuit 500 provides a high level signal or voltage V2 to the node 21. Then, the transistor 401_1 is turned on, and the wiring 118 and the node 11 are connected to each other. Therefore, the voltage V1 is applied to the transistor 401_1. Also, the signal SP2 goes high, so that the signal SP3 is supplied to the node 11 via the signal SP2. Therefore, the circuit 500 outputs a low level signal or voltage V1 to the node 12. Then, the transistor 401_2 is turned off, and the wiring 118 and the node The wiring 111 is supplied with a low-level signal CK1. Therefore, the voltage of the wiring 111 becomes V1. Voltage V2 is supplied to node 31. Then, transistor 402 is turned on, and wiring 1 18 and the wiring 111 are electrically connected via the transistor 402. Therefore, the voltage V1 The power is supplied to the wiring 111 through the transistor 402. However, this is not a limitation. For example, in the period A2, the circuit 500 applies a low-level signal or voltage V1 to the node 21. In this case, the transistor 401_1 is turned off, so the wiring 118 and node 11 can be in a non-conductive state. In this case, the circuit 500 can provide a low level signal or voltage V1 to the node 31. In this case, the transistor 402 is turned off, and the wiring 118 and the wiring 111 are connected. can be in a non-conducting state.

[0253] During period B2, the voltage at node 11 is maintained at approximately V1, so that circuit 500: A high level signal or voltage V2 is applied to node 21. This causes transistor 401_ 1 is turned on, so that the wiring 118 and the node 11 are electrically connected via the transistor 401_1. Therefore, the voltage V1 is supplied to the node 11 through the transistor 401_1. As the voltage at node 12 rises due to bootstrap action, circuit 500 A low level signal or voltage V1 is applied to node 22. This turns on transistor 401. 2 is turned off, so that there is no electrical continuity between the wiring 118 and the node 12. Since a high-level signal CK1 is supplied, the voltage of the wiring 111 becomes V2. Path 500 provides a low level signal or voltage V1 to node 31. Since the starter 402 is turned off, the wiring 118 and the wiring 111 are not electrically connected. For example, in the period B2, the circuit 500 outputs a low-level signal or Voltage V1 can be applied to node 21. In this case, transistor 401_1 is turned off, so that the wiring 118 and the node 11 can be brought out of conduction.

[0254] During the period C2 to the period E2, the voltage of the node 11 becomes approximately V1. provides a high level signal or voltage V2 to node 21. Thus, transistor 40 1_1 is turned on, the wiring 118 and the node 11 are connected via the transistor 401_1. Then, the voltage V1 is supplied from the wiring 118 to the node 401_1 through the transistor 401_1. The voltage at node 12 is approximately V1, so the circuit 500 is Therefore, the transistor 401_2 supplies a high-level signal or voltage V2 to the node 22. is turned on, so that the wiring 118 and the node 12 are electrically connected via the transistor 401_2. Then, the voltage V1 is supplied from the wiring 118 to the node 1 through the transistor 401_2. 2. Since the voltage of the wiring 111 is approximately V1, the circuit 500 is This provides a signal or voltage V2 to node 31, thus turning on transistor 402. Therefore, the wiring 118 and the wiring 111 are brought into electrical continuity via the transistor 402. The voltage V1 is supplied from the wiring 118 to the wiring 111 through the transistor 402. However, the present invention is not limited to this. For example, in one of the periods D2 and E2, the circuit 500 applies a low level signal or voltage V1 to node 21, node 22, and / or node 31. Therefore, the transistor 401_1, the transistor 401_ 2 and / or transistor 402 can be turned off. 8 and node 11, the wiring 118 and node 12, and / or the wiring 118 and wiring 111 are not connected to each other. It is possible to be in a conductive state.

[0255] The channel width of the transistor 401_1 and the channel width of the transistor 401_2 are It is preferable that they are approximately equal. By doing so, the The change in voltage at node 12 during period T2 can be made approximately equal to the change in voltage at node 12 during period T3. Therefore, the waveform of the signal OUT can be made roughly the same. However, the channel width of the transistor 401_1 and the channel width of the transistor 401_2 are not limited. The width can be different.

[0256] The channel width of the transistor 401_1 and the channel width of the transistor 401_2 are The thickness is preferably 100 μm to 4000 μm, and more preferably 500 μm to 30 It is more preferable that the thickness is 1000 μm to 2000 μm. However, the present invention is not limited to this.

[0257] The channel width of the transistor 402 is preferably 500 μm to 5000 μm. It is more preferable that the thickness is 1000 μm to 3000 μm. Preferably, the thickness is 2000 μm to 3000 μm. However, the thickness is not limited to this. stomach.

[0258] As shown in FIG. 17(A), multiple transistors can be connected in parallel. The transistors can be turned on in sequence or randomly. FIG. 17(A) shows an example in which two transistors are connected in parallel. In this case, the two transistors are connected for each gate selection period or clock. The transistor 401 can be turned on and off repeatedly every half cycle of the clock signal. 1 to 401_2 and the transistor 402, For example, the transistor 401_1 is connected in parallel with the transistor 401_2. The transistor 411_1 is newly added so that the first The first terminal of the transistor 411_1 is connected to the wiring 118, and the second terminal of the transistor 411_1 is connected to the node 11. The gate of the transistor 411_1 is connected to the circuit 500. A transistor 411_2 is newly added so as to be connected in parallel with 401_2. A first terminal of the transistor 411_2 is connected to the wiring 118, and a third terminal of the transistor 411_2 is connected to the wiring 118. The second terminal of the transistor 411_2 is connected to the node 11, and the gate of the transistor 411_2 is connected to the circuit 500. A new transistor 412 is added so as to be connected in parallel with the transistor 402. A first terminal of the transistor 412 is connected to the wiring 118. The second terminal is connected to node 11, and the gate of transistor 412 is connected to circuit 500. However, the present invention is not limited to this, and the transistors 411_1 to 411_2 and the transistor It is possible to add only one of the parameters 412.

[0259] As shown in FIG. 17B, the first terminal of the transistor 411_1 is connected to the wiring 115_ 1, and the gate of the transistor 411_1 can be connected to the wiring 113. Alternatively, the first terminal of the transistor 411_2 is connected to the wiring 115_2. The gate of the transistor 411_2 can be connected to the wiring 113. The gate of the transistor 412 can be connected to the wiring 113. Therefore, the conduction state of the transistors 411_1 to 411_2 and the transistor 412 is controlled. However, the transistor is not limited to this and the circuit for controlling the , can be connected in a variety of configurations. For example, transistors 401_ the second terminal of transistor 401_1, the second terminal of transistor 401_2, and / or the second terminal of transistor 402 The second terminal can be connected to the wiring 113. Since a reverse bias can be applied to the transistor, deterioration of the transistor characteristics can be suppressed. It is possible to do this.

[0260] As shown in FIGS. 18A and 18B, the transistors 401_1 to 401_ The gate of transistor 402 and the gate of transistor 403 can be connected together. In the semiconductor device shown in FIG. 18A, the transistors 401_1 and 401_2 are transistors. 18B shows a configuration in which the gate of the transistor 401_1 is connected to the gate of the transistor 402. Alternatively, 401_2 is connected to the gate of the transistor 402. In this case, 500 indicates a low level signal or voltage V 1 to the gates of the transistors 401_1, 401_2, and 402. On the other hand, the circuit 500 supplies the following during the periods C1 to E1 and C2 to E2: A high level signal or voltage V2 is applied to the gates of these transistors. The transistors 401_1 to 401_2 and the transistor 402 are in the periods A1 to B1, and It is turned off during periods A2 to B2, and turned on during periods C1 to E1 and C2 to E2. Thus, the transistors 401_1 to 401_2 and the transistor Since the circuit for controlling the conduction state of the resistor 402 can be shared, the circuit size can be reduced. However, the present invention is not limited to this. For example, the circuit 500 can be During one of the periods D1 and E1, and one of the periods D2 and E2, a low-level signal A signal or voltage V1 is applied to the gates of the transistors 401_1 to 401_2 and the transistor 402. Alternatively, the circuit 500 may supply the signal to the period C1 to E1 and the period C2 to E 2, a low level signal or voltage V1 is applied to the transistors 401_1 to 401_2. _2 and the gate of transistor 402. This causes the transistor to repeatedly turn on and off for each gate selection period or each frame. This makes it possible to suppress the deterioration of transistor characteristics. The gate of the transistor 402 is connected to the gate of the transistor 401_1 and the gate of the transistor 402_2. It is possible to connect only one of the gates of 01_1 and 01_2.

[0261] As shown in FIG. 18C, the first terminal of the transistor 401_1 and the second terminal of the transistor 4 The first terminal of the transistor 401_2 and the first terminal of the transistor 402 are connected to different wirings. In FIG. 18C, as an example, the wiring 118 includes wirings 118C to 118D. The circuit 500 is connected to the wiring 118C. The first terminal of the transistor 401_1 is connected to the wiring 118D, and the second terminal of the transistor 401_2 is connected to the wiring 118D. A first terminal of the transistor 401 is connected to the wiring 118E, and a first terminal of the transistor 402 is connected to the wiring 118 F. However, this is not limiting. For example, The terminal, the first terminal of the transistor 401_2, and the first terminal of the transistor 402 are It is possible to connect the wirings 118C to 118D to various nodes. F can have the same function as the wiring 118. Therefore, the wirings 118C to 11 Voltages such as voltage V1 can be input to 8F. However, this is not limited to this. Various signals, various voltages, or various currents can be input to the wirings 118C to 118F. It is possible to do this.

[0262] As in FIG. 18(A), FIGS. 16(A), 17(A) to 17(B), and 18(B) In the configurations described in (C) to (C), the second terminals of the transistors 401_1 to 401_2 and The first terminal of the transistor 401 and the second terminal of the transistor 402 can be connected to separate wires. In the configuration described in FIGS. 17(A) and 17(B), the transistors 411_1 and 411_2 The second terminal of the transistor 412 and the second terminal of the transistor 413 can be connected to separate wires. be.

[0263] As shown in FIG. 19A, the transistor 401_1 is connected to one terminal (hereinafter referred to as the positive terminal) of the The other terminal (hereinafter also referred to as the negative terminal) is connected to node 21. Alternatively, the transistor 401_2, one terminal (hereinafter also referred to as the positive terminal) is connected to the node 12, and the other terminal (hereinafter also referred to as the negative pole) is replaced with a diode 401a_2 connected to node 22. Alternatively, one terminal of the transistor 402 (hereinafter also referred to as a positive electrode) can be The other terminal (hereinafter also referred to as a negative terminal) of the diode is connected to the wiring 111 and the other terminal of the diode is connected to the node 31. However, it is not limited to this. For example, As shown in FIG. 19A, the first terminal of the transistor 401_1 is connected to the node 21. The second terminal of the transistor 401_1 is connected to the node 11, The transistor 401_1 can be diode-connected. A first terminal of the transistor 401_2 is connected to the node 22, and a second terminal of the transistor 401_2 is connected to the node 12, the transistor 401_2 is diode-connected. The first terminal of the transistor 402 is connected to the node 31, and the second terminal of the transistor 403 is connected to the node 32. When the second terminal of the transistor 402 is connected to the wiring 111, the transistor 402 becomes a diode. It is possible to connect the two devices via a single cable.

[0264] 19(A)-(B), as well as FIGS. 16(A), 17(A)-(B), and 1 In the configurations described in 8(A) to (C), the transistors may be replaced with diodes. It is possible to connect these transistors as diodes.

[0265] Next, a specific example of the circuit 500 will be described with reference to FIG. The circuit includes circuits 501_1 to 501_2 and a circuit 502. The circuit 502 has a function as a NOT circuit or an inverter, for example. The input terminal of the circuit 501_1 is connected to the node 11. The output terminal of the circuit 501_2 is connected to the node 21. The input terminal of the circuit 501_2 is connected to the node 12. The output terminal of the circuit 501_2 is connected to the node 22. The input terminal of the circuit 502 is , is connected to the wiring 111, and the output terminal of the circuit 502 is connected to the node 31.

[0266] Another example of the circuit 500 will be described with reference to FIG. 20B. 03. For example, the circuit 503 has a function as a two-input NOR circuit. One input terminal of the circuit 503 is connected to the node 11, and the other input terminal of the circuit 503 is connected to the node 12. One input terminal of the circuit 503 is connected to the node 12, and the other output terminal of the circuit 503 is connected to the transistor 401. The gate of transistor 401_1, the gate of transistor 401_2, and / or the gate of transistor 402 It is connected to the port.

[0267] Another example of the circuit 500 will be described with reference to FIG. 20C. The circuit 511_1 to 511_2 and the circuit 512 are included. The circuit 512 is, for example, a logic circuit that combines a two-input AND circuit and a NOT circuit. One input terminal of the circuit 511_1 is connected to the wiring 113. The other input terminal of the circuit 511_1 is connected to the node 11, and the other input terminal of the circuit 511_ An output terminal of the circuit 511_2 is connected to the node 21. One input terminal of the circuit 511_2 is connected to the wiring 1. 13, and the other input terminal of the circuit 511_2 is connected to the node 12, and the other input terminal of the circuit 51 The output terminal of the circuit 512 is connected to the node 22. The other input terminal of the circuit 512 is connected to the wiring 111. The output terminal is connected to node 31 .

[0268] Another example of the circuit 500 will be described with reference to FIG. 20D. The circuit 513 is a logic circuit that combines a three-input AND circuit and a NOT circuit. The first input terminal of the circuit 513 is connected to the wiring 113. The second input terminal of the circuit 513 is connected to the node 11, and the third input terminal of the circuit 513 is connected to the node 12. The input terminal of the circuit 513 is connected to the node 12, and the output terminal of the circuit 513 is connected to the transistor 401_ the gate of transistor 401_1, the gate of transistor 401_2, and / or the gate of transistor 402 It is connected to the

[0269] Another example of the circuit 500 will be described with reference to FIG. 20(E). The circuit 521_1 to 521_2 and the circuit 522. As an example, the circuit 522 can function as a two-input NOR circuit. One input terminal of the circuit 521_1 is connected to the wiring 113, and the other input terminal of the circuit 521_1 is connected to the wiring 113. The input terminal of the circuit 521_1 is connected to the node 11, and the output terminal of the circuit 521_2 is connected to the node 21. One input terminal of the circuit 521_2 is connected to the wiring 113, and the other input terminal of the circuit 521_2 is connected to the wiring 113. The input terminal of the circuit 521_1 is connected to the node 12, and the output terminal of the circuit 521_2 is connected to the node 22. One input terminal of the circuit 522 is connected to the wiring 113, and the other input terminal of the circuit 522 is connected to the wiring 113. The input terminal of the circuit 522 is connected to the wiring 111 , and the output terminal of the circuit 522 is connected to the node 31 .

[0270] Another example of the circuit 500 will be described with reference to FIG. The circuit 523 can function as a three-input NOR circuit. The first input terminal of the circuit 523 is connected to the wiring 113, and the second input terminal of the circuit 523 is connected to the wiring 113. The third input terminal of the circuit 523 is connected to the node 11, and the third input terminal of the circuit 523 is connected to the node 12. The output terminal of the circuit 523 is connected to the gate of the transistor 401_1, the gate of the transistor 401_2, The gate and / or the gate of the transistor 402 are connected.

[0271] Another example of the circuit 500 will be described with reference to FIG. The circuit 514 is a logic circuit that combines a two-input AND circuit and a NOT circuit. The first input terminal of the circuit 514 is connected to the wiring 113. , the second input terminal of the circuit 514 is connected to the wiring 111, and the output terminal of the circuit 514 is connected to the wiring 112. The gate of the transistor 401_1, the gate of the transistor 401_2, and / or , and is connected to the gate of transistor 402.

[0272] Another example of the circuit 500 will be described with reference to FIG. The circuit 524 can function as a two-input NOR circuit. The first input terminal of the circuit 524 is connected to the wiring 113, and the second input terminal of the circuit 524 is connected to the wiring 113. The terminal of the circuit 524 is connected to the wiring 111, and the output terminal of the circuit 524 is connected to the gate of the transistor 401_1. , the gate of the transistor 401_2 and / or the gate of the transistor 402. will be done.

[0273] Next, the circuits 501_1 to 501_2, the circuit 502, and the circuit 503 shown in FIGS. 20(A) to 20(H) are 3, circuit 511_1~511_2, circuit 512, circuit 513, circuit 514, circuit 521_ 1 to 521_2, the circuit 522, the circuit 523, and the circuit 524 are shown in FIG. 22(A) to (D). 501_2, circuit 502, circuit 503, circuit 511_1~511_2, circuit 512, circuit 513, circuit 514, circuit 521_1~521_2, circuit 522, circuit 523, circuit 52 Various other configurations can be used for 4.

[0274] In the circuit of FIG. 21(A), the first terminal is connected to the wiring 114, and the second terminal is connected to the output terminal 591. a transistor 531 having a first terminal connected to a wiring 114 and a gate connected to a wiring 11 8, the second terminal is connected to the output terminal 591, and the gate is connected to the input terminal 592. The circuit in FIG. 21A includes circuits 501_1 and 501_2. , and / or the circuit 502. Therefore, the output terminal 591 is , node 21, node 22, or node 31, etc., or The input terminal 592 can be connected to the node 11, the node 12, the wiring 111, or the like. It is Noh.

[0275] In the circuit of FIG. 21B, the first terminal is connected to the wiring 114 and the second terminal is connected to the transistor 53. a transistor 531 connected to the gate of the first terminal 3 and the gate of which is connected to the wiring 114; The first terminal is connected to the wiring 118, the second terminal is connected to the gate of the transistor 533, and the gate a transistor 532 having a first terminal connected to an input terminal 592 and a second terminal connected to a wiring 114; a transistor 533 having a second terminal connected to the output terminal 591 and a first terminal connected to the wiring 118; , the second terminal is connected to the output terminal 591, and the gate is connected to the input terminal 592. The circuit in FIG. 21B includes circuits 501_1 and 501_2. , and / or the circuit 502. Therefore, the output terminal 591 is , node 21, node 22, or node 31, etc., or The input terminal 592 can be connected to the node 11, the node 12, the wiring 111, or the like. It is Noh.

[0276] In the circuit of FIG. 21(C), the first terminal is connected to the wiring 114, and the second terminal is connected to the output terminal 591. a transistor 541 having a first terminal connected to a wiring 114 and a gate connected to a wiring 11 8, the second terminal is connected to the output terminal 591, and the gate is connected to the input terminal 592. A transistor 542 has a first terminal connected to the wiring 118 and a second terminal connected to the output terminal 59. 1 and a transistor 543 whose gate is connected to an input terminal 593. The circuit of 21(C) is the circuit 503, the circuit 521_1, the circuit 521_2, the circuit 522, or The output terminal 591 can be applied to the transistor 524. The connection point between the gates of 401_1 to 401_2 and the gate of the transistor 402, node 2 1, node 22, or node 31. Alternatively, input terminal 5 92 to 593 are connected to the node 11, the node 12, the wiring 111, or the wiring 113. It is possible to do this.

[0277] In the circuit of FIG. 21D, the first terminal is connected to the wiring 114 and the second terminal is connected to the transistor 54. a transistor 541 connected to the gate of the first terminal 4 and the gate of which is connected to the wiring 114; The first terminal is connected to the wiring 118, the second terminal is connected to the gate of the transistor 544, and the gate a transistor 542 having a first terminal connected to an input terminal 592 and a second terminal connected to a wiring 118; The second terminal is connected to the gate of the transistor 544, and the gate is connected to the input terminal 593. A first terminal of the transistor 543 is connected to the wiring 114, and a second terminal of the transistor 543 is connected to the output terminal 59. A transistor 544 connected to 1, a first terminal connected to wiring 118, and a second terminal output A transistor 545 connected to the force terminal 591 and a gate connected to the input terminal 592, A transistor 546 having a first terminal connected to wiring 118, a second terminal connected to the output terminal 591, and a gate connected to the input Terminal 593. The circuit of FIG. 21(D) can be applied to circuit 5 03, circuit 521_1, circuit 521_2, circuit 522, or circuit 524, etc. Therefore, the output terminal 591 is the gate of transistors 401_1 to 401_2 It can be connected to the connection point with the gate of transistor 402, node 21, node 22, or node 31, etc. Alternatively, the input terminals 592 to 593 can be connected to node 11 Node 12, wiring 111, or wiring 113, etc.

[0278] The circuit of FIG. 21(E) has a transistor 541 with a first terminal connected to wiring 114, a second terminal connected to the output terminal 591, and a gate connected to wiring 114, a transistor 542 with a first terminal connected to wiring 11 8, a second terminal connected to the output terminal 591, and a gate connected to the input terminal 592 Connected, a transistor 543 having a first terminal connected to wiring 118, a second terminal connected to the output terminal 59 1, and a gate connected to the input terminal 593, and a transistor 547 having a first terminal connected to Wiring 118, a second terminal connected to the output terminal 591, and a gate connected to the input terminal 595 Connected. The circuit of FIG. 21(E) can be applied to circuit 523, etc. Therefore, the output terminal 591 can be connected to the connection point between the gates of transistors 401_1 to 40 1_2 and the gate of transistor 402, etc. It is possible. ​​Alternatively, the input terminals 592 to 594 may be connected to the node 11, the node 12, the wiring 113, etc. It is possible to connect to

[0279] In the circuit of FIG. 21F, the first terminal is connected to the wiring 114, and the second terminal is connected to the transistor 54. a transistor 541 connected to the gate of the first terminal 4 and the gate of which is connected to the wiring 114; The first terminal is connected to the wiring 118, the second terminal is connected to the gate of the transistor 544, and the gate a transistor 542 having a first terminal connected to an input terminal 592 and a second terminal connected to a wiring 118; The second terminal is connected to the gate of the transistor 544, and the gate is connected to the input terminal 593. a transistor 543 connected to the wiring 118 and a second terminal of the transistor a transistor 547 whose gate is connected to the gate of the transistor 544 and whose gate is connected to an input terminal 594; , a transistor having a first terminal connected to the wiring 114 and a second terminal connected to the output terminal 595 a first terminal of the capacitor 544 connected to the wiring 118 and a second terminal of the capacitor 544 connected to the output terminal 595; A transistor 545 having a gate connected to an input terminal 592 and a first terminal connected to a wiring 118 a transistor having a first terminal connected to the output terminal 595 and a gate connected to the input terminal 593; A first terminal of the transistor 546 is connected to the wiring 118, and a second terminal of the transistor 546 is connected to the output terminal 595. 21(a) and 21(b) have a transistor 548 connected to the input terminal 594 and a gate connected to the input terminal 594. The circuit of F) can be applied to the circuit 523, etc. Therefore, the output terminal 595 is , the connection between the gates of the transistors 401_1 to 401_2 and the gate of the transistor 402 Alternatively, the input terminals 592 to 594 may be connected to the node 11. , node 12, or wiring 113, etc.

[0280] The circuit of FIG. 22(A) has a first terminal connected to an input terminal 592 and a second terminal connected to a transistor 553 and a transistor 551 whose gate is connected to an input terminal 592; , a first terminal is connected to the wiring 118, and a second terminal is connected to the gate of the transistor 553. , a transistor 552 whose gate is connected to the input terminal 593, and a transistor 553 whose first terminal is connected to the input terminal 59 2 and a second terminal connected to the output terminal 591; is connected to the wiring 118, the second terminal is connected to the output terminal 591, and the gate is connected to the input terminal 59 22A includes a circuit 511_1 and a transistor 554 connected to the circuit 511_1. , can be applied to the circuit 511_2, the circuit 512, and / or the circuit 514. Therefore, the output terminal 591 is connected to the node 21, the node 22, the node 31, etc. Alternatively, the input terminal 592 may be connected to the wiring 113 or the like. Alternatively, the input terminal 593 may be connected to the node 11, the node 12, or the wiring 111. It is possible to continue.

[0281] The circuit of FIG. 22(B) has a first terminal connected to the input terminal 592 and a second terminal connected to a transistor 553 and a transistor 551 whose gate is connected to an input terminal 592; , a first terminal is connected to the wiring 118, and a second terminal is connected to the gate of the transistor 553. , a transistor 552 whose gate is connected to the input terminal 593, and a transistor 553 whose first terminal is connected to the input terminal 59 2 and a second terminal connected to the output terminal 591; is connected to the wiring 118, the second terminal is connected to the output terminal 591, and the gate is connected to the input terminal 59 3, a transistor 554 having a first terminal connected to the wiring 118 and a second terminal connected to the transistor A transistor connected to the gate of the transistor 553 and having a gate connected to an input terminal 594. A first terminal of the capacitor 555 is connected to the wiring 118, and a second terminal of the capacitor 555 is connected to the output terminal 591. The gate of the transistor 556 is connected to the input terminal 594. The circuit can be applied to the circuit 513, etc. Therefore, the output terminal 591 is Connection points between the gates of the resistors 401_1 and 401_2 and the gate of the transistor 402, etc. Alternatively, the input terminal 592 may be connected to the wiring 113 or the like. Alternatively, the input terminals 593 to 594 may be connected to the node 11 or the node 12, etc. It is possible to connect with.

[0282] In the circuit of FIG. 22(C), the first terminal is connected to the wiring 118, and the second terminal is connected to the output terminal 591. A transistor 561 having one electrode connected to an input terminal 593 and a gate connected to an input terminal 594. a capacitance element 562 having one electrode connected to an input terminal 592 and the other electrode connected to an output terminal 591; The circuit in FIG. 22C includes a circuit 511_1, a circuit 511_2, a circuit 512, and / or a Alternatively, it can be applied to the circuit 514. Therefore, the output terminal 591 is a node 21, node 22, node 31, or the gates and transistors of the transistors 401_1 to 401_2. It can be connected to the connection point with the gate of the transistor 402. The terminal 592 can be connected to the wiring 113 or the like. , node 11, node 12, or wiring 111, etc.

[0283] In the circuit of FIG. 22(D), the first terminal is connected to the wiring 118, and the second terminal is connected to the output terminal 591. A transistor 561 having one electrode connected to an input terminal 593 and a gate connected to an input terminal 594. a capacitor 562 having one electrode connected to an input terminal 592 and the other electrode connected to an output terminal 591; The first terminal is connected to the wiring 118, the second terminal is connected to the output terminal 591, and the gate is connected to the input The circuit in FIG. 22(D) has a transistor 563 connected to a terminal 594. Therefore, the output terminal 591 is The connection points between the gates of the transistors 401_1 and 401_2 and the gate of the transistor 402, Alternatively, the input terminal 592 may be connected to the wiring 113, etc. Alternatively, the input terminals 593 and 594 may be connected to the node 11 or the node 12. It is possible to connect to

[0284] The circuit configuration is not limited to those shown in FIGS. 21(A) to 21(F) and 22(A) to 22(D). For example, as shown in FIG. 22(E), each terminal of the transistor is connected to a separate wire or a separate terminal. Alternatively, in the example of FIG. 22E, the transistor 551 A first terminal of the transistor 551 is connected to a wiring 581, and a first terminal of the transistor 552 is connected to a wiring 582. The first terminal of the transistor 552 is connected to the wiring 583, and the second terminal of the transistor 55 The first terminal of transistor 4 is connected to wiring 584. The wiring (for example, wirings 581 to 584) is connected to various wirings or various nodes. Alternatively, the wiring connected to each terminal of these transistors may be connected to a voltage or signal. etc. can be input, and can function as a power supply line or a signal line. As another example, as shown in FIG. 22(F), instead of a diode-connected transistor, Instead, a resistor or another element such as a diode may be used. An element 535 is used instead of the element 531. One terminal of the element 535 is connected to the wiring 114. The other terminal of the element 535 is connected to the output terminal 591. The element 535 is a resistor Function as an element having a resistive component (such as a transistor, resistor, or diode) As another example, as shown in FIG. 22(G), a transistor is used as a capacitance element. The capacitor 562 can be a transistor or an MIS capacitor. The first and second terminals of the transistor 562A are connected to the output terminal 59. 1, and the gate of transistor 562A is connected to input terminal 592.

[0285] Next, another example of the circuit 200 will be described with reference to FIG. , can include a circuit 600. The circuit 600 shows a portion of the circuit 200. 23A, as an example, the circuit 200 is connected to the circuit 300, the circuit 400, and the circuit 600. The circuit 300, the circuit 400, and the circuit 600 are parts of a circuit or The circuit 600 may be shared across one or more transistors, as an example. These transistors may include transistors 101_1 to It is preferable that the polarity is the same as that of 101_2, but it is not limited to this.

[0286] The circuit 600 includes, for example, a wiring 117, a wiring 118, a node 11, a node 12, and a wiring The circuit 600 is connected to the line 111. However, the circuit 600 is not limited to this, and may be configured as follows depending on the circuit configuration: In addition, it is possible to connect to various wires, various nodes, or various terminals.

[0287] For example, the circuit 600 controls the conduction state between the wiring 118 and the node 11, The electrical continuity between the wiring 118 and the node 12 and / or the electrical continuity between the wiring 118 and the wiring 111 For example, a signal such as a voltage V1 or a signal CK 2, the circuit 600 may be configured to receive the voltage or signal supplied to the wiring 118. The timing of supplying the signal to the node 11, the node 12, and / or the wiring 111 is controlled. Alternatively, the circuit 600 may have a function of reducing the voltage of the wiring 111 to, for example, V1. As described above, the circuit 600 has a function of controlling the control circuit, the reset operation, However, the present invention is not limited to this and may be applied to circuits, switches, etc. The circuit 600 can have various other functions. It is not necessary to have all of the above.

[0288] Next, an example of the operation of the circuit 600 in FIG. 23A will be described with reference to the timing chart in FIG. This will be explained in light of the above.

[0289] In the periods A1 to B1, D1 to E1, A2 to B2, and D2 to E2, the signal Since RE is low, the circuit 600 applies a signal or voltage to the nodes 11, 12, In many cases, the current is not supplied to the wiring 111. However, this is not limitative. For example, in the period A 1. During the periods D1 to E1, A2, and / or D2 to E2, the circuit 600 , a voltage V1 or a low-level signal is applied to the node 11, the node 12, and / or the wiring 111. It is possible to supply

[0290] In the periods C1 and C2, the signal RE is at a high level, so that the circuit 600 supplying a voltage V1 or a low-level signal to the node 11, the node 12, and / or the wiring 111; However, the circuit 600 can be configured to generate a voltage, a signal, etc. It is possible that no supply is made to the node 11, the node 12, and / or the wiring 111.

[0291] Next, a specific example of the circuit 600 will be described with reference to FIG. A plurality of transistors 601_1 to 601_2 and a transistor 60 However, the circuit 600 is not limited to this. 1_2 and transistor 602, or It is possible to use a plurality of transistors 601_1 to 601_2. The transistor 602 has the same polarity as the transistors 101_1 and 101_2. Preferably, the transistor is an N-channel type. However, the transistor is not limited to this. The plurality of transistors 601_1 to 601_2 and the transistor 602 are P-channel transistors. It is possible for the filter to be of a panel type.

[0292] A first terminal of the transistor 601_1 is connected to the wiring 118. The second terminal of the transistor 601_1 is connected to the node 11. The gate of the transistor 601_1 is connected to the wiring 117. A first terminal of the transistor 601_2 is connected to the wiring 118. The second terminal of the transistor 601_2 is connected to the node 12, and the gate of the transistor 601_1 is connected to the node 12. The first terminal of the transistor 602 is connected to the wiring 118. The second terminal of the transistor 602 is connected to the wiring 111, and the gate of the transistor 602 is connected to the wiring 111. The port is connected to wiring 117 .

[0293] The transistor 601_1 controls electrical continuity between the wiring 118 and the node 11, for example. Alternatively, the transistor 601_1 supplies the voltage of the wiring 118 to the node 11. For example, the wiring 118 has a function of controlling the timing at which a voltage such as voltage V1 is supplied. When a signal such as the signal CK1 or the signal CK2 is supplied, the transistor 601_1 is connected to the wiring 118 The timing of supplying a voltage or signal to the node 11 is controlled by the As described above, the transistor 601_1 can function as a switch. However, the transistor 601_1 is not limited to this, and may have various other functions. It should be noted that the transistor 601_1 can have all of the above functions. There is no need to do so.

[0294] The transistor 601_2 controls electrical continuity between the wiring 118 and the node 12, for example. Alternatively, the transistor 601_2 supplies the voltage of the wiring 118 to the node 12. For example, the wiring 118 has a function of controlling the timing at which a voltage such as voltage V1 is supplied. When a signal such as the signal CK1 or the signal CK2 is supplied, the transistor 601_2 is connected to the wiring 118 The timing of supplying a voltage or signal to the node 12 is controlled by the As described above, the transistor 601_2 can function as a switch. However, the transistor 601_2 is not limited to this, and may have various other functions. It should be noted that the transistor 601_2 can have all of the above functions. There is no need to do so.

[0295] The transistor 602 has a function of controlling electrical continuity between the wiring 118 and the wiring 111, for example. Alternatively, the transistor 602 may be a transistor that supplies the voltage of the wiring 118 to the wiring 111. For example, the wiring 118 may be connected to a voltage such as a voltage V1 or a signal When a signal such as signal CK2 is supplied, transistor 602 turns on the The wiring 111 has a function of controlling the timing of supplying a voltage, a signal, or the like to the wiring 111. Thus, the transistor 602 can function as a switch. However, the transistor 602 can have various other functions. It should be noted that the transistor 602 does not necessarily have all of the above functions.

[0296] Next, an example of the operation of the semiconductor device of FIG. The operation of the semiconductor device is the same as that of the semiconductor device shown in FIG. 16(A). ) will be described as appropriate. A schematic diagram of the operation is shown in FIG. 44A, and a schematic diagram of the operation of the semiconductor device in the period B1 is shown in FIG. 4(B), a schematic diagram of the operation of the semiconductor device in the period C1 is shown in FIG. 45(A), and A schematic diagram of the operation of the semiconductor device in the periods D1 and E1 is shown in FIG. A schematic diagram of the operation of the semiconductor device in period A2 is shown in FIG. 46(A), and a schematic diagram of the operation of the semiconductor device in period B2 is shown in FIG. A schematic diagram of the operation of the semiconductor device is shown in FIG. 46B. 47A is a schematic diagram of the operation of the semiconductor device in the periods D2 and E2. 45 to 47, the configuration of FIG. 6(B) is used as the circuit 300. 16A is used as the circuit 400, and the semiconductor device shown in FIG. 23B is used as the circuit 600. This shows the case where the configuration shown in Fig.

[0297] In the periods A1 to B1, D1 to E1, A2 to B2, and D2 to E2, the signal Since RE is at a low level, the transistors 601_1 to 601_2 and the transistor 602 is turned off. Therefore, the wiring 118 and the node 11, the wiring 118 and the node 12, and The wiring 118 and the wiring 111 are brought into a non-conductive state.

[0298] During periods C1 and C2, the signal RE is at a high level, so that the transistor 60 1_1 to 601_2 and the transistor 602 are turned on. The node 11, the wiring 118 and the node 12, and the wiring 118 and the wiring 111 are brought into a conductive state.

[0299] The channel width of the transistor 601_1 and the channel width of the transistor 601_2 are It is preferable that they are approximately equal. By doing so, the The change in voltage at node 12 during period T2 can be made approximately equal to the change in voltage at node 12 during period T3. Therefore, the waveform of the signal OUT can be made roughly the same. The channel width of the transistor 601_1 and the channel width of the transistor 601_2 are not limited to The width can be different.

[0300] The channel width of the transistor 601_1 and the channel width of the transistor 601_2 are The thickness is preferably 100 μm to 3000 μm. More preferably, it is 300 μm to 2 000 μm, and more preferably 300 μm to 1000 μm. However, the present invention is not limited to this.

[0301] The channel width of the transistor 602 is preferably 500 μm to 5000 μm. It is more preferable that the thickness is 1000 μm to 3000 μm. Preferably, the thickness is 2000 μm to 3000 μm. However, the thickness is not limited to this. stomach.

[0302] The circuit 600 includes transistors 601_1 to 601_2 and a transistor 602. It is not necessary to have all of these transistors. It is possible to have:

[0303] As shown in FIG. 23C, the first terminal of the transistor 601_1 and the second terminal of the transistor 6 The first terminal of the transistor 601_2 and the first terminal of the transistor 602 are connected to different wirings. In the example of FIG. 23(C), the wiring 118 is made up of wirings 118G to 118I. The first terminal of the transistor 601_1 is connected to the wiring 118G. The first terminal of the transistor 601_2 is connected to the wiring 118H, and the second terminal of the transistor 601_3 is connected to the wiring 118H. The first terminal of the transistor 602 is connected to the wiring 118I. a first terminal of the transistor 601_1, a first terminal of the transistor 601_2, and a first terminal of the transistor 60 The first terminal of the second transistor can be connected to various wirings or various nodes. The wirings 118G to 118I can have the same function as the wiring 118. , a voltage such as voltage V1 can be input to the wirings 118G to 118I. However, the wirings 118G to 118I are not limited to this. It is possible to input various signals, various voltages, or various currents to the.

[0304] As shown in FIG. 23(D), the transistor 601_1 is connected to one terminal (hereinafter, the positive terminal) The other terminal (hereinafter also referred to as a negative electrode) is connected to the wiring 118. It is possible to replace the connected diode 601a_1. The positive terminal of the capacitor 601_2 is connected to the node 12, and the positive terminal of the capacitor 601_2 is connected to the node 12. The negative electrode (hereinafter also referred to as the negative electrode) of the diode 601a_2 is connected to the wiring 118. Similarly, the transistor 602 can be connected to one terminal (hereinafter also referred to as the positive terminal) of the ) is connected to the wiring 111, and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 118. However, the present invention is not limited to this. For example, as shown in FIG. 23(E), the first terminal of the transistor 601_1 is connected to the node 11. By connecting the transistor 601_1 to the Similarly, the first terminal of the transistor 601_2 can be connected to the node 12. By this, the transistor 601_2 can be configured to be diode-connected. Similarly, when the first terminal of the transistor 602 is connected to the wiring 111, The transistor 602 may be configured to be diode-connected.

[0305] As in the configurations shown in FIGS. 23(D) to 23(E), Transistors (for example, transistors 601_1 to 601_2 or transistor 602) can be replaced with a diode and can be diode-connected.

[0306] Here, one example of a semiconductor device in which the contents described in the first to third embodiments are combined is shown. Examples are shown in Figs. 48 and 49. However, the present invention is not limited to these examples, and other examples may be used in addition to the first embodiment. The semiconductor device can be configured in various ways by combining the contents described in Mode 4.

[0307] The semiconductor device of FIG. 48 includes a circuit 100 and a circuit 200. The circuit 200 includes a circuit 300, The semiconductor device shown in FIG. 48 includes a circuit 400 and a circuit 600, and the circuit 400 includes a circuit 500. In the device, the circuit 100 has the configuration shown in FIG. The circuit 300 has the configuration shown in FIG. 16A is used as the circuit 600 included in the circuit 200. 23B is used as the circuit 500 included in the circuit 400. The circuit 500 includes circuits 501_1 to 501_2 and a circuit The path 502 has the configuration shown in FIG. 21(A).

[0308] In the semiconductor device of FIG. 49, the circuit 100 has the structure shown in FIG. The circuit 300 in the circuit 200 has the configuration shown in FIG. The circuit 400 has the structure shown in FIG. The circuit 600 has the configuration shown in FIG. As a result, the configuration shown in FIG. 21(D) is used.

[0309] In the semiconductor device of FIG. 50, the circuit 100 has the structure shown in FIG. The circuit 300 in the circuit 200 has the configuration shown in FIG. The circuit 400 has the structure shown in FIG. The circuit 600 has the configuration shown in FIG. As such, the configuration shown in FIG. 22(A) is used.

[0310] As an example, the operation of the semiconductor device shown in FIG. , the signal SP1 goes high. Then, the transistor 301_1 turns on, The wiring 115_1 and the node 11 are brought into electrical continuity. The voltage at node 11 rises as a result of the supply of the voltage to transistor 10. 1_1 is turned on, so that the wiring 118 and the wiring 111 are in a conductive state. Since the signal CK1 is supplied to the line 111, the voltage of the line 111 decreases. P2 goes low, and the transistor 301_2 turns off. If the initial value of the voltage of node 12 is V1, the voltage of node 12 remains at V1. In the circuit 501_1, the transistor 532A is turned on, and the wiring 118 and the transistor Therefore, the voltage V1 is applied to the gate of the transistor 401_1. 01_1, the voltage at the gate of transistor 401_1 decreases. Then, the transistor 401_1 is turned off, and the wiring 118 and the node 11 are electrically disconnected. In the circuit 501_2, the transistor 532B is turned off, so that the wiring 118 and the gate of the transistor 401_2 are in a non-conductive state. The voltage is supplied to the gate of the transistor 401_2 through the transistor 531B. The voltage at the gate of the transistor 401_2 rises, and the transistor 401_2 turns on. Therefore, the wiring 118 and the node 12 are electrically connected. In the circuit 502, the transistor 532C is turned off, and therefore the wiring 11 8 and the gate of transistor 402 are in a non-conductive state. The voltage is supplied to the gate of transistor 402 via capacitor 531C, so that transistor 402 Then, the voltage of the gate of the transistor 402 is turned on, and the wiring 118 and the wiring 111 are electrically connected. Therefore, the voltage V1 is supplied to the wiring 111.

[0311] During period B1, node 11 remains at V2+Vth101_1+Vx, and node 1 2 remains approximately at V1. Therefore, transistor 101_1 remains on. Therefore, the wiring 112 and the wiring 111 remain in a conductive state. Then, the high-level signal CK 1 is supplied to the wiring 111, the voltage of the wiring 111 rises. During period A1, the transistor 532A remains on, as in period A1. The transistor 401_1 remains off. In the circuit 501_1, the transistor Therefore, the transistor 401_2 remains on. In the circuit 502, the transistor 532C is turned on, and the wiring 118 and the transistor Therefore, the voltage V1 is applied to the gate of the transistor 402. As a result, the voltage at the gate of transistor 402 decreases. Since the starter 402 is turned off, the wiring 118 and the wiring 111 are not electrically connected.

[0312] During the periods C1 and C2, the signal RE is at a high level. 1_1, the transistor 601_2, and the transistor 602 are turned on, so that the wiring 11 8 and node 11 are brought into a conductive state, and wiring 118 and node 12 are brought into a conductive state. 118 and the wiring 111 are electrically connected. Therefore, the voltage V1 is applied to the nodes 11 and 12. , and the wiring 111, the voltage of the node 11, the voltage of the node 12, and the wiring 1 At this time, in the circuit 501_1, the transistor 532A is turned off. As a result, there is no electrical continuity between the wiring 118 and the gate of the transistor 401_1. , the voltage V2 is supplied to the gate of the transistor 401_1 through the transistor 531A. As a result, the voltage at the gate of the transistor 401_1 rises. Since the node 1_1 is turned on, electrical continuity is established between the wiring 118 and the node 11. In this period, similar to the period A1, the transistor 532B remains off. In the circuit 502, the transistor 401_2 remains on as in the period A1. Therefore, transistor 402 remains on.

[0313] During the periods D1 to E1 and D2 to E2, the transistor 401_1 and the transistor 40 1_2 and the transistor 402 are turned on, so that the wiring 118 and the node 11 are in electrical continuity. The wiring 118 and the node 12 are electrically connected, and the wiring 118 and the wiring 111 are electrically connected. Therefore, the voltage V1 is supplied to the node 11, the node 12, and the wiring 111. Therefore, the voltage of the node 11, the voltage of the node 12, and the voltage of the wiring 111 are approximately V1 At this time, in the circuit 501_1, as in the period C1, the transistor 532 A is turned off. Therefore, the transistor 401_1 is turned on. In the circuit 501_2 As a result, the transistor 532B remains off, as in the period A1. In the circuit 502, the transistor 501_2 remains on as in the period A1. 32C remains off, so transistor 402 remains on.

[0314] During a period A2, the signal SP1 goes low. Here, if the initial value of the voltage at node 11 is V1, the voltage at node 11 is On the other hand, the signal SP2 goes high. Then, the transistor 30 1_2 is turned on, so that the wiring 115_2 and the node 12 are brought into electrical continuity. Since the high-level signal SP2 is supplied to the node 12, the voltage of the node 12 rises. At this time, the transistor 101_2 is turned on, so that the wiring 118 and the wiring 111 are electrically connected. Therefore, the low-level signal CK1 is supplied to the wiring 111, and the wiring 111 At this time, in the circuit 501_1, as in the period C1, the voltage of the transistor The transistor 532A is turned off, and the transistor 401_1 is turned on. In 2, the transistor 532B is turned on, so that the wiring 118 and the transistor 401 Therefore, the voltage V1 is applied to the gate of transistor 531B. Since the voltage is supplied to the gate of the transistor 401_2, the voltage of the gate of the transistor 401_2 Then, the transistor 401_2 is turned off, and the wiring 118 and the node In the circuit 502, as in the period A1, the transistor 53 2C is turned off, so that transistor 402 is turned off.

[0315] During period B2, node 11 remains at approximately V1, and node 12 is at V2+Vth. Therefore, transistor 101_2 remains on. Therefore, the wiring 112 and the wiring 111 remain in a conductive state. Then, the high-level signal CK 1 is supplied to the wiring 111, the voltage of the wiring 111 rises. In period A_1, the transistor 532A remains off, as in period A2. The transistor 401_1 remains on. In the circuit 501_2, the transistor Therefore, the transistor 401_2 remains off. In the circuit 502, the transistor 532C is turned on, as in the period B1. , transistor 402 is turned off.

[0316] Furthermore, the operation of the semiconductor device shown in Fig. 49 was verified. The verification results are shown in Fig. 51. 51 is a diagram showing the calculation results of the semiconductor device of this embodiment. As a comparative example, the transistor of the semiconductor device shown in FIG. transistor 101_2, transistor 301_2, transistor 303_1, transistor 30 3_2, transistor 401_2, transistor 555, transistor 556, and transistor The operation of a semiconductor device having a circuit configuration without the transistor 601_2 was also verified. ,The verification was performed with Vdd=30V, Vss=0V, clock frequency=25kHz (1 cycle=20 μsec), mobility of each transistor = 1 cm 2 / Vs, threshold voltage of each transistor = 5 The test was performed with V and output capacitance set to 50 pF.

[0317] FIG. 51(A) is a timing chart showing the verification results for the semiconductor device of the comparative example. As shown in 51(A), in the semiconductor device of the comparative example, the node n The transistor 101_1 is turned on in accordance with the voltage of 1, and the wiring 112 and the wiring 111 are connected to each other. The transistor 101_1 is turned on, and the signal CK1 is transmitted from the wiring 112 to the transistor 101_2. The signal is supplied to the wiring 111 via the starter 101_1.

[0318] FIG. 51(B) is a timing chart of the verification results for the semiconductor device shown in FIG. As shown in FIG. 51(B), in the semiconductor device shown in FIG. 48, the signal SEL1 The voltage of the node 11 changes according to the voltage of the node 11, and the transistor 101_1 is turned on, and the wiring 112 and the wiring 111 are brought into a conductive state via the transistor 101_1. The signal CK1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_1. During the period T2, the voltage of the node 12 changes in accordance with the signal SEL2. The transistor 101_2 is turned on in response to the voltage, and the wiring 112 and the wiring 111 are connected to each other. The signal CK1 is transmitted from the wiring 112 to the transistor 101_1. 01_1 to the wiring 111. Therefore, as shown in FIG. In the semiconductor device, different transistors are turned on and operated in each period, It can be seen that the number of times the transistor is turned on and the time it is turned on can be reduced.

[0319] (Fourth embodiment) In this embodiment, an example of a display device and a shift register included in the display device will be described. The shift register may include the semiconductor device according to any one of the first to third embodiments. It is possible to refer to a shift register as a semiconductor device or a gate driver. It should be noted that the contents described in the first to third embodiments will not be described here. The contents described in the first to third embodiments can be freely combined with the contents described in this embodiment. can be combined.

[0320] First, an example of a display device will be described with reference to FIGS. 26(A) to 26(D). The display device of the present invention includes a circuit 1001, a circuit 1002, a circuit 1003, a pixel portion 1004, and The pixel portion 1004 has a plurality of wirings extending from the circuit 1003_1. The plurality of wirings can be arranged as gate signal lines or scanning lines. Alternatively, the pixel portion 1004 may include a circuit 1002 or a terminal 1003. A plurality of wirings can be arranged extending from the wiring 05. The pixel portion 1004 has a function as a signal line or a data line. A plurality of wirings can be arranged extending from the wiring. It is possible for the pixel portion to function as a node line, but is not limited to this. The wiring arranged in the pixel section 1004 may be various wirings depending on the configuration of the pixel in the pixel section 1004. It is possible to place

[0321] The circuit 1001 supplies a signal, a voltage, a current, or the like to the circuit 1002 and the circuit 1003. The circuit 1001 has a function of controlling the timing of the circuit 1002 and the circuit In this way, the circuit 1001 functions as a controller, a control circuit, and a It functions as a circuit, timing generator, power supply circuit, regulator, etc. It is possible.

[0322] The circuit 1002 has a function of controlling the timing of supplying a video signal to the pixel portion 1004. Alternatively, the circuit 1002 may include a pixel portion 1004 having pixels and a The circuit 1002 has a function of controlling the luminance or transmittance of the pixel. The pixel has a function as a circuit, a source driver, a signal line driver circuit, or the like.

[0323] The circuit 1003_1 supplies a scanning signal or a gate signal to the pixel portion 1004. Alternatively, the circuit 1003_1 has a function of selecting a pixel included in the pixel portion 1004. In this way, the circuit 1003_1 can be used as a driver circuit, a gate driver, or The circuit 1003_1 has a function as a scanning line driver circuit. The circuit 1003_1 is formed on the same substrate 1006. However, it is not limited to this. It can be formed on a substrate separate from portion 1004.

[0324] Note that as shown in FIG. 26B, the display device can include a circuit 1003_2. The circuit 1003_2 has a function similar to that of the circuit 1003_1. The circuit 1003_1 and the circuit 1003_2 supply signals to the pixel portion 1004 at the same timing. This makes it possible to reduce the load on the display device. Alternatively, the circuit 1003_1 may select an odd-numbered pixel, and the circuit 100 3_2 can select pixels in even rows. By doing so, the driving frequency Since the number of stages is small, power consumption can be reduced. This allows for a larger area to be displayed, making it possible to make the display device higher definition. do.

[0325] As shown in FIG. 26C, the circuit 1002 is mounted on the same substrate 1006 as the pixel portion 1004. Alternatively, as shown in FIG. 26(D), a part of the circuit 1002 can be formed. The path 1002a can be formed on the same substrate 1006 as the pixel section 1004. Another circuit 1002 b can be formed on a substrate separate from the substrate 1006 .

[0326] Next, an example of a shift register will be described with reference to FIG. may be included in the circuit 1002, the circuit 1003_1, and / or the circuit 1003_2. Alternatively, the shift register may be used as a semiconductor device, a driver circuit, or a gate driver. It is possible to show.

[0327] The shift register 1100 includes flip-flops 1101_1 to 1101_N (N is 2 or more). The flip-flops 1101_1 to 1101_2 are natural numbers. 101_N corresponds to the semiconductor device described in the first to third embodiments. For example, flip-flops 1101_1 to 1101_N are each This shows a configuration in which a semiconductor device is used. However, this is not limited to this, and a flip-flop As 1101_1 to 1101_N, for example, It is possible to use a semiconductor device or circuit having such a configuration.

[0328] The shift register 1100 includes wirings 1111_1 to 1111_N, wiring 1112, and wiring 1113. 13, wiring 1114, wiring 1115_1~1115_2, wiring 1116_1~1116_ 2, wiring 1117, wiring 1118, wiring 1200_1 to 1200_N, and wiring 1201 1 to 1201_N. And, the flip-flops 1101_i (i is 1 to In any one of the wirings 111, 112, 113, 114, and 115, 15_1, wiring 115_2, wiring 116_1, wiring 116_2, wiring 117, wiring 118 , the wiring 711_1, and the wiring 711_2 are respectively connected to the wiring 1111_i, the wiring 1112, and the wiring 711_3. Wire 1113, wire 1114, wire 1200_i-1, wire 1201_i-1, wire 111 6_1, wiring 1116_2, wiring 1111_i+1, wiring 1118, wiring 1200_i, However, odd-numbered flip-flops and even-numbered flip-flops are connected to the wiring 1201_i. In many cases, the destinations of the wiring 112 and the wiring 113 are different between the flops. In the flip-flop of the second stage, the wiring 112 is connected to the wiring 1112, and the wiring 113 is connected to the wiring 1112. When connected to the wiring 1113, the flip-flop in the (i+1)th stage or the flip-flop in the (i-1)th stage In the flip-flop, wire 112 is connected to wire 1113, and wire 113 is connected to wire 1112. In the flip-flop 1101_1, the wiring 115_1 is , when the wiring 1115_1 is connected to the wiring 1115_2, and the wiring 1115_2 is connected to the wiring 1115_3, In the flip-flop 1101_N, the wiring 117 is connected to the wiring 1117. In many cases, however, it is not limited to this.

[0329] For example, signals GOUT_1 to GOUT_N are output from the wirings 1111_1 to 1111_N, respectively. The signals GOUT_1 to GOUT_N are each a flip-flop. The signals GOUT_1 to GOUT_N are output from the gates 1101_1 to 1101_N. UT_N has the same function as the signal OUT. CK1 is input to the wiring 1111, and, as an example, signal GCK2 is input to the wiring 1113. The signals GCK1 and GCK2 have the same functions as the signals CK1 and CK2. For example, a voltage V2 is supplied to the wiring 1114. For example, a signal GSP1 is input to the wiring 1115_1, and for example, a signal The signal GSP1 has the same function as the signal SP1, The signal GSP2 has the same function as the signal SP2. For example, a signal SEL1 is input to the wiring 1116_1, and a signal SEL2 is input to the wiring 1116_2. For example, a signal GRE is input to the wiring 1117. The signal GRE has the same function as the signal RE. For example, the wiring 1118 is connected to a voltage V 1 is supplied from the wiring 1200_1 to 1200_N. SOUT1_1 to SOUT1_N are output, and from wiring 1201_1 to 1201_N, As an example, signals SOUT2_1 to SOUT2_N are output. T1_1 to SOUT1_N have the same function as the signal SOUT1, and the signals SOUT2_1 1 to SOUT2_N have the same function as the signal SOUT2. However, this is not limited to this. , various other signals, various voltages, or various currents can be input to these wires. It is possible.

[0330] Next, the operation of the shift register in FIG. 27 will be explained with reference to the timing chart in FIG. 28. FIG. 28 is an example of a timing chart for explaining the operation of the shift register. FIG. 28 shows the signals GCK1, GCK2, GSP1, GSP2, and GRE, signal SEL1, signal SEL2, signal GOUT_1~GOUT_N, signal SOUT 10 shows an example of signals SOUT1_1 to SOUT1_N and signals SOUT2_1 to SOUT2_N.

[0331] Regarding the operation of the flip-flop 1101_i in the kth frame (k is a natural number equal to or greater than 2), First, the signal SOUT1_i-1 goes high. The flip-flop 1101_i starts operation in period A1. Then, the signals GCK1 and The signal GCK2 is inverted. Then, the flip-flop 1101_i is The operation starts, and the signal GOUT_i and the signal SOUT1_i become high level. OUT1_i is input to the flip-flop 1101_i+1, The process 1101_i+1 starts operation in the period A1. Then, the signals GCK1 and When the signal GCK2 is inverted again, the flip-flop 1101_i+1 outputs the The signal GOUT_i+1 and the signal SOUT1_i+1 become high level. The signal GOUT_i+1 is input to the flip-flop 1101_i. The flip-flop 1101_i starts its operation in the period C1. i becomes low level. After that, the signal SOUT1_i-1 becomes high level again. The flip-flop 1101_i operates in the period D1 and the period E1. Repeat.

[0332] The operation of the flip-flop 1101_i in the (k+1)th frame will be described. Then, the signal SOUT2_i-1 goes high. starts operation in period A2. After that, the signals GCK1 and GCK2 are inverted. Then, the flip-flop 1101_i starts its operation in the period B2, and the signal The signal SOUT2_i and the signal GOUT_i become high level. Since it is input to flip-flop 1101_i+1, flip-flop 1101_i+1 After that, the signal GCK1 and the signal GCK2 are again When the flip-flop 1101_i+1 is inverted, it starts operating in period B2 and outputs the signal The signal GOUT_i+1 and the signal SOUT2_i+1 become high level. i+1 is input to the flip-flop 1101_i, so the flip-flop 1101 _i starts operation in period C2. Therefore, the signal GOUT_i is at a low level. After that, the flip-flop remains in the ON state until the signal SOUT2_i-1 goes high again. The process 1101_i repeats the operation in the period D2 and the operation in the period E2.

[0333] In addition, in the flip-flop 1101_1, instead of the output signal of the previous stage flip-flop, In other words, the signal GSP1 is input via the wiring 1115_1, and the signal GSP2 is input via the wiring 1115_2. Therefore, the flip-flop 1101_1 receives the signal GSP1 through When signal GSP2 goes low, the operation in period A1 begins. The operation in the interval A2 starts.

[0334] In addition, in the flip-flop 1101_N, instead of the output signal of the next stage flip-flop, Therefore, the signal GRE is input via the wiring 1117. When this occurs, the flip-flop 1101_N starts operating in the period C1 or the period C2. do.

[0335] (Embodiment 5) In this embodiment, an example of a signal line driver circuit will be described. It can be referred to as a conductor device or a signal generating circuit.

[0336] An example of a signal line driver circuit will be described with reference to FIG. Multiple circuits named circuits 2002_1 to 2002_N (N is a natural number greater than or equal to 2) and circuit 20 00 and a circuit 2001. The circuits 2002_1 to 2002_N each include: Multiple transistors named 2003_1 to 2003_k (k is a natural number greater than or equal to 2) The transistors 2003_1 to 2003_k are N-channel type. However, the present invention is not limited to this, and the transistors 2003_1 to 2003_k may be P-channel transistors. It can be a channel type switch or a CMOS type switch.

[0337] The connection relationship of the signal line driver circuit will be described using the circuit 2002_1 as an example. The first terminals of the transistors 2003_1 to 2003_k are connected to the wiring 2005_1. The second terminals of the first and second terminals 2003_1 to 2003_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 2003_1 to 2003_k are connected to the wirings 2004_1 to 2004_k, respectively. For example, the first terminal of the transistor 2003_1 is connected to the wiring 2005_1. The second terminal of the transistor 2003_1 is connected to the wiring S1. The gate of the transistor 2003_1 is connected to a wiring 2004_1.

[0338] The circuit 2000 transmits signals to the circuits 2002_1 to 2002_k via the wirings 2004_1 to 2004_k. 2002_N and functions as a shift register or decoder. This signal is often a digital signal and functions as a selection signal. The wirings 2004_1 to 2004_k function as signal lines. It is possible to do this.

[0339] The circuit 2001 has a function of outputting signals to the circuits 2002_1 to 2002_N, and For example, the circuit 2001 can function as a signal generating circuit. A signal is supplied to the circuit 2002_1 via the wiring 2005_1. The signal is often an analog signal, and is often a video signal. The wiring 2005_1 to 2005_N can function as a video signal. , can function as a signal line.

[0340] The circuits 2002_1 to 2002_N determine to which wiring the output signal of the circuit 2001 is output. For example, the circuit 2002_1 is a signal output from the circuit 2001 to the wiring 2005_1. It has the function of selecting which wiring to output to.

[0341] The transistors 2003_1 to 2003_N are each configured to: The wiring 2005_1 has a function of controlling the conduction state between the wirings S1 to Sk, and functions as a switch. It works like this.

[0342] Next, the operation of the signal line driver circuit of FIG. 29(A) will be explained with reference to the timing chart of FIG. 29(B). 29B shows the signal 614_1 input to the wiring 2004_1. 1, signal 614_2 input to wiring 2004_2, signal 614_k input to wiring 2004_k 614_k, a signal 615_1 input to the wiring 2005_1, and a signal 615_2 input to the wiring 2005_2. 6 shows an example of an input signal 615_2.

[0343] One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is the period during which pixels belonging to a certain row are selected and a video signal is written to the pixel. This refers to the period during which it is possible to

[0344] One gate selection period is divided into a period T0 and periods T1 to Tk. is a period for simultaneously applying a precharge voltage to pixels belonging to a selected row. The periods T1 to Tk can function as precharge periods. This is the period for writing video signals to pixels belonging to the selected row, and functions as a write period. It is possible to do this.

[0345] For convenience, the operation of the signal line driver circuit will be described using the operation of the circuit 2002_1 as an example.

[0346] First, in a period T0, the circuit 2000 supplies high-level This outputs a signal from the GND terminal. Then, transistors 2003_1 to 2003_k turn on. Then, the wiring 2005_1 and the wirings S1 to Sk are electrically connected. Since the precharge voltage Vp is supplied to the wiring 2005_1, the precharge voltage V p is output to wirings S1 to Sk via transistors 2003_1 to 2003_k, respectively. Then, the precharge voltage Vp is written to the pixels belonging to the selected row. Therefore, the pixels belonging to the selected row are precharged.

[0347] Next, in the period T1, the circuit 2000 outputs a high-level signal to the wiring 2004_1. Then, the transistor 2003_1 is turned on, and the wiring 2005_1 and the wiring S 1 is in a conductive state. Then, the wiring 2005_1 and the wirings S2 to Sk are in a non-conductive state. At this time, the circuit 2001 outputs the signal Data (S1) to the wiring 2005_1. Then, the signal Data (S1) is input to the wiring S1 via the transistor 2003_1. In this way, the signal Data (S1) is output from selected pixels connected to the line S1. The pixels belonging to the selected row are written.

[0348] Next, in a period T2, the circuit 2000 outputs a high-level signal to the wiring 2004_2. Then, the transistor 2003_2 is turned on, and the wiring 2005_2 and the wiring S Then, the wiring 2005_1 and the wiring S1 are brought into a non-conductive state, and the wiring The line 2005_1 and the wirings S3 to Sk remain in a non-conductive state. If the signal Data(S2) is output to the wiring 2005_1, the signal Data( S2) is output to the wiring S2 via the transistor 2003_2. Data(S1) is written to the pixels that belong to the selected row among the pixels connected to the wiring S1. Get sucked in.

[0349] After that, until the period Tk, the circuit 2000 outputs a high level to the wirings 2004_1 to 2004_k. Since the signals are output in sequence, from period T3 to period Tk, similar to periods T1 and T2, The circuit 2000 sequentially outputs high-level signals to the wirings 2004_3 to 2004_k. Therefore, transistors 2003_3 to 2003_k are turned on in order, Therefore, the outputs from the circuit 2001 are The signals are output to the wirings S1 to Sk in order. , signals can be written in order.

[0350] An example of the signal line driver circuit has been described above. Since the circuit has a function as a connector, the number of signals or the number of wirings can be reduced. Alternatively, before writing a video signal to the pixel (period T0), a voltage for precharging is set to Since the video signal is written to the pixel, the time required to write the video signal can be shortened. It is possible to increase the size of the display device and to increase the resolution of the display device. However, this is not limited to this. , it is possible to omit period T0 and not precharge the pixel.

[0351] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so it is preferable that k≦6. More preferably, k≦3. Further preferably, k=2. It's nice.

[0352] In particular, if the color elements of a pixel are divided into n (n is a natural number greater than or equal to 2), k = n. For example, if the color components of a pixel are divided into three, red (R), green (G), and blue (B), In this case, one gate selection period is T0, It is divided into periods T1, T2, and T3. means writing video signals to red (R), green (G), and blue (B) pixels, respectively. However, the present invention is not limited to this, and the order of the periods T1, T2, and T3 can be arbitrary. It is possible to set it as desired.

[0353] In particular, a pixel has n (n is a natural number equal to or greater than 2) sub-pixels (hereinafter referred to as sub-pixels or sub-sub-pixels). For example, if a pixel is divided into two sub-pixels, k=n. When divided into pixels, k can be 2. In this case, one gate selection period is , period T0, period T1, and period T2. In period T1, two sub-pixels In period T1, a video signal is written to one of the two sub-pixels, and in period T2, a video signal is written to the other of the two sub-pixels. It is possible to incorporate it.

[0354] The driving frequencies of the circuit 2000 and the circuits 2002_1 to 2002_N are 1, and the transistors formed in the same process as the transistors formed in the pixel area A transistor can be used in the circuit 2000 and the circuits 2002_1 to 2002_N. The circuit 2000 and the circuits 2002_1 to 2002_N are formed on the same substrate as the pixel section. In this way, the number of connections between the substrate on which the pixel section is formed and the external circuit can be reduced. This allows for an improvement in yield and reliability. In addition, as shown in FIG. 24(C), the scanning line driving circuit is also formed on the same substrate as the pixel section. This further reduces the number of connections to external circuits.

[0355] The circuit 2000 may be any of the semiconductor devices or shift registers according to the first to fourth embodiments. In this case, the polarity of all the transistors in the circuit 2000 can be The characteristics can be N-channel or P-channel. This can reduce the number of defects, improve yield, or reduce costs.

[0356] In addition to the circuit 2000, all the transistors included in the circuits 2002_1 to 2002_N are The polarity of the transistor can be either N-channel or P-channel. The circuit 2000 and the circuits 2002_1 to 2002_N are formed on the same substrate as the pixel section. In this case, it is possible to reduce the number of steps, improve the yield, or reduce costs. By making the polarity of all transistors N-channel, the semiconductor layer of the transistor and As the semiconductor layer, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. This is because the driving frequencies of the circuit 2000 and the circuits 2002_1 to 2002_N are In many cases, the resistance is lower than that of the circuit 2001, and the transistors are formed in the same process as those formed in the pixel portion. This is because the transistors formed can be used in the circuits 2002_1 to 2002_N. do.

[0357] (Sixth embodiment) In this embodiment, a pixel configuration and pixel operation applicable to a liquid crystal display device will be described. explain.

[0358] 30A shows an example of a pixel. The pixel 3020 includes a transistor 3021, a liquid crystal element The first terminal of the transistor 3021 is The second terminal of the transistor 3021 is connected to a wiring 3031, and the second terminal of the transistor 3021 is connected to a part of the liquid crystal element 3022. one electrode of the capacitor 3023 and the gate of the transistor 3021. The other electrode of the liquid crystal element 3022 is connected to the electrode 3034. The other electrode of the capacitor 3023 is connected to a wiring 3033 .

[0359] For example, a video signal can be input to the wiring 3031. For example, a scan signal, a selection signal, or a gate signal can be input to the input terminal 2. For example, a constant voltage can be supplied to the wiring 3033. For example, a constant voltage may be supplied to the 034. The precharge voltage is supplied to the wiring 3031, and the It is possible to shorten the writing time. Alternatively, a signal can be input to the wiring 3033. By this, it is possible to control the voltage applied to the liquid crystal element 3022. By inputting a signal to the line 3033 or the electrode 3034, frame inversion driving is realized. It is possible to do this.

[0360] The wiring 3031 can function as a signal line, a video signal line, or a source line. The wiring 3032 can function as a signal line, a scanning line, or a gate signal line. The wiring 3033 can function as a power supply line or a capacitance line. The electrode 034 can function as a common electrode or a counter electrode. When a voltage is supplied to the wiring 3031 and the wiring 3032, these wirings are Alternatively, when a signal is input to the wiring 3033, the wiring 3033 can function as a power line. The line 3033 can function as a signal line.

[0361] The transistor 3021 controls electrical continuity between the wiring 3031 and one electrode of the liquid crystal element 3022. By controlling the timing of writing a video signal to the pixel, The capacitor element 3023 can function as a switch. The voltage difference between the electrode on one side and the wiring 3033 is maintained, and the voltage applied to the liquid crystal element 3022 is The capacitor has a function of keeping the capacitance constant, and functions as a storage capacitor. However, the invention is not limited to this.

[0362] FIG. 30B is a timing chart for explaining the operation of the pixel of FIG. 30A. 30B shows an example of a signal 3042_j (j is a natural number), a signal 3042_j+1 , signal 3041_i (i is a natural number), signal 3041_i+1, and voltage 3043 are shown. FIG. 30B shows the kth (k is a natural number equal to or greater than 2) frame and the k+1th frame. In addition, the signals 3042_j, ​​3042_j+1, 3041_i, and 3042_j+2 are 41_i+1 and a voltage 3043 are signals input to the j-th line wiring 3032, A signal input to the wiring 3032 in the +1th row, a signal input to the wiring 3031 in the i-th column, This is an example of a signal input to the wiring 3031 in the +1st column and a voltage supplied to the wiring 3033. .

[0363] The operation of the pixel 3020 in the jth row and the ith column will be described. When the i-th column wiring 3031 and the liquid crystal display Since the signal 3041_j is connected to one electrode of the element 3022, the signal 3041_j is input to the transistor 3 The signal is input to one electrode of the liquid crystal element 3022 via the capacitance element 3023. is the potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033. Therefore, the liquid crystal element The voltage applied to the liquid crystal element 3022 is constant. It expresses gradation according to the

[0364] In FIG. 30B, positive and negative signals are alternately arranged for each row selection period. This shows an example of a case where a signal is input to the line 3031. A positive signal is a signal that is input when the voltage is equal to or greater than the reference value (for example, A negative signal is a signal whose voltage is higher than the reference value (potential of electrode 3034). (for example, the potential of the electrode 3034). The signal input to the wiring 3031 can have the same polarity during one frame period. do.

[0365] In addition, in FIG. 30(B), the polarity of the signal 3041_i and the polarity of the signal 3041_i+1 are different. However, the present invention is not limited to this example, and the polarity and The polarity of the signal 3041_i+1 can be the same.

[0366] 30B shows a period in which the signal 3042_j is at a high level and a period in which the signal 3042_ This is an example of a case where the period j+1 is at a high level does not overlap. As shown in FIG. 30(C), the period when the signal 3042_j is at a high level and the period when the signal 3042_j is at a high level are not determined. It is possible for the period when the signal 3042_j+1 is at a high level to overlap. It is preferable that a signal of the same polarity is supplied to the line 3031 during one frame period. By doing so, the signal 3041_j written to the pixel in the jth row is used to write the pixel in the j+1th row. In this way, the time it takes to write a video signal to the pixel can be reduced. Therefore, the display device can be made high-definition. Alternatively, the display area of ​​the device can be enlarged by connecting the wiring 3031 to the wiring 3031 during one frame period. Since signals of the same polarity are input, power consumption can be reduced.

[0367] It should be noted that the pixel configuration of FIG. 31(A) and the timing chart of FIG. 30(C) can be combined. In this way, dot inversion driving can be realized. The pixel 3020(i, j) is connected to the wiring 3031_i. j+1) is connected to the wiring 3031_i+1. In this way, the wiring 3031_i and the wiring 3031_i+1 are connected alternately. The pixels belonging to the eye are written with positive and negative polarity signals alternately, row by row. However, the present invention is not limited to this, and the dot inversion driving can be realized. The pixels are arranged in a plurality of rows (for example, two or three rows) alternately with the wiring 3031_i and the wiring 3031 _i+1.

[0368] It is possible to use a sub-pixel structure as the pixel configuration. 31(a) and 31(b) show the configuration when a pixel is divided into two sub-pixels. B) is called 1S+2G (for example, one signal line and two scanning lines). The subpixel structure is shown in FIG. 31(C), which shows 2S+1G (for example, two signal lines and one The subpixel structure shown is called a subpixel structure (using a scan line). The pixel 3020B corresponds to the pixel 3020. The transistor 3021A and the transistor The transistor 3021B corresponds to the transistor 3021. The liquid crystal element 3022A and the liquid crystal element 3 3022B corresponds to the liquid crystal element 3022. The capacitors 3023A and 3023B corresponds to the capacitor 3023. The wiring 3031A and the wiring 3031B are The wiring 3032A and the wiring 3032B correspond to the wiring 3032.

[0369] Here, the pixel of this embodiment, the semiconductor device of the first to fifth embodiments, and the shift register By combining it with a display, a signal line driver circuit, or a For example, when a subpixel structure is used as a pixel, the display device can be driven Therefore, the number of gate signal lines or source lines increases. As a result, the number of connections between the substrate on which the pixel section is formed and the external circuitry increases. However, even if the number of gate signal lines increases, the width of the gate electrode 100 shown in the fifth embodiment can be increased. As shown in FIG. 1, the scanning line driver circuit can be formed on the same substrate as the pixel portion. The number of connections between the substrate on which the pixel part is formed and the external circuitry can be reduced significantly. Alternatively, even if the number of source lines increases, the signal line structure of the fifth embodiment can be used. By using a source line driver circuit, the number of source lines can be reduced. Sub-pixels can be formed without significantly increasing the number of connections between the substrate on which the pixel part is formed and the external circuit. Pixels of the structure can be used.

[0370] Alternatively, when a signal is input to a capacitance line, the number of connections between the substrate on which the pixel unit is formed and the external circuit is Therefore, the semiconductor of the first to fifth embodiments is used for the capacitance line. A physical device or a shift register can be used to provide the signal. The semiconductor device or shift register of the first to fifth embodiments may be formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel section is formed and the external circuit can be greatly reduced. A signal can be input to the capacitance line without increasing the capacitance.

[0371] Alternatively, when AC driving is used, the time required to write a video signal to a pixel becomes long. As a result, there may not be enough time to write the video signal to the pixels. In addition, when using pixels with a subpixel structure, the time required to write a video signal to the pixel is shortened. As a result, there may be insufficient time to write the video signal to the pixels. Therefore, it is possible to write a video signal to the pixel by using the signal line driver circuit of the fifth embodiment. In this case, a precharge voltage is applied to the pixel before writing the video signal to the pixel. Since the video signal is written to the pixel in a short time, the video signal can be written to the pixel in a short time. As shown, by overlapping the period in which one row is selected with the period in which another row is selected, , a video signal of another row can be used as a voltage for precharging.

[0372] (Embodiment 7) In this embodiment, examples of the structure of a transistor are shown in FIGS. ) will be referred to for explanation.

[0373] FIG. 32(A) is a diagram showing an example of the structure of a display device, and also shows a top gate type transistor. 32(A) is a diagram showing an example of the structure of a display device; FIG. 32(C) is a diagram showing an example of the structure of a bottom-gate transistor. 1 is a diagram illustrating an example of a structure of a transistor manufactured using a semiconductor substrate.

[0374] An example of a transistor in FIG. 32(A) is a transistor including an insulating layer 5261 formed over a substrate 5260 and a , formed on the insulating layer 5261, and regions 5262a, 5262b, 5262c, A semiconductor layer 5262 having regions 5262d and 5262e, and a semiconductor layer 5262 covering the semiconductor layer 5262 The insulating layer 5263 is formed as follows: a conductive layer 5264 formed on the insulating layer 5263 and the conductive layer 5264 and having an opening; and a conductive layer 5265 formed on the insulating layer 5265 and in the opening of the insulating layer 5265. and an electrically conductive layer 5266.

[0375] An example of the transistor in FIG. 32B includes a substrate 5300 and a A conductive layer 5301, an insulating layer 5302 formed to cover the conductive layer 5301, and the conductive layer 5302 301 and a semiconductor layer 5303a formed on the insulating layer 5302, and a semiconductor layer 5303b formed on the insulating layer 5302; A conductive layer 5304 is formed on the insulating layer 5302 and a conductive layer 5304 is formed on the insulating layer 5302. an insulating layer 5305 having an opening; and a conductive layer 5306 formed on the insulating film 5304.

[0376] An example of the transistor in FIG. 32C is a semiconductor substrate having a region 5353 and a region 5355. a plate 5352, an insulating layer 5356 formed on the semiconductor substrate 5352, and a semiconductor substrate 53 An insulating layer 5354 is formed on the insulating layer 5356, and a conductive layer 535 is formed on the insulating layer 5356. 7, and an insulating layer 5354, an insulating layer 5356, and a conductive layer 5357 are formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357, and an opening is formed. and an insulating layer 5358 having a conductive film formed on the insulating layer 5358 and in the opening of the insulating layer 5358. The region 5350 and the region 5351 each have a conductive layer 5359. A transduction device is created.

[0377] Note that when a display device is configured using the transistor of this embodiment, for example, As shown in 32(A), a conductive layer 5266 and an insulating layer 5265 are formed on the conductive layer 5266 and an opening 5266 is formed on the insulating layer 5265. an insulating layer 5267 having a portion, and a conductive film formed on the insulating layer 5267 and in the opening of the insulating layer 5267; a conductive layer 5268 formed on the insulating layer 5267 and the conductive layer 5268; an insulating layer 5269 having a thickness of 100 μm and a thickness of 100 μm formed on the insulating layer 5269 and in the opening of the insulating layer 5269; a light-emitting layer 5270 formed on the insulating layer 5269 and the light-emitting layer 5270; 271 and can be formed.

[0378] 32(B), a conductive layer 5306 is disposed on the insulating layer 5305. A liquid crystal layer 5307 is formed on the substrate 5301, and a conductive layer 5308 is formed on the liquid crystal layer 5307. It is possible to do this.

[0379] The insulating layer 5261 can function as a base film. The insulating layer 5263, the insulating layer 5302, and the insulating layer 5303 function as an isolation layer (for example, a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as gate electrodes. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are interlayer films or flat films. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5305 can function as a conductive film. 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a partition wall. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode, a common electrode, or the like. It is possible to do this.

[0380] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, a semiconductor substrate ( For example, silicon substrates, SOI substrates, plastic substrates, metal substrates, stainless steel substrates, Substrate with stainless steel foil, tungsten substrate, tungsten foil Examples of glass substrates include barium borosilicate glass substrates. Examples of flexible substrates include glass and aluminoborosilicate glass. Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone Plastics such as polyethersulfone (PES) or flexible synthetic resins such as acrylic Other examples include laminated films (polypropylene, polyester, vinyl, poly vinyl fluoride, vinyl chloride, etc.), paper containing fibrous materials, base film (polyester , polyamide, polyimide, inorganic vapor deposition film, paper, etc.

[0381] The semiconductor substrate 5352 is, for example, a single-crystal Si substrate having n-type or p-type conductivity. The region 5353 is, for example, a semiconductor substrate 5352 having impurities. For example, if the semiconductor substrate 5352 is a p-type When the region 5353 has a conductivity type of n-type, the region 5353 functions as an n-well. On the other hand, if the semiconductor substrate 5352 has n-type conductivity, the region 5353 has p-type conductivity. The region 5355 has a conductivity type and functions as a p-well. It is a region doped in the plate 5352 and functions as a source region or a drain region. In the semiconductor substrate 5352, an LDD region can be formed.

[0382] Examples of the insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and oxynitride. Silicon nitride (SiOxNy) (x>y>0), silicon nitride oxide (SiNxOy) (x>y>0) The insulating layer 5261 may be a film containing oxygen or nitrogen, such as a film containing oxygen or nitrogen, or a laminate structure of these. In one example of a two-layer structure, a silicon nitride film is provided as the first insulating layer, A silicon oxide film can be provided as the second insulating layer. The insulating layer 5261 has a three-layer structure. For example, a silicon oxide film is provided as the first insulating layer, and a silicon dioxide film is provided as the second insulating layer. It is possible to provide a silicon nitride film as an insulating layer and a silicon oxide film as a third insulating layer. do.

[0383] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single layer. Crystalline semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon) etc.), single crystal semiconductors, oxide semiconductors (e.g. ZnO, InGaZnO, IZO, ITO , SnO, TiO, AZTO), compound semiconductors (e.g., SiGe, GaAs), organic semiconductors Conductors, or carbon nanotubes.

[0384] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, when impurities are added to the region 5262a, the region 5262a functions as a channel region. The impurity added to the region 5262a can be added to the region 5262b, the region 5262c, and the region 5262d. 2c, region 5262d, or region 5262e. It is preferable that the region 5262b and the region 5262d are not included in the region 5262c or the region 5262e. It is a region where impurities are added at a lower concentration than that of the LDD (Lightly Doped Diode). However, the area 5262b and the area 5262 The region 5262c and the region 5262e are regions containing highly concentrated impurities. The material is added to the semiconductor layer 5262 and functions as a source region or a drain region. do.

[0385] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0386] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0387] An example of the insulating layer 5263, the insulating layer 5273, and the insulating layer 5356 is silicon oxide (Si Ox), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y>0), nitriding acid a film containing oxygen or nitrogen, such as silicon carbide (SiNxOy) (x>y>0), or There are also laminated structures.

[0388] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 The conductive film 9 can have a single layer structure or a multilayer structure and is formed using a conductive film. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum ( Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), Platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (C o), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C ), scandium (Sc), zinc (Zn), gallium (Ga), indium (In), tin (Sn), zirconium (Zr), and cesium (Ce) It can be a film of a single element, or a compound containing one or more elements selected from a group. The single film or compound may contain phosphorus (P), boron (B), arsenic (As), and / or It is possible for the compound to contain oxygen (O). Alloys containing one or more elements selected from the elements (e.g., indium tin oxide (I TO), indium zinc oxide (IZO), indium tin oxide with silicon oxide (ITS O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminum Aluminum neodymium (Al-Nd), aluminum tungsten (Al-Ta), aluminum Zirconium (Al-Zr), Aluminum Titanium (Al-Ti), Aluminum Cesium Al-Ce, Magnesium-Silver (Mg-Ag), Molybdenum-Niobium (Mo-Nb), Alloy materials such as molybdenum tungsten (Mo-W) and molybdenum tantalum (Mo-Ta) a compound of nitrogen with one or more elements selected from the above elements (e.g., For example, nitride films such as titanium nitride, tantalum nitride, and molybdenum nitride), or a combination of the above. Compounds of silicon with one or more elements selected from the elements (e.g., tungsten Silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Other examples include carbon nanotubes, Nanotube materials such as organic nanotubes, inorganic nanotubes, or metallic nanotubes be.

[0389] An insulating layer 5265, an insulating layer 5267, an insulating layer 5269, an insulating layer 5305, and an insulating layer 535 Examples of the insulating layer 8 include a single-layer insulating layer and a laminated structure of these layers. The material may be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (Si Oxygen such as silicon nitride (OxNy)(x>y>0) and silicon oxide nitride (SiNxOy)(x>y>0) or a film containing nitrogen, a film containing carbon such as DLC (diamond-like carbon), or , siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzo Examples include organic materials such as cyclobutene and acrylic.

[0390] An example of the light-emitting layer 5270 is an organic EL element or an inorganic EL element. An example of the element is a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material; an electron transport layer made of an electron transport material; A single layer structure of an electron injection layer, or a layer in which a plurality of materials among these materials are mixed, or These include laminated structures.

[0391] An example of the liquid crystal layer 5307, an example of a liquid crystal material applicable to the liquid crystal layer 5307, or the liquid crystal layer 530 Examples of liquid crystal modes applicable to liquid crystal elements including 7 include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals Cliotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), Ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma addressed liquid crystal (P ALC), banana type LCD, TN (Twisted Nematic) mode, STN (S Super Twisted Nematic mode, IPS (In-Plane-Switched) mode Fringe Field Switching (FFS) mode mode, MVA (Multi-domain Vertical Alignment) mode code, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Sym metric aligned Micro-cell) mode, OCB (Optica) l Compensated Birefringence mode, ECB (Electronic Control Board) Electrically Controlled Birefringence mode, FL C (Ferroelectric Liquid Crystal) mode, AFLC ( AntiFerroelectric Liquid Crystal) mode, PDL C (Polymer Dispersed Liquid Crystal) mode, There are various modes, such as Stormhost mode and Blue Phase mode.

[0392] Note that an insulating layer functioning as an alignment film is provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0393] Note that a color filter, a black matrix, or a protrusion may be formed on the conductive layer 5308. An insulating layer or the like that functions as an alignment film can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0394] The transistor of this embodiment can be applied to the first to sixth embodiments. In particular, in FIG. 32(B), the semiconductor layer is made of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or the like. When a semiconductor or an oxide semiconductor is used, the transistor may deteriorate. Therefore, the transistor of this embodiment can be used in a semiconductor device, a shift register, or a display device. However, the semiconductor devices of the first to sixth embodiments have a shorter lifespan. In semiconductor devices, shift registers, or display devices, deterioration of transistors can be suppressed. Therefore, the transistor of this embodiment can be used in combination with the semiconductors of the first to sixth embodiments. By applying it to devices, shift registers, or display devices, the life of these devices can be extended. It is possible.

[0395] (Embodiment 8) In this embodiment, an example of a cross-sectional structure of a display device will be described with reference to FIGS. Here, a liquid crystal display device will be described as an example.

[0396] 33A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. The pixel portion 5393 has pixels, and the pixels are connected to a driver circuit 53. For example, in the case of a liquid crystal display device, the output of the driver circuit 5392 The signal sets the voltage applied to the liquid crystal element.

[0397] FIG. 33(B) shows an example of the AB cross section of FIG. 33(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and the conductive layer 5404; a conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; a liquid crystal layer 5407 formed on the insulating layer 5405; 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0398] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a wiring, a pixel electrode, or a planarization film. The insulating layer 5408 can function as a polarizer or a reflector. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0399] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the voltage of each node may be rounded or delayed. However, as shown in Figure 33(B), An insulating layer 5408 that can function as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance generated between the driving circuit 5392 and the conductive layer 5409 can be reduced. This is because the dielectric constant of the sealing material is often lower than that of the liquid crystal layer. Therefore, the output signal of the driving circuit 5392 or the voltage of each node may be rounded. Alternatively, the delay can be reduced. Alternatively, the power consumption of the driver circuit 5392 can be reduced. can.

[0400] As shown in FIG. 33C, a film that functions as a sealant is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. The parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the voltage of each node. However, it is not limited to this, and a film that functions as a sealant can be provided on the driver circuit 5392. It is possible that the insulating layer 5408 is not formed.

[0401] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0402] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. and a semiconductor device or shift register according to any one of the first to fifth embodiments. For example, the semiconductor layer of the transistor can be formed of an amorphous semiconductor, a microcrystalline semiconductor, When an organic semiconductor or an oxide semiconductor is used, the channel width of the transistor becomes large. However, if the parasitic capacitance of the drive circuit can be reduced as in this embodiment, The channel width of the transistor can be reduced, which contributes to reducing the layout area. Therefore, the frame of the display device can be narrowed. It can be made thinner.

[0403] (Embodiment 9) In this embodiment, an example of a manufacturing process of a transistor and a capacitor will be described. A manufacturing process in the case where an oxide semiconductor is used for the layer will be described.

[0404] Referring to FIGS. 34A to 34C, a transistor 5441 and a capacitor 5442 are fabricated. An example of the process will be described. In FIGS. 34(A) to 34(C), a transistor and a capacitor element are The transistor 5441 is an example of an inverted staggered thin film transistor. a wiring is provided over the oxide semiconductor layer with a source electrode or a drain electrode interposed therebetween; This is an example of a transistor.

[0405] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. The conductive layers 5421 and 5422 are used as wirings, gate electrodes, or electrodes of a capacitor. After this, the resist mask is removed.

[0406] Next, the insulating layer 5423 is formed on the conductive layer 5421 by using a plasma CVD method or a sputtering method. The insulating layer 5423 is formed on the entire surface of the substrate 5420 via the conductive layer 5422. The conductive layer 5421 and the conductive layer 5422 may be formed by insulating the conductive layer 5421 and the conductive layer 5422. The insulating layer 5423 is formed as follows. The thickness of the insulating layer 5423 is often 50 nm to 250 nm. stomach.

[0407] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After this, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After the formation, a contact hole 5424 can be formed. The cross-sectional view corresponds to FIG.

[0408] Next, an oxide semiconductor layer is formed on the entire surface by sputtering. The oxide semiconductor layer is formed by sputtering, and a buffer layer (e.g., For example + The oxide semiconductor layer can be formed with a thickness of 5 nm to 2 00nm in most cases.

[0409] Next, a resist mask formed by a photolithography process using a third photomask The oxide semiconductor layer is selectively etched using the resist mask. do.

[0410] Next, a second conductive layer is formed on the entire surface by sputtering. The second conductive layer is selectively formed using a resist mask formed by a photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. It is possible to include

[0411] If heat treatment (for example, at 200°C to 600°C) is to be performed after this, Therefore, the second conductive layer is preferably made of Al and a heat-resistant material. Highly thermally conductive materials (e.g., Ti, Ta, W, Mo, Cr, Nd, Sc, Zr, Ce) Elements such as these, alloys combining these elements, or nitrides containing these elements However, it is not limited to this, and the second conductive material is also preferable. By forming the second conductive film into a laminated structure, it is possible to provide the second conductive film with high heat resistance. For example, it is possible to provide a highly heat-resistant conductive material such as Ti or Mo above and below Al. It is Noh.

[0412] When etching the second conductive layer, a part of the oxide semiconductor layer is also etched. By this etching, an oxide semiconductor layer 5425 overlapping with the conductive layer 5421 is formed. the oxide semiconductor layer 5425 in a portion where the second conductive layer is not formed or the oxide semiconductor layer 5425 in a portion where the second conductive layer is not formed The oxide semiconductor layer 5425 is often thinned by being etched. Therefore, the oxide semiconductor layer 5425 may not be etched. On the nitride semiconductor layer 5425 + In the case where a layer is formed, the oxide semiconductor layer 5425 is After this, the resist mask is removed. At this stage, the transistor 5441 and the capacitor 5442 are completed. The plan view corresponds to Figure 34(B).

[0413] Next, a heat treatment is performed at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. This thermal treatment causes rearrangement at the atomic level in the oxide semiconductor layer 5425. This heating (including photo-annealing) releases the strain that inhibits carrier movement. The timing of the treatment is not limited, and various timings can be used after the formation of the oxide semiconductor film. This can be done in a group.

[0414] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 may have a single-layer structure. For example, the insulating layer 5432 may be an organic insulating layer. When using the above, a composition that is a material for the organic insulating layer is applied, and the composition is then heated under an air atmosphere or a nitrogen atmosphere. Then, a heat treatment is performed at 200 to 600°C to form an organic insulating layer. By forming an organic insulating layer in contact with the semiconductor layer 5425, a highly reliable thin film transistor can be obtained. When an organic insulating layer is used as the insulating layer 5432, A silicon nitride film or a silicon oxide film can be provided under the insulating layer.

[0415] In addition, in FIG. 34(C), a mode in which the insulating layer 5432 is formed using a non-photosensitive resin is shown. For illustration, in the cross section of the region where the contact hole is to be formed, the end of the insulating layer 5432 is However, when the insulating layer 5432 is formed using a photosensitive resin, the contact In the cross section of the region where the cut hole is formed, the end of the insulating layer 5432 can be curved. As a result, the coverage of the third conductive layer or pixel electrode to be formed later is improved.

[0416] Instead of applying the composition, dipping, spray application, or ink application may be used depending on the material. Ink jet method, printing method, doctor knife, roll coater, curtain coater, or An ifcoater or the like can be used.

[0417] Note that the composition of the material for the organic insulating layer was not subjected to heat treatment after the oxide semiconductor layer was formed. The heat treatment can also serve as heat treatment for the oxide semiconductor layer 5425.

[0418] The thickness of the insulating layer 5432 is 200 nm to 5 μm, preferably 300 nm to 1 μm. It is possible to do this.

[0419] Next, a third conductive layer is formed on the entire surface. Next, a photolithography process is performed using a fifth photomask. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. The cross section at this stage is shown in FIG. The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, and the like. The conductive layer 5434 can function as a photo-transistor or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, the conductive layer 5422 can function as an electrode of the capacitor 5442. However, the present invention is not limited to this, and the conductive layer formed using the first conductive layer and the second conductive layer may be used. For example, the conductive layer may have a function of connecting to the conductive layer formed by using the conductive layer. By connecting the layer 5433 and the conductive layer 5434, the conductive layer 5422 and the conductive layer 543 0 can be connected via the third conductive layer (conductive layer 5433 and conductive layer 5434). becomes.

[0420] Note that the capacitor 5442 is formed by the conductive layer 5422 and the conductive layer 5434. Since the structure is such that 1 is sandwiched, the capacitance value of the capacitor 5442 can be increased. However, the present invention is not limited to this, and one of the conductive layer 5422 and the conductive layer 5434 may be omitted. It is Noh.

[0421] After the resist mask is removed by wet etching, the substrate is etched in air or nitrogen atmosphere. It is possible to carry out a heat treatment at 200 to 600°C under the above temperature.

[0422] Through the above steps, the transistor 5441 and the capacitor 5442 can be manufactured. .

[0423] As shown in FIG. 34D, an insulating layer 5435 is formed over the oxide semiconductor layer 5425. The insulating layer 5435 can be used to prevent oxidation when the second conductive layer is patterned. It has the function of preventing the nitride semiconductor layer 5425 from being scraped off, and functions as a stop film. Therefore, the thickness of the oxide semiconductor layer 5425 can be reduced, Reduction of drive voltage, reduction of off-current, improvement of on / off ratio of drain current, improvement of S value, etc. Note that the insulating layer 5435 is formed by continuously forming the oxide semiconductor layer and the insulating layer. The pattern is then formed on the entire surface, and then a pattern is formed by a photolithography process using a photomask. The insulating layer is selectively patterned using a resist mask to form a Thereafter, a second conductive layer is formed on the entire surface, and an oxide semiconductor layer is formed simultaneously with the second conductive layer. That is, the oxide semiconductor layer and the second In this case, an oxide film must be formed under the second conductive layer. In this way, the insulating layer 543 is formed without increasing the number of steps. In such a manufacturing process, an oxide semiconductor layer is formed under the second conductive layer. However, the present invention is not limited to this, and the oxide semiconductor layer may be patterned. After the wiring, an insulating layer is formed on the entire surface, and the insulating layer is patterned to form an insulating film. A layer 5435 can be formed.

[0424] In FIG. 34D, the capacitor 5442 includes a conductive layer 5422 and a conductive layer 5431. The insulating layer 5423 and the oxide semiconductor layer 5436 are sandwiched between the insulating layer 5423 and the oxide semiconductor layer 5436. The oxide semiconductor layer 5436 can be omitted. 5431 is connected via a conductive layer 5437 formed by patterning the third conductive layer. Such a structure can be used, for example, in the pixels of a liquid crystal display device. For example, the transistor 5441 functions as a switching transistor and The element 5442 can function as a storage capacitor. The conductive layer 5422, the conductive layer 5429, and the conductive layer 5437 are gate signal lines, capacitance lines, and so on, respectively. It can function as a pixel electrode, but is not limited to this. As in FIG. 34(D), in FIG. 34(C), a conductive layer 5430 and a conductive layer 5431 are The connection can be made via a third conductive layer.

[0425] As shown in FIG. 34(E), after the second conductive layer is patterned, the oxide semiconductor layer 5425. By doing so, the second conductive layer can be patterned. When the oxide semiconductor layer is removed, the oxide semiconductor layer is not formed. Therefore, the thickness of the oxide semiconductor layer can be reduced, and therefore, the driving Reduction of voltage, reduction of off-current, improvement of on / off ratio of drain current, improvement of S value, etc. Note that the oxide semiconductor layer 5425 is formed after the second conductive layer is patterned. After that, an oxide semiconductor layer is formed on the entire surface, and then photolithography is performed using a photomask. The oxide semiconductor layer is selectively patterned using a resist mask formed by a patterning process. It can be formed by

[0426] In FIG. 34E, the capacitor 5442 is formed by connecting the conductive layer 5422 and the third conductive layer. The insulating layer 5423 and the insulating layer 5432 are formed by the conductive layer 5439 formed by turning. The conductive layer 5422 and the conductive layer 5430 are sandwiched between the third conductive layer. The connection is made via a conductive layer 5438 formed by patterning. 9 is connected to a conductive layer 5440 formed by patterning the second conductive layer. 34(E), in FIGS. 34(C) and (D), the conductive layer 5430 and the conductive layer 54 22 can be connected via a conductive layer 5438.

[0427] The thickness of the oxide semiconductor layer (or chann...

Claims

1. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a scanning line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a power supply line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the scanning line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; the first conductive layer serving as one of a source electrode and a drain electrode of the first transistor serves as one of a source electrode and a drain electrode of the second transistor; the second conductive layer serving as the other of the source electrode and the drain electrode of the first transistor also serves as the other of the source electrode and the drain electrode of the second transistor; In a plan view, the first conductive layer has a plurality of first regions extending in a first direction and a second region connected to the plurality of first regions in a region that does not overlap with a semiconductor layer having a channel formation region of the first transistor; In a plan view, the second conductive layer has a plurality of third regions extending in the first direction and a fourth region connected to the plurality of third regions in a region overlapping with the semiconductor layer, the second conductive layer has an opening; the opening has a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer, The opening has a region overlapping with a third conductive layer that functions as a gate electrode of the first transistor, and a region not overlapping with the third conductive layer.

2. A semiconductor device comprising first to fourth transistors, one of a source electrode and a drain electrode of the first transistor is always electrically connected to a scanning line; the other of the source electrode and the drain electrode of the first transistor is always electrically connected to a power supply line; one of a source electrode and a drain electrode of the second transistor is always electrically connected to the scanning line; the other of the source electrode and the drain electrode of the second transistor is always electrically connected to the power supply line; one of a source electrode and a drain electrode of the third transistor is always electrically connected to a gate electrode of the first transistor; one of a source electrode and a drain electrode of the fourth transistor is always electrically connected to a gate electrode of the second transistor; the first conductive layer serving as one of a source electrode and a drain electrode of the first transistor serves as one of a source electrode and a drain electrode of the second transistor; the second conductive layer serving as the other of the source electrode and the drain electrode of the first transistor also serves as the other of the source electrode and the drain electrode of the second transistor; In a plan view, the first conductive layer has a plurality of first regions extending in a first direction and a second region connected to the plurality of first regions in a region that does not overlap with a semiconductor layer having a channel formation region of the first transistor; In a plan view, the second conductive layer has a plurality of third regions extending in the first direction and a fourth region connected to the plurality of third regions in a region overlapping with the semiconductor layer, the second conductive layer has an opening; the opening has a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer, The opening has a region overlapping with a third conductive layer that functions as a gate electrode of the first transistor, and a region not overlapping with the third conductive layer.

3. In claim 1 or claim 2, The third conductive layer is always electrically connected to a fifth conductive layer that functions as one of a source electrode and a drain electrode of the third transistor through a fourth conductive layer.

4. In any one of claims 1 to 3, The first conductive layer is always electrically connected to the scanning line via a sixth conductive layer.

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