Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device that can ensure normal operation of an analog circuit.SOLUTION: A semiconductor device includes a first semiconductor chip, a die attach film, a second semiconductor chip, and a resin molding member. The first semiconductor chip is attached to the second semiconductor chip via the die attach film. The second semiconductor chip includes an analog circuit, bonding pads, and at least one irregular-shaped bonding pad that serves as an alignment mark for the first semiconductor chip. In a plan view, the analog circuit is located inside the outer periphery of the die attach film. The resin molding member seals the first semiconductor chip, the second semiconductor chip, and the die attach film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and can be suitably used, for example, in a system-in-package type semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Japanese Patent Application Laid-Open Publication No. 2014-132682 (Patent Document 1) discloses a method for manufacturing a resin-encapsulated semiconductor device. The method for manufacturing a resin-encapsulated semiconductor device in Patent Document 1 includes a step of preparing a wiring substrate and a step of mounting a semiconductor chip on the wiring substrate. The wiring substrate has a plurality of pads and an L-shaped alignment target. In the step of mounting the semiconductor chip on the wiring substrate, the alignment target is recognized to align the semiconductor chip with the wiring substrate, and then the semiconductor chip is mounted on the wiring substrate.

[0003] Japanese Patent Laid-Open Publication No. 2006-222147 (Patent Document 2) discloses a semiconductor device. The semiconductor device described in Patent Document 2 has a bonding pad and a discrimination mark provided at a distance from the bonding pad. The bonding pad includes a probing mark formation area and a bonding area. The probing mark formation area and the bonding area are configured to be distinguishable based on the planar shape of the discrimination mark. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-132682 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-222147 Summary of the Invention [Problem to be solved by the invention]

[0005] A known example of a resin-encapsulated semiconductor device is a system-in-package semiconductor device in which multiple semiconductor chips stacked with a die attach film interposed therebetween are resin-encapsulated. When viewed from above in the stacking direction of the multiple semiconductor chips, if the outer edge of the die attach film overlaps the analog circuit of one of the multiple semiconductor chips located below the die attach film, stress is applied to the analog circuit, which may cause the analog circuit to malfunction. Other issues and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a first semiconductor chip, a die attach film provided on the first semiconductor chip, a second semiconductor chip, and a resin molding member. The first semiconductor chip is attached to the second semiconductor chip via the die attach film. The second semiconductor chip includes an analog circuit, bonding pads, and at least one irregular-shaped bonding pad having a shape different from that of the bonding pads. The at least one irregular-shaped bonding pad is an alignment mark for the first semiconductor chip. In a plan view from the stacking direction of the first semiconductor chip and the die attach film, the analog circuit is located inside the outer periphery of the die attach film. The resin molding member seals the first semiconductor chip, the second semiconductor chip, and the die attach film.

[0007] According to one embodiment, a method for manufacturing a semiconductor device includes providing a die attach film on a first semiconductor chip and aligning the first semiconductor chip with respect to a second semiconductor chip. The second semiconductor chip includes an analog circuit, bonding pads, and at least one irregular-shaped bonding pad having a shape different from that of the bonding pads. In the step of aligning the first semiconductor chip with respect to the second semiconductor chip, the first semiconductor chip is aligned with respect to the second semiconductor chip using the at least one irregular-shaped bonding pad as an alignment mark for the first semiconductor chip so that the analog circuit is located inside the outer periphery of the die attach film in a plan view from the stacking direction of the first semiconductor chip and the die attach film. The method for manufacturing a semiconductor device includes attaching the first semiconductor chip to the second semiconductor chip via the die attach film and providing a resin molding member that encapsulates the first semiconductor chip, the second semiconductor chip, and the die attach film. [Effects of the Invention]

[0008] According to the embodiment, it is possible to provide a semiconductor device that can ensure normal operation of analog circuits. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 2] 12 is a schematic cross-sectional view of the semiconductor device according to the first and second embodiments taken along the cross-sectional line II-II shown in FIGS. 2 and 11. FIG. [Figure 3] FIG. 1 is a flowchart showing a method for manufacturing semiconductor devices according to first, second, fourth and fifth embodiments. [Figure 4] 10 is a schematic plan view showing a step of aligning a first semiconductor chip with a second semiconductor chip in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 5]13 is a schematic cross-sectional view taken along the cross-sectional line VV shown in FIGS. 4 and 12, illustrating a step of aligning a first semiconductor chip with a second semiconductor chip in the manufacturing method of the semiconductor device according to the first and second embodiments. FIG. [Figure 6] 4 is a schematic cross-sectional view showing a resin molding step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 7] FIG. 10 is a schematic plan view of a semiconductor device according to a modified example of the first embodiment. [Figure 8] 8 is a schematic cross-sectional view of the semiconductor device according to a modified example of the first embodiment, taken along the cross-sectional line VIII-VIII shown in FIG. 7. [Figure 9] 10 is a schematic plan view showing a step of aligning a first semiconductor chip with a second semiconductor chip in a manufacturing method of a semiconductor device according to a modification of the first embodiment. FIG. [Figure 10] 10 is a schematic cross-sectional view taken along the cross-sectional line XX in FIG. 9, illustrating a step of aligning the first semiconductor chip with the second semiconductor chip in the method for manufacturing the semiconductor device according to the modified example of the first embodiment. [Figure 11] FIG. 10 is a schematic plan view of a semiconductor device according to a second embodiment. [Figure 12] 10 is a schematic plan view showing a step of aligning a first semiconductor chip with a second semiconductor chip in the method for manufacturing a semiconductor device according to the second embodiment. FIG. [Figure 13] FIG. 11 is a schematic plan view of a semiconductor device according to a third embodiment. [Figure 14] 14 is a schematic cross-sectional view of the semiconductor device of the third embodiment taken along the cross-sectional line XIV-XIV shown in FIG. 13. [Figure 15] FIG. 11 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 16] 13 is a schematic plan view showing a step of aligning a first semiconductor chip with a second semiconductor chip in the method for manufacturing a semiconductor device according to the third embodiment. FIG. [Figure 17]17 is a schematic cross-sectional view taken along the cross-sectional line XVII-XVII shown in FIG. 16, illustrating a step of aligning the first semiconductor chip with the second semiconductor chip in the method for manufacturing the semiconductor device according to the third embodiment. [Figure 18] FIG. 10 is a schematic plan view of a semiconductor device according to a fourth embodiment. [Figure 19] 19 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment taken along the cross-sectional line XIX-XIX shown in FIG. 18. [Figure 20] 13 is a schematic cross-sectional view showing a step of providing a die attach film on a first semiconductor chip in a manufacturing method of a semiconductor device according to a fourth embodiment. FIG. [Figure 21] 21 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 20 of providing a die attach film on a first semiconductor chip in the method for manufacturing a semiconductor device in accordance with the fourth embodiment. [Figure 22] 22 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 21 of providing a die attach film on a first semiconductor chip in the method for manufacturing a semiconductor device in accordance with the fourth embodiment. [Figure 23] 13 is a schematic plan view showing a step of aligning a first semiconductor chip with a second semiconductor chip in a manufacturing method of a semiconductor device according to a fourth embodiment. FIG. [Figure 24] 24 is a schematic cross-sectional view taken along the cross-sectional line XXIV-XXIV shown in FIG. 23, illustrating a step of aligning the first semiconductor chip with the second semiconductor chip in the method for manufacturing the semiconductor device according to the fourth embodiment. [Figure 25] FIG. 10 is a schematic plan view of a semiconductor device according to a fifth embodiment. [Figure 26] 26 is a schematic cross-sectional view of the semiconductor device of the fifth embodiment taken along the cross-sectional line XXVI-XXVI shown in FIG. 25. [Figure 27] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a first modified example of the fifth embodiment. [Figure 28] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a second modified example of the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The semiconductor device according to the embodiment will be described below, with the same reference numerals being used to designate the same components, and description thereof will not be repeated.

[0011] (Embodiment 1) The configuration of the semiconductor device DEV of the first embodiment will be described with reference to Figures 1 and 2. The semiconductor device DEV of the present embodiment is, for example, a system-in-package (SiP) type semiconductor device. The semiconductor package configuration is, for example, a land grid array (LGA) type semiconductor device. The semiconductor device DEV mainly includes a first semiconductor chip CHP1, a die attach film DAF, a second semiconductor chip CHP2, a resin molding member RMB, a wiring board WB, and conductive wires WIR.

[0012] The first semiconductor chip CHP1 is, but is not limited to, an ASIC (Application Specific Integrated Circuit) chip, for example. The first semiconductor chip CHP1 includes a plurality of bonding pads BP3. The plurality of bonding pads BP3 are formed on a main surface of the first semiconductor chip CHP1 opposite to the main surface facing the second semiconductor chip CHP2. The plurality of bonding pads BP3 are formed of a conductive material such as copper (Cu) or aluminum (Al). The first semiconductor chip CHP1 has a first corner portion CN1 and a second corner portion CN2 diagonally located to the first corner portion CN1. The outer periphery of the first semiconductor chip includes an outer periphery portion extending in a first direction DR1 and an outer periphery portion extending in a second direction DR2 intersecting the first outer periphery portion. The second direction DR2 is, for example, perpendicular to the first direction DR1.

[0013] The die attach film DAF is provided on the first semiconductor chip CHP1. For example, the die attach film DAF is attached to the first semiconductor chip CHP1. The storage modulus of the die attach film DAF at 150 degrees Celsius is 20 MPa or less. The storage modulus of the die attach film DAF at 150 degrees Celsius may be 50 MPa or less, or may be 20 MPa or less.

[0014] The second semiconductor chip CHP2 is, but is not limited to, a motor driver, for example. The operation of the second semiconductor chip CHP2 is controlled by the first semiconductor chip CHP1. The second semiconductor chip CHP2 controls a motor (not shown).

[0015] The second semiconductor chip CHP2 has a main surface MSF. The main surface MSF extends along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The second semiconductor chip CHP2 includes a chip body CBD, an analog circuit ANC, a plurality of bonding pads BP1, and at least one variant bonding pad BP2. The second semiconductor chip CHP2 may further include a protective layer PRL.

[0016] The chip body CBD is made of a semiconductor material such as silicon (Si) or silicon carbide (SiC).

[0017] The analog circuit ANC is formed on the surface of the chip body CBD on the main surface MSF side. The analog circuit ANC is, for example, an operational amplifier or a constant current circuit, and is an electric circuit that is sensitive to stress.

[0018] The bonding pads BP1 and at least one variant bonding pad BP2 are formed on the surface of the chip body CBD on the main surface MSF side. The bonding pads BP1 and at least one variant bonding pad BP2 are made of a conductive material such as copper (Cu) or aluminum (Al).

[0019] At least one variant bonding pad BP2 has a shape different from that of the bonding pad BP1. For example, in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF (hereinafter simply referred to as "plan view"), the bonding pad BP1 has a rectangular shape, and at least one variant bonding pad BP2 has a rectangular shape with chamfered corners. At least one variant bonding pad BP2 may have a rectangular shape with rounded corners. The number of the at least one variant bonding pad BP2 is less than the number of the multiple bonding pads BP1. The second semiconductor chip CHP2 may include multiple variant bonding pads BP2. In this embodiment, the second semiconductor chip CHP2 includes four variant bonding pads BP2.

[0020] The at least one variant bonding pad BP2 is an alignment mark for the first semiconductor chip CHP1, that is, the first semiconductor chip CHP1 is aligned with respect to the second semiconductor chip CHP2 by using the at least one variant bonding pad BP2 as an alignment mark.

[0021] In a plan view, an extension line EXL of the outer periphery of at least one variant bonding pad BP2 is offset from the analog circuit ANC. In a plan view, the extension line EXL of the outer periphery of at least one variant bonding pad BP2 extends outside the analog circuit ANC. In a plan view, the outer periphery of the first semiconductor chip CHP1 is located on the extension line EXL of the outer periphery of at least one variant bonding pad BP2.

[0022] For example, the at least one variant bonding pad BP2 includes variant bonding pads BP2a1 and BP2a2 for aligning the first corner CN1 of the first semiconductor chip CHP1 and variant bonding pads BP2b1 and BP2b2 for aligning the second corner CN2 of the first semiconductor chip CHP1. The variant bonding pads BP2a1 and BP2a2 include a variant bonding pad BP2a1 for guiding the outer peripheral edge portion of the first semiconductor chip CHP1 extending in the first direction DR1 and a variant bonding pad BP2a2 for guiding the outer peripheral edge portion of the first semiconductor chip CHP1 extending in the second direction DR2. The variant bonding pads BP2b1, BP2b2 include a variant bonding pad BP2b1 for guiding the outer edge portion of the first semiconductor chip CHP1 extending in the first direction DR1, and a variant bonding pad BP2b2 for guiding the outer edge portion of the first semiconductor chip CHP1 extending in the second direction DR2.

[0023] The protective layer PRL is formed of an insulating material such as polyimide. The protective layer PRL covers the analog circuit ANC. The bonding pad BP1 and at least one variant bonding pad BP2 are exposed from the protective layer PRL. The surface of the protective layer PRL opposite to the chip body CBD constitutes part of the main surface MSF.

[0024] The first semiconductor chip CHP1 is attached to the main surface MSF of the second semiconductor chip CHP2 via the die attach film DAF. In plan view, the analog circuit ANC is located inside the outer periphery of the die attach film DAF. In plan view, the analog circuit ANC is shifted from the outer periphery of the die attach film DAF. In plan view, the outer periphery of the die attach film DAF is located inside the outer periphery of the first semiconductor chip CHP1.

[0025] The wiring board WB is, for example, a multilayer wiring board including multiple wiring layers. The insulating layer that electrically insulates adjacent wiring layers from each other is made of, for example, prepreg formed by impregnating glass fiber with resin. The multiple wiring layers are made of, for example, a metal such as copper (Cu). The wiring board WB supports a second semiconductor chip CHP2. For example, the second semiconductor chip CHP2 is fixed to the upper surface of the wiring board WB using a die bonding paste DBP or a die attach film (not shown). The die bonding paste DBP is, for example, an acrylic resin-based adhesive. A plurality of bonding pads BP4 are formed on the upper surface of the wiring board WB. Furthermore, a plurality of terminals (not shown) are formed on the lower surface of the wiring board WB. The plurality of bonding pads BP4 and the multiple terminals are each made of a conductive material such as copper (Cu) or aluminum (Al). The wiring board WB supplies electrical signals to the first semiconductor chip CHP1 and the second semiconductor chip CHP2, and receives electrical signals from the first semiconductor chip CHP1 and the second semiconductor chip CHP2.

[0026] The conductive wire WIR is a metal wire such as a gold wire, a copper wire, or an aluminum wire. The conductive wire WIR is bonded to the bonding pad BP1 or the variant bonding pad BP2 and the bonding pad BP4, electrically connecting the bonding pad BP1 or the variant bonding pad BP2 and the bonding pad BP4. The conductive wire WIR is bonded to the bonding pad BP1 or the variant bonding pad BP2 and the bonding pad BP3, electrically connecting the bonding pad BP1 or the variant bonding pad BP2 and the bonding pad BP3. The conductive wire WIR is bonded to the bonding pad BP3 and the bonding pad BP4, electrically connecting the bonding pad BP3 and the bonding pad BP4.

[0027] The resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF. The resin molding member RMB includes, for example, a thermosetting resin and a filler dispersed in the thermosetting resin. The thermosetting resin is, for example, an epoxy resin. The filler is, for example, silica particles. The filler content of the resin molding member RMB is, for example, 70 weight percent or more and 90 weight percent or less.

[0028] An example of a method for manufacturing the semiconductor device DEV of this embodiment will be described with reference to FIGS.

[0029] 3, a die attach film DAF is provided on the first semiconductor chip CHP1 (step S1). For example, the die attach film DAF is attached to the first semiconductor chip CHP1. The outer periphery of the die attach film DAF is flush with the outer periphery of the first semiconductor chip CHP1, for example.

[0030] 3 to 5, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 (step S2). Specifically, while using at least one variant bonding pad BP2 as an alignment mark for the first semiconductor chip CHP1, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF in plan view.

[0031] For example, in a plan view, an extension line EXL of the outer periphery of at least one variant bonding pad BP2 is offset from the analog circuit ANC. The first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the outer periphery of the first semiconductor chip CHP1 is positioned on the extension line EXL of the outer periphery of at least one variant bonding pad BP2 in a plan view. In this way, the first semiconductor chip CHP1 can be aligned with the second semiconductor chip CHP2 so that the outer periphery of the die attach film DAF is offset from the analog circuit ANC in a plan view.

[0032] Specifically, the at least one variant bonding pad BP2 includes multiple variant bonding pads BP2a1, BP2a2, BP2b1, and BP2b2. In a plan view, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that a first corner CN1 of the first semiconductor chip CHP1 is positioned on an extension line EXL of the outer peripheries of the variant bonding pads BP2a1 and BP2a2, and a second corner CN2 of the first semiconductor chip CHP1 is positioned on an extension line EXL of the outer peripheries of the variant bonding pads BP2b1 and BP2b2. For example, the outer periphery of the first semiconductor chip CHP1 extending in the first direction DR1 is positioned on the extension line EXL of the outer peripheries of the variant bonding pads BP2a1 and BP2b1. The outer periphery of the first semiconductor chip CHP1 extending in the second direction DR2 is positioned on the extension line EXL of the outer peripheries of the variant bonding pads BP2a2 and BP2b2.

[0033] 3, the first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF (step S3). Specifically, the die attach film DAF is brought into contact with the main surface MSF of the second semiconductor chip CHP2. The die attach film DAF is heated to 150 degrees Celsius to harden the die attach film DAF. In this way, the first semiconductor chip CHP1 is attached to the main surface MSF of the second semiconductor chip CHP2 via the die attach film DAF.

[0034] 3, the second semiconductor chip CHP2 is fixed to the wiring substrate WB using die bonding paste DBP or a die attach film (not shown) (step S4). Here, the wiring substrate WB has a plurality of package formation areas (not shown), and the second semiconductor chip CHP2 is fixed to each of these plurality of package formation areas. In this embodiment, the description focuses on one package formation area. Also, in this embodiment, the mounting order has been described in which the first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 and then the second semiconductor chip CHP2 is fixed to the wiring substrate WB, but the mounting order may be such that the second semiconductor chip CHP2 is fixed to the wiring substrate WB and then the first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2.

[0035] 3, the conductive wires WIR are bonded to the bonding pads (step S5). In this embodiment, the conductive wires WIR are bonded to the bonding pads BP1, BP3, BP4 and the variant bonding pad BP2.

[0036] 3 and 6, a resin molding member RMB is provided to seal the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF (step S6). For example, the mold MLD is opened, and a stack of the first semiconductor chip CHP1, the die attach film DAF, and the second semiconductor chip CHP2 located in each of the multiple package formation areas is placed in the cavity of the mold MLD. The mold MLD is closed, and a molding resin is injected into the cavity of the mold MLD to collectively seal the multiple package formation areas. The molding resin is heated, for example, to a molding temperature (e.g., 150°C) to harden. In this manner, the resin molding member RMB is formed. Note that in this embodiment, a land grid array (LGA) type semiconductor device has been described as the semiconductor package configuration, but a ball grid array (LGA) type semiconductor device may also be used. In the case of a ball grid array (LGA) type semiconductor device, after the resin molding member RMB is formed, multiple solder balls are formed on multiple terminals.

[0037] 3, the wiring board WB and the resin molding member RMB are divided into package formation areas, and the stack of the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the wiring board WB is diced into individual pieces (step S7). In this way, the semiconductor device DEV of the present embodiment is obtained.

[0038] The configuration of a semiconductor device DEV according to a modification of the present embodiment will be described with reference to FIGS.

[0039] In a modification of the present embodiment, in plan view, an extension line EXL of the outer periphery of at least one variant bonding pad BP2 is located on the outer periphery of the analog circuit ANC. In plan view, the outer periphery of the first semiconductor chip CHP1 is shifted from the extension line EXL of the outer periphery of at least one variant bonding pad BP2.

[0040] Referring to Figures 3, 9 and 10, an example of a method for manufacturing a semiconductor device DEV of a modified example of this embodiment has steps similar to those of an example of a method for manufacturing a semiconductor device DEV of this embodiment, but differs from the example of a method for manufacturing a semiconductor device DEV of this embodiment mainly in step S2.

[0041] In step S2 of the modification of the present embodiment, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the outer peripheral edge of the first semiconductor chip CHP1 is offset from an extension line EXL of the outer peripheral edge of at least one variant bonding pad BP2 in plan view. In this way, the first semiconductor chip CHP1 can be aligned with the second semiconductor chip CHP2 so that the outer peripheral edge of the die attach film DAF is offset from the analog circuit ANC in plan view.

[0042] The functions of the semiconductor device DEV of this embodiment and its modified example and the manufacturing method thereof will be described.

[0043] The storage modulus of the die attach film DAF at the molding temperature (e.g., 150 degrees Celsius) is small, at 20 MPa or less, and is therefore smaller than the injection pressure of the molding resin. Therefore, when the molding resin is injected, the die attach film DAF is pressed by the molding resin and shrinks. In a plan view, the outer periphery of the die attach film DAF is located, for example, inside the outer periphery of the first semiconductor chip CHP1.

[0044] However, the first semiconductor chip CHP1 provided with the die attach film DAF is aligned with the second semiconductor chip CHP2 by using at least one variant bonding pad BP2 as an alignment mark for the first semiconductor chip CHP1. Therefore, the first semiconductor chip CHP1 can be aligned with the second semiconductor chip CHP2 so that the outer periphery of the die attach film DAF is offset from the analog circuit ANC in a plan view. For example, the first semiconductor chip CHP1 can be aligned with the second semiconductor chip CHP2 so that the distance between the analog circuit and the outer periphery of the die attach film DAF in a plan view is greater than the contracted length of the die attach film DAF in the step (step S6) of providing the resin molding member RMB.

[0045] Even if the die attach film DAF shrinks in the process of providing the resin mold member RMB (step S6), the outer periphery of the die attach film DAF remains positioned outside the analog circuit ANC in a plan view and is offset from the analog circuit ANC. This reduces the stress applied to the analog circuit ANC from the die attach film DAF, ensuring normal operation of the analog circuit ANC.

[0046] In contrast, when the outer edge of the die attach film DAF overlaps the analog circuit ANC in a plan view, a large stress difference occurs at the interface between the die attach film DAF and the resin molding member RMB, causing the analog circuit ANC to operate abnormally.

[0047] The effects of the semiconductor device DEV of this embodiment and the manufacturing method thereof will be described.

[0048] The semiconductor device DEV of this embodiment includes a first semiconductor chip CHP1, a die attach film DAF provided on the first semiconductor chip CHP1, a second semiconductor chip CHP2, and a resin molding member RMB. The first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF. The second semiconductor chip CHP2 includes an analog circuit ANC, bonding pads BP1, and at least one irregular-shaped bonding pad BP2 having a shape different from that of the bonding pads BP1. The at least one irregular-shaped bonding pad BP2 is an alignment mark for the first semiconductor chip CHP1. In a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the analog circuit ANC is located inside the outer periphery of the die attach film DAF. The resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0049] At least one variant bonding pad BP2 is used as an alignment mark for the first semiconductor chip CHP1, and the first semiconductor chip CHP1 provided with the die attach film DAF is aligned with the second semiconductor chip CHP2. Therefore, in a plan view, the outer edge of the die attach film DAF can be offset from the analog circuit ANC. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a plan view. Therefore, normal operation of the analog circuit ANC can be ensured.

[0050] In the semiconductor device DEV of this embodiment, in plan view, an extension line EXL of the outer periphery of at least one variant bonding pad BP2 is offset from the analog circuit ANC. In plan view, the outer periphery of the first semiconductor chip CHP1 is located on the extension line EXL of the outer periphery of at least one variant bonding pad BP2.

[0051] Therefore, by using at least one variant bonding pad BP2 as an alignment mark for the first semiconductor chip CHP1, the outer edge of the die attach film DAF can be offset from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0052] In the semiconductor device DEV of this embodiment, the first semiconductor chip CHP1 has a first corner CN1 and a second corner CN2 diagonally located to the first corner CN1. At least one variant bonding pad BP2 includes a first variant bonding pad (variant bonding pads BP2a1, BP2a2) and a second variant bonding pad (variant bonding pads BP2b1, BP2b2). The first variant bonding pad is for aligning the first corner CN1. The second variant bonding pad is for aligning the second corner CN2.

[0053] This allows the first semiconductor chip CHP1 to be two-dimensionally aligned with the second semiconductor chip CHP2. In plan view, the outer periphery of the die attach film DAF can be offset from the analog circuit ANC. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in plan view. This ensures normal operation of the analog circuit ANC.

[0054] In the semiconductor device DEV of this embodiment, the outer periphery of the first semiconductor chip CHP1 includes a first outer periphery portion and a second outer periphery portion extending in a direction intersecting the first outer periphery portion. At least one variant bonding pad BP2 includes a first variant bonding pad (variant bonding pads BP2a1, BP2b1) for guiding the first outer periphery portion and a second variant bonding pad (variant bonding pads BP2a2, BP2b2) for guiding the second outer periphery portion.

[0055] This allows the first semiconductor chip CHP1 to be two-dimensionally aligned with the second semiconductor chip CHP2. In plan view, the outer periphery of the die attach film DAF can be offset from the analog circuit ANC. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in plan view. This ensures normal operation of the analog circuit ANC.

[0056] In the semiconductor device DEV of this embodiment, in plan view, an extension line EXL of the outer periphery of at least one variant bonding pad BP2 is located on the outer periphery of the analog circuit ANC. In plan view, the outer periphery of the first semiconductor chip CHP1 is shifted from the extension line EXL of the outer periphery of at least one variant bonding pad BP2.

[0057] Therefore, by using at least one variant bonding pad BP2 as an alignment mark for the first semiconductor chip CHP1, the outer edge of the die attach film DAF can be offset from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0058] In the semiconductor device DEV of this embodiment, the storage modulus of the die attach film DAF at 150 degrees Celsius is 20 MPa or less.

[0059] Therefore, even if the die attach film DAF shrinks when attached to the resin mold member RMB, the outer edge of the die attach film DAF can be offset from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin mold member RMB, where there is a large stress difference, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0060] The manufacturing method of the semiconductor device DEV of this embodiment includes a step of providing a die attach film DAF on a first semiconductor chip CHP1 (step S1) and a step of aligning the first semiconductor chip CHP1 with respect to a second semiconductor chip CHP2 (step S2). The second semiconductor chip CHP2 includes an analog circuit ANC, bonding pads BP1, and at least one variant bonding pad BP2 having a shape different from that of the bonding pads BP1. In the step of aligning the first semiconductor chip CHP1 (step S2), the at least one variant bonding pad BP2 is used as an alignment mark for the first semiconductor chip CHP1. In the step of aligning the first semiconductor chip CHP1 (step S2), the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF. The manufacturing method of the semiconductor device DEV of this embodiment includes a step (step S3) of attaching the first semiconductor chip CHP1 to the second semiconductor chip CHP2 via the die attach film DAF, and a step (step S6) of providing a resin molding member RMB that seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0061] The first semiconductor chip CHP1 provided with the die attach film DAF is aligned with the second semiconductor chip CHP2 using at least one irregular bonding pad BP2 as an alignment mark for the first semiconductor chip CHP1. Therefore, even if the die attach film DAF shrinks in the process of providing the resin molding member RMB (step S6), the outer periphery of the die attach film DAF can be shifted from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. Therefore, normal operation of the analog circuit ANC can be ensured.

[0062] In the manufacturing method of the semiconductor device DEV of the present embodiment, an extension line EXL of the outer periphery of at least one variant bonding pad BP2 is deviated from the analog circuit ANC in plan view. In the step (step S2) of aligning the first semiconductor chip CHP1, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the outer periphery of the first semiconductor chip CHP1 is positioned on the extension line EXL of the outer periphery of at least one variant bonding pad BP2 in plan view.

[0063] Therefore, even if the die attach film DAF shrinks in the process of providing the resin mold member RMB (step S6), the outer periphery of the die attach film DAF can be shifted from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin mold member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0064] In the manufacturing method of the semiconductor device DEV of this embodiment, the first semiconductor chip CHP1 has a first corner CN1 and a second corner CN2 located diagonally to the first corner CN1. The at least one variant bonding pad BP2 includes a first variant bonding pad (variant bonding pads BP2a1, BP2a2) and a second variant bonding pad (variant bonding pads BP2b1, BP2b2). In the step (step S2) of aligning the first semiconductor chip CHP1, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that, in a plan view, the first corner CN1 is positioned on an extension line EXL of the outer periphery of the first variant bonding pad and the second corner CN2 is positioned on an extension line EXL of the outer periphery of the second variant bonding pad.

[0065] This allows the first semiconductor chip CHP1 to be two-dimensionally aligned with the second semiconductor chip CHP2. In plan view, the outer periphery of the die attach film DAF can be offset from the analog circuit ANC. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in plan view. This ensures normal operation of the analog circuit ANC.

[0066] In the manufacturing method of the semiconductor device DEV of this embodiment, the outer periphery of the first semiconductor chip CHP1 includes a first outer periphery portion and a second outer periphery portion extending in a direction intersecting the first outer periphery portion (e.g., a second direction DR2). At least one variant bonding pad BP2 includes a first variant bonding pad (variant bonding pads BP2a1, BP2b1) and a second variant bonding pad (variant bonding pads BP2a2, BP2b2). In the step of aligning the first semiconductor chip CHP1, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that, in a plan view, the first outer periphery portion is positioned on an extension line EXL of the outer periphery of the first variant bonding pad and the second outer periphery portion is positioned on an extension line EXL of the outer periphery of the second variant bonding pad.

[0067] This allows the first semiconductor chip CHP1 to be two-dimensionally aligned with the second semiconductor chip CHP2. In plan view, the outer periphery of the die attach film DAF can be offset from the analog circuit ANC. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in plan view. This ensures normal operation of the analog circuit ANC.

[0068] In the manufacturing method of the semiconductor device DEV of the present embodiment, an extension line EXL of the outer periphery of at least one variant bonding pad BP2 is located on the outer periphery of the analog circuit ANC in plan view. In the step of aligning the first semiconductor chip CHP1 (step S2), the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the outer periphery of the first semiconductor chip CHP1 is deviated from the extension line EXL of the outer periphery of at least one variant bonding pad BP2 in plan view.

[0069] Therefore, even if the die attach film DAF shrinks in the process of providing the resin mold member RMB (step S6), the outer periphery of the die attach film DAF can be shifted from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin mold member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0070] In the manufacturing method of the semiconductor device DEV of this embodiment, the storage modulus of the die attach film DAF at the molding temperature in the process of providing the resin molding member RMB (step S6) is smaller than the injection pressure of the molding resin in the process of providing the resin molding member RMB (step S6).

[0071] Therefore, even if the die attach film DAF shrinks in the process of providing the resin mold member RMB (step S6), the outer periphery of the die attach film DAF can be shifted from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin mold member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0072] (Embodiment 2) 2 and 11, the configuration of the semiconductor device DEV of the second embodiment will be described. The semiconductor device DEV of the present embodiment has a configuration similar to that of the semiconductor device DEV of the first embodiment, but differs from the semiconductor device DEV of the first embodiment mainly in the following points.

[0073] In this embodiment, the second semiconductor chip CHP2 does not include the variant bonding pads BP2 (see FIG. 1). In this embodiment, all of the bonding pads are bonding pads BP1.

[0074] The second semiconductor chip CHP2 further includes at least one passive electronic element PED. The second semiconductor chip CHP2 may include multiple passive electronic elements PED. In this embodiment, the second semiconductor chip CHP2 includes two passive electronic elements PED. The passive electronic element PED is formed on the surface of the chip body CBD on the main surface MSF side. The passive electronic element PED is, for example, a capacitance cell or a diffused resistor.

[0075] The passive electronic element PED is an alignment mark for the first semiconductor chip CHP1. In a plan view, the passive electronic element PED has, for example, an L-shape. In a plan view, the passive electronic element PED may have, but is not limited to, a cross shape. One of the two passive electronic elements PED is used to align a first corner CN1 of the first semiconductor chip. The other of the two passive electronic elements PED is used to align a second corner CN2 of the first semiconductor chip located diagonally from the first corner CN1.

[0076] Referring to Figures 3 and 12, an example of a method for manufacturing a semiconductor device DEV in this embodiment has steps similar to those of an example of a method for manufacturing a semiconductor device DEV in embodiment 1, but differs from the example of a method for manufacturing a semiconductor device DEV in embodiment 1 mainly in step S2.

[0077] In step S2 of the present embodiment, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 while using the passive electronic elements PED as alignment marks for the first semiconductor chip CHP1. Specifically, the second semiconductor chip CHP2 includes a plurality of passive electronic elements PED. In a plan view, a first corner portion CN1 of the first semiconductor chip CHP1 is aligned with corresponding ones of the plurality of passive electronic elements PED, and a second corner portion CN2 of the first semiconductor chip CHP1 is aligned with corresponding ones of the plurality of passive electronic elements PED. For example, the first semiconductor chip CHP1 can be aligned with the second semiconductor chip CHP2 so that the distance between the analog circuit and the outer periphery of the die attach film DAF in a plan view is greater than the contraction length of the die attach film DAF in the step (step S6) of providing the resin molding member RMB.

[0078] In this way, the first semiconductor chip CHP1 can be aligned with the second semiconductor chip CHP2 so that the outer periphery of the die attach film DAF is misaligned from the analog circuit ANC in plan view.

[0079] The semiconductor device DEV and the manufacturing method thereof according to the present embodiment have the following advantages similar to those of the semiconductor device DEV and the manufacturing method thereof according to the first embodiment.

[0080] The semiconductor device DEV of this embodiment includes a first semiconductor chip CHP1, a die attach film DAF provided on the first semiconductor chip CHP1, a second semiconductor chip CHP2, and a resin molding member RMB. The first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF. The second semiconductor chip CHP2 includes an analog circuit ANC and passive electronic elements PED. The passive electronic elements PED are alignment marks for the first semiconductor chip CHP1. In a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the analog circuit ANC is located inside the outer periphery of the die attach film DAF. The resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0081] Using the passive electronic elements PED as alignment marks for the first semiconductor chip CHP1, the first semiconductor chip CHP1, on which the die attach film DAF is provided, is aligned with the second semiconductor chip CHP2. Therefore, even if the die attach film DAF shrinks when the resin molding member RMB is provided, the outer edge of the die attach film DAF can be shifted from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. Therefore, normal operation of the analog circuit ANC can be ensured.

[0082] The manufacturing method of the semiconductor device DEV of this embodiment includes a step (step S1) of providing a die attach film DAF on the first semiconductor chip CHP1 and a step (step S2) of aligning the first semiconductor chip CHP1 with respect to the second semiconductor chip CHP2. The second semiconductor chip CHP2 includes an analog circuit ANC and passive electronic elements PED. In the step (step S2) of aligning the first semiconductor chip CHP1, the passive electronic elements PED are used as alignment marks for the first semiconductor chip CHP1. In the step (step S2) of aligning the first semiconductor chip CHP1, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF. The manufacturing method of the semiconductor device DEV of this embodiment includes a step (step S3) of attaching the first semiconductor chip CHP1 to the second semiconductor chip CHP2 via the die attach film DAF, and a step (step S6) of providing a resin molding member RMB that seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0083] The first semiconductor chip CHP1, on which the die attach film DAF is provided, is aligned with the second semiconductor chip CHP2 using the passive electronic elements PED as alignment marks for the first semiconductor chip CHP1. Therefore, even if the die attach film DAF shrinks in the process of providing the resin molding member RMB (step S6), the outer periphery of the die attach film DAF can be shifted from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. Therefore, normal operation of the analog circuit ANC can be ensured.

[0084] (Embodiment 3) The configuration of the semiconductor device DEV of the third embodiment will be described with reference to Figures 13 and 14. The semiconductor device DEV of the present embodiment has a configuration similar to that of the semiconductor device DEV of the first embodiment, but differs from the semiconductor device DEV of the first embodiment mainly in the following points.

[0085] In this embodiment, the second semiconductor chip CHP2 does not include the variant bonding pads BP2 (see FIG. 11). The semiconductor device DEV further includes a resin frame RSF.

[0086] In plan view, the resin frame RSF surrounds the die attach film DAF and separates the die attach film DAF from the resin molding member RMB. The resin frame RSF fills a gap GP defined by, for example, the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0087] The resin frame RSF includes, for example, a thermosetting resin and a filler dispersed in the thermosetting resin. The thermosetting resin is, for example, an epoxy resin. The filler is, for example, silica particles. The filler content of the resin frame RSF is lower than the filler content of the resin molded member RMB. The filler content of the resin molded member RMB is, for example, 50 weight percent or more and less than 70 weight percent. The storage modulus of the resin frame RSF at 150 degrees Celsius is greater than the storage modulus of the die attach film DAF at 150 degrees Celsius.

[0088] The resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, the die attach film DAF, and the resin frame RSF.

[0089] Referring to Figures 15 to 17, an example of a manufacturing method for the semiconductor device DEV of this embodiment has steps similar to those of the example of a manufacturing method for the semiconductor device DEV of embodiment 1, but differs from the example of a manufacturing method for the semiconductor device DEV of embodiment 1 mainly in the following points.

[0090] 15, a die attach film DAF is provided on the first semiconductor chip CHP1 (step S1). Step S1 in this embodiment is similar to step S1 in the first embodiment (see FIG. 3), but in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the outer periphery of the die attach film DAF is located, for example, inside the outer periphery of the first semiconductor chip CHP1.

[0091] 15 to 17, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 (step S2). Specifically, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF in plan view. In plan view, the outer periphery of the die attach film DAF is misaligned with the analog circuit ANC.

[0092] 15, the first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF (step S3). Step S3 in this embodiment is similar to step S3 in the first embodiment (see FIG. 3), but a gap GP is formed between the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0093] Referring to Fig. 15, a resin frame RSF is formed (step S8). For example, using a dispenser (not shown), a resin containing a filler is supplied around the die attach film DAF. The resin containing the filler is filled, for example, into the gap GP. The resin containing the filler is heated to harden the resin containing the filler. In this way, the resin frame RSF is formed.

[0094] 15, the second semiconductor chip CHP2 is fixed to the wiring substrate WB using a die bonding paste DBP or a die attach film (not shown) (step S4). Step S4 in the present embodiment is similar to step S4 in the first embodiment.

[0095] 15, the conductive wires WIR are bonded to the bonding pads (step S5). Specifically, the conductive wires WIR are bonded to the bonding pads BP1, BP3, and BP4.

[0096] 15, a resin molding member RMB is provided (step S6). Step S6 in the present embodiment is similar to step S6 in the first embodiment, but in the present embodiment, the resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, the die attach film DAF, and the resin frame RSF.

[0097] 15, the wiring substrate WB and the resin molding member RMB are divided to separate the stack of the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the wiring substrate WB (step S7). Step S7 in this embodiment is the same as step S7 in embodiment 1. In this way, the semiconductor device DEV of this embodiment is obtained.

[0098] The operation of the semiconductor device DEV of this embodiment and the manufacturing method thereof will be described.

[0099] The storage elastic modulus of the die attach film DAF at the molding temperature (e.g., 150°C) is smaller than the injection pressure of the molding resin. In contrast, the storage elastic modulus of the resin frame RSF at the molding temperature (e.g., 150°C) is larger than that of the die attach film DAF and is equal to or greater than the injection pressure of the molding resin. Therefore, even if the resin frame RSF is pressed by the molding resin when the molding resin is injected, the resin frame RSF does not shrink and functions as a barrier against the molding resin. The resin frame RSF can prevent the die attach film DAF from shrinking. In a plan view, the outer peripheral edge of the die attach film DAF is still located outside the analog circuit ANC and is offset from the analog circuit ANC. Because the resin frame RSF is between the die attach film DAF and the molding resin, the interface between the die attach film DAF and the resin molding member RMB, where there is a large stress difference, does not overlap with the analog circuit ANC in a plan view. Therefore, normal operation of the analog circuit ANC can be ensured.

[0100] The semiconductor device DEV and the manufacturing method thereof according to the present embodiment have the following advantages similar to those of the semiconductor device DEV and the manufacturing method thereof according to the first embodiment.

[0101] The semiconductor device DEV of this embodiment includes a first semiconductor chip CHP1, a die attach film DAF provided on the first semiconductor chip CHP1, a second semiconductor chip CHP2, a resin frame RSF, and a resin molding member RMB. The first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF. The second semiconductor chip CHP2 includes an analog circuit ANC. The resin frame RSF surrounds the die attach film DAF in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF and separates the die attach film DAF from the resin molding member RMB. The storage elastic modulus of the resin frame RSF at 150 degrees Celsius is greater than the storage elastic modulus of the die attach film DAF at 150 degrees Celsius. In a plan view, the analog circuit ANC is located inside the outer periphery of the die attach film DAF. The resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, the die attach film DAF, and the resin frame RSF.

[0102] The manufacturing method of the semiconductor device DEV of this embodiment includes a step of providing a die attach film DAF on the first semiconductor chip CHP1 (step S1) and a step of aligning the first semiconductor chip CHP1 with respect to the second semiconductor chip CHP2 (step S2). The second semiconductor chip CHP2 includes an analog circuit ANC. In the step of aligning the first semiconductor chip CHP1 (step S2), the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF. The manufacturing method of the semiconductor device DEV of this embodiment includes a step of attaching the first semiconductor chip CHP1 to the second semiconductor chip CHP2 via the die attach film DAF (step S3) and a step of forming a resin frame RSF that surrounds the die attach film DAF in a plan view (step S8). The storage elastic modulus of the resin frame RSF at 150 degrees Celsius is greater than the storage elastic modulus of the die attach film DAF at 150 degrees Celsius. The manufacturing method of the semiconductor device DEV of the present embodiment includes a step (step S6) of providing a resin molding member RMB that seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, the die attach film DAF, and the resin frame RSF.

[0103] The resin frame RSF functions as a barrier against the molding resin injected to form the resin mold member RMB. When forming the resin mold member RMB, the resin frame RSF prevents the die attach film DAF from shrinking. This allows the outer edge of the die attach film DAF to be offset from the analog circuit ANC in a planar view. Because the resin frame RSF is located between the die attach film DAF and the molding resin, the interface between the die attach film DAF and the resin mold member RMB, where there is a large stress difference, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0104] (Fourth embodiment) The configuration of the semiconductor device DEV of the fourth embodiment will be described with reference to Figures 18 and 19. The semiconductor device DEV of the present embodiment has a configuration similar to that of the semiconductor device DEV of the first embodiment, but differs from the semiconductor device DEV of the first embodiment mainly in the following points.

[0105] In this embodiment, the second semiconductor chip CHP2 does not include variant bonding pads BP2 (see FIG. 11). In a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the outer periphery of the die attach film DAF is located outside the outer periphery of the first semiconductor chip CHP1. In a plan view, the analog circuit ANC is located inside the outer periphery of the die attach film DAF and inside the outer periphery of the first semiconductor chip CHP1.

[0106] An example of a method for manufacturing the semiconductor device DEV of the present embodiment will be described with reference to Fig. 3 and Fig. 20 to Fig. 24. The example of the method for manufacturing the semiconductor device DEV of the present embodiment includes the same steps as the example of the method for manufacturing the semiconductor device DEV of the first embodiment, but differs from the example of the method for manufacturing the semiconductor device DEV of the first embodiment mainly in the following points.

[0107] 3, a die attach film DAF is provided on the first semiconductor chip CHP1 (step S1). In the present embodiment, in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the outer periphery of the die attach film DAF is located outside the outer periphery of the first semiconductor chip CHP1. With reference to FIGS. 20 to 22, an example of a method for providing the die attach film DAF on the first semiconductor chip CHP1 will be described.

[0108] 20, a die attach tape DAT is attached to a semiconductor wafer SWF. A plurality of first semiconductor chips CHP1 are formed on a semiconductor wafer SWF such as a silicon wafer.

[0109] 21, the semiconductor wafer SWF is cut into a plurality of first semiconductor chips CHP1. For example, the semiconductor wafer SWF is cut using a first blade BLD1. The die attach tape DAT is not cut by the first blade BLD1.

[0110] 22, the die attach tape DAT is cut to separate the die attach tape DAT into a plurality of die attach films DAF. For example, the die attach tape DAT is cut using a second blade BLD2. The first semiconductor chip CHP1 is not cut by the second blade BLD2. The cutting margin CF2 of the die attach tape DAT is narrower than the cutting margin CF1 of the semiconductor wafer SWF. For example, the width W2 of the second blade BLD2 is narrower than the width W1 of the first blade BLD1. Therefore, in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the outer periphery of the die attach film DAF is located, for example, outside the outer periphery of the first semiconductor chip CHP1.

[0111] 3, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 (step S2). Specifically, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF and inside the first semiconductor chip CHP1 in plan view. In plan view, the outer periphery of the die attach film DAF is misaligned with the analog circuit ANC.

[0112] 3, 23, and 24, the first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF (step S3). Step S3 in this embodiment is similar to step S3 in the first embodiment (see FIG. 3), but in plan view, the outer periphery of the die attach film DAF is located outside the outer periphery of the first semiconductor chip CHP1.

[0113] 3, the second semiconductor chip CHP2 is fixed to the wiring substrate WB using a die bonding paste DBP or a die attach film (not shown) (step S4). The conductive wires WIR are bonded to the bonding pads (step S5). Steps S4 and S5 of the present embodiment are the same as steps S4 and S5 of the third embodiment (see FIG. 15).

[0114] 3, a resin molding member RMB that seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF is provided (step S6). Step S6 in the present embodiment is similar to step S6 in the first embodiment.

[0115] 3, the wiring substrate WB and the resin molding member RMB are divided to separate the stack of the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the wiring substrate WB (step S7). Step S7 in this embodiment is the same as step S7 in embodiment 1. In this way, the semiconductor device DEV of this embodiment is obtained.

[0116] The operation of the semiconductor device DEV of this embodiment and the manufacturing method thereof will be described.

[0117] The storage modulus of the die attach film DAF at the molding temperature (e.g., 150 degrees Celsius) is smaller than the injection pressure of the molding resin. Therefore, when the molding resin is injected, the die attach film DAF is pressed by the molding resin and shrinks. However, in the step of attaching the first semiconductor chip CHP1 to the main surface MSF of the second semiconductor chip CHP2 (step S3), the outer periphery of the die attach film DAF is located outside the outer periphery of the first semiconductor chip CHP1 in a plan view.

[0118] Therefore, even if the die attach film DAF shrinks when the molding resin is injected, the outer peripheral edge of the die attach film DAF remains positioned outside the analog circuit ANC in a plan view and is offset from the analog circuit ANC. The interface between the die attach film DAF and the resin molding member RMB does not overlap the analog circuit ANC in a plan view. This ensures normal operation of the analog circuit ANC.

[0119] In this embodiment, it is sufficient that the outer peripheral edge of the die attach film DAF is located outside the outer peripheral edge of the first semiconductor chip CHP1 in step S3, and that the outer peripheral edge of the die attach film DAF is located outside the analog circuit ANC after step S6, and that the outer peripheral edge of the die attach film DAF is located inside the outer peripheral edge of the first semiconductor chip CHP1 after step S6.

[0120] The semiconductor device DEV and the manufacturing method thereof according to this embodiment have the following effects similar to those of the semiconductor device DEV and the manufacturing method thereof according to the first embodiment.

[0121] The semiconductor device DEV of this embodiment includes a first semiconductor chip CHP1, a die attach film DAF provided on the first semiconductor chip CHP1, a second semiconductor chip CHP2, and a resin molding member RMB. The first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF. The second semiconductor chip CHP2 includes an analog circuit ANC. In a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the outer periphery of the die attach film DAF is located outside the outer periphery of the first semiconductor chip CHP1. In a plan view, the analog circuit ANC is located inside the outer periphery of the die attach film DAF and inside the outer periphery of the first semiconductor chip CHP1. The resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0122] The manufacturing method of the semiconductor device DEV of this embodiment includes a step (step S1) of providing a die attach film DAF on the first semiconductor chip CHP1. In a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the outer periphery of the die attach film DAF is located outside the outer periphery of the first semiconductor chip CHP1. The manufacturing method of the semiconductor device DEV of this embodiment includes a step (step S2) of aligning the first semiconductor chip CHP1 with the second semiconductor chip CHP2. The second semiconductor chip CHP2 includes an analog circuit ANC. In the step (step S2) of aligning the first semiconductor chip CHP1, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF and inside the outer periphery of the first semiconductor chip CHP1 in a plan view. The manufacturing method of the semiconductor device DEV of this embodiment includes a step (step S3) of attaching the first semiconductor chip CHP1 to the second semiconductor chip CHP2 via the die attach film DAF, and a step (step S6) of providing a resin molding member RMB that seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0123] Therefore, even if the die attach film DAF shrinks when the resin mold member RMB is formed, the outer periphery of the die attach film DAF can be offset from the analog circuit ANC in a planar view. The interface between the die attach film DAF and the resin mold member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in a planar view. This ensures normal operation of the analog circuit ANC.

[0124] In the manufacturing method of the semiconductor device DEV of this embodiment, the step of providing a die attach film DAF on the first semiconductor chip CHP1 (step S1) includes a step of attaching a die attach tape DAT to a semiconductor wafer SWF. The step of providing a die attach film DAF on the first semiconductor chip CHP1 (step S1) includes a step of cutting the semiconductor wafer SWF to separate the semiconductor wafer SWF into a plurality of first semiconductor chips CHP1, and a step of cutting the die attach tape DAT to separate the die attach tape DAT into a plurality of die attach films DAF. A cutting margin CF2 of the die attach tape DAT is narrower than a cutting margin CF1 of the semiconductor wafer SWF.

[0125] Therefore, in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the outer periphery of the die attach film DAF can be positioned outside the outer periphery of the first semiconductor chip CHP1. Even if the die attach film DAF shrinks in the step of providing the resin molding member RMB (step S6), the outer periphery of the die attach film DAF can be shifted from the analog circuit ANC in a plan view. The interface between the die attach film DAF and the resin molding member RMB, where there is a large stress difference, does not overlap with the analog circuit ANC in a plan view. This ensures normal operation of the analog circuit ANC.

[0126] (Embodiment 5) 25 and 26, the configuration of the semiconductor device DEV of the fifth embodiment will be described. The semiconductor device DEV of the present embodiment has a similar configuration to the semiconductor device DEV of the first embodiment, but differs from the semiconductor device DEV of the first embodiment mainly in the following points.

[0127] In this embodiment, the second semiconductor chip CHP2 does not include variant bonding pads BP2 (see FIG. 11). The protective layer PRL is provided with protrusions PRT. The protrusions PRT are formed, for example, from the same material as the protective layer PRL. The protective layer PRL having the protrusions PRT may be formed by applying a resin that will become the protective layer PRL twice, or by etching a part of the protective layer PRL.

[0128] In a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the protrusion PRT is arranged inside the outer periphery of the die attach film DAF. In a plan view, the protrusion PRT extends along the outer periphery of the die attach film DAF. In a plan view, the protrusion PRT surrounds the analog circuit ANC. In a plan view, the analog circuit ANC is located inside the protrusion PRT. A portion of the die attach film DAF is engaged with the protrusion PRT.

[0129] An example of a method for manufacturing the semiconductor device DEV of this embodiment will be described with reference to Fig. 3. The example of the method for manufacturing the semiconductor device DEV of this embodiment includes the same steps as the example of the method for manufacturing the semiconductor device DEV of embodiment 1, but differs from the example of the method for manufacturing the semiconductor device DEV of embodiment 1 mainly in the following points.

[0130] 3, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 (step S2). Specifically, the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer periphery of the die attach film DAF and inside the protrusions PRT in a plan view. In a plan view, the outer periphery of the die attach film DAF is misaligned with the analog circuit ANC. In a plan view, the protrusions PRT overlap the die attach film DAF and surround the analog circuit ANC.

[0131] 3, the first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF (step S3). Step S3 in this embodiment is similar to step S3 in the first embodiment (see FIG. 3), but a part of the die attach film DAF engages with the protrusion PRT.

[0132] 27, in a semiconductor device DEV according to a first modification of the present embodiment, a recess RCS is provided in the protective layer PRL instead of the protrusion PRT. The protective layer PRL having the recess RCS may be formed by applying a resin to become the protective layer PRL twice, or may be formed by etching a part of the protective layer PRL. A part of the die attach film DAF engages with the recess RCS.

[0133] 28, in a semiconductor device DEV according to a second modification of the present embodiment, both a protrusion PRT and a recess RCS are provided in the protective layer PRL. The protrusion PRT is disposed inside the recess RCS. The recess RCS may be disposed outside the protrusion PRT. A portion of the die attach film DAF is engaged with at least one of the protrusion PRT or the recess RCS.

[0134] The operation of the semiconductor device DEV of this embodiment and the manufacturing method thereof will be described.

[0135] The storage modulus of the die attach film DAF at the molding temperature (e.g., 150°C) is smaller than the injection pressure of the molding resin. Therefore, when the molding resin is injected, the die attach film DAF is pressed by the molding resin and shrinks. However, the analog circuit ANC is surrounded by at least one of the protrusions PRT or recesses RCS of the protective layer PRL. A portion of the die attach film DAF engages with at least one of the protrusions PRT or recesses RCS of the protective layer PRL.

[0136] Therefore, even if the die attach film DAF shrinks when the molding resin is injected, the die attach film DAF is prevented from shrinking to a position inside at least one of the protrusions PRT or the recesses RCS. In plan view, the outer edge of the die attach film DAF is still positioned outside the analog circuit ANC and is offset from the analog circuit ANC. The interface between the die attach film DAF and the resin molding member RMB, where the stress difference is large, does not overlap with the analog circuit ANC in plan view. This ensures normal operation of the analog circuit ANC.

[0137] The semiconductor device DEV and the manufacturing method thereof according to this embodiment have the following effects similar to those of the semiconductor device DEV and the manufacturing method thereof according to the first embodiment.

[0138] The semiconductor device DEV of this embodiment includes a first semiconductor chip CHP1, a die attach film DAF formed on the first semiconductor chip CHP1, a second semiconductor chip CHP2, and a resin molding member RMB. The first semiconductor chip CHP1 is attached to the second semiconductor chip CHP2 via the die attach film DAF. The second semiconductor chip CHP2 includes an analog circuit ANC and a protective layer PRL covering the analog circuit ANC. At least one of a protrusion PRT or a recess RCS is provided on the protective layer PRL. A portion of the die attach film DAF engages with at least one of the protrusion PRT or the recess RCS. In a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF, the analog circuit ANC is located inside the outer periphery of the die attach film DAF and inside at least one of the protrusion PRT or the recess RCS. The resin molding member RMB seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0139] The manufacturing method of the semiconductor device DEV of this embodiment includes a step of providing a die attach film DAF on the first semiconductor chip CHP1 (step S1) and a step of aligning the first semiconductor chip CHP1 with respect to the second semiconductor chip CHP2 (step S2). The second semiconductor chip CHP2 includes an analog circuit ANC and a protective layer PRL covering the analog circuit ANC. At least one of a protrusion PRT or a recess RCS is provided on the protective layer PRL. In the step of aligning the first semiconductor chip CHP1 (step S2), the first semiconductor chip CHP1 is aligned with the second semiconductor chip CHP2 so that the analog circuit ANC is located inside the outer edge of the die attach film DAF and inside at least one of the protrusion PRT or the recess RCS in a plan view from the stacking direction of the first semiconductor chip CHP1 and the die attach film DAF. The manufacturing method of the semiconductor device DEV of this embodiment also includes a step of attaching the first semiconductor chip CHP1 to the second semiconductor chip CHP2 via the die attach film DAF (step S3). A portion of the die attach film DAF engages with at least one of the protrusions PRT or the recesses RCS. The method for manufacturing the semiconductor device DEV of the present embodiment includes a step (step S6) of providing a resin molding member RMB that seals the first semiconductor chip CHP1, the second semiconductor chip CHP2, and the die attach film DAF.

[0140] The die attach film DAF shrinks when the resin mold member RMB is formed. However, the analog circuit ANC is surrounded by at least one of the protrusions PRT or recesses RCS of the protective layer PRL. The die attach film DAF engages with at least one of the protrusions PRT or recesses RCS. This prevents the die attach film DAF from shrinking further inward than at least one of the recesses RCS or protrusions PRT. In a plan view, the outer edge of the die attach film DAF remains positioned outside the analog circuit ANC and offset from the analog circuit ANC. The interface between the die attach film DAF and the resin mold member RMB, where the stress difference is large, does not overlap the analog circuit ANC in a plan view. This ensures normal operation of the analog circuit ANC.

[0141] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0142] ANC analog circuit, BLD1 first blade, BLD2 second blade, BP1, BP3, BP4 bonding pads, BP2, BP2a1, BP2a2, BP2b1, BP2b2 irregular bonding pads, CBD chip body, CF1, CF2 cutting edge, CHP1 first semiconductor chip, CHP2 second semiconductor chip, CN1 first corner, CN2 second corner, DAF die attach film, DAT die attach tape, DEV semiconductor device, DR1 first direction, DR2 second direction, EXL extension line, GP gap, MLD mold, MSF main surface, PED passive electronic element, PRL protective layer, PRT protrusion, RCS recess, RSF resin frame, SWF semiconductor wafer, W1, W2 width, WB wiring board, WIR conductive wire.

Claims

1. a first semiconductor chip; a die attach film provided on the first semiconductor chip; a second semiconductor chip; a resin molding member that seals the first semiconductor chip, the second semiconductor chip, and the die attach film; the first semiconductor chip is attached to the second semiconductor chip via the die attach film; the second semiconductor chip includes an analog circuit, a bonding pad, and at least one variant bonding pad having a shape different from that of the bonding pad; the at least one variant bonding pad is an alignment mark for the first semiconductor chip; In a plan view from the stacking direction of the first semiconductor chip and the die attach film, the analog circuit is located inside the outer periphery of the die attach film.

2. an extension line of an outer periphery of the at least one variant bonding pad is offset from the analog circuit in the plan view; The semiconductor device according to claim 1 , wherein, in the plan view, an outer periphery of the first semiconductor chip is located on the extension line.

3. the first semiconductor chip has a first corner portion and a second corner portion diagonally opposite the first corner portion, 3. The semiconductor device according to claim 2, wherein the at least one variant bonding pad includes a first variant bonding pad for aligning the first corner portion and a second variant bonding pad for aligning the second corner portion.

4. the outer periphery of the first semiconductor chip includes a first outer periphery portion and a second outer periphery portion extending in a direction intersecting the first outer periphery portion; 3. The semiconductor device according to claim 2, wherein the at least one variant bonding pad includes a first variant bonding pad for guiding the first outer peripheral portion, and a second variant bonding pad for guiding the second outer peripheral portion.

5. an extension line of an outer periphery of the at least one variant bonding pad is located on an outer periphery of the analog circuit in the plan view; The semiconductor device according to claim 1 , wherein an outer periphery of the first semiconductor chip is offset from the extension line in the plan view.

6. 2. The semiconductor device according to claim 1, wherein the die attach film has a storage modulus of 20 MPa or less at 150 degrees Celsius.

7. providing a die attach film on the first semiconductor chip; aligning the first semiconductor chip with respect to a second semiconductor chip; attaching the first semiconductor chip to the second semiconductor chip via the die attach film; providing a resin molding member that seals the first semiconductor chip, the second semiconductor chip, and the die attach film; the second semiconductor chip includes an analog circuit, a bonding pad, and at least one variant bonding pad having a shape different from that of the bonding pad; A method for manufacturing a semiconductor device, wherein in the step of aligning the first semiconductor chip, the first semiconductor chip is aligned with the second semiconductor chip while using the at least one irregular bonding pad as an alignment mark for the first semiconductor chip so that the analog circuit is positioned inside the outer edge of the die attach film when viewed in a planar view from the stacking direction of the first semiconductor chip and the die attach film.

8. an extension line of an outer periphery of the at least one variant bonding pad is offset from the analog circuit in the plan view; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of aligning the first semiconductor chip, the first semiconductor chip is aligned with the second semiconductor chip so that the outer peripheral edge of the first semiconductor chip is positioned on the extension line in the planar view.

9. the first semiconductor chip has a first corner portion and a second corner portion diagonally opposite the first corner portion, the at least one heteromorphic bonding pad includes a first heteromorphic bonding pad and a second heteromorphic bonding pad; 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the step of aligning the first semiconductor chip, the first semiconductor chip is aligned with the second semiconductor chip so that, in the planar view, the first corner portion is located on an extension of the outer periphery of the first irregular bonding pad, and the second corner portion is located on an extension of the outer periphery of the second irregular bonding pad.

10. the outer periphery of the first semiconductor chip includes a first outer periphery portion and a second outer periphery portion extending in a direction intersecting the first outer periphery portion; the at least one heteromorphic bonding pad includes a first heteromorphic bonding pad and a second heteromorphic bonding pad; 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the step of aligning the first semiconductor chip, the first semiconductor chip is aligned with the second semiconductor chip so that, in the planar view, the first outer peripheral edge portion is located on an extension of the outer peripheral edge of the first irregular bonding pad, and the second outer peripheral edge portion is located on an extension of the outer peripheral edge of the second irregular bonding pad.

11. an extension line of an outer periphery of the at least one variant bonding pad is located on an outer periphery of the analog circuit in the plan view; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of aligning the first semiconductor chip, the first semiconductor chip is aligned with the second semiconductor chip so that the outer peripheral edge of the first semiconductor chip is offset from the extension line in the planar view.

12. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a storage modulus of the die attach film at a molding temperature in the step of providing the resin molding member is smaller than an injection pressure of the molding resin in the step of providing the resin molding member.

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