Semiconductor device and transfer method for its memory request

Abstract

To provide a semiconductor device and a transfer method for its memory request.SOLUTION: A semiconductor device includes: a first processor that generates a first memory physical address and a first memory request; a second processor that generates a second memory physical address and a second memory request; a first system-on-chip that is physically connected to the first processor and converts the first memory physical address into a first device address; a second system-on-chip that is physically connected to the second processor and the first system-on-chip and converts the second memory physical address into a second device address; and first and second memories that are physically connected to the first and second systems-on-chip respectively, wherein the first and second systems-on-chip transfer the first and second memory requests to one of a plurality of memories including the first and second memories respectively based on the first and second device addresses.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for transferring memory requests thereto, and more particularly to a semiconductor device using a chiplet structure and a method for transferring memory requests thereto. [Background technology]

[0002] For the past few decades, the memory wall has been one of the biggest performance barriers for computer system engineers. With Moore's Law nearing its end, technology is not expected to be able to solve this memory wall problem in the near future. Emerging super applications, including artificial intelligence, machine learning, and genome analysis, require enormous memory capacity. Therefore, the recent trend of these new applications is placing an extremely heavy load on current computer systems.

[0003] The CXL (Compute eXpress Link) interface memory solution is expected to be a solution to this memory wall problem. In a NUMA (Non-Uniform Memory Access) environment, the host processor treats the CXL interface memory as slow memory, and the host treats the DDR memory as fast memory.

[0004] One important application of CXL interface memory is memory pooling, or pooled memory, in which multiple processors can access and share multiple CXL interface memory modules. The current method for building pooled memory is to place a CXL switch between the processors and the CXL memory modules, as shown in Figure 1. However, this method introduces three problems to computer systems: (1) additional latency, (2) additional power consumption, and (3) additional cost. Of these three problems, the additional latency introduced by the CXL switch is the most important concern for system designers.

[0005] This paper proposes a mechanism for building pooled memory without using a switch between the processor and the memory module. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Korean Patent Publication No. 10-2023-0038082 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device that uses a chiplet structure to efficiently transfer memory requests.

[0008] Another object of the present invention is to provide a memory request transfer method for a semiconductor device that efficiently transfers memory requests using a chiplet structure.

[0009] The objects of the present invention are not limited to the objects mentioned above, and other unmentioned objects and advantages of the present invention will be understood from the following description and will become more clearly understood by the embodiments of the present invention. Furthermore, it will be easily understood that the objects and advantages of the present invention can be realized by the means described in the claims and combinations thereof. [Means for solving the problem]

[0010] In order to solve the above problem, a semiconductor device according to some embodiments of the present invention includes a first processor that generates a first memory physical address and a first memory request, a second processor that generates a second memory physical address and a second memory request, a first system-on-chip physically connected to the first processor and that converts the first memory physical address into a first device address, a second system-on-chip physically connected to the second processor and the first system-on-chip and that converts the second memory physical address into a second device address, and first and second memories physically connected to the first and second system-on-chips, respectively, and the first and second system-on-chips transfer the first and second memory requests to one of a plurality of memories including the first and second memories, based on the first and second device addresses.

[0011] The first system-on-chip may also include a first MMU (Memory Management Unit) that converts the first memory physical address into the first device address, and a router that determines whether the first device address corresponds to the first memory and transfers the first memory request to the first memory or the second system-on-chip.

[0012] The first and second systems-on-chips may also control the memories according to a CXL (Compute Express Link) protocol.

[0013] Also, the first memory may have a first range of device addresses, and the second memory may have a second range of device addresses larger than the first range, and the router may compare the first device addresses with the first range and forward the first memory request.

[0014] Additionally, the first range may be defined as a range from a start address to an end address, and the router may forward the first memory request to the second system-on-chip if the first device address is greater than the end address.

[0015] The system may further include a third processor that generates a third memory physical address and a third memory request, and a third system-on-chip that is physically connected to the third processor and the first and second system-on-chips and that converts the third memory physical address into a third device address.

[0016] Also, the router may define contour numbers in order of proximity to the current system-on-chip and transfer the first memory request through an optimal path.

[0017] The first and second systems-on-chip may be connected by a die-to-die interface or a chip-to-chip interface.

[0018] In order to solve the other problems, a memory request transfer method for a semiconductor device according to some embodiments of the present invention includes: a first processor receives a first memory request and a first physical address to which the first memory request is to be transferred; a first system-on-chip physically connected to the first processor converts the first physical address into a first device address; the first system-on-chip compares the first device address with a device address of a first memory connected to the first system-on-chip; and if the first device address corresponds to the device address of the first memory, the first system-on-chip transfers the first memory request to the first memory; may include: if the first device address does not correspond to a device address of the first memory, transferring the first memory request to a second system-on-chip connected to the first system-on-chip; the second system-on-chip comparing the first device address with a device address of a second memory connected to the second system-on-chip; if the second system-on-chip corresponds to the device address of the second memory, transferring the first memory request to the second memory; and if the second system-on-chip does not correspond to the device address of the second memory, transferring the first memory request to a third system-on-chip connected to the second system-on-chip.

[0019] Furthermore, the device address of the first memory may be defined as a first range, and comparing the first device address with the device address of the first memory may include comparing the first device address with a minimum value of the first range and comparing the first device address with a maximum value of the first range.

[0020] Also, the path between the first system-on-chip and the third system-on-chip may be an optimal path. [Effects of the Invention]

[0021] The semiconductor device and memory request transfer method of the present invention can minimize the delay time between the processor and the memory by using a chiplet structure.

[0022] Furthermore, the chiplet structure allows for flexible expansion and combination of processors and memories, thereby increasing the efficiency of the entire device.

[0023] In addition to the above, specific effects of the present invention will be described in detail below in conjunction with the explanation of specific matters for carrying out the invention. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a conceptual diagram showing a conventional semiconductor element. [Figure 2] 1 is a block diagram illustrating a semiconductor device according to some embodiments of the present invention. [Figure 3] FIG. 3 is a block diagram for explaining the host system of FIG. 2 in more detail. [Figure 4] FIG. 3 is a block diagram for explaining the shared memory of FIG. 2 in detail. [Figure 5] 1 is a conceptual diagram illustrating a coupling structure of a processor, a system-on-chip, and a shared memory of a semiconductor device according to some embodiments of the present invention. [Figure 6] FIG. 6 is a conceptual diagram for explaining in more detail the structure of the system-on-chip of FIG. 5. [Figure 7] FIG. 1 is a conceptual diagram illustrating a process in which multiple systems-on-chips transfer memory requests to each other. [Figure 8] FIG. 8 is a diagram for explaining in detail the structure of the system-on-chip of FIG. 7. [Figure 9] 1 is a flowchart illustrating a memory request forwarding method for a semiconductor device according to some embodiments of the present invention. [Figure 10] 10 is a flowchart illustrating in detail a step of determining whether a first device address of FIG. 9 falls within a first range. [Figure 11] 1 is a diagram illustrating a first system-on-chip of a semiconductor device according to some embodiments of the present invention. [Figure 12] 1A and 1B are diagrams illustrating a memory request transfer method for a semiconductor device according to some embodiments of the present invention. [Figure 13] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 14] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 15] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 16] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 17] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 18] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 19] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 20] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 21] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. [Figure 22] 12 is an intermediate view for explaining a method in which the semiconductor device of FIG. 11 transfers a memory request. DETAILED DESCRIPTION OF THE INVENTION

[0025] The terms and phrases used in this specification and claims should not be interpreted as being limited to their general or dictionary meanings. They should be interpreted based on the meanings and concepts that are consistent with the technical idea of ​​the present invention, based on the principle that the inventor can define the concepts of the terms and phrases in order to best describe his or her invention. Furthermore, the embodiments described in this specification and the configurations shown in the drawings are merely examples in which the present invention is realized, and do not represent the entire technical idea of ​​the present invention. It should be understood that there may be various equivalents, modifications, and applications that can replace them at the time of filing this application.

[0026] Terms such as "first," "second," "A," and "B" used in this specification and claims may be used to describe various components, but these components should not be limited by these terms. These terms are used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the present invention. The term "and / or" means the inclusion of a combination of multiple associated listed items or any of multiple associated listed items.

[0027] The terms used in this specification and claims are merely used to describe specific embodiments and are not intended to limit the present invention. Singular expressions also include plural expressions unless the context clearly indicates otherwise. In this application, terms such as "comprises" or "has" should be understood as not precluding the presence or additional possibility of features, numerical values, steps, operations, components, parts, or combinations thereof described herein.

[0028] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0029] Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0030] Furthermore, the configurations, processes, steps, methods, etc. included in the embodiments of the present invention may be shared to the extent that they are not technically inconsistent with each other.

[0031] This specification provides a mechanism for building pooled memory without using a switch between the processor and the memory module.

[0032] This specification describes a system-on-chip (SoC) device consisting of multiple SoC devices and memory modules. Each SoC has a directly connected memory module. Each SoC may be connected to other SoCs via a die-to-die interface or a chip-to-chip interface.

[0033] The host processor sends a memory request to the system-on-chip, which extracts destination information from the memory request and determines the target memory module and the control system of the system-on-chip based on the destination information.

[0034] Each system-on-chip provides a method for forwarding memory requests to other systems-on-chips via a die-to-die interface or a chip-to-chip interface if the system-on-chip is not the target of the memory request.

[0035] The objects of the present invention are not limited to the above objects, and other objects and advantages not described will be understood from the following description and will be more clearly understood by the embodiments of the present invention. Furthermore, it is clear that the objects and advantages of the present invention can be realized by the devices and combinations thereof described in the claims.

[0036] The system-on-chip device of the present invention can reduce the delay time between the processor and the memory device by using a chiplet structure.

[0037] The chiplet architecture also allows for flexible expansion and combination of processors and memory devices, improving the efficiency of all devices.

[0038] Semiconductor devices according to some embodiments of the present invention will be described below with reference to FIGS.

[0039] FIG. 2 is a block diagram illustrating a semiconductor device according to some embodiments of the present invention.

[0040] Referring to FIG. 2 , a semiconductor device 1 according to some embodiments of the present invention may include a host system 10, a host memory 20, an accelerator 30, a shared memory 40, an accelerator memory 50, a first interface 60, a first CXL interface 71, a second CXL interface 72, a second interface 80, and a third interface 90.

[0041] The semiconductor device 1 may be a computer or electronic system component integrated into a single integrated circuit, that is, a device having multiple functions mounted on a single chip.

[0042] The host system 10 may be a control device that controls the system of the semiconductor device 1 and executes program operations. As a general-purpose computing device, the host system 10 may be relatively inefficient at executing parallel and simple operations often used in deep learning and graphics processing. Therefore, the separate accelerator 30 can centrally execute deep learning inference, training tasks, and graphics processing operations, thereby achieving high efficiency for the semiconductor device 1 as a whole.

[0043] The host system 10 may exchange data and signals with the host memory 20 via the first interface 60. The host system 10 may also exchange data and signals with the shared memory 40 via the first CXL interface 71. The host system 10 may communicate data and signals to the accelerator 30 via the third interface 90.

[0044] The host system 10 may be, for example, a CPU (Central Processing Unit) of the semiconductor device 1. The host system 10 may instruct the accelerator 30 to perform a specific processing task and receive a report of the processing result.

[0045] The host memory 20 may be dedicated memory for the host system 10. That is, the host memory 20 may communicate with the host system 10 and store data for the host system 10.

[0046] Host memory 20 may be memory that continuously maintains stored information even in the absence of power. The host memory 20 may be, for example, a Read-Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Alterable ROM (EAROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM) (e.g., NAND Flash memory, NOR Flash memory), an Ultra-Violet Erasable Programmable Read-Only Memory (UVEPROM), a Ferroelectric Random Access Memory (FeRAM), a Magnetoresistive Random Access Memory (MRAM), a Phase-change Random Access Memory (PRAM), a silicon-oxide-nitride-oxide-silicon (SONOS), a Resistive Random Access Memory (RRAM), a Nanotube Random Access Memory (NRAM), a magnetic computer storage device (e.g., a hard disk, a diskette drive, a magnetic tape), an optical disk drive, and a 3D XPoint memory (3D XPoint memory). However, the present embodiment is not limited thereto.

[0047] The accelerator 30 may be a device that performs complex graphics processing or performs calculations using an artificial neural network. The accelerator 30 may be, for example, a graphic processing unit (GPU) that performs graphics processing or a neural processing unit (NPU) that performs deep learning calculation tasks. However, the present embodiment is not limited thereto.

[0048] Alternatively, the accelerator 30 may be, for example, either a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), although the present embodiment is not limited thereto.

[0049] Accelerator 30 may exchange data and signals with accelerator memory 50 via second interface 80. Accelerator 30 may also exchange data and signals with shared memory 40 via second CXL interface 72. Accelerator 30 may communicate data and signals with host system 10 via third interface 90.

[0050] The shared memory 40 may be memory shared by the host system 10 and the accelerator 30. That is, the shared memory 40 may store and load data for the host system 10. At the same time, the shared memory 40 may store and load data for the accelerator 30. That is, the shared memory 40 may operate as both the memory for the host system 10 and the memory for the accelerator 30.

[0051] The shared memory 40 may exchange data and signals with the host system 10 via a first CXL interface 71. The shared memory 40 may also exchange data and signals with the accelerator 30 via a second CXL interface 72. In this case, the shared memory 40 may be a CXL (Compute Express Link) memory. CXL memory is a next-generation interface used in high-performance computing systems, and its large bandwidth and compatibility with CPUs, GPUs, and NPUs can maximize overall memory efficiency. In particular, CXL memory has high performance and low power consumption, which can reduce system operating costs. In other words, the semiconductor device 1 can reduce system operating costs and ensure high memory efficiency via the shared memory 40.

[0052] The shared memory 40 may be a volatile memory, unlike the host memory 20. Unlike non-volatile memory, the volatile memory may be memory that continuously requires power to maintain stored information. The volatile memory may include, for example, at least one of a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), and a double data rate SDRAM (DDR SDRAM). However, the present embodiment is not limited thereto.

[0053] The accelerator memory 50 may be dedicated memory for the accelerator 30. That is, the accelerator memory 50 may communicate with the accelerator 30 and store data for the accelerator 30.

[0054] Accelerator memory 50 may be a non-volatile memory that continuously maintains stored information even when power is not supplied. The accelerator memory 50 may be, for example, a ROM (Read-Only Memory), a PROM (Programmable Read-Only Memory), an EAROM (Erasable Alterable ROM), an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable Programmable Read-Only Memory) (e.g., NAND Flash memory, NOR Flash memory), a UVEPROM (Ultra-Violet Erasable Programmable Read-Only Memory), a FeRAM (Ferroelectric Random Access Memory), a MRAM (Magnetoresistive Random Access Memory), a PRAM (Phase-change Random Access Memory), a SONOS (silicon-oxide-nitride-oxide-silicon), a RRAM (Resistive Random Access Memory), a NRAM (Nanotube Random Access Memory), a magnetic computer storage device (e.g., a hard disk, a diskette drive, a magnetic tape), an optical disk drive, and a 3D crosspoint memory (3D XPoint memory), but the present embodiment is not limited thereto.

[0055] The semiconductor device 1 may include dedicated non-volatile memories for the host system 10 and the accelerator 30, respectively, namely, a host memory 20 and an accelerator memory 50. In addition, although not shown in the drawings, the semiconductor device 1 may also include dedicated volatile memories for the host system 10 and the accelerator 30, respectively. However, the present embodiment is not limited thereto.

[0056] The first interface 60 may transmit data and signals between the host system 10 and the host memory 20. The second interface 80 may transmit data and signals between the accelerator 30 and the accelerator memory 50. The third interface 90 may transmit data and signals between the host system 10 and the accelerator 30.

[0057] The first interface 60 and the second interface 80 may each include at least one of PATA (Parallel Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), SATA (Serial Advanced Technology Attachment), and PCIe (PCI Express), for example, although the present embodiment is not limited thereto.

[0058] The first CXL interface 71 can transmit data and signals between the host system 10 and the shared memory 40. The second CXL interface 72 can transmit data and signals between the accelerator 30 and the shared memory 40. The first CXL interface 71 and the second CXL interface 72 can be, for example, CXL TM 3.0, etc. The first CXL interface 71 and the second CXL interface 72 can provide a switch function so that each device, such as the host system 10 and the accelerator 30, can share and use the shared memory 40.

[0059] In this embodiment, at least one interface from among SDR (Single Data Rate), DDR (Double Data Rate), QDR (Quad Data Rate), and XDR (eXtreme Data Rate, Octal Data Rate) can be used in place of the first CXL interface 71 and the second CXL interface 72.

[0060] FIG. 3 is a block diagram for explaining the host system of FIG. 1 in more detail.

[0061] Referring to FIG. 3, the host system 10 may include at least one processor 100 and at least one system-on-chip 200 .

[0062] The at least one processor 100 may include n processors, namely, a first processor 100_1, a second processor 100_2, and an n-th processor 100_n, where n may be an integer equal to or greater than 1.

[0063] The at least one system-on-chip 200 may include n systems-on-chips, i.e., a first system-on-chip 200_1, a second system-on-chip 200_2, and an n-th system-on-chip 200_n. That is, the number of systems-on-chips 200 may be n, which is the same as the number of processors 100. However, the present embodiment is not limited to this.

[0064] The processors 100 may be connected to the system-on-chips 200 in a one-to-one relationship. That is, one processor 100 may be connected to one system-on-chip 200. For example, the first processor 100_1 may be connected to the first system-on-chip 200_1, and the second processor 100_2 may be connected to the second system-on-chip 200_2. Similarly, the nth processor 100_n may be connected to the nth system-on-chip 200_n. However, the present embodiment is not limited to this.

[0065] FIG. 4 is a block diagram for explaining the shared memory of FIG. 2 in detail.

[0066] 4, the shared memory 40 may include at least one memory. Specifically, the shared memory 40 may include a first memory 40_1, a second memory 40_2, and an m-th memory 40_m. In this case, m may be an integer equal to or greater than 1. Furthermore, m may be greater than n, but this embodiment is not limited thereto.

[0067] The first memory 40_1 to the m-th memory 40_m may be defined as, for example, memory banks of the shared memory 40. Alternatively, they may be virtual unit memories obtained by dividing the internal area of ​​the shared memory 40 equally or unevenly.

[0068] FIG. 5 is a conceptual diagram illustrating a coupling structure of a processor, a system-on-chip, and a shared memory in a semiconductor device according to some embodiments of the present invention.

[0069] 5, the first to fourth processors 100_1 to 100_4 may be physically connected to the first to fourth system-on-chips 200_1 to 200_4, respectively. The first to fourth processors 100_1 to 100_4 may be physically connected to the first to fourth system-on-chips 200_1 to 200_4. That is, the first to fourth system-on-chips 200_1 to 200_4 may internally connect modules (processors, memories, etc.) having different functions and may also connect different system-on-chips to each other, thereby realizing a diverse and highly scalable connection structure.

[0070] The first to fourth system-on-chips 200_1 to 200_4 can be connected to each other by D2D (die to die), that is, the first to fourth system-on-chips 200_1 to 200_4 can exchange data with each other at high speed via ports arranged on each system-on-chip.

[0071] The shared memory 40 may also be physically connected to the first to fourth system-on-chips 200_1 to 200_4. The shared memory 40 may be connected to ports of the first to fourth system-on-chips 200_1 to 200_4, and the shared memory 40, the first to fourth system-on-chips 200_1 to 200_4, and the first to fourth processors 100_1 to 100_4 may be connected to one another via the first to fourth system-on-chips 200_1 to 200_4, respectively. However, the present embodiment is not limited to this.

[0072] Although the drawings show four processors and four system-on-chips, this is merely an example and the present embodiment is not limited thereto, i.e., the number of processors and system-on-chips can be changed arbitrarily in the present embodiment.

[0073] FIG. 6 is a conceptual diagram for explaining the structure of the system-on-chip of FIG. 5 in more detail.

[0074] 6, a first system-on-chip 200_1, a first processor 100_1, and a first memory 40_1 are shown. Descriptions of other system-on-chips, other processors, and other memories are omitted because they have the same or similar structures as the first system-on-chip 200_1, the first processor 100_1, and the first memory 40_1.

[0075] The first system-on-chip 200_1 may include a CXL controller CTRL_CXL, a first port Port1, a second port Port2, and a third port Port3.

[0076] The CXL controller CTRL_CXL is connected to the first processor 100_1 and may be responsible for forwarding memory requests of the first processor 100_1 to the shared memory including the first memory 40_1. The operation of the CXL controller CTRL_CXL will be described in detail below.

[0077] The first port Port1, the second port Port2, and the third port Port3 may be physical ports for exchanging data with the outside of the first system-on-chip 200_1. That is, the first system-on-chip 200_1 may exchange data and signals with other external devices via the first port Port1, the second port Port2, and the third port Port3. In this case, the other external devices may be other system-on-chips or other devices such as processors and memories. Furthermore, each port may be a part that connects system-on-chips to each other via D2D or that connects a system-on-chip to a different device via D2D.

[0078] In the drawings, the first system-on-chip 200_1 has three ports. However, the present embodiment is not limited to this. That is, the first system-on-chip 200_1 may have two or fewer ports, or four or more ports.

[0079] FIG. 7 is a conceptual diagram for explaining the process by which a plurality of systems-on-chips transfer memory requests to each other, and FIG. 8 is a diagram for explaining in detail the structure of the system-on-chip of FIG.

[0080] 3, 4, and 7, the first processor 100_1 may generate a first memory request and transfer it to the first system-on-chip 200_1 along with a first physical address PA_1. Similarly, the second processor 100_2 may generate a second memory request and transfer it to the second system-on-chip 200_2 along with a second physical address PA_2, and the third processor 100_3 may generate a third memory request and transfer it to the third system-on-chip 200_3 along with a third physical address PA_3. The nth processor 100_n may generate an nth memory request and transfer it to the nth system-on-chip 200_n along with an nth physical address PA_n.

[0081] In this case, the first through n-th memory requests may be requests for storing or loading data generated by the first through n-th processors 100_1 through 100_n, respectively, and the first through n-th physical addresses PA_1 through PA_n may be physical addresses of areas where the first through n-th memory requests are to be executed.

[0082] The first through n-th system-on-chips 200_n may include first through n-th CXL controllers CTRL_CXL1 through CTRL_CXLn, respectively. The first through n-th CXL controllers CTRL_CXL1 through CTRL_CXLn may receive first through n-th physical addresses PA_1 through PA_n from the first through n-th processors 100_1 through 100_n, respectively.

[0083] The first through n-th CXL controllers CTRL_CXL1 through CTRL_CXLn may convert the first through n-th physical addresses PA_1 through PA_n into the first through n-th device addresses DA_1 through DA_n, respectively. At this time, the first through n-th device addresses DA_1 through DA_n may be addresses that easily identify the first memory 40_1 through the m-th memory 40_m of the shared memory 40. That is, the first through n-th device addresses DA_1 through DA_n may be addresses in a format defined for identifying the first memory 40_1 through the m-th memory 40_m.

[0084] The first CXL controller CTRL_CXL1 of the first system-on-chip 200_1 may transfer the first memory request to any one of the first through n-th memories 40_1 through 40_n based on the first device address DA_1. While the number of processors, system-on-chips, and memories is shown as n in FIG. 6, this embodiment is not limited thereto. In particular, the number of memories may be m, which is different from n.

[0085] Similarly, the second through n-th CXL controllers CTRL_CXL2 through CTRL_CXLn of the second through n-th system-on-chips 200_2 through 200_n can transfer the second through n-th memory requests to any one of the second through n-th memories 40_2 through 40_n based on the second through n-th device addresses DA_2 through DA_n, respectively.

[0086] 7 and 8, the first CXL controller CTRL_CXL1 may include a first MMU MMU1 and a first router Rt1. The second CXL controller CTRL_CXL2 to the n-th CXL controller CTRL_CXLn have the same structure as the first CXL controller CTRL_CXL1, and therefore, the description thereof will be omitted.

[0087] The first MMU MMU1 may receive a first physical address PA_1 from the first processor 100_1 and convert it into a first device address DA_1. The first MMU MMU1 may convert the first physical address PA_1 into the first device address DA_1 in a preset manner.

[0088] The first router Rt1 may determine whether the first device address DA_1 corresponds to the first memory 40_1. If the first device address DA_1 corresponds to the first memory 40_1, the first router Rt1 may transfer the first memory request to the first memory 40_1.

[0089] On the other hand, if the first device address DA_1 does not correspond to the first memory 40_1, the first router Rt1 may transfer the first memory request to another system-on-chip other than the first system-on-chip 200_1. In this case, the first router Rt1 may transfer the first memory request using the first port 1pt1 or the second port 2pt2.

[0090] The first port 1pt1 and the second port 2pt2 may be ports connected to the outside in the left and right directions of the first system-on-chip 200_1. However, since there is no system-on-chip connected to the left side of the first system-on-chip 200_1 in Fig. 7, the first port 1pt1 is not used.

[0091] Specifically, the first router Rt1 determines whether the first device address DA_1 is greater than the maximum value End_1 of the device address of the first memory 40_1. If the first device address DA_1 is greater than the minimum value Start_1 of the device address of the first memory 40_1 and less than the maximum value End_1, the first router Rt1 can transfer the first memory request to the first memory 40_1.

[0092] If the first device address DA_1 is greater than the maximum value End_1 of the device address of the first memory 40_1, the first router Rt1 may forward the first memory request to the router of the second system-on-chip 200_2 via the second port 2pt2. Similarly, if the first device address DA_1 is greater than the minimum value Start_2 of the device address of the second memory 40_2 and less than the maximum value End_2, the router of the second system-on-chip 200_2 may forward the first memory request to the second memory 40_2.

[0093] If the first device address DA_1 is larger than the maximum value End_2 of the device address of the second memory 40_2, the first memory request may be transferred to the second memory 40_2. If the first device address DA_1 is smaller than the minimum value Start_2 of the device address of the second memory 40_2, the first memory request may be transferred to the first memory 40_1. However, this case is an erroneous judgment by the first router Rt1, and therefore may be executed exceptionally.

[0094] As in the above-described method, the routers of the first through n-th system-on-chips 200_1 through 200_n may forward the first memory request so as to correspond to the device address of the corresponding memory. This can be similarly applied to the second through n-th memory requests.

[0095] In FIG. 7, the connection structure of each system-on-chip is in a ring shape, but this is only an example, and the connection structure may be in a mesh shape or other shape instead of the ring shape.

[0096] The semiconductor device 1 according to some embodiments of the present invention can achieve the division and sharing function of the shared memory 40 by using a chiplet structure instead of the conventional CXL switch structure.

[0097] A CXL switch is an interface structure that allows each processor to use different CXL memories. For example, n processors and m shared memories can be freely connected to each other through a CXL switch.

[0098] However, conventional CXL switch architectures require processors to access shared memory via CXL switch modules, which can result in latencies of approximately 450 to 600 ns. Such latencies exceeding 250 to 300 ns can be a significant weakness in current computing devices and can cause degradation of overall device performance.

[0099] In contrast, this embodiment may result in a latency of approximately 150 to 240 ns due to the chiplet architecture (system on chip). This latency is only about 40 ns higher than the latency when a single processor accesses a single CXL memory. Therefore, this embodiment may result in a latency reduction of 300 to 450 ns compared to the conventional CXL switch architecture.

[0100] Hereinafter, memory request transfer methods for a semiconductor device according to some embodiments of the present invention will be described with reference to Figures 9 and 10. Portions that overlap with the above-described embodiments will be simplified or omitted.

[0101] FIG. 9 is a flowchart illustrating a memory request transfer method for a semiconductor device according to some embodiments of the present invention, and FIG. 10 is a flowchart illustrating in detail the step of determining whether the first device address in FIG. 9 falls within the first range.

[0102] Referring to FIG. 9, a first memory request and a first physical address are received (S100), and the first physical address is converted into a first device address (S200).

[0103] 7 and 8, the first processor 100_1 may generate a first memory request and transfer it to the first system-on-chip 200_1 together with a first physical address PA_1. The first CXL controller CTRL_CXL1 may convert the first physical address PA_1 into a first device address DA_1. At this time, the first device address DA_1 may be an address that makes it easy to identify the first memory 40_1 of the shared memory 40. That is, the first device address DA_1 may be an address in a format defined for identifying the first memory 40_1.

[0104] 9 and 10, it is determined whether the first device address falls within the first range (S300). If the first device address falls within the first range, the first memory request is transferred to the first memory (S400). If the first device address does not fall within the first range, the first memory request is transferred to the second memory (S500).

[0105] 10, in step S300, it is determined whether the first device address is equal to or greater than the minimum value of the first range (S310). If the first device address is not equal to or greater than the minimum value of the first range, the process proceeds to step S500. If the first device address is equal to or greater than the minimum value of the first range, it is determined whether the first device address is equal to or less than the maximum value of the first range (S320). If the first device address is equal to or greater than the maximum value of the first range, the process proceeds to step S500. If the first device address is equal to or less than the maximum value of the first range, the process proceeds to step S400.

[0106] 7 and 8, the first router Rt1 determines whether the first device address DA_1 falls within a first range, i.e., the range between a minimum value Start_1 and a maximum value End_1. Specifically, the first router Rt1 determines whether the first device address DA_1 is greater than the maximum value End_1 of the device addresses of the first memory 40_1. If the first device address DA_1 is greater than the minimum value Start_1 and less than the maximum value End_1 of the device addresses of the first memory 40_1, the first router Rt1 may forward the first memory request to the first memory 40_1.

[0107] If the first device address DA_1 is greater than the maximum value End_1 of the device address of the first memory 40_1, the first router Rt1 may forward the first memory request to the router of the second system-on-chip 200_2 via the second port 2pt2. Similarly, the router of the second system-on-chip 200_2 may forward the first memory request to the second memory 40_2 if the first device address DA_1 is greater than the minimum value Start_2 of the device address of the second memory 40_2 and less than the maximum value End_2.

[0108] If the first device address DA_1 is larger than the maximum value End_2 of the device address of the second memory 40_2, the first memory request may be transferred to the second memory 40_2. If the first device address DA_1 is smaller than the minimum value Start_2 of the device address of the second memory 40_2, the first memory request may be transferred to the first memory 40_1. However, this case is an erroneous judgment by the first router Rt1, and therefore may be executed exceptionally.

[0109] Similar to the above-described method, the routers of the first through n-th system-on-chips 200_1 through 200_n may forward the first memory request to the corresponding device address of the memory, which may be similarly applied to the second through n-th memory requests.

[0110] Hereinafter, semiconductor devices and memory request transfer methods thereof according to several embodiments of the present invention will be described with reference to Figures 11 to 22. Descriptions of parts that overlap with the above-described embodiments will be omitted or will be described briefly.

[0111] FIG. 11 is a diagram illustrating a first system-on-chip of a semiconductor device according to some embodiments of the present invention, and FIG. 12 is a diagram illustrating a memory request transfer method of a semiconductor device according to some embodiments of the present invention.

[0112] 11, the first system-on-chip 200_1 may include a first MMU MMU1 and a first router Rt1. In the embodiments of FIGS. 2 to 10, all system-on-chips including the first system-on-chip 200_1 are configured to transfer data only left and right, but the first system-on-chip 200_1 of FIG. 11 may include a first router Rt1 that exchanges data in four directions. However, this embodiment is not limited thereto. The first system-on-chip 200_1 may also exchange data in more than four directions, for example, in eight directions.

[0113] 12, first, a first memory request and a first physical address are received (S1100), and the first physical address is converted into a first device address (S1200). Next, the first memory request is transferred to a first system-on-chip corresponding to the first device address via an optimal path (S1300).

[0114] 13 to 22 are intermediate views for explaining a method for transferring a memory request by the semiconductor device of Fig. 11. Hereinafter, step S1300 of Fig. 12 will be described with reference to Figs.

[0115] Referring to Figure 13, there are shown 16 system-on-chips similar to the first system-on-chip 200_1 in Figure 11. These system-on-chips may be arranged in rows and columns. Although Figure 13 shows four rows and four columns, this embodiment is not limited thereto.

[0116] In this case, each system-on-chip may have one-to-one correspondence with a processor, and one processor may receive a memory request to be transferred, derive an optimal path between the respective system-on-chips, and transfer the memory request.

[0117] In FIG. 13, since there are 16 total system-on-chips, a contour number of "17," which is one more than the total number, may be initially assigned to all system-on-chips. A system-on-chip corresponding to a processor that transmits a memory request may be assigned a contour number of "1" as a sender. A "current system-on-chip" refers to a system-on-chip that has a current memory request. A system-on-chip assigned a contour number of "1" may be the sender and initially receive a memory request from a processor.

[0118] 14, the contour numbers of the system-on-chips adjacent to the "current system-on-chip" may all be changed to "2", which is one greater than the "1" of the "current system-on-chip". Also, any one of the system-on-chips having the contour number "2" may be designated as the "current system-on-chip". In this case, if the contour number to be changed is smaller than the existing contour number, the contour number may be changed.

[0119] Here, "adjacent" means a state in which the "current system-on-chip" is directly connected to the "current system-on-chip" via a D2D connection. That is, the "current system-on-chip" and the adjacent system-on-chip can be directly connected via a D2D connection without any other system-on-chip therebetween.

[0120] It also checks whether the "current system on chip" is a "receiver" that has the device address for the memory request, and if it is not a "receiver," it repeats the process of changing the "current system on chip."

[0121] 15, the contour numbers of all system-on-chips adjacent to the "current system-on-chip" may be changed to "3", which is one greater than the "2" of the "current system-on-chip". Also, any one of the system-on-chips having the contour number "3" may be designated as the "current system-on-chip". At this time, it is confirmed that the "current system-on-chip" is not a "receiver".

[0122] Next, referring to Figure 16, the contour numbers of all system-on-chips adjacent to the "current system-on-chip" may be changed to "4", which is one greater than the "3" of the "current system-on-chip". Also, any one of the system-on-chips having the contour number "4" may be designated as the "current system-on-chip". At this time, it is confirmed that the "current system-on-chip" is not a "receiver".

[0123] 17, the contour numbers of all system-on-chips adjacent to the "current system-on-chip" may be changed to "5", which is one greater than the "4" of the "current system-on-chip". Also, any one of the system-on-chips having the contour number "5" may be designated as the "current system-on-chip". At this time, it is confirmed that the "current system-on-chip" is not a "receiver".

[0124] 18, since the contour numbers of the system-on-chips adjacent to the "current system-on-chip" are all "4", which is smaller than the "5" of the "current system-on-chip", the contour numbers of the adjacent system-on-chips cannot be changed any further, and another system-on-chip having a contour number of "5" can become the "current system-on-chip". At this time, it is confirmed that the "current system-on-chip" is not a "receiver".

[0125] 19, among the system-on-chips adjacent to the "current system-on-chip," all system-on-chips with a contour number greater than that of the "current system-on-chip" may be changed to "6," which is one greater than the "5" of the "current system-on-chip." Also, the system-on-chip with the contour number of "6" may be designated as the "current system-on-chip." At this time, it is confirmed that the "current system-on-chip" is not a "receiver."

[0126] 20, among the system-on-chips adjacent to the "current system-on-chip," all of the system-on-chips having the same contour number "5" as the "current system-on-chip" are not "receivers," so among the system-on-chips having the smaller contour number "4" that was not previously the "current system-on-chip" can be designated as the "current system-on-chip." At this time, it is confirmed that the "current system-on-chip" is a "receiver."

[0127] Next, referring to Fig. 21, it is possible to derive the optimal path that passes through the minimum number of systems-on-chips that have "senders" and "receivers" and is configured in the direction of increasing contour numbers. In Fig. 21, any of (a), (b), and (c) can be the optimal path.

[0128] Next, referring to Figure 22, an optimum route OP can be determined by selecting one of (a), (b), and (c) in Figure 21. In Figure 22, (b) in Figure 21 can be selected as the optimum route OP.

[0129] 13 to 22 are merely examples for generating the optimum route OP, that is, the optimum route OP may be generated by any number of other methods.

[0130] 12 again, a first memory request is transferred to a first memory (S1400). At this time, the first memory may be the "receiver" described with reference to FIGS. 12 to 21. That is, the first memory request may be transferred to the first memory via an optimal path OP.

[0131] The above description merely exemplifies the technical idea of ​​the present embodiment, and those skilled in the art to which the present embodiment pertains can make various changes and modifications without departing from the essential features of the present embodiment. Therefore, the present embodiment does not limit the technical idea of ​​the present embodiment, but serves to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the scope of the claims set forth below, and all technical ideas within the equivalent range should be interpreted as being included in the technical scope of the present embodiment.

Claims

1. a first processor generating a first memory physical address and a first memory request; a second processor generating a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to translate the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip, and configured to translate the second memory physical addresses into second device addresses; first and second memories physically connected to the first and second system-on-chips, respectively; The first and second system-on-chips transfer the first and second memory requests to one of a plurality of memories including the first and second memories, respectively, based on the first and second device addresses.

2. The first system-on-chip includes: a first MMU (Memory Management Unit) that converts the first memory physical address into the first device address; 2. The semiconductor device according to claim 1, further comprising a router that determines whether said first device address corresponds to a first memory and transfers said first memory request to said first memory or said second system-on-chip.

3. 3. The semiconductor device according to claim 2, wherein said first and second system-on-chips control said plurality of memories in accordance with a CXL (Compute Express Link) protocol.

4. the first memory has a first range of device addresses; the second memory has a second range of device addresses greater than the first range; 3. The semiconductor device according to claim 2, wherein said router compares said first device address with said first range and transfers said first memory request.

5. the first range is defined as a range from a start address to an end address; 5. The semiconductor device according to claim 4, wherein said router transfers said first memory request to said second system-on-chip if said first device address is greater than said end address.

6. a third processor generating a third memory physical address and a third memory request; 3. The semiconductor device according to claim 2, further comprising a third system-on-chip physically connected to said third processor and said first and second system-on-chips, and translating said third memory physical addresses into third device addresses.

7. 7. The semiconductor device according to claim 6, wherein said router defines contour numbers in order of proximity to a current system-on-chip and transfers said first memory request via an optimal route.

8. 2. The semiconductor device according to claim 1, wherein the first and second systems-on-chips are connected by a die-to-die interface or a chip-to-chip interface.

9. a first processor receiving a first memory request and a first physical address to which the first memory request is to be forwarded; a first system-on-chip physically connected to the first processor converts the first physical address into a first device address; the first system-on-chip compares the first device address with a device address of a first memory connected to the first system-on-chip; If the first system-on-chip corresponds to a device address of the first memory, forward the first memory request to the first memory; If the first system-on-chip does not correspond to the device address of the first memory, the first system-on-chip transfers the first memory request to a second system-on-chip connected to the first system-on-chip; the second system-on-chip compares the first device address with a device address of a second memory connected to the second system-on-chip; The second system-on-chip forwards the first memory request to the second memory if the first memory request corresponds to a device address of the second memory; A memory request transfer method for a semiconductor device, comprising: transferring the first memory request to a third system-on-chip connected to the second system-on-chip when the second system-on-chip does not correspond to a device address of the second memory.

10. device addresses of the first memory are defined as a first range; Comparing the first device address with the device address of the first memory includes: comparing the first device address with a minimum value of the first range; 10. The memory request transfer method for a semiconductor device according to claim 9, further comprising comparing a maximum value of said first range with said first device address.

11. 10. The memory request transfer method for a semiconductor device according to claim 9, wherein the path between the first system-on-chip and the third system-on-chip is an optimal path.

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