Semiconductor device

Abstract

To provide a semiconductor device that can reduce loss.SOLUTION: In an embodiment, a semiconductor device includes first and second elements, first to sixth terminals, and a circuit part. Each of the first and second elements includes first to fourth electrodes and a semiconductor member. The circuit part has the second terminal at a first potential in a first period. The circuit part has the second terminal at a third potential in a second period after the first period. The circuit part has the second terminal at a second potential in a third period after the second period. The second potential is lower than the first potential. The third potential is between the first potential and the second potential. The circuit part has the third terminal at the first potential in the first and second periods. The circuit part has the third terminal at the second potential in the third period. The circuit part has the fifth and sixth terminals at a fourth potential in the first and second periods. The circuit part has the fifth and sixth terminals at a fifth potential in the third period. The fourth potential is lower than the fifth potential.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, semiconductor devices such as IGBTs (insulated gate bipolar transistors) are used in power conversion circuits, etc., and it is desirable to reduce losses. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7352443 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of reducing loss. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first element, a second element, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a circuit unit. Each of the first element and the second element includes a first electrode, a second electrode, a third electrode, a fourth electrode, and a semiconductor member. The semiconductor member is provided between the first electrode and the second electrode. A second direction from the third electrode to the fourth electrode intersects with a first direction from the first electrode to the second electrode. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type. The first semiconductor region includes a first partial region, a second partial region, a third partial region, and a fourth partial region. The direction from the first partial region to the third electrode is along the first direction. The direction from the second partial region to the fourth electrode is along the first direction. The second semiconductor region is connected to the second electrode. The direction from a portion of the third electrode to the second semiconductor region is along the second direction. A portion of the third semiconductor region is between the third partial region and the second semiconductor region in the first direction. The direction from the portion of the third electrode to the portion of the third semiconductor region is along the second direction. Another portion of the third semiconductor region is between the fourth partial region and the fourth semiconductor region in the first direction. The direction from the another portion of the third semiconductor region to the portion of the fourth electrode is along the second direction. The fifth semiconductor region is provided between the first electrode and the first semiconductor region in the first direction. The sixth semiconductor region is provided between the first electrode and the first semiconductor region in the first direction. The direction from the fifth semiconductor region to the sixth semiconductor region is along the fourth direction. The fourth direction is along a plane including the second direction and a third direction intersecting a plane including the first direction and the second direction. The first terminal is electrically connected to the second electrode of the first element. The second terminal is electrically connected to the third electrode of the first element. The third terminal is electrically connected to the fourth electrode of the first element. The fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element.The fifth terminal is electrically connected to the third electrode of the second element. The sixth terminal is electrically connected to the fourth electrode of the second element. The circuit unit is configured to set the second terminal to a first potential based on the potential of the first terminal during a first period. The circuit unit is configured to set the second terminal to a third potential based on the potential of the first terminal during a second period after the first period. The circuit unit is configured to set the second terminal to a second potential based on the potential of the first terminal during a third period after the second period. The second potential is lower than the first potential. The third potential is between the first potential and the second potential. The circuit unit is configured to set the third terminal to the first potential during the first period and the second period. The circuit unit is configured to set the third terminal to the second potential during the third period. The circuit unit is configured to set the fifth terminal and the sixth terminal to a fourth potential based on the potential of the fourth terminal during the first period and the second period. The circuit section is configured to set the fifth terminal and the sixth terminal to a fifth potential based on the potential of the fourth terminal during the third period, the fourth potential being lower than the fifth potential. [Brief explanation of the drawings]

[0006] [Figure 1] 1(a) to 1(d) are schematic views illustrating the operation of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is an equivalent circuit illustrating the semiconductor device according to the first embodiment. [Figure 5] 5(a) to 5(d) are schematic views illustrating the operation of the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) 1(a) to 1(d) are schematic views illustrating the operation of the semiconductor device according to the first embodiment. 2 and 3 are schematic cross-sectional views illustrating the semiconductor device according to the first embodiment. FIG. 4 is an equivalent circuit illustrating the semiconductor device according to the first embodiment.

[0009] As shown in Figures 2 and 3, the semiconductor device 110 of the embodiment includes a first element 10A, a second element 10B, a first terminal T1, a second terminal T2, a third terminal T3, a fourth terminal T4, a fifth terminal T5, a sixth terminal T6, and a circuit section 70.

[0010] Each of the first element 10A and the second element 10B includes a first electrode 51, a second electrode 52, a third electrode 53, a fourth electrode 54, and a semiconductor member 10M. The semiconductor member 10M is provided between the first electrode 51 and the second electrode 52.

[0011] The second direction D2 from the third electrode 53 to the fourth electrode 54 intersects with the first direction D1 from the first electrode 51 to the second electrode 52. The first direction D1 is defined as the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction. The second direction D2 may be, for example, the X-axis direction.

[0012] For example, the third electrode 53 and the fourth electrode 54 may extend along a third direction D3, which intersects with a plane including the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0013] The semiconductor member 10M includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, a fourth semiconductor region 14, a fifth semiconductor region 15, and a sixth semiconductor region 16. The semiconductor member 10M may include, for example, silicon. The semiconductor member 10M may include, for example, a compound semiconductor. The compound semiconductor may include, for example, Ga and N. The compound semiconductor may include, for example, silicon carbide. The semiconductor member 10M extends along a second direction D2 and a third direction D3.

[0014] The first semiconductor region 11 is of a first conductivity type. The first conductivity type is either n-type or p-type. Hereinafter, the first conductivity type will be referred to as n-type.

[0015] The first semiconductor region 11 includes a first partial region 11a, a second partial region 11b, a third partial region 11c, and a fourth partial region 11d. The direction from the first partial region 11a to the third electrode 53 is along the first direction D1. The direction from the second partial region 11b to the fourth electrode 54 is along the first direction D1.

[0016] The region overlapping with the third electrode 53 in the Z-axis direction corresponds to the first partial region 11a. The first partial region 11a is located between the third electrode 53 and the first electrode 51. The region overlapping with the fourth electrode 54 in the Z-axis direction corresponds to the second partial region 11b. The second partial region 11b is located between the third electrode 53 and the first electrode 51. The boundaries between the first partial region 11a, the second partial region 11b, the third partial region 11c, and the fourth partial region 11d may be clear or unclear.

[0017] The direction from a portion of the third electrode 53 to a portion of the first semiconductor region 11 is along the second direction D2. The direction from a portion of the fourth electrode 54 to a portion of the first semiconductor region 11 is along the second direction D2. The direction from a portion of the first insulating member 41 to a portion of the third partial region 11c is along the second direction D2. The portion of the first insulating member 41 that is in contact with the third electrode 53 is in contact with a portion of the third partial region 11c. The direction from the portion of the first insulating member 41 to a portion of the fourth partial region 11d is along the second direction D2. The portion of the first insulating member 41 that is in contact with the fourth electrode 54 is in contact with a portion of the fourth partial region 11d.

[0018] The second semiconductor region 12 is of the first conductivity type. The direction from a portion of the third electrode 53 to the second semiconductor region 12 is along the second direction D2. For example, the second semiconductor region 12 is provided between the first electrode 51 and the second electrode 52 in the first direction D1. The second semiconductor region 12 is in contact with a portion of the first insulating member 41 that is in contact with the third electrode 53. The second semiconductor region 12 is in contact with the second electrode 52.

[0019] The third semiconductor region 13 has a second conductivity type. The second conductivity type is the other of n-type and p-type. Hereinafter, the second conductivity type will be referred to as p-type. The third semiconductor region 13 may be connected to the second electrode 52. The boundary between the third semiconductor region 13 and the first semiconductor region 11 contacts the first insulating member 41. A portion 13p of the third semiconductor region 13 is located between the third partial region 11c and the second semiconductor region 12 in the first direction D1. The direction from a portion of the third electrode 53 to the portion 13p of the third semiconductor region 13 is along the second direction D2. In the first semiconductor region 11, the region that overlaps with the second semiconductor region 12 in the first direction D1 corresponds to the third partial region 11c. The portion 13p of the third semiconductor region 13 contacts a portion of the first insulating member 41 that contacts the third electrode 53.

[0020] The fourth semiconductor region 14 is of the second conductivity type. Another portion 13q of the third semiconductor region 13 is located between the fourth partial region 11d and the fourth semiconductor region 14 in the first direction D1. The direction from the other portion 13q of the third semiconductor region 13 to a portion of the fourth electrode 54 is along the second direction D2. In the first semiconductor region 11, a region that overlaps with the fourth semiconductor region 14 in the first direction D1 corresponds to the fourth partial region 11d. For example, the fourth semiconductor region 14 is provided between the first semiconductor region 11 and the second electrode 52 in the first direction D1. Another portion 13q of the third semiconductor region 13 contacts a portion of the first insulating member 41 that contacts the fourth electrode 54. The fourth semiconductor region 14 contacts a portion of the first insulating member 41 that contacts the fourth electrode 54. The fourth semiconductor region 14 contacts the second electrode 52.

[0021] The fifth semiconductor region 15 is provided in the first direction D1 between the first electrode 51 and the first semiconductor region 11. The fifth semiconductor region 15 is of the first conductivity type.

[0022] The sixth semiconductor region 16 is provided between the first electrode 51 and the first semiconductor region 11 in the first direction D1. The sixth semiconductor region 16 is of the second conductivity type. The direction from the fifth semiconductor region 15 to the sixth semiconductor region 16 is along the fourth direction D4. The fourth direction D4 is along a plane PL1 that includes the second direction D2 and the third direction D3. The fourth direction D4 is, for example, along the second direction D2.

[0023] A plurality of fifth semiconductor regions 15 and a plurality of sixth semiconductor regions 16 may be provided. The fifth semiconductor regions 15 and the sixth semiconductor regions 16 may be provided alternately. The fifth semiconductor regions 15 and the sixth semiconductor regions 16 are in contact with the first electrode 51.

[0024] 2, the first terminal T1 is electrically connected to the second electrode 52 of the first element 10A. The second terminal T2 is electrically connected to the third electrode 53 of the first element 10A. The third terminal T3 is electrically connected to the fourth electrode 54 of the first element 10A.

[0025] 2 and 3, the fourth terminal T4 is electrically connected to the second electrode 52 of the second element 10B and the first electrode 51 of the first element 10A. The second electrode 52 of the second element 10B is electrically connected to the first electrode 51 of the first element 10A.

[0026] 3, the fifth terminal T5 is electrically connected to the third electrode 53 of the second element 10B. The sixth terminal T6 is electrically connected to the fourth electrode 54 of the second element 10B.

[0027] In the first element 10A and the second element 10B, the current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53 and the potential of the fourth electrode 54. The first electrode 51 functions as, for example, a collector electrode. The second electrode 52 functions as, for example, an emitter electrode. The third electrode 53 functions as, for example, a first gate electrode. The fourth electrode 54 functions as, for example, a second gate electrode. The third electrode 53 functions as, for example, a main gate. The fourth electrode 54 functions as, for example, a control gate electrode.

[0028] The semiconductor device 110 is, for example, a double-gate RC-IEGT (Reverse-Conducting Injection Enhanced Gate Transistor).

[0029] The circuit section 70 is electrically connected to the first terminal T1, the second terminal T2, the third terminal T3, the fourth terminal T4, the fifth terminal T5, and the sixth terminal T6, and is configured to control the potential of each of these terminals.

[0030] FIG. 1(a) illustrates the potential Vg2 at the fifth terminal T5 of the second element 10B. FIG. 1(b) illustrates the potential Vc2 at the sixth terminal T6 of the second element 10B. FIG. 1(c) illustrates the potential Vg1 at the second terminal T2 of the first element 10A. FIG. 1(d) illustrates the potential Vc1 at the third terminal T3 of the first element 10A. The horizontal axis of these figures represents time tm.

[0031] As shown in FIG. 1(c), the circuit unit 70 is configured to set the second terminal T2 to a first potential V1 during a first period TP1. The first potential V1 is a potential based on the potential of the first terminal T1. The circuit unit 70 is configured to set the second terminal T2 to a third potential V3 during a second period TP2 following the first period TP1. The third potential V3 is a potential based on the potential of the first terminal T1.

[0032] The circuit unit 70 is configured to set the second terminal T2 to a second potential V2 during a third period TP3 following the second period TP2. The second potential V2 is a potential based on the potential of the first terminal T1. The second potential V2 is lower than the first potential V1. The third potential V3 is between the first potential V1 and the second potential V2.

[0033] In one example, the first potential V1 is +15 V. In one example, the second potential V2 is −15 V. In one example, the third potential V3 may be, for example, 0 V.

[0034] 1(d), the circuit section 70 is configured to set the third terminal T3 to a first potential V1 during the first period TP1 and the second period TP2, and to set the third terminal T3 to a second potential V2 during the third period TP3.

[0035] As shown in FIGS. 1(a) and 1(b), the circuit unit 70 is configured to set the fifth terminal T5 and the sixth terminal T6 to a fourth potential V4 during the first period TP1 and the second period TP2. The fourth potential V4 is a potential based on the potential of the fourth terminal T4. The circuit unit 70 is configured to set the fifth terminal T5 and the sixth terminal T6 to a fifth potential V5 during the third period TP3. The fifth potential V5 is a potential based on the potential of the fourth terminal T4. The fourth potential V4 is lower than the fifth potential V5. The value of the fourth potential V4 may be the same as the value of the second potential V2. The value of the fifth potential V5 may be the same as the value of the first potential V1. For example, the fifth potential V5 is positive and the fourth potential V4 is negative.

[0036] For example, before the first period TP1, the first element 10A is in a steady on state. During the first period TP1, the first element 10A is in diode mode. The first period TP1 corresponds to, for example, an electron extraction period. The second period TP2 corresponds to a transition period (dead time) for mode switching. During the third period TP3, the first element 10A is in reverse recovery mode. Meanwhile, during the first period TP1 and the second period TP2, the second element 10B is in an off state. For example, during the third period TP3, the second element 10B operates in IEGT mode. At the second time t2, the second element 10B starts to turn on.

[0037] In the embodiment, during the second period TP2, the potential Vg1 of the second terminal T2 of the first element 10A is set to an intermediate third potential V3. This causes the first element 10A to function as a low injection diode. This suppresses high injection diode operation during the transition period (dead time) of mode switching. For example, reverse recovery is performed in a state where carriers are reduced. This makes it possible to reduce reverse recovery loss Err. According to the embodiment, a semiconductor device capable of reducing loss can be provided.

[0038] As described above, the fourth electrode 54 is provided with the fourth semiconductor region 14 of the first conductivity type, rather than the second semiconductor region 12 of the first conductivity type. This prevents electrons from moving toward the second electrode 52 near the fourth electrode 54, even if the potential Vc1 of the third terminal T3 (fourth electrode 54) is the first potential V1 during the second period TP2.

[0039] In the embodiment, after the potential Vg1 of the second terminal T2 (third electrode 53) drops from the first potential V1, the potential Vg2 of the fifth terminal T5 and the potential Vc2 of the sixth terminal T6 change from the fourth potential V4 to the fifth potential V5. This substantially prevents a short circuit between the first terminal T1 and the seventh terminal T7. This prevents element damage due to a short circuit.

[0040] For example, in the first reference example, in the first period TP1, the potential Vg1 of the second terminal T2 (third electrode 53) and the potential Vc1 of the third terminal T3 (fourth electrode 54) are the first potential V1. In the second period TP2 and the third period TP3, these potentials are the second potential V2. On the other hand, in the first period TP1 and the second period TP2, the potential Vg2 of the fifth terminal T5 (third electrode 53) and the potential Vc2 of the sixth terminal T6 (fourth electrode 54) are the fourth potential V4. In the third period TP3, these potentials are the fifth potential V5. In this first reference example, reverse recovery is performed in a state where there are many carriers. Therefore, the reverse recovery loss Err is large.

[0041] For example, in the second reference example, the second semiconductor region 12 of the first conductivity type is provided on the side of the fourth electrode 54, instead of the fourth semiconductor region 14 of the second conductivity type. Furthermore, in the second reference example, the potential Vc1 of the third terminal T3 (fourth electrode 54) becomes the second potential V2 during the second period TP2. Except for this, the potential changes in the second reference example are the same as the potential changes in the semiconductor device 110. In such a second reference example, reverse recovery occurs in a state where there are many carriers near the fourth electrode 54 of the first element 10A. For this reason, there is a limit to the reduction in reverse recovery loss Err.

[0042] When the reverse recovery loss Err in the first reference example is 1, the reverse recovery loss Err in the second reference example is 0.947. When the reverse recovery loss Err in the first reference example is 1, the reverse recovery loss Err in the semiconductor device 110 according to the embodiment is 0.918. In this way, according to the embodiment, it is possible to suppress losses.

[0043] 3, the semiconductor device 110 may further include a seventh terminal T7. The seventh terminal T7 is electrically connected to the first electrode 51 of the second element 10B.

[0044] As shown in FIG. 4, the circuit section 70 is configured to apply a controlled voltage Vcc between the first terminal T1 and the seventh terminal T7.

[0045] In the embodiment, for example, the third potential V3 may be less than the threshold voltage of the first element 10A. In the embodiment, the third potential V3 may be substantially midway between the first potential V1 and the second potential V2. For example, a first absolute value of a first difference between the third potential V3 and the first potential V1 may be 0.8 to 1.2 times a second absolute value of a second difference between the third potential V3 and the second potential V2. In the embodiment, for example, the first potential V1 is positive. The second potential V2 is negative.

[0046] In the embodiment, the second length of the second period TP2 is shorter than the first length of the first period TP1. For example, the second length may be 10 times or more and 100 times or less than the first length. For example, the first length may be 10 μs or more and 200 μs or less. For example, the second length may be 1 μs or more and less than 10 μs.

[0047] As shown in Figures 1(c) and 1(d), the first period TP1 is the period from time t0 to the first time t1, the second period TP2 is the period from the first time t1 to the second time t2, and the third period TP3 is the period after the second time t2.

[0048] As shown in FIG. 1(c), the circuit section 70 may be configured to change the potential Vg1 of the second terminal T2 from a first potential V1 to a second potential V2 from a first time t1. As already described, the first potential V1 is a potential based on the potential of the first terminal T1. The second potential V2 is a potential based on the potential of the first terminal T1. The second potential V2 is lower than the first potential V1. The circuit section 70 is configured to set the potential Vg1 of the second terminal T2 to the second potential V2 at a second time t2 after the first time t1.

[0049] As shown in FIG. 1(d), the circuit section 70 is configured to change the potential Vc1 of the third terminal T3 from the first potential V1 to the second potential V2 at the second time t2.

[0050] As shown in Figures 1(a) and 1(b), the circuit section 70 is configured to change the potential Vg2 of the fifth terminal T5 and the potential Vc2 of the sixth terminal T6 from the fourth potential V4 to the fifth potential V5 at the second time t2.

[0051] The time between the first time t1 and the second time t2 (second period TP2) is longer than the time Δt1 during which the potential Vc1 of the third terminal T3 changes from the first potential V1 to the second potential V2. The time between the first time t1 and the second time t2 (second period TP2) is longer than the time (time Δt2 and time Δt3) during which the potential Vg2 of the fifth terminal T5 and the potential Vc2 of the sixth terminal T6 change from the fourth potential V4 to the fifth potential V5. For example, the first period TP1 is longer than the second period TP2. The slope (dV / dt) of the change in the potential Vg1 of the second terminal T2 during the period between time t0 and the first time t1 is smaller than the slope of the change in the potential Vg1 of the second terminal T2 at the first time t1. The gradient (dV / dt) of the change in the potential Vg1 of the second terminal T2 during the period between the first time t1 and the second time t2 is smaller than the gradient of the change in the potential Vg1 of the second terminal T2 at the first time t1. The gradient of the change in the potential Vg1 of the second terminal T2 during the period between the first time t1 and the second time t2 is smaller than the gradient of the change in the potential Vg1 of the second terminal T2 at the second time t2.

[0052] In the example shown in FIGS. 1(a) to 1(d), the time when the fifth terminal T5 and the sixth terminal T6 reach the fifth potential V5 is the same as the time when the third terminal T3 reaches the second potential V2.

[0053] 5(a) to 5(d) are schematic views illustrating the operation of the semiconductor device according to the first embodiment. These figures show another example of the operation of the semiconductor device 110. In the example of FIGS. 5(a) to 5(d), after the time (second time t2) when the fifth terminal T5 and the sixth terminal T6 are at the fifth potential V5, the third terminal T3 is at the second potential V2. The time Δt between the time (second time t2) when the fifth terminal T5 and the sixth terminal T6 are at the fifth potential V5 and the time ta2 when the third terminal T3 is at the second potential V2 is 1 μs or less. In this way, the time ta2 may be after the second time t2. By making the time difference between these two times short, 1 μs or less, it is possible to suppress, for example, losses.

[0054] 2 and 3, for example, each of the first element 10A and the second element 10B may further include a first insulating member 41. The first insulating member 41 of the first element 10A is provided between the third electrode 53 of the first element 10A and the semiconductor member 10M of the first element 10A, and between the fourth electrode 54 of the first element 10A and the semiconductor member 10M of the first element 10A.

[0055] The first insulating member 41 of the second element 10B is provided between the third electrode 53 of the second element 10B and the semiconductor member 10M of the second element 10B, and between the fourth electrode 54 of the second element 10B and the semiconductor member 10M of the second element 10B.

[0056] For example, a portion of the first insulating member 41 contacts a portion of the third electrode 53 and the second semiconductor region 12 in the second direction D2. Another portion of the first insulating member 41 contacts a portion of the fourth electrode 54 and the fourth semiconductor region 14 in the second direction D2.

[0057] 2 and 3, each of the first element 10A and the second element 10B may further include a second insulating member 42. The second insulating member 42 of the first element 10A is provided between the third electrode 53 of the first element 10A and the second electrode 52 of the first element 10A, and between the fourth electrode 54 of the first element 10A and the second electrode 52 of the first element 10A.

[0058] The second insulating member 42 of the second element 10B is provided between the third electrode 53 of the second element 10B and the second electrode 52 of the second element 10B, and between the fourth electrode 54 of the second element 10B and the second electrode 52 of the second element 10B.

[0059] In the embodiment, for example, the second impurity concentration of the first conductivity type in the second semiconductor region 12 is higher than the first impurity concentration of the first conductivity type in the first semiconductor region 11. For example, the fifth impurity concentration of the first conductivity type in the fifth semiconductor region 15 is higher than the first impurity concentration.

[0060] For example, the concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region 14 is higher than the concentration of the third impurity of the second conductivity type in the third semiconductor region 13. For example, the concentration of the sixth impurity of the second conductivity type in the sixth semiconductor region 16 is higher than the third impurity concentration.

[0061] 2 and 3, each of the first element 10A and the second element 10B of the semiconductor device 110 may further include a fifth electrode 55. The fifth electrode 55 is electrically connected to the second electrode 52. The direction from a portion of the fifth electrode 55 to a portion of the first semiconductor region 11 is along the second direction D2. The direction from a portion of the fifth electrode 55 to a portion of the third semiconductor region 13 is along the second direction D2. The direction from a portion of the fifth electrode 55 to a portion of the fourth semiconductor region 14 is along the second direction D2. By providing the fifth electrode 55, for example, a high breakdown voltage is easily obtained.

[0062] In the embodiment, information about the shape of the semiconductor region is obtained by, for example, electron microscope observation. Information about the impurity concentration in the semiconductor region is obtained by, for example, EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information about the carrier concentration in the semiconductor region is obtained by, for example, SCM (Scanning Capacitance Microscopy).

[0063] The embodiments may include the following technical solutions. (Technical proposal 1) a first element; and a second element; and A first terminal; A second terminal; A third terminal; The fourth terminal, The fifth terminal, The sixth terminal, A circuit unit; Equipped with Each of the first element and the second element is A first electrode; A second electrode; A third electrode; A fourth electrode; a semiconductor member provided between the first electrode and the second electrode; Including, a second direction from the third electrode to the fourth electrode intersects with a first direction from the first electrode to the second electrode; The semiconductor member is a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, the direction from the first partial region to the third electrode being along the first direction, and the direction from the second partial region to the fourth electrode being along the first direction; a second semiconductor region of the first conductivity type, the direction from a portion of the third electrode to the second semiconductor region being along the second direction, and the second semiconductor region being connected to the second electrode; a third semiconductor region of a second conductivity type, a portion of the third semiconductor region being between the third partial region and the second semiconductor region in the first direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction; a fourth semiconductor region of the second conductivity type, wherein another part of the third semiconductor region is between the fourth partial region and the fourth semiconductor region in the first direction, and a direction from the other part of the third semiconductor region to a part of the fourth electrode is along the second direction; a fifth semiconductor region of the first conductivity type provided between the first electrode and the first semiconductor region in the first direction; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region in the first direction, the direction from the fifth semiconductor region to the sixth semiconductor region being along a fourth direction, the fourth direction being along a plane including the second direction and a third direction intersecting a plane including the first direction and the second direction; Including, the first terminal is electrically connected to the second electrode of the first element; the second terminal is electrically connected to the third electrode of the first element; the third terminal is electrically connected to the fourth electrode of the first element, the fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element; the fifth terminal is electrically connected to the third electrode of the second element, the sixth terminal is electrically connected to the fourth electrode of the second element, the circuit unit is configured to set the second terminal to a first potential based on a potential of the first terminal during a first period; the circuit unit is configured to set the second terminal to a third potential based on the potential of the first terminal during a second period after the first period; the circuit unit is configured to set the second terminal to a second potential based on the potential of the first terminal in a third period after the second period, the second potential being lower than the first potential, and the third potential being between the first potential and the second potential; the circuit unit is configured to set the third terminal to the first potential during the first period and the second period; the circuit unit is configured to set the third terminal to the second potential during the third period; the circuit unit is configured to set the fifth terminal and the sixth terminal to a fourth potential based on a potential of the fourth terminal during the first period and the second period; The semiconductor device, wherein the circuit unit is configured to set the fifth terminal and the sixth terminal to a fifth potential based on the potential of the fourth terminal during the third period, and the fourth potential is lower than the fifth potential.

[0064] (Technical proposal 2) a seventh terminal electrically connected to the first electrode of the second element; The semiconductor device according to Technical Solution 1, wherein the circuit section is configured to apply a controlled voltage between the first terminal and the seventh terminal.

[0065] (Technical proposal 3) The semiconductor device according to Technical Solution 1 or 2, wherein the third potential is less than the threshold voltage of the first element.

[0066] (Technical proposal 4) A semiconductor device described in any one of Technical Solutions 1 to 3, wherein a first absolute value of a first difference between the third potential and the first potential is 0.8 to 1.2 times the second absolute value of a second difference between the third potential and the second potential.

[0067] (Technical proposal 5) the first potential is positive; The semiconductor device according to any one of Technical Solutions 1 to 4, wherein the second potential is negative.

[0068] (Technical proposal 6) 6. The semiconductor device according to any one of Technical Solutions 1 to 5, wherein a second length of the second period is shorter than a first length of the first period.

[0069] (Technical proposal 7) The semiconductor device according to Technical Solution 6, wherein the second length is 10 times or more and 100 times or less than the first length.

[0070] (Technical proposal 8) the first length is equal to or greater than 10 μs and equal to or less than 200 μs, The semiconductor device according to Technical Scheme 6 or 7, wherein the second length is greater than or equal to 1 μs and less than 10 μs.

[0071] (Technical proposal 9) The semiconductor device according to any one of Technical Solutions 1 to 8, wherein the time at which the fifth terminal and the sixth terminal reach the fifth potential is the same as the time at which the third terminal reaches the second potential.

[0072] (Technical proposal 10) After the fifth terminal and the sixth terminal are at the fifth potential, the third terminal is at the second potential; The semiconductor device according to any one of Technical Solutions 1 to 8, wherein the time between the time when the fifth terminal and the sixth terminal become the fifth potential and the time when the third terminal becomes the second potential is 1 μs or less.

[0073] (Technical proposal 11) each of the first element and the second element further includes a first insulating member; the first insulating member of the first element is provided between the third electrode of the first element and the semiconductor member of the first element, and between the fourth electrode of the first element and the semiconductor member of the first element, A semiconductor device described in any one of Technical Proposals 1 to 10, wherein the first insulating member of the second element is provided between the third electrode of the second element and the semiconductor member of the second element, and between the fourth electrode of the second element and the semiconductor member of the second element.

[0074] (Technical proposal 12) A semiconductor device described in Technical Proposal 11, wherein a portion of the first insulating member contacts a portion of the third electrode and the second semiconductor region in the second direction.

[0075] (Technical proposal 13) A semiconductor device described in Technical Proposal 12, wherein another portion of the first insulating member contacts a portion of the fourth electrode and the fourth semiconductor region in the second direction.

[0076] (Technical proposal 14) each of the first element and the second element further includes a second insulating member; The second insulating member of the first element is provided between the third electrode of the first element and the second electrode of the first element, and between the fourth electrode of the first element and the second electrode of the first element. A semiconductor device described in any one of Technical Proposals 1 to 13, wherein the second insulating member of the second element is provided between the third electrode of the second element and the second electrode of the second element, and between the fourth electrode of the second element and the second electrode of the second element.

[0077] (Technical proposal 15) The semiconductor device according to any one of Technical Schemes 1 to 14, wherein the second impurity concentration of the first conductivity type in the second semiconductor region is higher than the first impurity concentration of the first conductivity type in the first semiconductor region.

[0078] (Technical proposal 16) The semiconductor device according to Technical Proposal 15, wherein a fifth impurity concentration of the first conductivity type in the fifth semiconductor region is higher than the first impurity concentration.

[0079] (Technical proposal 17) The semiconductor device according to any one of technical proposals 1 to 16, wherein the fourth impurity concentration of the second conductivity type in the fourth semiconductor region is higher than the third impurity concentration of the second conductivity type in the third semiconductor region.

[0080] (Technical proposal 18) The semiconductor device according to Technical Proposal 17, wherein a sixth impurity concentration of the second conductivity type in the sixth semiconductor region is higher than the third impurity concentration.

[0081] (Technical proposal 19) The semiconductor device according to any one of technical proposals 1 to 18, wherein the third electrode and the fourth electrode extend along a third direction that intersects with a plane including the first direction and the second direction.

[0082] (Technical proposal 20) a first element; and a second element; and A first terminal; A second terminal; A third terminal; The fourth terminal, The fifth terminal, The sixth terminal, A circuit unit; Equipped with Each of the first element and the second element is A first electrode; A second electrode; A third electrode; A fourth electrode; a semiconductor member provided between the first electrode and the second electrode; Including, a second direction from the third electrode to the fourth electrode intersects with a first direction from the first electrode to the second electrode; The semiconductor member is a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, the direction from the first partial region to the third electrode being along the first direction, and the direction from the second partial region to the fourth electrode being along the first direction; a second semiconductor region of the first conductivity type, the direction from a portion of the third electrode to the second semiconductor region being along the second direction; a third semiconductor region of a second conductivity type, a portion of the third semiconductor region being between the third partial region and the second semiconductor region in the second direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction; a fourth semiconductor region of the second conductivity type, wherein another part of the third semiconductor region is between the fourth partial region and the fourth semiconductor region in the second direction, and a direction from the other part of the third semiconductor region to a part of the fourth electrode is along the second direction; a fifth semiconductor region of the first conductivity type provided between the first electrode and the first semiconductor region in the first direction; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region in the first direction, the direction from the fifth semiconductor region to the sixth semiconductor region being along a fourth direction, the fourth direction being along a plane including the second direction and a third direction intersecting a plane including the first direction and the second direction; Including, the first terminal is electrically connected to the second electrode of the first element; the second terminal is electrically connected to the third electrode of the first element; the third terminal is electrically connected to the fourth electrode of the first element, the fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element; the fifth terminal is electrically connected to the third electrode of the second element, the sixth terminal is electrically connected to the fourth electrode of the second element, the circuit section is configured to change the potential of the second terminal from a first potential to a second potential from a first time; the first potential is a potential based on the potential of the first terminal, the second potential is a potential relative to the potential of the first terminal, the second potential is lower than the first potential; the circuit section is configured to set the potential of the second terminal to the second potential at a second time after the first time; the circuit section is configured to change the potential of the third terminal from the first potential to the second potential at the second time; the circuit unit is configured to change the potential of the fifth terminal and the potential of the sixth terminal from a fourth potential to a fifth potential at the second time; the fourth potential is a potential based on the potential of the fourth terminal, the fifth potential is a potential relative to the potential of the fourth terminal, the fourth potential is lower than the fifth potential; the time between the first time and the second time is longer than the time required for the potential of the third terminal to change from the first potential to the second potential; The semiconductor device, wherein the time between the first time and the second time is longer than the time for the potential of the fifth terminal and the time for the potential of the sixth terminal to change from the fourth potential to the fifth potential.

[0083] According to the embodiment, a semiconductor device capable of reducing loss can be provided.

[0084] In this specification, "perpendicular" and "parallel" do not only mean strictly perpendicular and strictly parallel, but also include variations in the manufacturing process, and may mean substantially perpendicular and substantially parallel.

[0085] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of each element included in the semiconductor device, such as elements, terminals, circuit parts, electrodes, semiconductor members, and insulating members, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0086] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0087] In addition, all semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0088] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and these modifications and alterations are also considered to fall within the scope of the present invention.

[0089] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0090] 10A, 10B: first and second elements, 10M: semiconductor member, 11-16: first to sixth semiconductor regions, 11a-11d: first to fourth partial regions, 13p, 13q: part, 41, 42: first and second insulating members, 51-54: first to fourth electrodes, 70: circuit portion, 110: semiconductor device, D1-D4: first to fourth directions, PL1: plane, T1-T7: first to seventh terminals, TP1-TP3: first to third periods, V1-V3: first to third potentials, Vc1, Vc2, Vg1, Vg2: potentials, Vcc: controlled voltage, t0: time, t1, t2: first time, ta2: time, tm: time, Δt, Δt1-Δt3: time

Claims

1. a first element; and a second element; and A first terminal; A second terminal; A third terminal; A fourth terminal; A fifth terminal; A sixth terminal; A circuit unit; Equipped with Each of the first element and the second element is A first electrode; A second electrode; A third electrode; A fourth electrode; a semiconductor member provided between the first electrode and the second electrode; Including, a second direction from the third electrode to the fourth electrode intersects with a first direction from the first electrode to the second electrode; The semiconductor member is a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, the direction from the first partial region to the third electrode being along the first direction, and the direction from the second partial region to the fourth electrode being along the first direction; a second semiconductor region of the first conductivity type, the direction from a portion of the third electrode to the second semiconductor region being along the second direction, and the second semiconductor region being connected to the second electrode; a third semiconductor region of a second conductivity type, a portion of the third semiconductor region being between the third partial region and the second semiconductor region in the first direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction; a fourth semiconductor region of the second conductivity type, wherein another portion of the third semiconductor region is between the fourth partial region and the fourth semiconductor region in the first direction, and a direction from the other portion of the third semiconductor region to a portion of the fourth electrode is along the second direction; a fifth semiconductor region of the first conductivity type provided between the first electrode and the first semiconductor region in the first direction; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region in the first direction, the direction from the fifth semiconductor region to the sixth semiconductor region being along a fourth direction, the fourth direction being along a plane including the second direction and a third direction intersecting a plane including the first direction and the second direction; Including, the first terminal is electrically connected to the second electrode of the first element; the second terminal is electrically connected to the third electrode of the first element; the third terminal is electrically connected to the fourth electrode of the first element; the fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element; the fifth terminal is electrically connected to the third electrode of the second element; the sixth terminal is electrically connected to the fourth electrode of the second element, the circuit unit is configured to set the second terminal to a first potential based on a potential of the first terminal during a first period; the circuit unit is configured to set the second terminal to a third potential based on the potential of the first terminal during a second period after the first period; the circuit unit is configured to set the second terminal to a second potential based on the potential of the first terminal in a third period after the second period, the second potential being lower than the first potential, and the third potential being between the first potential and the second potential; the circuit unit is configured to set the third terminal to the first potential during the first period and the second period; the circuit unit is configured to set the third terminal to the second potential during the third period; the circuit unit is configured to set the fifth terminal and the sixth terminal to a fourth potential based on a potential of the fourth terminal during the first period and the second period; the circuit unit is configured to set the fifth terminal and the sixth terminal to a fifth potential based on the potential of the fourth terminal during the third period, and the fourth potential is lower than the fifth potential.

2. a seventh terminal electrically connected to the first electrode of the second element; 2. The semiconductor device according to claim 1, wherein said circuit section is configured to apply a controlled voltage between said first terminal and said seventh terminal.

3. 3. The semiconductor device according to claim 1, wherein the third potential is lower than a threshold voltage of the first element.

4. 2. The semiconductor device according to claim 1, wherein a first absolute value of a first difference between the third potential and the first potential is 0.8 to 1.2 times a second absolute value of a second difference between the third potential and the second potential.

5. each of the first element and the second element further includes a first insulating member; the first insulating member of the first element is provided between the third electrode of the first element and the semiconductor member of the first element, and between the fourth electrode of the first element and the semiconductor member of the first element, 2. The semiconductor device according to claim 1, wherein the first insulating member of the second element is provided between the third electrode of the second element and the semiconductor member of the second element, and between the fourth electrode of the second element and the semiconductor member of the second element.

6. The semiconductor device according to claim 5 , wherein a portion of said first insulating member is in contact with a portion of said third electrode and said second semiconductor region in said second direction.

7. The semiconductor device according to claim 6 , wherein another portion of said first insulating member is in contact with a portion of said fourth electrode and said fourth semiconductor region in said second direction.

8. 2. The semiconductor device according to claim 1, wherein a concentration of the second impurity of the first conductivity type in the second semiconductor region is higher than a concentration of the first impurity of the first conductivity type in the first semiconductor region.

9. 2. The semiconductor device according to claim 1, wherein a fourth impurity concentration of said second conductivity type in said fourth semiconductor region is higher than a third impurity concentration of said second conductivity type in said third semiconductor region.

10. a first element; and a second element; and A first terminal; A second terminal; A third terminal; A fourth terminal; A fifth terminal; A sixth terminal; A circuit unit; Equipped with Each of the first element and the second element is A first electrode; A second electrode; A third electrode; A fourth electrode; a semiconductor member provided between the first electrode and the second electrode; Including, a second direction from the third electrode to the fourth electrode intersects with a first direction from the first electrode to the second electrode; The semiconductor member is a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, the direction from the first partial region to the third electrode being along the first direction, and the direction from the second partial region to the fourth electrode being along the first direction; a second semiconductor region of the first conductivity type, the direction from a portion of the third electrode to the second semiconductor region being along the second direction; a third semiconductor region of a second conductivity type, a portion of the third semiconductor region being between the third partial region and the second semiconductor region in the second direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction; a fourth semiconductor region of the second conductivity type, wherein another part of the third semiconductor region is between the fourth partial region and the fourth semiconductor region in the second direction, and a direction from the other part of the third semiconductor region to a part of the fourth electrode is along the second direction; a fifth semiconductor region of the first conductivity type provided between the first electrode and the first semiconductor region in the first direction; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region in the first direction, the direction from the fifth semiconductor region to the sixth semiconductor region being along a fourth direction, the fourth direction being along a plane including the second direction and a third direction intersecting a plane including the first direction and the second direction; Including, the first terminal is electrically connected to the second electrode of the first element; the second terminal is electrically connected to the third electrode of the first element; the third terminal is electrically connected to the fourth electrode of the first element; the fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element; the fifth terminal is electrically connected to the third electrode of the second element, the sixth terminal is electrically connected to the fourth electrode of the second element, the circuit section is configured to change the potential of the second terminal from a first potential to a second potential from a first time; the first potential is a potential based on the potential of the first terminal, the second potential is a potential relative to the potential of the first terminal, the second potential is lower than the first potential; the circuit unit is configured to set the potential of the second terminal to the second potential at a second time after the first time; the circuit section is configured to change the potential of the third terminal from the first potential to the second potential at the second time; the circuit unit is configured to change the potential of the fifth terminal and the potential of the sixth terminal from a fourth potential to a fifth potential at the second time; the fourth potential is a potential based on the potential of the fourth terminal, the fifth potential is a potential based on the potential of the fourth terminal, the fourth potential is lower than the fifth potential, a time period between the first time point and the second time point is longer than a time period for the potential of the third terminal to change from the first potential to the second potential; The semiconductor device, wherein the time between the first time and the second time is longer than the time for the potential of the fifth terminal and the time for the potential of the sixth terminal to change from the fourth potential to the fifth potential.

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