Semiconductor device
The semiconductor device addresses Fermi level pinning issues by incorporating a single-layer insulating film between the channel and electrode, enhancing design margin and stability of breakdown and threshold voltages.
Patent Information
- Application Number
- JP2024039358
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2025-09-29
AI Technical Summary
Existing Schottky MOSFETs face challenges in expanding design margin due to issues with Fermi level pinning and reduced barrier height at the metal-semiconductor interface, leading to difficulties in adjusting breakdown voltage and threshold voltage.
A semiconductor device with a single-layer insulating film between the channel portion and the second electrode, which reduces the influence of Fermi level pinning and allows for a higher barrier height, enabling better control over breakdown voltage and threshold voltage.
The insulating film enhances the design margin by maintaining the breakdown voltage and threshold voltage stability, while also suppressing leakage current at corners and improving current-voltage characteristics.
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Figure 2025140161000001_ABST
Abstract
Description
[Technical Field]
[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]
[0002] A Schottky MOSFET has been proposed as a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) that achieves an off state by using a depletion layer extending from the Schottky junction between the source electrode and the semiconductor layer at the trench contact area, without providing a p-type base layer. [Prior art documents] [Non-patent literature]
[0003] [Non-Patent Document 1] Yee-Chia Yeo, Pushkar Ranade, Tsu-Jae King, Chenming Hu "Effects of High-k Gate Dielectric Materials on Metal and Silicon Gate Workfunctions" IEEE ELECTRON DEVICE LETTERS, VOL.23, NO.6, JUNE 2002 Summary of the Invention [Problem to be solved by the invention]
[0004] An object of the embodiments of the present invention is to provide a semiconductor device that allows for an expansion of the design margin. [Means for solving the problem]
[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a semiconductor layer of a first conductivity type provided on the first electrode, the semiconductor layer having a plurality of mesa portions spaced apart from each other in a first direction, a second electrode located in a recess extending from an upper surface of the mesa portion in a second direction perpendicular to the first direction, a gate electrode located between adjacent mesa portions in the first direction among the plurality of mesa portions, and a single-layer insulating film located in the recess, wherein the mesa portion has a channel portion located between the recess and the gate electrode in the first direction, and a contact portion provided on the channel portion and having a higher first conductivity type impurity concentration than the channel portion, the channel portion has a first side surface facing the gate electrode in the first direction and a second side surface located opposite the first side surface in the first direction, the insulating film is provided on the second side surface, and the second electrode is in contact with the contact portion and the insulating film in the recess. [Brief explanation of the drawings]
[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 3] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 5(a) and 5(b) are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, identical or similar elements are given the same reference numerals.
[0008] 1, the semiconductor device 1 of the embodiment includes a first electrode 41, a semiconductor layer 100 provided on the first electrode 41, and a second electrode 42 provided on the semiconductor layer 100. The semiconductor device 1 has a vertical MOSFET structure in which current flows in the thickness direction of the semiconductor layer 100 provided between the first electrode 41 and the second electrode 42. The first electrode 41 functions as a drain electrode, and the second electrode 42 functions as a source electrode. The first electrode 41 and the second electrode 42 contain metal.
[0009] The thickness direction of the semiconductor layer 100 is along the second direction Z. Two directions perpendicular to the second direction Z are defined as the first direction X and the third direction Y. In FIG. 1, the first direction X is the horizontal direction, the second direction Z is the vertical direction, and the third direction Y is the direction penetrating the page.
[0010] The semiconductor layer 100 is of a first conductivity type. In this specification, the first conductivity type is described as n-type, but the first conductivity type may also be p-type. The semiconductor layer 100 is, for example, a silicon layer. Alternatively, the semiconductor layer 100 may be a silicon carbide layer, a gallium nitride layer, or the like.
[0011] The semiconductor layer 100 includes an n-type first semiconductor layer 10 provided on a first electrode 41, an n-type second semiconductor layer 20 provided on the first semiconductor layer 10, and an n-type third semiconductor layer 30 provided on the second semiconductor layer 20. The n-type impurity concentration of the first semiconductor layer 10 is higher than the n-type impurity concentration of the second semiconductor layer 20. The first semiconductor layer 10 is electrically connected to the first electrode 41 and functions as a drain layer in the MOSFET. The n-type impurity concentration of the second semiconductor layer 20 is lower than the n-type impurity concentration of the first semiconductor layer 10 and the n-type impurity concentration of the third semiconductor layer 30. The second semiconductor layer 20 functions as a drift layer in the MOSFET. The n-type impurity concentration of the third semiconductor layer 30 is higher than the n-type impurity concentration of the second semiconductor layer 20. The third semiconductor layer 30 is electrically connected to a second electrode 42 and functions as a source layer in the MOSFET. In the semiconductor layer 100, no p-type base layer is provided between the second semiconductor layer 20 (drift layer) and the third semiconductor layer 30 (source layer). The semiconductor device 1 has a Schottky MOSFET structure. Hereinafter, unless otherwise specified, the magnitude relationship of impurity concentrations can be interpreted as the magnitude relationship of carrier concentrations.
[0012] The semiconductor layer 100 has a root portion extending in the first direction X and the third direction Y, and a plurality of mesa portions 100A spaced apart from each other in the first direction X. The mesa portion 100A is located on the upper surface of the semiconductor layer 100 where the second electrode 42 is located. The root portion is located between the first electrode 41 and the gate electrode 50 in the second direction Z. The mesa portion 100A includes a part of the second semiconductor layer 20 and the third semiconductor layer 30.
[0013] The semiconductor device 1 includes a gate electrode 50 located between adjacent mesa portions 100A in the first direction X. The semiconductor device 1 includes, for example, a plurality of gate electrodes 50. The mesa portions 100A and the gate electrodes 50 are arranged alternately in the first direction X. The mesa portions 100A and the gate electrodes 50 extend in the third direction Y. The gate electrodes 50 can be made of, for example, polycrystalline silicon.
[0014] The mesa portion 100A has a recess 100B that opens to the upper surface side. The recess 100B extends in the second direction Z from the upper surface of the mesa portion 100A. The recess 100B also extends in the third direction Y. One mesa portion 100A has two sidewall portions 100C separated in the first direction X by the recess 100B. The recess 100B is located between the two sidewall portions 100C that are located apart from each other in the first direction X. The bottom of the recess 100B is located between two adjacent gate electrodes 50 in the first direction X.
[0015] The sidewall portion 100C has a channel portion 21 and a contact portion 31. The channel portion 21 is included in the second semiconductor layer 20. The channel portion 21 is located between the recess 100B and the gate electrode 50 in the first direction X. The contact portion 31 is provided on the channel portion 21 and is included in the third semiconductor layer 30. The n-type impurity concentration of the contact portion 31 is higher than the n-type impurity concentration of the channel portion 21. The n-type carrier concentration of the contact portion 31 is higher than the n-type carrier concentration of the channel portion 21. For example, the p-type impurity concentration of the contact portion 31 is lower than the p-type impurity concentration of the channel portion 21. In this case, the n-type impurity concentration of the contact portion 31 and the n-type impurity concentration of the channel portion 21 may be the same, for example.
[0016] The channel portion 21 has a first side surface 21A facing the side surface of the gate electrode 50 in the first direction X, and a second side surface 21B located on the opposite side of the first side surface 21A in the first direction X.
[0017] The semiconductor device 1 includes an insulating film 70 located in the recess 100B. The insulating film 70 is provided on the second side surface 21B of the channel portion 21. The insulating film 70 is a single-layer film, such as a silicon oxide film. Alternatively, a silicon nitride film may be used as the insulating film 70.
[0018] The semiconductor device 1 includes a gate insulating film 81 provided between the first side surface 21A of the channel portion 21 and a side surface of the gate electrode 50. The semiconductor device 1 also includes a first interlayer insulating film 82 provided between the gate electrode 50 and the second electrode 42. The gate insulating film 81 and the first interlayer insulating film 82 may be, for example, a silicon oxide film.
[0019] The second electrode 42 has a base portion extending in the first direction X and the third direction Y, and multiple protrusions spaced apart from each other in the first direction X. The protrusions are located between the base portion of the second electrode 42 and the first electrode 41 in the second direction Z. In this example, one protrusion contacts one mesa portion 100A. The second electrode 42 is located in the recess 100B. The second electrode 42 is also located on the contact portion 31 and the first interlayer insulating film 82. The second electrode 42 contacts the upper surface of the contact portion 31. The contact portion 31 is located in the recess 100B and has an inner side surface 31B that is continuous with the second side surface 21B of the channel portion 21. At least a portion of the inner side surface 31B of the contact portion 31 is exposed from the insulating film 70, and the second electrode 42 contacts the inner side surface 31B of the contact portion 31. The second electrode 42 is electrically connected to the contact portion 31 on the upper surface and inner side surface 31B of the contact portion 31. The second electrode 42 covers the insulating film 70 in the recess 100B and is in contact with the insulating film 70. Note that, although the second electrode 42 and the contact portion 31 shown in FIG. 1 face each other and are in contact with each other in the first direction X and the second direction Z, they may be configured to face each other and be in contact with each other in the first direction X but not in contact with each other in the second direction Z.
[0020] In the first direction X, the insulating film 70 is located between the second electrode 42 and the channel portion 21 in the recess 100B, the channel portion 21 is located between the insulating film 70 and the gate insulating film 81, and the gate insulating film 81 is located between the channel portion 21 and the gate electrode 50. The channel portion 21 is in contact with the insulating film 70 and the gate insulating film 81. In the first direction X, only one channel portion 21 is located between adjacent gate electrodes 50 and protruding portions of the second electrode 42. Exactly one gate electrode 50 or exactly one protruding portion of the second electrode 42 is located between two adjacent channel portions 21 in the first direction X. The contact portion 31 is located between the channel portion 21 and the second electrode 42 in the second direction Z. In this example, two channel portions 21 are provided in one mesa portion 100A.
[0021] For example, a positive potential (e.g., 20 V or more and 50 V or less) is applied to the first electrode 41, and a ground potential is applied to the second electrode 42. In this state, when the potential of the gate electrode 50 is lower than the threshold voltage, the channel portion 21 is depleted by a depletion layer extending from the interface between the second side surface 21B of the channel portion 21 and the insulating film 70, and the semiconductor device 1 is in an off state. When the potential of the gate electrode 50 becomes equal to or higher than the threshold voltage, the depletion layer in the channel portion 21 disappears or narrows, and the semiconductor device 1 is in an on state. In the on state, a current flows from the first electrode 41 to the second electrode 42 via the first semiconductor layer 10, the channel portion 21 of the second semiconductor layer 20, and the contact portion 31 (third semiconductor layer 30).
[0022] Depletion of the channel portion 21 provides a high breakdown voltage in the off state. To facilitate depletion of the channel portion 21, it is preferable that the width of the channel portion 21 in the first direction X is small. In this embodiment, the width of the channel portion 21 in the first direction X is smaller than the width of the recess 100B in the first direction X. The width of the channel portion 21 in the first direction X is, for example, 20 nm or more and 80 nm or less. The threshold voltage of the semiconductor device 1 also depends on the width of the channel portion 21 in the first direction X. The width of the channel portion 21 in the first direction X is very thin, and from the standpoint of process difficulty, it is difficult to adjust the breakdown voltage and threshold voltage of the semiconductor device 1 by adjusting the width of the channel portion 21 in the first direction X.
[0023] The breakdown voltage and threshold voltage of the semiconductor device 1 also depend on the barrier height between the metal of the second electrode 42 and the semiconductor layer 100. By using a metal with a high work function, such as Pt, Ni, or Co, as the second electrode 42, the barrier height between the second electrode 42 and the semiconductor layer 100 can be increased, and the breakdown voltage can be increased.
[0024] In the comparative example in which the second electrode 42 and the second side surface 21B of the channel portion 21 are in direct contact, there is a problem in that the barrier height derived from the work function of the metal of the second electrode 42 cannot be obtained due to the influence of Fermi level pinning. For example, when Pt is used as the metal of the second electrode 42 and Si is used as the semiconductor layer 100, the ideal barrier height is calculated as 5.6 eV (work function of Pt) - 4.05 eV (electron affinity of Si) - 0.05 eV (mirror effect) = 1.5 eV. However, in the actual sample, the barrier height was 0.8 eV to 0.85 eV. This can reduce the design margin.
[0025] According to this embodiment, by providing the insulating film 70 between the second side surface 21B of the channel portion 21 and the second electrode 42, it is possible to reduce the influence of Fermi level pinning and realize a barrier height that reflects the work function of the metal of the second electrode 42. This increases the options for the metal of the second electrode 42, and enables the design margin of the semiconductor device 1 to be expanded.
[0026] An electric field tends to concentrate at the corners on the bottom side of the recess 100 B. By providing the insulating film 70 at the corners, leakage current generated at the corners during OFF can be suppressed.
[0027] A simulation was performed to determine whether the insulating film 70 provided on the second side surface 21B of the channel portion 21 affects the current-voltage characteristics (IV characteristics) of the semiconductor device 1. The calculations were performed assuming that the material of the channel portion 21 was Si, the insulating film 70 was a silicon oxide film (SiO2 film), the work function of the metal of the second electrode 42 was 5.3 eV, and the barrier height between the second electrode 42 and Si was 1.2 eV. The IV characteristics were calculated by fixing the thickness (thickness in the first direction X) of the insulating film 70 to 10 nm and varying the height (thickness in the second direction Z) of the insulating film 70 from the bottom of the recess 100B to 100 nm, 200 nm, and 280 nm. The height of the insulating film 70 was also fixed to 100 nm, and the thickness of the insulating film 70 was varied to 10 nm, 50 nm, and 100 nm. The IV characteristics were substantially the same for all of the calculated thicknesses and heights, confirming that the insulating film 70 does not affect the breakdown voltage of the semiconductor device 1.
[0028] The thickness of the insulating film 70 can be set to, for example, 1 nm or more and 10 nm or less.
[0029] The semiconductor device 1 can be used as a switching element in applications such as inverters and motor drives. In this case, the semiconductor device 1 is required to function as a freewheeling diode that passes a reverse current generated during switching. Therefore, it is preferable that the insulating film 70 is not provided at the bottom of the recess 100B, and the second electrode 42 contacts the second semiconductor layer 20 at the bottom of the recess 100B. This ensures a current path (a current path that does not pass through the channel portion) when the semiconductor device operates as a freewheeling diode.
[0030] The semiconductor device 1 may further include a field plate electrode 60 located below the gate electrode 50 between adjacent mesa portions 100A in the first direction X. The field plate electrode 60 may be made of, for example, polycrystalline silicon. A second interlayer insulating film 83 is provided between the gate electrode 50 and the field plate electrode 60 and between the field plate electrode 60 and the second semiconductor layer 20. The second interlayer insulating film 83 may be made of, for example, a silicon oxide film.
[0031] The same potential as that of the second electrode 42 is applied to the field plate electrode 60. This can reduce the electric field (vertical electric field) applied in the second direction Z in the second semiconductor layer 20, improving the breakdown voltage. The field plate electrode 60 can be applied with a potential lower than that of the first electrode 41, rather than being limited to the same potential as that of the second electrode 42.
[0032] In another embodiment of the semiconductor device 2 shown in FIG. 2 , the second electrode 42 includes a first metal portion 42A facing the second side surface 21B of the channel portion 21 via the insulating film 70, and a second metal portion 42B in contact with the inner side surface 31B of the contact portion 31. The protruding portion of the second electrode 42 includes the first metal portion 42A and the second metal portion 42B. The work function of the first metal portion 42A is higher than the work function of the second metal portion 42B. This increases the barrier height between the first metal portion 42A and the semiconductor layer 100 while reducing the contact resistance between the second metal portion 42B and the contact portion 31. For example, the first metal portion 42A mainly contains at least one selected from Pt, Ni, and Co, and the second metal portion 42B mainly contains Ti.
[0033] An example of a method for forming the insulating film 70 will be described with reference to FIGS. 3(a) to 4(b).
[0034] By forming the recess 100B on the upper surface side of the mesa portion 100A, a sidewall portion 100C is formed on the upper surface side of the mesa portion 100A. The recess 100B can be formed by, for example, RIE (Reactive Ion Etching) method.
[0035] After forming the recess 100B, as shown in Fig. 3(a), an inhibitor film 91 is formed on the side surface of the recess 100B (the inner surface of the side wall portion 100C). The inhibitor film 91 is formed on the side surface on the opening side of the recess 100B. For example, a resist film can be used as the inhibitor film 91.
[0036] After forming the inhibitor film 91, as shown in Fig. 3(b), an insulating film 70 is formed on the side and bottom surfaces of the recess 100B where the inhibitor film 91 is not formed. As the insulating film 70, for example, a silicon oxide film can be formed by an ALD (Atomic Layer Deposition) method.
[0037] After the insulating film 70 is formed, the inhibitor film 91 is removed. As a result, the side surface of the opening of the recess 100B is exposed as shown in Fig. 4(a). The inhibitor film 91 can be removed by, for example, purging or etching.
[0038] After removing the inhibitor film 91, the insulating film 70 is etched by RIE. As a result, as shown in FIG. 4(b), the insulating film 70 formed on the bottom surface of the recess 100B is removed, exposing the bottom surface of the recess 100B. The portion of the sidewall 100C adjacent to the insulating film 70 becomes a channel portion. Furthermore, a contact portion having a higher n-type impurity concentration than the channel portion is formed on the upper portion of the sidewall 100C by, for example, ion implantation. The contact portion contacts a second electrode formed in the recess 100B on the upper portion of the side surface of the recess 100B where the insulating film 70 is not formed. For example, Pt can be formed as the second electrode in the recess 100B by sputtering.
[0039] Another example of the method for forming the insulating film 70 will be described with reference to FIGS. 5(a) to 7(b).
[0040] After forming the recess 100B in the mesa portion 100A, as shown in Fig. 5(a), a precursor 92 is formed continuously on the upper surface of the sidewall portion 100C and the side and bottom surfaces of the recess 100B. As the precursor 92, for example, a TDMAS (trisdimethylsilane) precursor can be formed by the ALD method.
[0041] After the precursor 92 is formed, a portion of the precursor 92 is removed, as shown in FIG. 5(b). The precursor 92 on the upper surface of the sidewall 100C and the precursor 92 on the side surface of the opening of the recess 100B are removed. The precursor 92 on the side surface of the bottom of the recess 100B and the precursor 92 on the bottom remain. For example, a reduced pressure atmosphere or O2 plasma gas can be used to remove a portion of the precursor 92.
[0042] After removing a portion of the precursor 92, for example, O plasma or O gas is supplied to convert the remaining precursor 92 into SiO. As a result, an SiO film 71 is formed on the side and bottom surfaces of the bottom side of the recess 100B, as shown in FIG. 6(a).
[0043] After the precursor 92 is converted into SiO2, a precursor 93 is again formed on the upper surface of the sidewall portion 100C and the side and bottom surfaces of the recess 100B. As shown in Figure 6(b), the precursor 93 covers the SiO2 film 71 formed in the previous step.
[0044] After the precursor 93 is formed, a portion of the precursor 93 is removed as shown in Fig. 7(a). The precursor 93 on the upper surface of the sidewall 100C and the precursor 93 on the side surface of the opening of the recess 100B are removed. The precursor 93 stacked on the SiO2 film 71 remains.
[0045] After removing a portion of the precursor 93, the remaining precursor 93 is converted to SiO2. As a result, as shown in FIG. 7(b), an SiO2 film 72 is formed on the side surfaces and bottom surface of the bottom surface of the recess 100B. The SiO2 film 72 is a film formed by converting the precursor 92 to SiO2 and a film of the precursor 93 to SiO2. Thereafter, the steps of forming the precursor again, removing a portion of the precursor, and converting the precursor to SiO2 are repeated until the SiO2 film formed on the side surfaces and bottom surface of the bottom surface of the recess 100B has a desired thickness.
[0046] Thereafter, the SiO2 film is etched by RIE to remove the SiO2 film formed on the bottom surface of the recess 100B, thereby forming an insulating film 70 of a desired thickness on the side surface of the bottom surface of the recess 100B.
[0047] The insulating film 70 is a single layer film. The manufacturing process for the single layer insulating film 70 is simple. The single layer insulating film 70 has no variation in thickness, is less affected by the crystal quality at the interface of the stacked films, and has stable quality.
[0048] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]
[0049] REFERENCE SIGNS LIST 1, 2... semiconductor device, 10... first semiconductor layer, 20... second semiconductor layer, 21... channel portion, 21A... first side surface, 21B... second side surface, 30... third semiconductor layer, 31... contact portion, 31B... inner surface, 41... first electrode, 42... second electrode, 42A... first metal portion, 42B... second metal portion, 50... gate electrode, 60... field plate electrode, 70... insulating film, 81... gate insulating film, 82... first interlayer insulating film, 83... second interlayer insulating film, 100... semiconductor layer, 100A... mesa portion, 100B... recess, 100C... side wall portion
Claims
1. A first electrode; a semiconductor layer of a first conductivity type provided on the first electrode, the semiconductor layer having a plurality of mesa portions spaced apart from each other in a first direction; a second electrode located in a recess extending from an upper surface of the mesa portion in a second direction perpendicular to the first direction; a gate electrode located between adjacent mesa portions in the first direction among the plurality of mesa portions; a single-layer insulating film located in the recess; Equipped with the mesa portion has a channel portion located between the recess and the gate electrode in the first direction, and a contact portion provided on the channel portion and having a first conductivity type impurity concentration higher than that of the channel portion; the channel portion has a first side surface facing the gate electrode in the first direction and a second side surface located on the opposite side of the first side surface in the first direction; the insulating film is provided on the second side surface, The second electrode is in contact with the contact portion and the insulating film in the recess.
2. The semiconductor device according to claim 1 , wherein the second electrode is in contact with the semiconductor layer at the bottom of the recess.
3. the second electrode has a first metal portion facing the channel portion via the insulating film and a second metal portion in contact with the contact portion; The semiconductor device according to claim 1 , wherein the first metal portion has a work function higher than a work function of the second metal portion.
4. the first metal portion includes Pt, Ni, or Co; The semiconductor device according to claim 3 , wherein the second metal portion contains Ti.
5. The semiconductor device according to claim 1 , wherein the width of said channel portion in said first direction is smaller than the width of said recess in said first direction.
6. The semiconductor layer is a first semiconductor layer provided on the first electrode; a second semiconductor layer provided on the first semiconductor layer, having a first conductivity type impurity concentration lower than that of the first semiconductor layer, and including the channel portion; a third semiconductor layer provided on the second semiconductor layer, having a first conductivity type impurity concentration higher than that of the second semiconductor layer, and including the contact portion; The semiconductor device according to claim 1 , further comprising:
7. 3. The semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film.
8. 3. The semiconductor device according to claim 1, wherein the insulating film has a thickness of 1 nm or more and 10 nm or less.
9. 3. The semiconductor device according to claim 1, further comprising a field plate electrode located below said gate electrode between said mesa portions adjacent to each other in said first direction.
10. 10. The semiconductor device according to claim 9, wherein the same potential as that of the second electrode is applied to the field plate electrode.
11. A first electrode; a semiconductor layer of a first conductivity type provided on the first electrode, the semiconductor layer having a plurality of mesa portions spaced apart from each other in a first direction; a second electrode located in a recess extending from an upper surface of the mesa portion in a second direction perpendicular to the first direction; a gate electrode located between adjacent mesa portions in the first direction among the plurality of mesa portions; a single-layer insulating film located in the recess; Equipped with the mesa portion has a channel portion located between the recess and the gate electrode in the first direction, and a contact portion provided on the channel portion and having a second conductivity type carrier concentration lower than that of the channel portion, the channel portion has a first side surface facing the gate electrode in the first direction and a second side surface located on the opposite side of the first side surface in the first direction; the insulating film is provided on the second side surface, The second electrode is in contact with the contact portion and the insulating film in the recess.
12. A first electrode; a semiconductor layer of a first conductivity type provided on the first electrode, the semiconductor layer having a plurality of mesa portions spaced apart from each other in a first direction; a second electrode located in a recess extending from an upper surface of the mesa portion in a second direction perpendicular to the first direction; a gate electrode located between adjacent mesa portions in the first direction among the plurality of mesa portions; a single-layer insulating film located in the recess; Equipped with the mesa portion has a channel portion located between the recess and the gate electrode in the first direction, and a contact portion provided on the channel portion and having a first conductivity type carrier concentration higher than that of the channel portion, the channel portion has a first side surface facing the gate electrode in the first direction and a second side surface located on the opposite side of the first side surface in the first direction; the insulating film is provided on the second side surface, The second electrode is in contact with the contact portion and the insulating film in the recess.