Semiconductor device

Abstract

To provide a semiconductor device that can reduce on-state voltage and turn-off switching loss.SOLUTION: A first surface side region of a semiconductor part includes a second semiconductor layer that faces a first gate electrode through a first insulating film, and a third semiconductor layer in contact with a first electrode. A second surface side region of the semiconductor part includes a fourth semiconductor layer facing a second gate electrode through a second insulating film, a fifth semiconductor layer of a second conductivity type in contact with a second electrode, a sixth semiconductor layer of a first conductivity type in contact with the second electrode, and a seventh semiconductor layer of the second conductivity type whose second conductivity type impurity concentration is lower than that of the fourth semiconductor layer and the fifth semiconductor layer and which is in contact with the second electrode. In a second direction X, the seventh semiconductor layer exists between the second gate electrodes.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] An IGBT (Insulated Gate Bipolar Transistor) with a double-sided gate structure in which gate electrodes are provided on both the front and back sides of a semiconductor layer has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-49610 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of an embodiment of the present invention is to provide a semiconductor device capable of reducing turn-off switching loss. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes: a first electrode, a second electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion having a first semiconductor layer of a first conductivity type, a first-side region located between the first electrode and the first semiconductor layer in the first direction, and a second-side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes facing the first-side region, a plurality of first insulating films provided between the first-side region and the plurality of first gate electrodes, a plurality of second gate electrodes facing the second-side region in the first direction, and a plurality of second insulating films provided between the second-side region and the plurality of second gate electrodes. The first-side region includes a second semiconductor layer of a second conductivity type facing the first gate electrode via the first insulating film, and a third semiconductor layer of a first conductivity type in contact with the first electrode, the third semiconductor layer having a higher first-conductivity-type impurity concentration than the first semiconductor layer. The second-surface side region includes a fourth semiconductor layer of a second conductivity type facing the second gate electrode via the second insulating film, a fifth semiconductor layer of the second conductivity type having a higher second conductivity type impurity concentration than the second semiconductor layer and the fourth semiconductor layer and in contact with the second electrode, a sixth semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the second electrode, and a seventh semiconductor layer of the second conductivity type having a lower second conductivity type impurity concentration than the fourth semiconductor layer and the fifth semiconductor layer and in contact with the second electrode. In a second direction perpendicular to the first direction, the seventh semiconductor layer is located between the second gate electrodes. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 2 is a schematic plan view of the second surface side of the semiconductor device of the first embodiment. FIG. [Figure 3] 2 is a schematic plan view of the second surface side of the semiconductor device of the first embodiment. FIG. [Figure 4] 2 is a schematic plan view of the second surface side of the semiconductor device of the first embodiment. FIG. [Figure 5]2 is a schematic plan view of the second surface side of the semiconductor device of the first embodiment. FIG. [Figure 6] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a modified example of the second embodiment. [Figure 9] 10 is a graph showing a simulation result. DETAILED DESCRIPTION OF THE INVENTION

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. Furthermore, identical or similar elements are given the same reference numerals.

[0008] [First embodiment] 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 includes a first electrode 51, a second electrode 52, a semiconductor portion 10, a plurality of first gate electrodes 61, a plurality of first insulating films 71, a plurality of second gate electrodes 62, and a plurality of second insulating films 72. The semiconductor device 1 is an IGBT, with the first electrode 51 serving as an emitter electrode and the second electrode 52 serving as a collector electrode.

[0009] The semiconductor portion 10 is located between the first electrode 51 and the second electrode 52 in the first direction Z. Two directions perpendicular to the first direction Z are defined as the second direction X and the third direction Y. The second direction X and the third direction Y are perpendicular to each other.

[0010] The material of the semiconductor portion 10 is, for example, silicon. Alternatively, the material of the semiconductor portion 10 may be silicon carbide, gallium nitride, or the like. In this specification, the first conductivity type of the semiconductor portion 10 is described as n-type, and the second conductivity type is described as p-type. However, the first conductivity type may also be p-type, and the second conductivity type may also be n-type.

[0011] The semiconductor part 10 has a first surface 10A and a second surface 10B located on the opposite side of the first surface 10A in the first direction Z. The first electrode 51 faces the first surface 10A in the first direction Z, and the second electrode 52 faces the second surface 10B in the first direction Z.

[0012] The semiconductor unit 10 has an n-type first semiconductor layer 21, a first surface side region 11 located between the first electrode 51 and the first semiconductor layer 21 in the first direction Z, and a second surface side region 12 located between the second electrode 52 and the first semiconductor layer 21 in the first direction Z. The first semiconductor layer 21 is a drift layer in the IGBT. The first surface side region 11 includes a first surface 10A of the semiconductor unit 10 and a portion between the first surface 10A and the first semiconductor layer 21. The second surface side region 12 includes a second surface 10B of the semiconductor unit 10 and a portion between the second surface 10B and the first semiconductor layer 21.

[0013] The first gate electrode 61 faces the first-surface side region 11 of the semiconductor portion 10 via a first insulating film 71. The first insulating film 71 is provided between the first-surface side region 11 and the first gate electrode 61, and between the first semiconductor layer 21 and the first gate electrode 61. The first gate electrode 61 is provided in a trench extending from the first surface 10A in the first direction Z and penetrating the first-surface side region 11, with the first insulating film 71 interposed therebetween. A plurality of first gate electrodes 61, each extending in the third direction Y, are aligned in the second direction X. An insulating layer 73 is provided between the first gate electrode 61 and the first electrode 51 in the first direction Z, and the first gate electrode 61 is not in contact with the first electrode 51.

[0014] The first surface side region 11 has a p-type second semiconductor layer 22 and an n-type third semiconductor layer 23. The second semiconductor layer 22 is a base layer of the IGBT. The third semiconductor layer 23 is an emitter layer of the IGBT.

[0015] The second semiconductor layer 22 is located on the first semiconductor layer 21 in the first direction Z and is in contact with the first semiconductor layer 21. The second semiconductor layer 22 is located between the first gate electrodes 61 adjacent to each other in the second direction X. A side surface of the second semiconductor layer 22 faces the first gate electrode 61 via the first insulating film 71. In other words, the first gate electrode 61 faces the second semiconductor layer 22 via the first insulating film 71 in the second direction X. The second semiconductor layer 22 is in contact with the first insulating film 71.

[0016] The n-type impurity concentration of the third semiconductor layer 23 is higher than the n-type impurity concentration of the first semiconductor layer 21. The third semiconductor layer 23 is located on the second semiconductor layer 22 in the first direction Z and is in contact with the second semiconductor layer 22. The third semiconductor layer 23 is in contact with the first electrode 51 and is electrically connected to the first electrode 51. Two third semiconductor layers 23 are provided between first gate electrodes 61 adjacent to each other in the second direction X and spaced apart from each other in the second direction X. A portion 22A of the second semiconductor layer 22 is located between the two third semiconductor layers 23 and is in contact with the first electrode 51. The p-type impurity concentration of the portion 22A of the second semiconductor layer 22 is higher than the p-type impurity concentration of the second semiconductor layer 22 other than the portion 22A. The third semiconductor layer 23 is in contact with the first insulating film 71.

[0017] The first-surface side region 11 may further include a p-type ninth semiconductor layer 29. The ninth semiconductor layer 29 is located between adjacent first gate electrodes 61 in the second direction X. The depth of the ninth semiconductor layer 29 from the first surface 10A is deeper than the depth of the second semiconductor layer 22 from the first surface 10A. An insulating layer 73 is provided between the ninth semiconductor layer 29 and the first electrode 51 in the first direction Z, and the ninth semiconductor layer 29 is not in contact with the first electrode 51. The third semiconductor layer 23 is not disposed on the ninth semiconductor layer 29. Of both side surfaces of the first gate electrode 61 in the second direction X, one side surface is adjacent to the third semiconductor layer 23 and the second semiconductor layer 22 via the first insulating film 71, and the other side surface is adjacent to the ninth semiconductor layer 29 via the first insulating film 71.

[0018] The second gate electrode 62 has a planar gate structure and faces the second-surface side region 12 in the first direction Z. The second insulating film 72 is provided between the second-surface side region 12 and the second gate electrode 62. The second gate electrode 62 is located within the second electrode 52, and the second insulating film 72 is provided between the second gate electrode 62 and the second electrode 52. The second insulating film 72 surrounds the upper surface, lower surface, and side surfaces of the second gate electrode 62. The second gate electrode 62 is not in contact with the second electrode 52.

[0019] The second surface side region 12 has a fourth semiconductor layer 24 of p-type, a fifth semiconductor layer 25 of p-type, a sixth semiconductor layer 26 of n-type, and a seventh semiconductor layer 27 of p-type.

[0020] The fourth semiconductor layer 24 has a first portion 24A that faces the second gate electrode 62 in the first direction Z, with the second insulating film 72 interposed therebetween. The first portion 24A functions as a channel portion, as will be described later. The fourth semiconductor layer 24 is in contact with the second insulating film 72, the fifth semiconductor layer 25, the sixth semiconductor layer 26, the seventh semiconductor layer 27, and the eighth semiconductor layer 28.

[0021] The p-type impurity concentration of the fifth semiconductor layer 25 is higher than the p-type impurity concentration of the second semiconductor layer 22 and the p-type impurity concentration of the fourth semiconductor layer 24. The fifth semiconductor layer 25 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. The fifth semiconductor layer 25 is a collector layer in the IGBT. The fifth semiconductor layer 25 is located between the second electrode 52 and the fourth semiconductor layer 24 in the first direction Z. The fifth semiconductor layer 25 is in contact with the fourth semiconductor layer 24, the sixth semiconductor layer 26, and the seventh semiconductor layer 27.

[0022] The n-type impurity concentration of the sixth semiconductor layer 26 is higher than the n-type impurity concentration of the first semiconductor layer 21. The sixth semiconductor layer 26 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. The sixth semiconductor layer 26 is located between the second electrode 52 and the fourth semiconductor layer 24 in the first direction Z. The sixth semiconductor layer 26 is in contact with the second insulating film 72, the fourth semiconductor layer 24, and the fifth semiconductor layer 25.

[0023] The p-type impurity concentration of the seventh semiconductor layer 27 is lower than the p-type impurity concentration of the fourth semiconductor layer 24 and the p-type impurity concentration of the fifth semiconductor layer 25. The seventh semiconductor layer 27 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. The seventh semiconductor layer 27 is located between the second electrode 52 and an eighth semiconductor layer 28, which will be described later, in the first direction Z. The seventh semiconductor layer 27 is in contact with the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the eighth semiconductor layer 28. In the plane formed by the second direction X and the third direction Y, the fifth semiconductor layer 25 is located between the adjacent seventh semiconductor layer 27 and the first portion 24A of the adjacent fourth semiconductor layer 24. In comparison with the fifth semiconductor layer 25 and the seventh semiconductor layer 27 that are in contact with the same fourth semiconductor layer 24, the distance between the fifth semiconductor layer 25 and the second gate electrode 62 in the plane formed by the second direction X and the third direction Y is smaller than the distance between the seventh semiconductor layer 27 and the second gate electrode 62. The seventh semiconductor layer 27 is located between two adjacent second gate electrodes 62 in the plane formed by the second direction X and the third direction Y. The seventh semiconductor layer 27 does not overlap the second gate electrode 62 in the first direction Z.

[0024] For example, the configuration shown in the cross section of FIG. 1 is repeated in the second direction X. The first surface side region 11 and the second surface side region 12 are arranged independently of each other. For example, the shape and arrangement interval of the first gate electrodes 61 and the shape and arrangement interval of the second gate electrodes 62 are configured independently of each other. Note that FIGS. 2 to 5, which will be described later, can be rotated at any angle within the plane formed by the second direction X and the third direction Y. The expressions of the second direction X and the third direction Y relating to the second surface side region 12 and the second gate electrode 62 can be replaced with arbitrary fourth and fifth directions, which are orthogonal to each other within the plane formed by the second direction X and the third direction Y, respectively. The fourth and fifth directions are not shown.

[0025] 2 is a schematic plan view showing an example of the arrangement of each layer of the second-surface side region 12 of the semiconductor device 1 and the second gate electrodes 62. A plurality of second gate electrodes 62 are aligned in the second direction X. FIG. 2 shows each layer of the second-surface side region 12 between two second gate electrodes 62 adjacent to each other in the second direction X.

[0026] For example, the first portion 24A (channel portion) of the fourth semiconductor layer 24, the fifth semiconductor layer 25, the sixth semiconductor layer 26, and the seventh semiconductor layer 28 extend in the third direction Y.

[0027] In the second direction X, the first portion 24A (channel portion) is adjacent to the sixth semiconductor layer 26. In the second direction X, the seventh semiconductor layer 27 is located between the multiple second gate electrodes 62. In the second direction X, the seventh semiconductor layer 27 is located farther from the second gate electrode 62 than the first portion 24A (channel portion). In the second direction X, the sixth semiconductor layer 26 is located between the first portion 24A (channel portion) and the fifth semiconductor layer 25. In the second direction X, the fifth semiconductor layer 25 is located between the sixth semiconductor layer 26 and the seventh semiconductor layer 27.

[0028] As shown in FIG. 1 , the second-surface side region 12 may further include an eighth semiconductor layer 28. The eighth semiconductor layer 28 is located between the first semiconductor layer 21 and the fourth semiconductor layer 24 and between the first semiconductor layer 21 and the seventh semiconductor layer 27 in the first direction Z. The eighth semiconductor layer 28 is in contact with the fourth semiconductor layer 24 and the seventh semiconductor layer 27. The n-type impurity concentration of the eighth semiconductor layer 28 is higher than the n-type impurity concentration of the first semiconductor layer 21. The eighth semiconductor layer 28 is a buffer layer in the IGBT. By providing the eighth semiconductor layer 28, the extension of the depletion layer can be stopped at the eighth semiconductor layer 28 when the semiconductor device 1 is in the off state, and the thickness of the first semiconductor layer 21 (thickness in the first direction Z) can be made thinner than when the eighth semiconductor layer 28 is not provided.

[0029] The portion 28A of the eighth semiconductor layer 28 penetrates the fourth semiconductor layer 24 in the first direction Z and is adjacent to the first portion 24A (channel portion) of the fourth semiconductor layer 24 in the first direction X.

[0030] With a positive voltage applied to the second electrode 52 and the first electrode 51 at ground potential, applying a gate voltage higher than the first threshold voltage to the first gate electrode 61 forms a first channel (inversion layer) in a portion of the second semiconductor layer 22 facing the first gate electrode 61, and the semiconductor device 1 enters an on-state. In the on-state, an electron current flows between the first electrode 51 and the second electrode 52 through the third semiconductor layer 23 (emitter layer), the first channel, the first semiconductor layer 21 (drift layer), and the fifth semiconductor layer 25 (collector layer). In the on-state, holes are supplied from the fifth semiconductor layer 25 and the seventh semiconductor layer 27 to the first semiconductor layer 21, creating a high density state of electrons and holes in the first semiconductor layer 21, resulting in a low on-resistance. The seventh semiconductor layer 27 also functions as a collector layer, but since the p-type impurity concentration of the seventh semiconductor layer 27 is lower than the p-type impurity concentration of the fifth semiconductor layer 25, the seventh semiconductor layer 27 functions as a low injection region in which the injection of holes is reduced more than that of the fifth semiconductor layer 25.

[0031] The semiconductor device 1 is turned off by applying a gate voltage lower than the threshold voltage to the first gate electrode 61. At the timing of turn-off when the gate voltage of the first gate electrode 61 is made lower than the first threshold voltage, the gate voltage of the second gate electrode 62 is turned on to a voltage higher than the second threshold voltage. Just before, just after, or simultaneously with the turn-off of the gate voltage of the first gate electrode 61, the gate voltage of the second gate electrode 62 is turned on.

[0032] When the gate voltage of the second gate electrode 62 is turned on, a second channel (inversion layer) is formed in the first portion 24A of the fourth semiconductor layer 24, and electrons in the first semiconductor layer 21 are discharged to the second electrode 52 via the portion 28A of the eighth semiconductor layer 28, the second channel, and the sixth semiconductor layer 26. The electrons in the first semiconductor layer 21 are discharged to the second electrode 52 via a path that does not pass through the p-type semiconductor layer. This suppresses injection of holes into the first semiconductor layer 21, and reduces turn-off switching loss of the semiconductor device 1. The gate voltage of the second gate electrode 62 is turned off before the gate voltage of the first gate electrode 61 is turned on.

[0033] In the first semiconductor layer 21, electrons in a region that is relatively far from the second gate electrode 62 are less likely to be discharged to the second electrode 52 through the above-mentioned path. According to the present embodiment, the seventh semiconductor layer 27 is provided as the above-mentioned low hole injection region at a position farther from the second gate electrode 62 in the second direction X than the first portion 24A (channel portion). This reduces the amount of holes injected into the region far from the second gate electrode 62 in the first semiconductor layer 21, and can improve the effect of reducing turn-off switching loss of the semiconductor device 1 by turning on the second gate electrode 62.

[0034] 9 shows the results of simulating the relationship between turn-off switching loss Eoff and on-voltage Vce (collector-emitter voltage). The results are for model a, which simulates the semiconductor device 1 of the first embodiment, and for comparative example b. Comparative example b differs from model a of the embodiment in that it does not include the seventh semiconductor layer 27.

[0035] In an IGBT, there is a trade-off between reducing the turn-off switching loss Eoff and reducing the on-voltage Vce. The simulation results in Fig. 9 show that, according to this embodiment, the trade-off between Eoff and Vce can be improved compared to the comparative example by improving the effect of reducing the turn-off switching loss Eoff.

[0036] In order to suppress the operation of a parasitic element (npn transistor) including the eighth semiconductor layer 28 (or the first semiconductor layer 21), the fourth semiconductor layer 24, and the sixth semiconductor layer 26, there may be limitations on reducing the p-type impurity concentration of the fourth semiconductor layer 24. According to the first embodiment, the seventh semiconductor layer 27, which has a lower p-type impurity concentration than the fourth semiconductor layer 24, is provided as a low hole injection region in addition to the fourth semiconductor layer 24, which increases the degree of design freedom.

[0037] 3 to 5, a plurality of seventh semiconductor layers 27 may be arranged in the third direction Y between the second gate electrodes 62 adjacent to each other in the second direction X. The sixth semiconductor layer 26 is located between the seventh semiconductor layers 27 adjacent to each other in the third direction Y.

[0038] 3 and 4, the sixth semiconductor layer 26 is located between the first portion 24A (channel portion) of the fourth semiconductor layer 24 and the seventh semiconductor layer 27 in the second direction X. The fifth semiconductor layer 25 is located between the sixth semiconductor layer 26 and the seventh semiconductor layer 27 in the second direction X. In the example shown in FIG. 4, the fourth semiconductor layer 24 is further located between the sixth semiconductor layer 26 and the seventh semiconductor layer 27 that are adjacent to each other in the third direction Y.

[0039] 5, the fifth semiconductor layer 25 is located between the first portion 24A (channel portion) of the fourth semiconductor layer 24 and the seventh semiconductor layer 27 in the second direction X. The sixth semiconductor layer 26 is adjacent to the fifth semiconductor layer 25 and the seventh semiconductor layer 27 in the third direction Y. The sixth semiconductor layer 26 is located between the first portions 24A (channel portions) in the second direction X.

[0040] 6, a p-type tenth semiconductor layer 30 may be provided between the fourth semiconductor layer 24 and the eighth semiconductor layer 28. The p-type impurity concentration of the tenth semiconductor layer 30 is higher than the p-type impurity concentration of the fourth semiconductor layer 24 and lower than the p-type impurity concentration of the fifth semiconductor layer 25.

[0041] [Second embodiment] 7 is a schematic cross-sectional view of the semiconductor device 2 of the second embodiment. The following mainly describes the configuration of the semiconductor device 2 of the second embodiment that differs from the semiconductor device 1 of the first embodiment.

[0042] In the semiconductor device 2 of the second embodiment, the fourth semiconductor layer 24 has a first portion (channel portion) 24A facing the second gate electrode 62 in the first direction Z via the second insulating film 72, and a second portion 24B located between the second gate electrodes 62 in the second direction X and in contact with the second electrode 52. The second portion 24B is located between the second electrode 52 and the eighth semiconductor layer 28 in the first direction Z.

[0043] The p-type impurity concentration of the second portion 24B is lower than the p-type impurity concentration of the fifth semiconductor layer 25. The second portion 24B functions as a low injection region in which the injection of holes is reduced compared to the fifth semiconductor layer 25. Therefore, the amount of holes injected into a region of the first semiconductor layer 21 far from the second gate electrode 62 can be reduced, and the effect of reducing turn-off switching loss of the semiconductor device 2 by turning on the second gate electrode 62 can be improved.

[0044] The layout of the layers of the second surface side region 12 and the second gate electrode 62 of the semiconductor device 2 of the second embodiment can be such that the seventh semiconductor layer 27 is replaced with the second portion 24B in FIGS.

[0045] As a modification of the semiconductor device of the second embodiment, as shown in FIG. 8, a fifth semiconductor layer 25 may be provided partially in the second portion 24B.

[0046] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0047] 1-2...semiconductor device, 10...semiconductor portion, 11...first surface side region, 12...second surface side region, 21...first semiconductor layer, 22...second semiconductor layer, 23...third semiconductor layer, 24...fourth semiconductor layer, 24A...first portion, 24B...second portion, 25...fifth semiconductor layer, 26...sixth semiconductor layer, 27...seventh semiconductor layer, 28...eighth semiconductor layer, 29...ninth semiconductor layer, 30...tenth semiconductor layer, 51...first electrode, 52...second electrode, 61...first gate electrode, 62...second gate electrode, 71...first insulating film, 72...second insulating film, 73...insulating layer

Claims

1. A first electrode; A second electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion having a first semiconductor layer of a first conductivity type, a first surface side region located between the first electrode and the first semiconductor layer in the first direction, and a second surface side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes facing the first surface side region; a plurality of first insulating films provided between the first surface side region and the plurality of first gate electrodes; a plurality of second gate electrodes facing the second surface region in the first direction; a plurality of second insulating films provided between the second surface side region and the plurality of second gate electrodes; Equipped with The first surface side region is a second semiconductor layer of a second conductivity type facing the first gate electrode via the first insulating film; a third semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the first electrode; and The second surface side region is a fourth semiconductor layer of the second conductivity type facing the second gate electrode via the second insulating film; a fifth semiconductor layer of the second conductivity type having a higher second conductivity type impurity concentration than the second semiconductor layer and the fourth semiconductor layer and in contact with the second electrode; a sixth semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the second electrode; a seventh semiconductor layer of the second conductivity type having a lower second conductivity type impurity concentration than the fourth semiconductor layer and the fifth semiconductor layer and in contact with the second electrode; and In a second direction perpendicular to the first direction, the seventh semiconductor layer is located between the plurality of second gate electrodes.

2. 2. The semiconductor device according to claim 1, wherein the second surface side region further includes an eighth semiconductor layer of the first conductivity type located between the first semiconductor layer and the fourth semiconductor layer and having a higher first conductivity type impurity concentration than the first semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the fifth semiconductor layer is located between the sixth semiconductor layer and the seventh semiconductor layer in the second direction.

4. A first electrode; A second electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion having a first semiconductor layer of a first conductivity type, a first surface side region located between the first electrode and the first semiconductor layer in the first direction, and a second surface side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes facing the first surface side region; a plurality of first insulating films provided between the first surface side region and the plurality of first gate electrodes; a plurality of second gate electrodes facing the second surface region in the first direction; a plurality of second insulating films provided between the second surface side region and the plurality of second gate electrodes; Equipped with The first surface side region is a second semiconductor layer of a second conductivity type facing the first gate electrode via the first insulating film; a third semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the first electrode; and The second surface side region is a fourth semiconductor layer of the second conductivity type; a fifth semiconductor layer of the second conductivity type having a higher second conductivity type impurity concentration than the second semiconductor layer and the fourth semiconductor layer and in contact with the second electrode; a sixth semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the second electrode; and The fourth semiconductor layer is a first portion facing the second gate electrode via the second insulating film; a second portion located between the plurality of second gate electrodes in a second direction perpendicular to the first direction and in contact with the second electrode; The semiconductor device has:

5. 5. The semiconductor device according to claim 4, wherein the second surface side region further includes an eighth semiconductor layer of the first conductivity type located between the first semiconductor layer and the fourth semiconductor layer and having a first conductivity type impurity concentration higher than that of the first semiconductor layer.

6. The semiconductor device according to claim 4 , wherein the fifth semiconductor layer is located between the sixth semiconductor layer and the second portion of the fourth semiconductor layer in the second direction.

7. the first gate electrode is provided in a trench formed in the first surface side region via the first insulating film, The semiconductor device according to claim 1 , wherein the first gate electrode faces the second semiconductor layer in the second direction, with the first insulating film interposed therebetween.

8. 7. The semiconductor device according to claim 1, wherein the first surface side region is located between the first gate electrodes adjacent to each other in the second direction and further includes a ninth semiconductor layer of a second conductivity type that is deeper than the second semiconductor layer.

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