Power converter and inverter device

Abstract

To provide a power converter and an inverter device capable of realizing autonomous synchronous rectification while using a drive signal from an existing drive circuit.SOLUTION: A control circuit CTL has a drive input terminal PDg2, a drive output terminal PDg1, a gate driver GD2, and a switch SW1. A gate voltage signal Vg1, which is a signal from a gate driver GD1 provided outside, is input to the drive input terminal PDg2. The drive output terminal PDg1 is connected to a gate electrode GE of a switching element QT, and outputs an ON / OFF drive signal to the gate electrode GE. The gate driver GD2 generates a gate voltage signal Vg2, which is a signal for driving the switching element QT to turn on. The switch SW1 connects the drive input terminal PDg2 and the drive output terminal PDg1, and is controlled to be turned off in a period in which the gate voltage signal Vg2 is generated.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power converter and an inverter device using the same. [Background technology]

[0002] Patent Document 1 discloses an inverter device capable of shortening dead time. The inverter device includes a switching element, a control circuit that outputs a control signal for instructing the on / off of the switching element, a determination circuit, and a drive circuit. The determination circuit outputs a determination signal indicating the state of the switching element based on the voltage between the main terminals of the switching element. The drive circuit controls the on / off of the switching element based on a control signal from the control circuit and a determination signal from the determination circuit. For example, the drive circuit provided in the upper arm controls the on / off of the switching element by performing an OR operation between a signal obtained by level-shifting the control signal from the control circuit and the determination signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-207737 Summary of the Invention [Problem to be solved by the invention]

[0004] An inverter device is a device capable of powering operation, in which DC power from a power source is converted into AC power and supplied to a load, and regenerative operation, in which AC power from the load is rectified and fed back to the power source. Inverter devices are widely used, for example, in motor control in automobiles, railway vehicles, industrial equipment, etc. Inverter devices typically have power converters for each phase in each of the upper and lower arms. The power converters include switching elements and freewheeling diodes connected in parallel with the switching elements. The freewheeling diodes may also include parasitic diodes of the switching elements. The inverter device performs powering operation or regenerative operation by controlling the on / off of the switching elements in the upper and lower arms.

[0005] During powering or regenerative operation, a rectification operation is generally performed, in which current flows through the freewheel diode of a switching element that is turned off. However, when current flows through the freewheel diode, power loss can occur due to the forward voltage drop of the freewheel diode. Furthermore, current flowing through the parasitic diode of the switching element can cause conduction degradation, a phenomenon in which the characteristics of the parasitic diode deteriorate. For this reason, it is beneficial to use synchronous rectification, which is a method of flowing current through a switching element instead of a freewheel diode.

[0006] When synchronous rectification is used, a dead time is usually provided by setting the timing of a control signal so that switching elements of the same phase in the upper and lower arms are not turned on at the same time. In this case, because current flows through the freewheeling diode during the dead time, it is desirable to shorten the dead time as much as possible. For this reason, it is possible to use a technique such as that shown in Patent Document 1, for example. Using this technique, the dead time can be shortened by performing autonomous synchronous rectification without relying on the timing setting of a control signal.

[0007] On the other hand, for example, consider a case where an existing inverter device is replaced with a new device. In this case, from the viewpoint of cost reduction, it is desirable to reuse the drive signal from the existing drive circuit, for example, the gate driver, and replace only the power converter portion to which the drive signal is output. However, the inverter device disclosed in Patent Document 1 requires input of a control signal from a control circuit, specifically, a logic signal for instructing the on / off of a switching element. This makes it difficult to reuse the existing drive signal in this inverter device.

[0008] Therefore, one object of the present invention is to provide a power converter and an inverter device that can realize autonomous synchronous rectification while using a drive signal from an existing drive circuit.

[0009] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A power converter according to one embodiment includes a switching element having a control electrode, a first electrode, and a second electrode, transmitting power via the first electrode and the second electrode, and a control circuit controlling the on / off of the switching element. The control circuit has a drive input terminal, a drive output terminal, a second drive circuit, and a first switch. The drive input terminal receives a first drive signal from an external first drive circuit, which is a signal for driving the switching element on or off. The drive output terminal is connected to the control electrode of the switching element and outputs an on / off drive signal to the control electrode. The second drive circuit generates a second drive signal for driving the switching element on. The first switch connects the drive input terminal and the drive output terminal, and is controlled to be off while the second drive signal is being generated. [Effects of the Invention]

[0011] According to the embodiment, autonomous synchronous rectification can be achieved using a drive signal from an existing drive circuit. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic diagram illustrating a configuration example of a power converter according to a first embodiment. [Figure 2] 2 is a circuit diagram showing a detailed configuration example of a step-down / shutdown circuit in FIG. 1. FIG. [Figure 3] 2 is a circuit diagram showing a detailed configuration example of a comparator in FIG. 1. FIG. [Figure 4] 2 is a circuit diagram showing a detailed configuration example of a gate driver in the control circuit in FIG. 1. FIG. [Figure 5] 2 is a schematic diagram showing an example of a package configuration of the power converter shown in FIG. 1. [Figure 6] FIG. 10 is a schematic diagram illustrating a configuration example of an inverter device according to a second embodiment. [Figure 7] 7 is a timing chart showing an example of the operation of the inverter device shown in FIG. 6 during power running. [Figure 8] 7 is a timing chart showing an example of the operation of the inverter device shown in FIG. 6 during regenerative operation. [Figure 9] FIG. 10 is a schematic diagram illustrating a configuration example of an inverter device according to a third embodiment. [Figure 10A] 1 is a schematic diagram showing a configuration example and an operation example of an inverter device serving as a comparative example; [Figure 10B] 10B is a timing chart showing an example of the operation of the inverter device shown in FIG. 10A. [Figure 11] FIG. 10 is a schematic diagram illustrating a configuration example of a power converter according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings used to explain the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations will be omitted. In the embodiments, an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will also be referred to as an nMOS transistor, and a p-channel MOSFET will also be referred to as a pMOS transistor.

[0014] (First embodiment) <Outline of power converter> Fig. 1 is a schematic diagram showing an example configuration of a power converter according to a first embodiment. The power converter 10 shown in Fig. 1, in other words, a power module, includes external terminals PNg, PNs, and PNd, a switching element QT, a control circuit CTL, a diode Db, a capacitor Cb, and a resistor Re. The switching element QT is, for example, a MOSFET, which is a power transistor, or an IGBT (Insulated Gate Bipolar Transistor). Here, the switching element QT is an n-channel MOSFET, for example.

[0015] The switching element QT has a gate electrode GE, which is a control electrode, and a source electrode (first electrode) SE and a drain electrode (second electrode) DE, which are main electrodes. If the switching element QT is an IGBT, the source electrode and drain electrode are replaced with an emitter electrode and a collector electrode, respectively. The switching element QT transmits power to an external load (not shown) via the source electrode SE and the drain electrode DE. The switching element QT also includes a parasitic diode Dp, with the source electrode SE side as the anode and the drain electrode DE side as the cathode. The parasitic diode Dp also functions as a freewheeling diode.

[0016] The external terminals PNs and PNd are connected to the source electrode SE and the drain electrode DE, respectively. The external terminal PNg is connected to a gate driver GD1, which is an externally provided drive circuit (first drive circuit). In this specification, the voltage of the gate electrode GE is referred to as a gate voltage or gate voltage signal Vg. The voltages of the source electrode SE and the drain electrode DE are referred to as a source voltage VS and a drain voltage VD, respectively.

[0017] Diode Db and capacitor Cb form a bootstrap circuit. In this example, diode Db and capacitor Cb are connected in series between external terminals PNd and PNs, with diode Db on the external terminal PNd side and capacitor Cb on the external terminal PNs side. Diode Db charges capacitor Cb when drain voltage VD is higher than source voltage VS, and blocks the discharge path from capacitor Cb to external terminal PNd when drain voltage VD is lower than source voltage VS. This allows capacitor Cb to function as a power supply that supplies power supply voltage VCC based on source voltage VS.

[0018] The control circuit CTL has a power supply terminal PDv, a drive input terminal PDg2, a drive output terminal PDg1, a source connection terminal (first terminal) PDs, and a drain connection terminal (second terminal) PDd. A power supply voltage VCC is supplied to the power supply terminal PDv from a capacitor Cb. A gate voltage signal Vg1, which is a drive signal (first drive signal) from the gate driver GD1, is input to the drive input terminal PDg2 via an external terminal PNg. The gate voltage signal Vg1 is a signal for driving the switching element QT on or off, and has an on-level or off-level voltage with respect to the source voltage VS.

[0019] The drive output terminal PDg1 is connected to the gate electrode GE of the switching element QT. The drive output terminal PDg1 outputs a gate voltage signal Vg, which is an on / off drive signal, to the gate electrode GE. The drain connection terminal PDd is connected to the external terminal PNd via a resistor element Re. The source connection terminal PDs is connected to the external terminal PNs. Here, the control circuit CTL is typically configured using a transistor with a lower breakdown voltage than the switching element QT. For this reason, the resistor element Re is provided to reduce the input voltage to the drain connection terminal PDd by a predetermined ratio.

[0020] The control circuit CTL includes a comparator CMP as a determination circuit, a gate driver GD2 as a drive circuit (second drive circuit), a step-down / shutdown circuit SDC, and two switches SW1 and SW2. The comparator CMP receives and compares the source voltage VS and the drain voltage VD via the source connection terminal PDs and the drain connection terminal PDd, and also via the step-down / shutdown circuit SDC. The step-down / shutdown circuit SDC mainly uses a resistor element Re and the like to step down the drain voltage VD with respect to the source voltage VS, and outputs the stepped-down drain output voltage VDo to the comparator CMP.

[0021] The comparator CMP receives the source voltage VS from the source connection terminal PDs at its non-inverting input node (+) and the stepped-down drain output voltage VDo from the step-down / shutdown circuit SDC at its inverting input node (-).The comparator CMP then outputs a comparison result signal Vc that indicates the magnitude relationship between the source voltage VS and the drain output voltage VDo, and therefore the drain voltage VD, in other words, the state of the switching element QT.

[0022] Specifically, when the source voltage VS is higher than the drain output voltage VDo, the comparison result signal Vc is controlled to approximately the level of the power supply voltage VCC, i.e., the "H" level. On the other hand, when the source voltage VS is lower than the drain output voltage VDo, the comparison result signal Vc is controlled to approximately the level of the source voltage VS, i.e., the "L" level.

[0023] The gate driver GD2 receives the comparison result signal Vc as input and generates a gate voltage signal Vg2 that has the same polarity as the comparison result signal Vc and the level of the power supply voltage VCC or the source voltage VS. The gate voltage signal Vg2 is a drive signal (second drive signal) for driving the switching element QT to ON. The gate driver GD2 also generates an inverted comparison result signal VcB, which is an inverted signal of the gate voltage signal Vg2 and the comparison result signal Vc.

[0024] The switches SW1 and SW2 are configured, for example, by n-channel MOSFETs. The switches SW1 and SW2 are not limited to this, and may be configured, for example, by CMOS (Complementary Metal Oxide Semiconductor) switches. The switch (first switch) SW1 connects the drive input terminal PDg2 and the drive output terminal PDg1, and is turned on / off by an inverted comparison result signal VcB from the gate driver GD2. As a result, the switch SW1 is controlled to be off during the period when an on-level gate voltage signal Vg2 is generated.

[0025] The switch (second switch) SW2 connects the gate driver GD2 and the drive output terminal PDg1, and is turned on / off by the comparison result signal Vc. As a result, the switch SW2 is controlled to be on, in contrast to the switch SW1, during the period when the on-level gate voltage signal Vg2 is being generated. In other words, the switch SW2 is controlled to be on / off in a complementary manner to the switch SW1.

[0026] More specifically, when the comparator CMP determines that the source voltage VS is higher than the drain voltage VD, it outputs a comparison result signal Vc at an "H" level to control the switches SW1 and SW2 to be turned off or on. As a result, the switch SW2 transmits an on-level gate voltage signal Vg2 from the gate driver GD2 to the gate electrode GE of the switching element QT as the gate voltage signal Vg.

[0027] On the other hand, if the comparator CMP determines that the source voltage VS is lower than the drain voltage VD, it outputs a comparison result signal Vc at a low level to control the on / off of the switches SW1 and SW2. As a result, the switch SW1 transmits an on-level or off-level gate voltage signal Vg1 from the gate driver GD1 to the gate electrode GE of the switching element QT as the gate voltage signal Vg.

[0028] 1 is configured to achieve autonomous synchronous rectification while using the gate voltage signal Vg1 from the gate driver GD1, which is an existing drive circuit. Specifically, when the source voltage VS is higher than the drain voltage VD, that is, when the condition for the freewheeling diode to be turned on is met, the power converter 10 autonomously controls the switching element QT to be turned on using the gate driver GD2.

[0029] This allows current to flow mainly through the path of the switching element QT, rather than the path of the parasitic diode Dp. On the other hand, when the source voltage VS is not higher than the drain voltage VD, the power converter 10 can drive the switching element QT based on the gate voltage signal Vg1 from the gate driver GD1.

[0030] By performing autonomous synchronous rectification in this manner, it is possible to suppress power loss that may occur when, for example, the freewheeling diode is composed only of the parasitic diode Dp. Furthermore, it is also possible to suppress degradation due to current flowing through the parasitic diode Dp. For example, consider a case where the switching element QT is a SiC MOSFET. In this case, the forward voltage drop of the parasitic diode Dp can reach approximately 3.0 V, which can result in significant power loss. Furthermore, the problem of degradation due to current flow can become more pronounced. Therefore, the configuration shown in FIG. 1 is particularly useful when the switching element QT is a SiC MOSFET.

[0031] Furthermore, by using a configuration that allows the use of the gate voltage signal Vg1 from the gate driver GD1, for example, device modifications can be easily and inexpensively realized. As a specific example, consider a case where an existing device is equipped with a power converter having external terminals PNg, PNs, and PNd, a switching element, and a freewheeling diode. In this case, autonomous synchronous rectification can be realized by simply replacing the existing power converter with the power converter 10 shown in FIG. 1 without modifying the gate driver GD1.

[0032] <Control circuit details> <<Details of the SDC Step-Down / Shutdown Circuit>> Fig. 2 is a circuit diagram showing a detailed configuration example of the step-down / shutdown circuit SDC in Fig. 1. The step-down / shutdown circuit SDC shown in Fig. 2 includes a constant current source CC2, nMOS transistors MN10 and MN11, and resistor elements R2 and R3. The resistor elements R2 and R3 resistively divide the voltage between the drain input voltage VDi from the drain connection terminal PDd shown in Fig. 1 and the source voltage VS of the switching element QT.

[0033] The source of the nMOS transistor MN10 is applied with the source voltage VS of the switching element QT, and the gate is applied with a voltage divided by the resistor elements R2 and R3. The drain of the nMOS transistor MN10 is connected to the constant current source CC2. The drain of the nMOS transistor MN11 is applied with the drain input voltage VDi from the drain connection terminal PDd, and the source outputs the drain output voltage VDo. The gate of the nMOS transistor MN11 is connected to the connection node between the nMOS transistor MN10 and the constant current source CC2.

[0034] In this configuration, the drain input voltage VDi is given by equation (1) using the resistance values ​​of resistor elements R2 and R3, the resistance value of resistor element Re, and the source voltage VS and drain voltage VD of switching element QT. For example, by setting the resistance value of resistor element Re to a large value, the differential voltage between the source voltage VS and the drain input voltage VDi can be reduced so as to satisfy the withstand voltage of nMOS transistors MN10 and MN11. VDi = {(R2 + R3) / (Re + R2 + R3)}(VD - VS) …(1)

[0035] Here, assume the case where the drain voltage VD of the switching element QT is higher than the source voltage VS. In this case, the nMOS transistor MN10 turns on when a positive voltage is applied between the gate and the source. As a result, approximately the source voltage VS is applied to the gate of the nMOS transistor MN11. Consequently, the nMOS transistor MN11 turns off. That is, the source of the nMOS transistor MN11 becomes an open state.

[0036] On the other hand, assume the case where the drain voltage VD of the switching element QT is lower than the source voltage VS. In this case, the nMOS transistor MN10 turns off when a negative voltage is applied between the gate and the source. As a result, the nMOS transistor MN11 turns on when approximately the power supply voltage VCC is applied to the gate via the constant current source CC2. Consequently, the nMOS transistor MN11 outputs the drain input voltage VDi (<VS) given by Equation (1) as the drain output voltage VDo.

[0037] Thus, when the state of the switching element QT is "VD > VS", the step-down / cutoff circuit SDC blocks the transmission path without transmitting the drain input voltage VDi to the comparator CMP. On the other hand, when the state of the switching element QT is "VD < VS", the step-down / cutoff circuit SDC transmits the drain input voltage VDi obtained by stepping down "VD - VS" based on Equation (1) to the comparator CMP as the drain output voltage VDo. At this time, sufficient voltage reduction is performed so as to satisfy the breakdown voltage of each transistor in the comparator CMP.

[0038] <<Details of the Comparator CMP>> Fig. 3 is a circuit diagram showing a detailed configuration example of the comparator CMP in Fig. 1. The comparator (decision circuit) CMP shown in Fig. 3 includes a constant current source CC1, pMOS transistors MP1-MP5, nMOS transistors MN1-MN3, a resistance element Ri, and a capacitor Ci. The comparator CMP operates on a power supply voltage VCC with the source voltage VS as the reference.

[0039] A current generated by a constant current source CC1 flows through the pMOS transistor MP4. The pMOS transistor MP4 forms a current mirror circuit with the pMOS transistors MP5 and MP3. As a result, the current from the constant current source CC1 is transferred to the pMOS transistor MP5 based on the size ratio of the pMOS transistors MP4 and MP5, and is transferred to the pMOS transistor MP3 based on the size ratio of the pMOS transistors MP4 and MP3.

[0040] The pMOS transistors MP1 and MP2, the nMOS transistors MN1 and MN2, and the pMOS transistor MP5 constitute a p-channel differential amplifier circuit DAMP. The pMOS transistors MP1 and MP2 function as a differential pair of transistors. The gate of the pMOS transistor MP1 is connected to the inverting input node (-) and receives the drain output voltage VDo from the step-down / shutdown circuit SDC. The gate of the pMOS transistor MP1 is connected to the non-inverting input node (+) and receives the source voltage VS of the switching element QT.

[0041] The nMOS transistors MN1 and MN2 form a current mirror circuit and function as a load current source for the differential amplifier circuit DAMP. The pMOS transistor MP5 functions as a tail current source for the differential amplifier circuit DAMP. This allows the differential amplifier circuit DAMP to compare the source voltage VS with the drain output voltage VDo, and ultimately the drain voltage VD, and output an output signal (here, an inverted output signal) based on this comparison from the drain of the pMOS transistor MP2.

[0042] The pMOS transistor MP3 and the nMOS transistor MN3 are provided at the subsequent stage of the differential amplification circuit DAMP and constitute the source grounded amplification circuit SAMP. The gate of the nMOS transistor MN3 inputs the inverted output signal from the differential amplification circuit DAMP. The pMOS transistor MP3 functions as a load current source of the source grounded amplification circuit SAMP. As a result, the source grounded amplification circuit SAMP outputs a comparison result signal Vc which becomes an inverted output signal in the source grounded amplification circuit SAMP and a non-inverted output signal in the entire comparator CMP from the drain of the nMOS transistor MN3.

[0043] Here, as described in FIG. 2, when the source voltage VS and the drain voltage VD of the switching element QT are "VD <VS", the drain output voltage VDo (<VS) based on Equation (1) is input to the inverted input node (-) of the comparator CMP. As a result, the comparison result signal Vc becomes the level of the substantially power supply voltage VCC, that is, the "H" level. On the other hand, when "VD> VS", the inverted input node (-) of the comparator CMP is in an open state. Therefore, in the example shown in FIG. 3, a resistor element Ri and a capacitor Ci are connected in parallel between the non-inverted input node (+) and the inverted input node (-).

[0044] The resistor element Ri has a sufficiently high resistance value and determines the inverted input node (-) to the same source voltage VS as the non-inverted input node (+) when the inverted input node (-) is in an open state. Here, the comparator CMP is offset in advance so as to output a comparison result signal Vc at the level of the substantially source voltage VS, that is, the "L" level when the non-inverted input node (+) and the inverted input node (-) are at the same potential. The capacitor Ci has, for example, a function of removing input noise.

[0045] <<Details of the gate driver GD2>> FIG. 4 is a circuit diagram showing a detailed configuration example of the gate driver GD2 in the control circuit in FIG. 1. The gate driver GD2 shown in FIG. 4 operates on a power supply voltage VCC with the source voltage VS as a reference. The gate driver GD2 includes two cascaded CMOS inverter circuits IV1 and IV2. As a result, the gate driver GD2 receives a comparison result signal Vc and generates a gate voltage signal Vg2 of the same polarity as the comparison result signal Vc. Furthermore, the gate driver GD2 outputs an inverted comparison result signal VcB, which is an inverted signal of the comparison result signal Vc, from the first-stage CMOS inverter circuit IV1.

[0046] <Modifications of the control circuit> In the configuration example shown in FIG. 4, the gate driver GD2 outputs an on-level or off-level voltage. Also, in FIG. 1, the switch SW1 is on during the period when the gate driver GD2 outputs an off-level voltage. At this time, the switch SW2 is controlled to be off so that the gate voltage signal Vg1 and the output of the gate driver GD2 do not compete with each other. However, the switch SW2 is not necessarily required.

[0047] For example, consider a case where gate driver GD2 is configured to output an on-level voltage and a high impedance instead of an off-level voltage, unlike the case in Figure 4. In this case, switch SW1 is off when gate driver GD2 is outputting an on-level voltage, and is on when it is outputting a high impedance. As a result, the output conflict described above does not occur even without switch SW2.

[0048] <Power converter package configuration> Fig. 5 is a schematic diagram showing an example of the package configuration of the power converter 10 shown in Fig. 1. In Fig. 5, the switching element QT is formed on one semiconductor chip CP1 and is configured as, for example, a vertical MOSFET. A gate electrode GE and a source electrode SE are formed on the front surface of the semiconductor chip CP1. Although not shown, a drain electrode DE is formed on the back surface of the semiconductor chip CP1.

[0049] The control circuit CTL is formed on a semiconductor chip CP2 separate from the switching element QT. A source connection terminal PDs, a drive output terminal PDg1, a drain connection terminal PDd, a power supply terminal PDv, and a drive input terminal PDg2 are formed on the surface of the semiconductor chip CP2.

[0050] Two semiconductor chips CP1 and CP2 are sealed in one package PKG. The package PKG has three external terminals PNs, PNg, and PNd. The three external terminals PNs, PNg, and PNd are formed of, for example, a metal plate such as a lead frame. In this case, the external terminal PNg also serves as an extraction control electrode for extracting the gate electrode GE of the switching element QT to the outside of the package PKG. Similarly, the external terminals PNs and PNd also serve as extraction electrodes for extracting the source electrode (first electrode) SE and drain electrode (second electrode) DE of the switching element QT to the outside of the package PKG, respectively.

[0051] The package PKG further includes five metal plates (element electrodes) PL1a, PL1b, PL2, PL3, and PL23. The metal plates PL1a and PL1b mount a resistor element Re and are connected to both ends of the resistor element Re. The metal plates PL2 and PL23 mount a capacitor Cb and are connected to both ends of the capacitor Cb. The metal plates PL3 and PL23 mount a diode Db and are connected to both ends of the diode Db. That is, the metal plate PL23 is commonly connected to one end of the capacitor Cb and one end, more specifically, the cathode, of the diode Db.

[0052] The semiconductor chip CP1 is mounted on an extraction electrode (second extraction electrode) that constitutes the external terminal PNd. As a result, the drain electrode DE of the switching element QT is connected to the external terminal PNd. Also, the source electrode SE of the switching element QT is connected to the extraction electrode (first extraction electrode) that constitutes the external terminal PNs via, for example, a bonding wire BW.

[0053] On the other hand, the semiconductor chip CP2 is mounted on lead electrodes (first lead electrodes) that constitute the external terminals PNs. The source connection terminals PDs of the control circuit CTL are connected to the external terminals PNs via bonding wires BW or the like. By mounting the semiconductor chip CP2 on the lead electrodes in this manner, the package PKG can be made smaller. Furthermore, since the source connection terminals PDs, which are also the ground power supply terminals of the control circuit CTL, can be connected to the external terminals PNs at a short distance, the ground power supply voltage of the control circuit CTL can be stabilized.

[0054] The metal plate PL1a is connected to the external terminal PNd via a bonding wire BW or the like. The metal plate PL1b is connected to the drain connection terminal PDd of the control circuit CTL via a bonding wire BW or the like. The metal plate PL2 is connected to the source electrode SE of the switching element QT via a bonding wire BW or the like. The metal plate PL3 is connected to the external terminal PNd via a bonding wire BW or the like. The metal plate PL23 is connected to the power supply terminal PDv of the control circuit CTL via a bonding wire BW or the like.

[0055] The external terminal PNg is connected to a drive input terminal PDg2 of the control circuit CTL via a bonding wire BW, etc. The external terminal PNg receives a gate voltage signal Vg1 from an external gate driver GD1, as shown in Fig. 1. The drive output terminal PDg1 of the control circuit CTL is connected to a gate electrode GE of the switching element QT via a bonding wire BW, etc.

[0056] In this way, by realizing the power converter 10 shown in Fig. 1 in a single package PKG, it is possible to reduce the size of the device or system in which the power converter 10 is installed. Furthermore, as described above, for example, when replacing an existing power converter installed in a specific device or system with a new power converter 10, it is sufficient to simply replace the existing package that mounts the switching element and / or the freewheeling diode with the package PKG shown in Fig. 5. Therefore, such replacement can be achieved easily or at low cost.

[0057] <Major Effects of the First Embodiment> As described above, the power converter according to the first embodiment mainly includes a switch that transmits a first drive signal from an existing drive circuit to a switching element, and a second drive circuit that generates a second drive signal for autonomous synchronous rectification. The switch is controlled to be off during the period when the second drive signal is generated. This allows autonomous synchronous rectification to be achieved while using the drive signal from the existing drive circuit. Furthermore, the ability to reuse the existing drive circuit allows, for example, device modifications to be easily implemented at low cost.

[0058] (Second embodiment) <Configuration of inverter device> Fig. 6 is a schematic diagram showing a configuration example of an inverter device according to a second embodiment. Fig. 6 shows a motor system 25 including an inverter device 20 and a motor MT driven by the inverter device 20. The inverter device 20 has a high-potential side power supply terminal Pp, a low-potential side power supply terminal Pn, and multiple, for example, three-phase, phase terminals Pu, Pv, and Pw.

[0059] A DC power supply 15 and a capacitor Cv are connected in parallel between the high-potential side power supply terminal Pp and the low-potential side power supply terminal Pn. The DC power supply 15 generates a high-potential side power supply voltage VP and a low-potential side power supply voltage VN and supplies them to the high-potential side power supply terminal Pp and the low-potential side power supply terminal Pn, respectively. The capacitor Cv mainly functions to remove power supply noise. The motor MT is connected to three phase terminals Pu, Pv, and Pw.

[0060] The inverter device 20 includes three-phase upper arms, three-phase lower arms, and a gate driver GD1. The three-phase upper arms are connected between a high-potential power supply terminal Pp and three-phase phase terminals Pu, Pv, and Pw, respectively. The three-phase lower arms are connected between a low-potential power supply terminal Pn and three-phase phase terminals Pu, Pv, and Pw, respectively. The three-phase upper arms are each composed of three power converters 10uh, 10vh, and 10wh. The three-phase lower arms are each composed of three power converters 10ul, 10vl, and 10wl, respectively.

[0061] The power converter 10 shown in Fig. 1 is applied to each of the six power converters 10uh, 10vh, 10wh, 10ul, 10vl, and 10wl. In this case, the source-side external terminal PNs is connected to the phase terminals Pu, Pv, and Pw of the upper-arm power converters 10uh, 10vh, and 10wh. Meanwhile, the drain-side external terminal PNd is connected to the phase terminals Pu, Pv, and Pw of the lower-arm power converters 10ul, 10vl, and 10wl.

[0062] The gate driver GD1 drives the six power converters 10. Specifically, the gate driver GD1 outputs gate voltage signals to the external terminals PNg of the six power converters 10, respectively, to drive the switching elements QT included in each power converter 10 to turn on or off. In this case, the gate voltage signal Vg1h directed to the upper-arm power converters 10uh, 10vh, and 10wh is a signal that changes based on the voltages of the phase terminals Pu, Pv, and Pw. On the other hand, the gate voltage signal Vg1l directed to the lower-arm power converters 10ul, 10vl, and 10wl is a signal that changes based on the low-potential-side power supply voltage VN.

[0063] <Inverter device operation> <<Operation during power running>> FIG. 7 is a timing chart showing an example of operation during power running of the inverter device shown in FIG. 6. FIG. 7 shows an example of operation of the upper arm power converter 10uh and the lower arm power converter 10ul, using the u-phase in FIG. 6 as an example. In FIG. 7, the thick solid line represents a waveform obtained when the method of the embodiment is used. On the other hand, the thick dashed line represents a waveform obtained when the method of the comparative example is used. The method of the comparative example is, for example, a method in FIG. 6 in which the control circuit CTL is not provided and the switching element QT is directly driven by the gate driver GD1.

[0064] In Figure 7, (a) shows the gate voltage signal Vg1h from the gate driver GD1 to the upper arm. For ease of explanation, the source voltage VS of the upper arm switching element QT is set to 0V. However, in reality, the source voltage VS fluctuates between the high-potential power supply voltage VP and the low-potential power supply voltage VN depending on the switching state. This description also applies to other waveforms related to the upper arm. (b) and (c) show the comparison result signal Vch and the inverted comparison result signal VcBh, respectively, from the upper arm comparator CMP. (d) shows the gate voltage signal Vg2h from the upper arm gate driver GD2.

[0065] Meanwhile, (e) is the gate voltage signal Vg1l from the gate driver GD1 to the lower arm. Here, the source voltage VS of the lower arm switching element QT, i.e., the low-potential power supply voltage VN, is set to 0V. This notation also applies to the other waveforms related to the lower arm. (f) and (g) are the comparison result signal Vcl and the inverted comparison result signal VcBl, respectively, from the lower arm comparator CMP. (h) is the gate voltage signal Vg2l from the lower arm gate driver GD2.

[0066] (i) is the gate voltage signal Vgh applied to the gate electrode GE of the upper arm switching element QT, and (j) is the gate voltage signal Vgl applied to the gate electrode GE of the lower arm switching element QT.

[0067] (k) is the output current Iqh that flows between the source and drain of the upper arm switching element QT. (l) is the diode current Idh that flows through the upper arm parasitic diode Dp. (m) is the output current Iql that flows between the source and drain of the lower arm switching element QT. (n) is the diode current Idl that flows through the lower arm parasitic diode Dp. (o) is the phase voltage Vu that occurs at the phase terminal Pu.

[0068] First, an outline of the timing chart shown in Fig. 7 will be explained. During powering operation, the gate driver GD1 drives each of the upper-arm and lower-arm switching elements QT to turn on or off at desired timing. As a result, a voltage near the high-potential side power supply voltage VP and a voltage near the low-potential side power supply voltage VN appear alternately at the phase terminal Pu.

[0069] Here, the period during which the gate driver GD1 drives the upper-arm switching element QT to ON, i.e., the period during which the gate voltage signal Vg1h is at ON level as shown in (a), is called the “upper-arm forced conduction period.” Also, the period during which the gate driver GD1 drives the lower-arm switching element QT to ON, i.e., the period during which the gate voltage signal Vg1l is at ON level as shown in (e), is called the “lower-arm forced conduction period.”

[0070] During power running, upper-arm forced conduction periods and lower-arm forced conduction periods are alternately repeated. Between the upper-arm forced conduction periods and the lower-arm forced conduction periods, a period Tp is provided during which both gate voltage signals Vg1h and Vg1l are at the off level, as shown in (a) and (e), in order to prevent shoot-through current. This period Tp is called the "external control pause period." Meanwhile, the period during which both upper and lower arm switching elements QT are off is called dead time. In the comparative example, the dead time is equal to the external control pause period Tp.

[0071] On the other hand, in the method of the embodiment, even during the external control pause period Tp, when either of the gate voltage signals Vg2h and Vg2l from the gate driver GD2 goes to the ON level, the corresponding switching element QT is turned on, as shown in (d) and (h). Therefore, in the method of the embodiment, the dead time is the period during the external control pause period Tp when both of the gate voltage signals Vg2h and Vg2l shown in (d) and (h) are at the OFF level. As can be seen from FIG. 7, the dead time when using the method of the embodiment is close to zero.

[0072] Next, the timing chart shown in Fig. 7 will be described in detail. In Fig. 7, the period from time t0 to t1 and the period from time t4 onwards are the "upper arm forced conduction period." The period from time t2 to t3 is the "lower arm forced conduction period." The periods from time t1 to t2 and from time t3 to t4 are the external control pause period Tp.

[0073] [Time t0-t1] During the upper arm forced conduction period (t0-t1), as shown in (a), the gate voltage signal Vg1h from the gate driver GD1 to the upper arm is at ON level. Also, as shown in (c), the inverted comparison result signal VcBh based on the comparison result of the upper arm comparator CMP is at “H” level. Therefore, the ON level gate voltage signal Vg1h is transmitted via the switch SW1. As a result, as shown in (i), the upper arm switching element QT receives the ON level gate voltage signal Vgh and turns ON.

[0074] On the other hand, as shown in (e), the gate voltage signal Vg1l sent from the gate driver GD1 to the lower arm is at the off level. Also, as shown in (g), the inverted comparison result signal VcBl based on the comparison result of the lower arm comparator CMP is at the "H" level. Therefore, the off-level gate voltage signal Vg1l is transmitted via the switch SW1. As a result, as shown in (j), the lower arm switching element QT receives the off-level gate voltage signal Vgl and is turned off.

[0075] When the upper arm switching element QT is turned on, an output current Iqh flows, as shown in (k). The direction of the output current Iqh is determined by the direction of the current flowing through the u-phase coil of the motor MT. In this example, the output current Iqh flows in the direction of the arrow shown in Figure 6, that is, from the drain to the source of the switching element QT. Meanwhile, the lower arm switching element QT is off during the period from time t0 to t1. Therefore, as shown in (m), the output current Iql is 0 A. As a result of the output current Iqh flowing through the upper arm, the phase voltage Vu becomes a voltage that is lower than the high-potential side power supply voltage VP by the voltage drop of the switching element QT, as shown in (o).

[0076] During the period from time t0 to t1, the drain voltage VD of the switching element QT is higher than the source voltage VS in both the upper and lower arms. Therefore, as shown in (b) and (f), the comparison result signals Vch and Vcl from the comparator CMP are both at the "L" level. This turns off the switch SW2. Furthermore, because a reverse voltage is applied to the parasitic diode Dp, the diode currents Idh and Idl are both 0 A, as shown in (l) and (n).

[0077] [Time t1-t2] During the external control pause period (t1-t2), as shown in (a), first, at time t1, the gate voltage signal Vg1h sent from the gate driver GD1 to the upper arm falls from the ON level to the OFF level. In response, as shown in (i), the gate voltage signal Vgh also falls, causing the upper arm switching element QT to transition from ON to OFF. When the upper arm switching element QT turns OFF, the output current Iqh becomes 0 A, as shown in (k). However, the u-phase coil of the motor MT continues to pass the same current due to the back electromotive force.

[0078] To maintain the current path during this time, in the comparative example, as shown by the thick dashed line in (n), the parasitic diode Dp of the lower arm passes a diode current Idl, i.e., a reflux current, toward the u-phase coil of the motor MT during the period from time t1 to time t2. Also, as shown by the thick dashed line in (j), the lower arm switching element QT continues to receive an off-level gate voltage signal Vgl during the period from time t1 to time t2. Therefore, as shown by the thick dashed line in (m), the output current Iql remains at 0 A. Also, as shown by the thick dashed line in (o), the phase voltage Vu becomes a voltage lower than the low-potential-side power supply voltage VN by the amount of the forward voltage of the parasitic diode Dp.

[0079] On the other hand, in the system of the embodiment, at time t1, when the parasitic diode Dp of the lower arm attempts to pass a diode current, i.e., a reflux current, the drain voltage VD of the switching element QT of the lower arm becomes lower than the source voltage VS. As a result, as shown in (f), the comparison result signal Vcl from the comparator CMP of the lower arm transitions from the "L" level to the "H" level. As a result, as shown in (h), the gate voltage signal Vg2l from the gate driver GD2 transitions from the OFF level to the ON level. Accordingly, as shown in (j), the switching element QT of the lower arm receives the ON level gate voltage signal Vgl via the switch SW2 and turns on.

[0080] When the lower arm switching element QT is turned on in this way, as shown by the thick solid line in (m), from time t1 onwards, the reflux current flows as reverse output current Iql through the lower arm switching element QT, not through the lower arm parasitic diode Dp. In other words, autonomous synchronous rectification is performed.

[0081] As a result, as shown in (o), the phase voltage Vu is lower than the low-potential-side power supply voltage VN by the voltage drop across the lower-arm switching element QT. The magnitude of this voltage drop is smaller than the voltage drop across the parasitic diode Dp, i.e., the magnitude of the forward voltage. As a result, power loss can be reduced. Furthermore, the dead time can be shortened. That is, the dead time when using the method of the embodiment is significantly shorter than the external control pause period Tp, which is the dead time when using the method of the comparative example, and is close to zero. Furthermore, since the diode current Idl is approximately 0 A, the conduction loss in the parasitic diode Dp can be suppressed.

[0082] [Time t2-t3] During the lower arm forced conduction period (t2-t3), as shown in (e), the gate voltage signal Vg1l from the gate driver GD1 to the lower arm is at ON level. That is, at time t2, the gate voltage signal Vg1l rises from OFF level to ON level. Here, in the comparative example, in response to the transition of the gate voltage signal Vg1l to ON level, the lower arm switching element QT receives the ON level gate voltage signal Vg1 and turns on, as shown by the thick dashed line in (j). That is, heteronomous synchronous rectification is performed.

[0083] On the other hand, in the system of the embodiment, the lower-arm switching element QT is already turned on by autonomous synchronous rectification at time t1. Furthermore, the lower-arm comparator CMP continues to output the comparison result signal Vcl at the "H" level as shown in (f) as long as the switching element QT continues to pass a reflux current from its source to its drain. As a result, from time t2 onwards, the lower-arm switching element QT continues to be driven by the gate voltage signal Vg2l from the gate driver GD2 and remains on, regardless of the gate voltage signal Vg1l from the gate driver GD1.

[0084] In this example, the polarity of the output current Iql flowing through the lower-arm switching element QT changes midway through the lower-arm forced conduction period (t2-t3), as shown in (m). That is, current flows from the drain to the source of the lower-arm switching element QT. This state continues until the end of the lower-arm forced conduction period (t2-t3).

[0085] When the polarity of the output current Iql switches in this way, as shown in (f), the lower-arm comparator CMP outputs a comparison result signal Vcl at an "L" level instead of an "H" level. This causes switch SW1 to turn on instead of switch SW2. Also, as shown in (h), the gate voltage signal Vg2l from the lower-arm gate driver GD2 also falls from an ON level to an OFF level. As a result, the lower-arm switching element QT is kept on by the gate voltage signal Vg1l from gate driver GD1 instead of the gate voltage signal Vg2l from gate driver GD2.

[0086] [Time t3-t4] During the external control pause period (t3-t4), as shown in (e), first, at time t3, the gate voltage signal Vg1l from the gate driver GD1 to the lower arm falls from ON level to OFF level. Also, as shown in (g), the inverted comparison result signal VcBl based on the comparison result of the lower arm comparator CMP is at "H" level. Therefore, the OFF level gate voltage signal Vg1l is transmitted via the switch SW1. As a result, as shown in (j), the lower arm switching element QT receives the OFF level gate voltage signal Vg1 and turns off.

[0087] As a result, as shown in (m), after time t3, the output current Iql of the lower arm switching element QT becomes 0 A. The operation during the subsequent external control pause period (t3-t4) is the same as the operation during the external control pause period (t1-t2) described above, except that the operations of the upper and lower arms are reversed.

[0088] In the comparative example, in order to maintain a current path through the u-phase coil of the motor MT, the parasitic diode Dp in the upper arm passes a diode current Idh during the period from time t3 to time t4, as shown by the thick dashed line in (l). As a result, the phase voltage Vu becomes higher than the high-potential side power supply voltage VP by the amount of the forward voltage of the parasitic diode Dp, as shown by the thick dashed line in (o).

[0089] On the other hand, in the system of the embodiment, at time t3, when the parasitic diode Dp in the upper arm attempts to pass the diode current Idh, i.e., the reflux current, the comparison result signal Vch from the comparator CMP in the upper arm transitions from low to high, as shown in (b). This causes the gate voltage signal Vg2h from the gate driver GD2 in the upper arm to rise from off to on, as shown in (d). As a result, the switching element QT in the upper arm receives the on-level gate voltage signal Vgh, as shown by the thick solid line in (i), and turns on.

[0090] When the switching element QT is turned on in this way, after time t3, the freewheeling current flows as the reverse output current Iqh through the switching element QT in the upper arm, not through the parasitic diode Dp in the upper arm, as shown by the thick dashed line in (k). In other words, autonomous synchronous rectification is performed.

[0091] As a result, as shown in (o), the phase voltage Vu becomes higher than the high-potential-side power supply voltage VP by the voltage drop across the upper-arm switching element QT. The magnitude of this voltage drop is smaller than the voltage drop across the parasitic diode Dp, i.e., the magnitude of the forward voltage. As a result, power loss can be reduced. Furthermore, the dead time can be shortened. That is, the dead time when using the method of the embodiment is significantly shorter than the external control pause period Tp, which is the dead time when using the method of the comparative example, and is close to zero. Furthermore, since the diode current Idh is approximately 0 A, the conduction loss in the parasitic diode Dp can be suppressed.

[0092] [About time t4 and after] The period from time t4 onward is again the upper-arm forced conduction period. Operation during this period is similar to that during the lower-arm forced conduction period (t2-t3), except that the upper and lower arms operate in reverse. That is, in the comparative example, as shown by the thick dashed line in (i), the upper-arm switching element QT receives an on-level gate voltage signal Vgh in response to the gate voltage signal Vg1h from the gate driver GD1 and turns on. As a result, as shown in (k) and (l), the upper-arm switching element QT flows current instead of the parasitic diode Dp.

[0093] On the other hand, in the method of the embodiment, as shown by the thick solid line in (i), the upper arm switching element QT continues to receive an ON-level gate voltage signal Vgh from the gate driver GD2 from time t3. Therefore, at time t4, the upper arm switching element QT remains ON regardless of the gate voltage signal Vg1h from the gate driver GD1. If, at some point thereafter, the direction of the current flowing through the u-phase coil of the motor MT changes again, the comparison result signal Vch from the upper arm comparator CMP transitions from the "H" level to the "L" level. Thereafter, the operation from time t0 is repeated.

[0094] <<Operation during regenerative operation>> Fig. 8 is a timing chart showing an example of operation during regenerative operation of the inverter device shown in Fig. 6. As in Fig. 7, Fig. 8 shows an example of operation of the upper arm power converter 10uh and the lower arm power converter 10ul, using the u-phase as an example. In Fig. 8, the thick solid line represents the waveform when the method of the embodiment is used, while the thick dashed line represents the waveform when the method of the comparative example is used.

[0095] In FIG. 8, (a) is the gate voltage signal Vg1h from gate driver GD1 to the upper arm. (b) is the gate voltage signal Vg2h from gate driver GD2 of the upper arm. Meanwhile, (c) is the gate voltage signal Vg1l from gate driver GD1 to the lower arm. (d) is the gate voltage signal Vg2l from gate driver GD2 of the lower arm. Furthermore, (e) is the gate voltage signal Vgh applied to the gate electrode GE of switching element QT of the upper arm. (f) is the gate voltage signal Vgl applied to the gate electrode GE of switching element QT of the lower arm.

[0096] (g) is the output current Iqh flowing between the source and drain of the switching element QT in the upper arm. (h) is the diode current Idh flowing through the parasitic diode Dp in the upper arm. (i) is the output current Iql flowing between the source and drain of the switching element QT in the lower arm. (j) is the diode current Idl flowing through the parasitic diode Dp in the lower arm. (k) is the phase voltage Vu generated at the phase terminal Pu. Note that the notation method for voltage levels is the same as in Figure 7. Also, here, the operation of the comparative example system will be described first, and then the operation of the embodiment system will be described.

[0097] [Operation of the comparative example method] In the comparative example, as shown by the thick dashed lines in (a) and (c), the gate driver GD1 may perform synchronous rectification by outputting gate voltage signals Vg1h and Vg1l even during regenerative operation. Specifically, for example, an inverter control circuit provided upstream of the gate driver GD1 monitors the phase voltages Vu, Vv, and Vw. When the phase voltages Vu, Vv, and Vw of each phase exceed a threshold voltage higher than the high-potential-side power supply voltage VP or fall below a threshold voltage lower than the low-potential-side power supply voltage VN, the inverter control circuit drives the switching element QT of each phase to ON via the gate driver GD1.

[0098] As a result, regenerative current from motor MT flows through switching element QT instead of through parasitic diode Dp. In accordance with this operation, in the comparative example, upper-arm forced conduction periods and lower-arm forced conduction periods are alternately repeated, as in the power running mode described with reference to FIG. 7. Between these periods, an external control pause period is provided, during which both upper and lower arm gate voltage signals Vgh and Vgl are 0 V.

[0099] In (a), the periods from time t10 to t11 and from time t18 onwards are upper-arm forced conduction periods. During these periods, the upper-arm switching element QT is driven on by the gate voltage signal Vg1h from the gate driver GD1. In (c), the periods before time t7 and from time t14 to t15 are lower-arm forced conduction periods. During these periods, the lower-arm switching element QT is driven on by the gate voltage signal Vg1l from the gate driver GD1. The periods from time t7 to t10, t11 to t14, and t15 to t18 are external control pause periods.

[0100] The period from time t8 to time t16 corresponds to one cycle of regenerative operation. Time t8 is the time when the regenerative current stops flowing through the lower-arm switching element QT. That is, as shown by the thick dashed line in (f), the gate voltage signal Vgl of the lower-arm switching element QT falls to a low level at time t8. Thereafter, due to the back electromotive force of the motor MT, as shown in (k), the phase voltage Vu begins to rise from time t8 and exceeds the high-potential-side power supply voltage VP at time t9.

[0101] In the comparative example, the external control pause period is equal to the dead time, so the dead time continues until time t10. Therefore, even if the phase voltage Vu exceeds the high-potential side power supply voltage VP at time t9, the gate voltage signal Vgh of the upper-arm switching element QT remains at the off level, as shown by the thick dashed line in (e). Therefore, as shown by the thick dashed line in (h), during the period from time t9 to t10, the regenerative current flows as diode current Idh through the parasitic diode Dp in the upper arm.

[0102] At time t10, when the dead time ends, the upper arm forced conduction period (t10-t11) begins. That is, as shown by the thick dashed line in (a), the gate driver GD1 outputs an on-level gate voltage signal Vg1h to the upper arm. As a result, as shown by the thick dashed line in (e), the upper arm switching element QT receives an on-level gate voltage signal Vgh at time t10 and turns on.

[0103] As a result, as shown by the thick dashed lines in (g) and (h), the regenerative current that had been flowing as diode current Idh through the parasitic diode Dp in the upper arm now flows as reverse output current Iqh through the switching element QT in the upper arm. As shown in (k), during the period from time t9 to t10, the phase voltage Vu exceeds the high-potential-side power supply voltage VP by the amount of the voltage drop across the parasitic diode Dp. Then, when the switching element QT turns on at time t10, the difference between the phase voltage Vu and the high-potential-side power supply voltage VP decreases.

[0104] At time t11, when the external control pause period, i.e., the dead time in the comparative example, starts again, the gate driver GD1 outputs an off-level gate voltage signal Vg1h to the upper arm, as shown by the thick dashed line in (a). As a result, the upper arm switching element QT receives an off-level gate voltage signal Vgh and turns off, as shown by the thick dashed line in (e).

[0105] As a result, as shown by the thick dashed lines in (g) and (h), the regenerative current that had been flowing as output current Iqh through switching element QT in the upper arm now flows as diode current Idh through parasitic diode Dp in the upper arm. As a result, as shown by the thick dashed line in (k), during the period from time t11 to t12, phase voltage Vu exceeds high-side power supply voltage VP by the amount of the voltage drop across parasitic diode Dp.

[0106] Then, at time t12, when the phase voltage Vu drops to the high-potential side power supply voltage VP, as shown by the thick dashed line in (h), the diode current Idh flowing through the parasitic diode Dp of the upper arm becomes 0 A. In other words, the regenerative current that had been flowing through the parasitic diode Dp stops flowing, and the regenerative current stops flowing in the upper arm.

[0107] The subsequent period from time t12 to t16 is a period during which a regenerative current flows through the lower arm. The operation from time t12 to t16 is the same as the operation from time t8 to t12 described above, except that the operations of the upper and lower arms are reversed. That is, the regenerative current flows through the parasitic diode Dp of the lower arm during the period from time t13 to t14. During this period, the phase voltage Vu is lower than the low-potential-side power supply voltage VN by the voltage drop of the parasitic diode Dp. Then, from time t16 onwards, the operation from time t8 to t16 is repeated.

[0108] [Operation according to the embodiment] On the other hand, in the method of the embodiment, the gate driver GD1 may maintain the gate voltage signals Vg1h and Vg1l to the upper and lower arms at the off level during regenerative operation, as shown by the thick solid lines in (a) and (c). In the method of the embodiment, the drain voltage VD of the switching element QT in the lower arm remains lower than the source voltage VS during the period before time t7. Therefore, the gate voltage signal Vg2l from the gate driver GD2 for the lower arm remains at the on level during the period before time t7, as shown in (d).

[0109] As a result, the lower arm switching element QT receives an on-level gate voltage signal Vgl and remains on, as shown by the thick solid line in (f). As a result, as shown by the thick solid line in (i), the regenerative current continues to flow through the switching element QT as the reverse output current Iql even during the period from time t7 to time t8. In other words, even during this period, the regenerative current flows through the switching element QT, not through the parasitic diode Dp.

[0110] Next, at time t8, as shown in (k), when the phase voltage Vu becomes equal to the low-potential-side power supply voltage VN, the drain voltage VD of the lower-arm switching element QT becomes equal to the source voltage VS. As a result, as shown in (d), the gate voltage signal Vg2l from the lower-arm gate driver GD2 falls from the ON level to the OFF level. As a result, as shown in (f), the OFF-level gate voltage signal Vgl is input to the lower-arm switching element QT, and it turns off. Then, as shown by the thick solid line in (i), at time t8, the output current Iql of the lower-arm switching element QT becomes 0 A. In other words, the regenerative current that had been flowing through the lower-arm switching element QT stops flowing.

[0111] After that, at time t9, when the phase voltage Vu exceeds the high-potential-side power supply voltage VP as shown in (k), the drain voltage VD of the upper-arm switching element QT becomes lower than the source voltage VS. As a result, as shown in (b), the gate voltage signal Vg2h from the upper-arm gate driver GD2 rises from the off level to the on level.

[0112] As a result, the upper-arm switching element QT receives an on-level gate voltage signal Vgh based on the on-level gate voltage signal Vg2h from the gate driver GD2, as shown by the thick solid line in (e), and turns on. As a result, during the period from time t9 to t10, the regenerative current flows not through the upper-arm parasitic diode Dp but through the upper-arm switching element QT as the reverse output current Iqh, as shown by the thick solid line in (g) and (h).

[0113] Even at time t11, the drain voltage VD of the upper-arm switching element QT remains lower than the source voltage VS. Therefore, as shown in (b), the gate voltage signal Vg2h from the upper-arm gate driver GD2 remains at the ON level. Also, as shown by the thick solid line in (e), the upper-arm switching element QT receives the ON-level gate voltage signal Vgh and remains ON. As a result, even during the period from time t11 to t12, the regenerative current continues to flow through the upper-arm switching element QT as the reverse output current Iqh, as shown by the thick solid line in (g) and (h).

[0114] After that, at time t12, when the phase voltage Vu drops to the high-potential side power supply voltage VP as shown in (k), the drain voltage VD of the upper-arm switching element QT becomes equal to the source voltage VS. As a result, as shown in (b), the gate voltage signal Vg2h from the upper-arm gate driver GD2 falls from the ON level to the OFF level.

[0115] As a result, the upper-arm switching element QT receives an off-level gate voltage signal Vgh based on the off-level gate voltage signal Vg1h from the gate driver GD1, as shown by the thick solid line in (e), and turns off. As a result, at time t12, the output current Iqh of the upper-arm switching element QT becomes 0 A, as shown by the thick solid line in (g). In other words, the regenerative current that had been flowing through the upper-arm switching element QT stops flowing.

[0116] During the period from time t9 to time t12 when a regenerative current flows through the upper arm switching element QT, as shown in (k), the phase voltage Vu is slightly higher than the high-side power supply voltage VP due to the voltage drop across the switching element QT. However, the difference between the phase voltage Vu and the high-side power supply voltage VP is smaller than that of the comparative example shown by the thick dashed line.

[0117] The subsequent operation from time t12 to t16 is the same as the operation from time t8 to t12 described above, except that the operations of the upper and lower arms are reversed. That is, during the period from time t13 to t16, as shown in (d), the gate voltage signal Vg2l from the lower arm gate driver GD2 is at the on level. Therefore, as shown by the thick solid line in (f), the lower arm switching element QT receives the on-level gate voltage signal Vgl based on the on-level gate voltage signal Vg2l from the gate driver GD2 and turns on. As a result, the regenerative current flows through the switching element QT instead of the lower arm parasitic diode Dp.

[0118] Therefore, during the period from time t13 to t16, as shown by the thick solid line in (k), the phase voltage Vu is lower than the low-potential-side power supply voltage VN by the voltage drop across the lower-arm switching element QT. However, the difference between the phase voltage Vu and the low-potential-side power supply voltage VN is smaller than that in the comparative example shown by the thick dashed line. Then, during the period from time t16 onwards, the operation during the period from time t8 to t16 is repeated.

[0119] As described above, in the system of the embodiment, during regenerative operation, the upper-arm or lower-arm switching element QT can be autonomously driven to ON even during the external control pause periods (t7-t10, t11-t14, t15-t18) in the system of the comparative example, i.e., the periods corresponding to the dead time. That is, autonomous synchronous rectification can be realized. As a result, as in the case of FIG. 7, it is possible to reduce power loss, suppress deterioration of the parasitic diode Dp, shorten the dead time, and the like. That is, the dead time when the system of the embodiment is used is the periods t8-t9, t12-t13, and t16-t17.

[0120] In the system of the embodiment, the gate driver GD1, and in turn the inverter control circuit provided in the preceding stage, may be configured to fix the gate voltage signals Vg1h and Vg1l to the off level during regenerative operation, which simplifies the configuration of the inverter control circuit and reduces power consumption.

[0121] However, the inverter control circuit and gate driver GD1 may be configured to drive the gate voltage signals Vg1h and Vg1l to an ON level / OFF level during regenerative operation, as in the comparative example. That is, for example, if an existing inverter control circuit and gate driver GD1 have such a configuration, that configuration may be used as is when modifying the device as described above. Even in this case, the same operation as that of the embodiment described in FIG. 8 is performed.

[0122] <Major Effects of the Second Embodiment> As described above, the inverter device according to the second embodiment can also provide the same effects as those described in the first embodiment. Furthermore, in the inverter device, the dead time can be reduced during power running or regenerative operation while using a drive signal from an existing drive circuit.

[0123] (Third embodiment) <Configuration of inverter device> Fig. 9 is a schematic diagram showing a configuration example of an inverter device according to a third embodiment. Fig. 9 shows a motor system 35 including an inverter device 30 and a motor MT driven by the inverter device 30. The inverter device 30 includes a high-potential side power supply terminal (first power supply terminal) Pp, a low-potential side power supply terminal (second power supply terminal) Pn, a midpoint power supply terminal (third power supply terminal) Pm, and multiple, for example, three-phase phase terminals Pu, Pv, and Pw.

[0124] A DC power supply 15 is connected between a high-potential side power supply terminal Pp and a low-potential side power supply terminal Pn. The DC power supply 15 generates a high-potential side power supply voltage (first power supply voltage) VP and a low-potential side power supply voltage (second power supply voltage) VN and supplies them to the high-potential side power supply terminal Pp and the low-potential side power supply terminal Pn, respectively. A motor MT is connected to three-phase terminals Pu, Pv, and Pw.

[0125] Furthermore, a capacitor Cv1 is connected between the high-potential power supply terminal Pp and the midpoint power supply terminal Pm, and a capacitor Cv2 is connected between the midpoint power supply terminal Pm and the low-potential power supply terminal Pn, respectively, so that a midpoint power supply voltage (third power supply voltage) VM having an intermediate voltage "(VP+VN) / 2" between the high-potential power supply voltage VP and the low-potential power supply voltage VN is supplied to the midpoint power supply terminal Pm.

[0126] The inverter device 30 includes three-phase upper arms UAu, UAv, and UAw, three-phase lower arms LAu, LAv, and LAw, a gate driver GD1, and three-phase bidirectional switch circuits. The three-phase bidirectional switch circuits are connected between a midpoint power supply terminal Pm and three-phase phase terminals Pu, Pv, and Pw, respectively. Each of the three-phase bidirectional switch circuits includes two power converters 10 as shown in FIG. 1.

[0127] Specifically, the u-phase bidirectional switch circuit has two power converters 10u1 and 10u2. The v-phase bidirectional switch circuit has two power converters 10v1 and 10v2. The w-phase bidirectional switch circuit has two power converters 10w1 and 10w2. For example, in the u-phase, the two switching elements QT included in each of the two power converters 10u1 and 10u2 have their source electrodes connected in common via their external terminals PNs. However, the two switching elements QT may have their drain electrodes connected in common instead of their source electrodes. The same applies to the v-phase and w-phase as to the u-phase.

[0128] An inverter device equipped with such a bidirectional switch circuit is called a three-level inverter or a multilevel inverter. Among these, a configuration in which a bidirectional switch circuit is provided between the midpoint power supply terminal Pm and each of the phase terminals Pu, Pv, and Pw is called a T-type three-level inverter. In a three-level inverter, the phase voltage can be set to the midpoint power supply voltage VM in addition to the high-potential side power supply voltage VP and the low-potential side power supply voltage VN. This allows, for example, the output waveform at the phase terminal to be closer to a sine wave. Furthermore, the reduced amplitude of voltage fluctuations due to switching reduces switching loss and switching noise.

[0129] The gate driver GD1 drives the three-phase upper arms UAu, UAv, and UAw, the lower arms LAu, LAv, and LAw, and the bidirectional switch circuit. Specifically, the gate driver GD1 drives a total of six switching elements (not shown) included in the three-phase upper and lower arms and a total of six switching elements QT included in the three-phase bidirectional switch circuit.

[0130] <Inverter device operation> [Operation of the comparative example method] FIG. 10A is a schematic diagram showing an example of the configuration and operation of an inverter device as a comparative example. FIG. 10B is a timing chart showing an example of the operation of the inverter device shown in FIG. 10A. FIG. 10A shows an example of the configuration of one phase included in a general T-type three-level inverter and an example of the operating state at each time. FIG. 10B shows an example of a method for driving one phase in the T-type three-level inverter. Here, FIG. 10A shows the operating state at each time t20-t24 shown in FIG. 10B.

[0131] In Figure 10A, switching element QT1 and freewheel diode D1 form the upper arm of a certain phase. Switching element QT2 and freewheel diode D2 form the lower arm of that phase. Switching elements QT3 and QT4 and freewheel diodes D3 and D4 form the bidirectional switch circuit of that phase. The source electrodes of switching elements QT3 and QT4 are connected in common. The drain electrodes of switching element QT3 and switching element QT4 are connected to a phase terminal and a neutral power supply terminal, respectively.

[0132] As described above, in the comparative example, the bidirectional switch circuit does not have a control circuit CTL as shown in FIG. 9. That is, the switching elements QT3 and QT4 are directly driven by the gate driver GD1 shown in FIG. 9. The high-potential side power supply voltage and the low-potential side power supply voltage are +E and -E, respectively. The midpoint power supply voltage of the midpoint power supply terminal is 0 V. A phase voltage Vout is generated at the phase terminals.

[0133] 10B shows an example of a PWM (Pulse Width Modulation) signal input to each switching element QT1-QT4, with a sine wave as the target voltage. The PWM signal is generated by, for example, comparing a triangular wave (not shown) having a predetermined PWM period with the target voltage. Time t22 is the time when the target voltage reaches zero crossing. Times t20 and t21 are the times immediately before the target voltage reaches zero crossing. Times t23 and t24 are the times immediately after the target voltage reaches zero crossing.

[0134] As can be seen from Figure 10B, in a T-type three-level inverter, the two switching elements QT1 and QT3 are driven on / off in a complementary manner with a dead time in between. Similarly, the two switching elements QT2 and QT4 are driven on / off in a complementary manner with a dead time in between. Below, we will explain the operation at each time t20-t24 using Figures 10A and 10B.

[0135] At time t20, switching elements QT1 and QT3 are driven on and off, respectively. Switching elements QT2 and QT4 are driven off and on, respectively. In this case, as shown in FIG. 10A, current flows through switching element QT1. As a result, phase voltage Vout becomes approximately +E. At this time, switching element QT3 and freewheeling diode D3 block the current path to the neutral power supply terminal.

[0136] Subsequently, at time t21, switching elements QT1 and QT3 are driven off and off, respectively. Meanwhile, switching elements QT2 and QT4 remain off and on, respectively. That is, when switching element QT1 is turned off, switching elements QT1 and QT3 operate during the dead time. In this case, as shown in FIG. 10A, current flows through switching element QT4 and freewheeling diode D3. As a result, phase voltage Vout becomes approximately 0 V.

[0137] Next, at time t22, switching elements QT1 and QT3 are driven off and on, respectively. Meanwhile, switching elements QT2 and QT4 remain off and on, respectively. That is, switching element QT3 turns on. In this case, as shown in FIG. 10A, current flows through switching elements QT4 and QT3. As a result, phase voltage Vout remains at approximately 0 V.

[0138] Subsequently, at time t23, switching elements QT1 and QT3 remain off and on, respectively. Meanwhile, switching elements QT2 and QT4 are driven off and off, respectively. That is, by turning off switching element QT4, switching elements QT2 and QT4 operate during the dead time. In this case, as shown in FIG. 10A, current flows through switching element QT3 and freewheeling diode D4. As a result, phase voltage Vout remains at approximately 0 V.

[0139] Next, at time t24, switching elements QT1 and QT3 remain off and on, respectively. Meanwhile, switching elements QT2 and QT4 are driven on and off, respectively. That is, switching element QT2 turns on. In this case, as shown in FIG. 10A, current flows through switching element QT2. As a result, phase voltage Vout becomes approximately -E. At this time, switching element QT4 and freewheeling diode D4 block the current path from the neutral power supply terminal.

[0140] [Operation according to the embodiment] 9, when current is about to flow through the freewheeling diode D3 at time t21 in FIG. 10A, the control circuit CTL autonomously turns on the switching element QT3, which is currently off. As a result, the dead time including time t21 can be shortened. Furthermore, power loss due to current flowing through the freewheeling diode D3, i.e., the parasitic diode Dp, can be reduced, and the problem of degradation due to current flow can be suppressed.

[0141] Furthermore, at time t23, when current attempts to flow through freewheel diode D4 instead of switching element QT4, which turns off, control circuit CTL autonomously keeps switching element QT4 on as long as current continues to flow from source to drain. As a result, the dead time, including time t23, can be shortened. This also reduces power loss due to current flowing through freewheel diode D4, i.e., parasitic diode Dp, and suppresses the problem of degradation during conduction.

[0142] <Outline of power converter> Fig. 11 is a schematic diagram showing an example configuration of a power converter according to a third embodiment. The power converter 40 shown in Fig. 11 is configured, for example, in a single package and can be applied to a bidirectional switch circuit such as that shown in Fig. 9. The power converter 40 includes two external terminals PNd1 and PNd2 for drains and two external terminals PNg1 and PNg2 for gates. The power converter 40 also includes two sets of switching elements QT and control circuits CTL such as those shown in Fig. 1.

[0143] That is, the power converter 40 includes two switching elements QT1 and QT2, parasitic diodes Dp1 and Dp2, and two control circuits CTL1 and CTL2 that drive the two switching elements QT1 and QT2, respectively. The power converter 40 also includes two sets of capacitors Cb1 and Cb2 and diodes Db1 and Db2 that form a bootstrap circuit, and two sets of resistors Re1 and Re2 that form a step-down resistor Re.

[0144] The switching elements QT1 and QT2 have their source electrodes SE connected in common and their drain electrodes DE connected to external terminals PNd1 and PNd2, respectively. The external terminals PNg1 and PNg2 are connected to control circuits CTL1 and CTL2, respectively. The switching elements QT1 and QT2 may have their drain electrodes DE connected in common instead of their source electrodes SE. In this case, two external terminals for sources are provided instead of the two external terminals PNd1 and PNd2 for drains.

[0145] <Major Effects of the Third Embodiment> As described above, the inverter device according to the third embodiment can achieve the same effects as those described in the first embodiment. Furthermore, in a three-level inverter, the dead time can be shortened while using a drive signal from an existing drive circuit. In particular, in a three-level inverter, the number of switching elements, and therefore the number of freewheeling diodes, can be increased by the bidirectional switch circuit compared to a typical two-level inverter. This can exacerbate problems of power loss and degradation in electrical conduction. By using the method according to the third embodiment, such problems can be suppressed. Note that in FIG. 9, the power converter 10 shown in FIG. 1 may be applied to the upper and lower arms as well as the bidirectional switch circuit.

[0146] The invention made by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0147] 10, 40: power converter, 20, 30: inverter device, CMP: comparator (decision circuit), CP1, CP2: semiconductor chip, CTL: control circuit, DE: drain electrode (second electrode), GD1, GD2: gate driver (drive circuit), GE: gate electrode (control electrode), LAu, LAv, LAw: lower arm, PDd: drain connection terminal, PDg1: drive output terminal, PDg2: drive input terminal, PDs: source connection terminal, PKG: package, PNg: external terminal (drawout control electrode), PNs, PNd: external terminal (drawout electrode), Pm: midpoint power supply terminal, Pn: low potential side power supply terminal, Pp: high potential side power supply terminal, Pu, Pv, Pw: phase terminal, QT: switching element, SE: source electrode (first electrode), SW1, SW2: switch, UAu, UAv, UAw: upper arm

Claims

1. a switching element having a control electrode, a first electrode, and a second electrode, and transmitting power via the first electrode and the second electrode; a control circuit for controlling the on / off of the switching element; Equipped with The control circuit a drive input terminal for inputting a first drive signal, which is a signal for driving the switching element to turn on or off and is a signal from an externally provided first drive circuit; a drive output terminal connected to the control electrode of the switching element and outputting an ON / OFF drive signal to the control electrode; a second drive circuit that generates a second drive signal that is a signal for driving the switching element to ON; a first switch that connects the drive input terminal and the drive output terminal and is controlled to be off during a period in which the second drive signal is generated; having Power converter.

2. 2. The power converter according to claim 1, The control circuit further comprises: a first terminal and a second terminal connected to the first electrode and the second electrode of the switching element, respectively; a determination circuit that receives a first voltage applied to the first electrode and a second voltage applied to the second electrode via the first terminal and the second terminal, compares the received voltages, and controls the first switch based on the magnitude relationship between the first voltage and the second voltage; having Power converter.

3. 3. The power converter according to claim 2, the control circuit further includes a second switch that is connected between the second drive circuit and the drive output terminal and whose on / off state is controlled in a complementary manner to the first switch. Power converter.

4. 3. The power converter according to claim 2, the first electrode is a source electrode or an emitter electrode; the second electrode is a drain electrode or a collector electrode, the determination circuit controls the first switch to be turned off when the first voltage is higher than the second voltage, and controls the first switch to be turned on when the first voltage is lower than the second voltage; Power converter.

5. 3. The power converter according to claim 2, The first switch is configured with a MOSFET. Power converter.

6. 2. The power converter according to claim 1, The switching element is composed of a SiC-MOSFET. Power converter.

7. 2. The power converter according to claim 1, the first electrode is a source electrode or an emitter electrode; the second electrode is a drain electrode or a collector electrode, the switching element is formed on a first semiconductor chip, the control circuit is formed on a second semiconductor chip and sealed together with the first semiconductor chip in a single package; the package has an extraction control electrode, a first extraction electrode, and a second extraction electrode for extracting the control electrode, the first electrode, and the second electrode to the outside of the package, respectively; the second semiconductor chip is mounted on the first extraction electrode; Power converter.

8. 2. The power converter according to claim 1, Two sets of the switching elements and the control circuits are provided, The two switching elements included in each of the two sets have the first electrodes connected in common or the second electrodes connected in common. Power converter.

9. a plurality of power converters each constituting an upper arm and a lower arm of a predetermined phase; a first drive circuit that drives the plurality of power converters; Equipped with Each of the plurality of power converters a switching element having a control electrode, a first electrode, and a second electrode, and transmitting power via the first electrode and the second electrode; a control circuit for controlling the on / off of the switching element; and The control circuit a drive input terminal for inputting a first drive signal, which is a signal for driving the switching element to turn on or off and is a signal from the first drive circuit; a drive output terminal connected to the control electrode of the switching element and outputting an ON / OFF drive signal to the control electrode; a second drive circuit that generates a second drive signal that is a signal for driving the switching element to ON; a first switch that connects the drive input terminal and the drive output terminal and is controlled to be off during a period in which the second drive signal is generated; Equipped with Inverter device.

10. 10. The inverter device according to claim 9, The control circuit further comprises: a first terminal and a second terminal connected to the first electrode and the second electrode of the switching element, respectively; a determination circuit that receives a first voltage applied to the first electrode and a second voltage applied to the second electrode via the first terminal and the second terminal, compares the received voltages, and controls the first switch based on the magnitude relationship between the first voltage and the second voltage; having Inverter device.

11. The inverter device according to claim 10, the control circuit further includes a second switch that connects the second drive circuit and the drive output terminal and whose on / off state is controlled complementarily to the first switch. Inverter device.

12. The inverter device according to claim 10, the first electrode is a source electrode or an emitter electrode; the second electrode is a drain electrode or a collector electrode, the determination circuit controls the first switch to be turned off when the first voltage is higher than the second voltage, and controls the first switch to be turned on when the first voltage is lower than the second voltage; Inverter device.

13. a first power supply terminal and a second power supply terminal to which a first power supply voltage and a second power supply voltage are respectively supplied; a third power supply terminal to which a third power supply voltage, which is an intermediate voltage between the first power supply voltage and the second power supply voltage, is supplied; Phase terminals and an upper arm connected between the first power supply terminal and the phase terminal; a lower arm connected between the second power supply terminal and the phase terminal; a bidirectional switch circuit connected between the third power supply terminal and the phase terminal, the bidirectional switch circuit having two power converters; a first drive circuit that drives the upper arm, the lower arm, and the bidirectional switch circuit; Equipped with Each of the two power converters a switching element having a control electrode, a first electrode, and a second electrode, and transmitting power via the first electrode and the second electrode; a control circuit for controlling the on / off of the switching element; and The control circuit a drive input terminal for inputting a first drive signal, which is a signal for driving the switching element to turn on or off and is a signal from the first drive circuit; a drive output terminal connected to the control electrode of the switching element and outputting an ON / OFF drive signal to the control electrode; a second drive circuit that generates a second drive signal that is a signal for driving the switching element to ON; a first switch that connects the drive input terminal and the drive output terminal and is controlled to be off during a period in which the second drive signal is generated; Equipped with The two switching elements included in each of the two power converters have the first electrodes connected in common or the second electrodes connected in common. Inverter device.

14. The inverter device according to claim 13, The control circuit further comprises: a first terminal and a second terminal connected to the first electrode and the second electrode of the switching element, respectively; a determination circuit that receives a first voltage applied to the first electrode and a second voltage applied to the second electrode via the first terminal and the second terminal, compares the received voltages, and controls the first switch based on the magnitude relationship between the first voltage and the second voltage; having Inverter device.

15. 15. The inverter device according to claim 14, the first electrode is a source electrode or an emitter electrode; the second electrode is a drain electrode or a collector electrode, the determination circuit controls the first switch to be turned off when the first voltage is higher than the second voltage, and controls the first switch to be turned on when the first voltage is lower than the second voltage; Inverter device.

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