Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor capable of suppressing generation of voids.SOLUTION: An internal electrode 15 comprises an opposite part 15a, which is opposed with an internal electrode 15 adjacent to each other in a lamination direction T, and a first pull-out part 15Ab which is pulled out of the opposite part 15a and connected with an external electrode 3. A laminate 2 includes an effective layer part 10 consisting of the opposite parts 15a and portions in a dielectric layer 14 held between the adjacent opposite parts 15a. The first pull-out part 15Ab includes a bent portion 21 which is bent so as to include an apex 22 on a central side T2 in the lamination direction. A shortest distance in a length direction L between the apex 22 of the bent portion 21 and the effective layer part 10 is larger than a dimension of the dielectric layer 14 in the lamination direction T and smaller than a shortest distance in the length direction L between the apex 22 of the bent portion 21 and an end face C on the side, which is proximate with the apex 22, among the end faces C.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end surfaces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, in which the external electrodes include base electrode layers formed by baking. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-237137 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a typical multilayer ceramic capacitor such as that described in Patent Document 1, voids (air gaps) are likely to form near the ends of the internal electrode layers. If voids exist in these areas, cracks may occur starting from the voids. Therefore, there is room for improvement in terms of reliability.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of voids. [Means for solving the problem]

[0006] In order to solve the above problems, the present invention provides a multilayer ceramic capacitor comprising: an inner layer portion including a plurality of dielectric layers and a plurality of internal electrodes that are alternately stacked; a laminate having first and second main surfaces that face each other in a stacking direction; first and second side surfaces that face each other in a width direction perpendicular to the stacking direction; and first and second end surfaces that face each other in a length direction perpendicular to the stacking direction and the width direction; and external electrodes that are arranged in pairs on each of the end surfaces, wherein the internal electrodes have opposing portions that face the internal electrodes adjacent to them in the stacking direction, and external electrodes that are drawn out from the opposing portions and connected to the external electrodes. and an extraction portion having a bent portion extending from the main surface toward the center of the stacking direction of the laminate, the laminate having an effective layer portion formed of each of the opposing portions and a portion of the dielectric layer sandwiched between the adjacent opposing portions, and when a direction from each of the main surfaces toward a center of the stacking direction of the laminate is defined as a center side of the stacking direction, the extraction portion has a bent portion that bends to have an apex on the center side of the stacking direction, and the shortest distance in the length direction between the apex of the bent portion and the effective layer portion is larger than the dimension of the dielectric layer in the stacking direction and smaller than the shortest distance in the length direction between the apex of the bent portion and one of the end faces closest to the apex. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of suppressing the occurrence of voids. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line II-II of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described with reference to FIGS.

[0010] (Multilayer ceramic capacitor 1) As shown in Fig. 1, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a so-called two-terminal structure. The multilayer ceramic capacitor 1 includes a laminate 2 and a pair of external electrodes 3. The laminate 2 is substantially rectangular and has six outer surfaces. The laminate 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode 15 are laminated.

[0011] In this specification, the direction in which the dielectric layers 14 and internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the length direction L. The direction perpendicular to both the length direction L and the stacking direction T is referred to as the width direction W. Within the stacking direction T, the direction from the center of the stacking direction T of the laminate 2 toward each main surface A is referred to as the "stacking direction outer side T1," and within the stacking direction T, the direction from each main surface A toward the center of the stacking direction T of the laminate 2 is referred to as the "stacking direction center side T2."

[0012] Of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides in the stacking direction T is referred to as the first main surface AA and the second main surface AB, a pair of outer surfaces extending in the stacking direction T and on both sides in the width direction W is referred to as the first side surface BA and the second side surface BB, and a pair of outer surfaces extending in the stacking direction T and on both sides in the length direction L is referred to as the first end surface CA and the second end surface CB. The first main surface AA and the second main surface AB may be collectively referred to as the "main surfaces A." The first side surface BA and the second side surface BB may be collectively referred to as the "side surfaces B." The first end surface CA and the second end surface CB may be collectively referred to as the "end surfaces C."

[0013] A pair of external electrodes 3 is provided on each end face C. The external electrodes 3 are aligned in the length direction L.

[0014] A cross section parallel to the lamination direction T and the length direction L is referred to as an “LT cross section.” The cross section of FIG.

[0015] (Laminate 2) The laminate 2 has an inner layer portion 11 and a pair of outer layer portions 12 arranged on either side of the inner layer portion 11 in the stacking direction T. The corners and ridges of the laminate 2 are preferably rounded. Note that a corner is a portion where three surfaces of the laminate intersect. A ridge is a portion where two surfaces of the laminate intersect.

[0016] (Inner layer 11) 2 and 3, the inner layer portion 11 has a plurality of dielectric layers 14 and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are alternately stacked.

[0017] The dielectric layer 14 is formed of a dielectric ceramic containing BaTiO as a main component, for example, and may contain a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like as a secondary component.

[0018] The internal electrodes 15 are formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. The internal electrodes 15 include a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A are exposed only at the first end face CA. The second internal electrodes 15B are exposed only at the second end face CB. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately. Of the internal electrodes 15, the one closest to the first principal face AA is the first internal electrode 15A. The one closest to the second principal face AB is the second internal electrode 15B.

[0019] The first internal electrode 15A has a first opposing portion 15Aa and a first lead portion 15Ab. The first opposing portion 15Aa is a portion of the first internal electrode 15A that faces the second internal electrode 15B adjacent to it in the stacking direction T. The first opposing portion 15Aa is located in the center between the end faces C. The first lead portion 15Ab is a portion of the first internal electrode 15A that is led out from the first opposing portion 15Aa toward the first end face CA. The first lead portion 15Ab is exposed at the first end face CA. The first lead portion 15Ab is connected to the external electrode 3.

[0020] The second internal electrode 15B has a second opposing portion 15Ba and a second lead portion 15Bb. The second opposing portion 15Ba is a portion of the second internal electrode 15B that faces the adjacent first internal electrode 15A (first opposing portion 15Aa). The second opposing portion 15Ba is located in the center between the end faces C. The second lead portion 15Bb is a portion of the second internal electrode 15B that is led out from the second opposing portion 15Ba toward the second end face CB. The second lead portion 15Bb is exposed at the second end face CB. The second lead portion 15Bb is connected to the external electrode 3.

[0021] The first internal electrode 15A and the second internal electrode 15B may be collectively referred to as "internal electrodes 15." The first opposing portion 15Aa and the second opposing portion 15Ba may be collectively referred to as "opposing portion 15a."

[0022] The laminate 2 also has an effective layer portion 10 consisting of each opposing portion 15a and a portion of each dielectric layer 14 sandwiched between adjacent opposing portions 15a. The effective layer portion 10 is a portion where the capacitance of the multilayer ceramic capacitor 1 is formed.

[0023] (Outer layer part 12) The outer layer portion 12 is formed of the same material as the dielectric layer 14 of the inner layer portion 11. Note that the outer layer portion 12 does not have an internal electrode 15 disposed thereon.

[0024] (External electrode 3) Each external electrode 3 is disposed on each end face C. Each external electrode 3 covers not only the end face C but also part of the main face A and part of the side face B. The external electrodes 3 include a base electrode layer 31 formed in contact with the surface of the laminate 2, a first plating layer 32 disposed on the base electrode layer 31, and a second plating layer 33 disposed on the first plating layer 32.

[0025] The base electrode layer 31 is, for example, a baked layer containing a conductive metal such as Cu (copper) and glass. Either the first internal electrode 15A or the second internal electrode 15B is connected to the base electrode layer 31. The first plating layer 32 is, for example, a Ni (nickel) plating layer. The second plating layer 33 is, for example, a Sn (tin) plating layer.

[0026] The structure of the multilayer ceramic capacitor 1 is generally symmetrical in the length direction L. Therefore, the following description will be given taking the region on the first end face CA side as an example.

[0027] Here, each of the first lead portions 15Ab has a bent portion 21 that is bent to have an apex 22 on the central side T2 in the stacking direction. In other words, the first lead portions 15Ab are bent at the bent portion 21 so as to be convex toward the central side T2 in the stacking direction.

[0028] The shortest distance (referred to as "D1") in the longitudinal direction L between the vertex 22 of the bent portion 21 and the effective layer portion 10 is greater than the dimension (referred to as "t1") in the stacking direction T of the dielectric layer 14, and is smaller than the shortest distance (referred to as "D2") in the longitudinal direction L between the vertex 22 of the bent portion 21 and the end face C (more specifically, the first end face CA) that is closer to the vertex 22 among the end faces C.

[0029] The dimension T of the dielectric layer 14 in the stacking direction is the dimension T of the dielectric layer 14 adjacent to the inner electrode 15 on the center side T2 in the stacking direction, which is the measurement target for D1 and D2.

[0030] The apex 22 of the bent portion 21 of the first internal electrode 15A is preferably located, for example, closer to the center T2 in the stacking direction than the portion of the dielectric layer 14 adjacent to the first internal electrode 15A that constitutes the effective layer portion 10. In other words, the bent portion 21 of the first internal electrode 15A preferably covers the portion of the dielectric layer 14 adjacent to the first internal electrode 15A that constitutes the effective layer portion 10 over the entire area in the stacking direction T. However, the bent portion 21 of the first internal electrode 15A does not necessarily have to cover the portion of the dielectric layer 14 adjacent to the first internal electrode 15A that constitutes the effective layer portion 10 over the entire area in the stacking direction T.

[0031] D1 is, for example, 50 μm or less.

[0032] Of the first drawn portions 15Ab, the first drawn portion 15Ab located closest to the first main surface AA side is referred to as the "first main surface side outermost first drawn portion 24." Of the first drawn portions 15Ab, the first drawn portion 15Ab located closest to the second main surface AB side is referred to as the "second main surface side outermost first drawn portion 25." The first main surface side outermost first drawn portion 24 has a bent portion 21. The second main surface side outermost first drawn portion 25 has a bent portion 21.

[0033] The length (referred to as "D3") of the line segment connecting the vertex 22 of the bent portion 21 of the first main surface side outermost first drawn portion 24 and the vertex 22 of the bent portion 21 of the second main surface side outermost first drawn portion 25 is smaller than the length (referred to as "D4") of the line segment connecting the end portion on the first end face CA side of the first main surface side outermost first drawn portion 24 and the end portion on the first end face CA side of the second main surface side outermost first drawn portion 25. Note that in Figure 2, D4 is shown at a position slightly shifted from its actual position for convenience of illustration.

[0034] D4 is smaller than the dimension in the stacking direction T of the effective layer 10. An end portion of each first lead portion 15Ab on the first end face CA side is bent toward the center T2 in the stacking direction.

[0035] An imaginary line passing through the end of the first main surface side outermost first extracted portion 24 on the first end face CA side and tangent to the first opposing portion 15Aa of the first internal electrode 15A having the first main surface side outermost first extracted portion 24 is defined as a "first imaginary line L1" (see FIG. 3). An imaginary line passing through the end of the second main surface side outermost first extracted portion 25 on the first end face CA side and tangent to the first opposing portion 15Aa of the first internal electrode 15A having the second main surface side outermost first extracted portion 25 is defined as a "second imaginary line L2".

[0036] The length (denoted as "D5") of a virtual line segment connecting the first virtual line L1 and the second virtual line L2, which passes through the vertex 22 of the bent portion 21 of the outermost first drawn-out portion 24 on the first main surface side and the vertex 22 of the bent portion 21 of the outermost first drawn-out portion 25 on the second main surface side, is greater than D3. Note that in Fig. 3, the arrow indicating D3 and the arrow indicating D5 are shown shifted in position for convenience of illustration.

[0037] In this case, compared to when D5 is equal to or smaller than D3, the distance between adjacent vertices 22 can be made smaller, thereby making it possible to suppress the occurrence of voids near the ends of the internal electrodes 15.

[0038] In addition, when D5 is equal to or smaller than D3, it is possible to consider a case where, for example, the outermost first drawn portion 24 on the first main surface side is bent so as to be convex toward the center side T2 in the stacking direction, and the outermost first drawn portion 25 on the second main surface side is bent so as to be convex toward the outside T1 in the stacking direction.

[0039] Furthermore, a region of each principal surface A near the first end face CA is bent toward the center T2 in the stacking direction. The step portion of each principal surface A forming the bend substantially coincides with the position of the bent portion 21 of the internal electrode 15 in the length direction L.

[0040] (Measurement method) Next, the method for measuring each value will be described. First, the laminate 2 is polished to expose a predetermined cross section at the center of the LT cross section passing through the width direction W of the laminate 2. Next, the exposed cross section is observed with a scanning electron microscope, and various dimensions or distances are measured.

[0041] When measuring the dimension T of the dielectric layer 14 in the stacking direction, the dimension T of the dielectric layer 14 in the stacking direction is measured at the center in the length direction L of the part of the dielectric layer 14 that forms the effective layer portion 10. The obtained value is defined as the dimension T of the dielectric layer 14 in the stacking direction.

[0042] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0043] A dielectric sheet for the dielectric layer 14 and a conductive paste for the internal electrode 15 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0044] On the dielectric sheets, a conductive paste for the internal electrodes 15 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode 15A is formed and a dielectric sheet on which the pattern of the second internal electrode 15B is formed are prepared.

[0045] A predetermined number of dielectric sheets without internal electrode patterns printed thereon are stacked to form the portion that will become the outer layer portion 12 on the first main surface AA side. A dielectric sheet with a first internal electrode 15A pattern printed thereon and a dielectric sheet with a second internal electrode 15B pattern printed thereon are stacked in this order to form the portion that will become the inner layer portion 11. A predetermined number of dielectric sheets without an internal electrode pattern printed thereon are stacked on top of this portion that will become the outer layer portion 12 on the second main surface AB side. In this way, a laminated sheet is produced.

[0046] A laminated block is produced by pressing the laminated sheets in the stacking direction using a means such as an isostatic press. At this time, each surface of the laminated sheets in the stacking direction T is covered with a rubber sheet material (referred to as "rubber"). Next, long round rod-shaped members (referred to as "push rods") are placed over the rubber at desired positions on each surface of the laminated sheets in the stacking direction T. In this state, the laminated sheets are pressed together with the rubber and push rods. This allows the push rods to bite into the laminated sheets, so that the conductive paste for the internal electrodes can be bent toward the center T2 in the stacking direction.

[0047] The bending of the conductive paste for the internal electrodes can be adjusted, for example, by adjusting the thickness and flexibility of the rubber. For example, a first press is performed using a thick rubber, and a second press is performed using a thinner rubber. By performing the pressing in multiple stages in this way, the laminated sheet is pressed while being deformed, and the bending of the conductive paste for the internal electrodes can be adjusted. In addition, by pressing the pressing rod into the laminated sheet, pressure is applied to the dielectric sheet. This allows air bubbles in the dielectric sheet to be removed, thereby suppressing the generation of voids in the dielectric layer.

[0048] Next, the laminated block is cut in the length direction L and the width direction W. By cutting the laminated block to a predetermined size, laminated chips are cut out. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0049] The laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrodes 15, but is preferably 900°C or higher and 1400°C or lower.

[0050] A conductive paste that will become the base electrode layer 31 is applied to both end surfaces of the laminate 2. In this embodiment, the base electrode layer 31 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 2 by a method such as dipping. A baking process is then performed to form the base electrode layer 31. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0051] In this embodiment, dipping is performed so that the base electrode layer 31 on the first end face CA side extends from the first end face CA to parts of the first principal face AA and the second principal face AB. Furthermore, dipping is performed so that the base electrode layer 31 on the second end face CB side extends from the second end face CB to parts of the first principal face AA and the second principal face AB. At the same time, dipping is preferably performed so that the base electrode layer on the first end face CA side extends to parts of the first side face BA and the second side face BB. Furthermore, dipping is preferably performed so that the base electrode layer 31 on the second end face CB side extends to parts of the first side face BA and the second side face BB.

[0052] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 14 as the ceramic material added. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 2 with the fired layer formed.

[0053] Thereafter, a plating layer is formed on the surface of the base electrode layer 31. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0054] In this manner, the multilayer ceramic capacitor 1 shown in FIG. 1 is obtained.

[0055] (Effects of the embodiment) According to this embodiment, the following effects can be obtained.

[0056] According to this embodiment, the first lead portion 15Ab has a bent portion 21 that bends to have an apex 22 on the center side T2 in the stacking direction. The shortest distance in the length direction L between the apex 22 of the bent portion 21 and the effective layer portion 10 is larger than the dimension of the dielectric layer 14 in the stacking direction T, and is smaller than the shortest distance in the length direction L between the apex 22 of the bent portion 21 and one of the end faces C (more specifically, the first end face CA) closest to the apex 22.

[0057] In the laminate 2, the vicinity of the boundary between the opposing portion of the internal electrode 15 and the lead-out portion is a region where the number of laminated layers in the laminate changes, and therefore voids are likely to occur near this boundary in the longitudinal direction L, particularly near the end of the internal electrode 15. If voids exist in this portion, electrostrictive cracks and poor moisture resistance are likely to occur starting from the voids. By adopting the configuration of this embodiment, it is possible to suppress the occurrence of voids that cause electrostrictive cracks and poor moisture resistance. In other words, the configuration of this embodiment is a configuration that allows the lead-out portion to be pressed so hard that a bend is formed, thereby filling the voids and suppressing the occurrence of voids.

[0058] According to this embodiment, the shortest distance in the length direction L between the vertex 22 of the bent portion 21 and the effective layer portion 10 is 50 μm or less.

[0059] According to this configuration, the voids can be filled more efficiently, and the electrostrictive resistance and moisture resistance can be further improved.

[0060] According to this embodiment, the first main surface side outermost first drawn portion 24 has a bent portion 21. The second main surface side outermost first drawn portion 25 has a bent portion 21. The length of the line segment connecting the vertex 22 of the bent portion 21 of the first main surface side outermost first drawn portion 24 and the vertex 22 of the bent portion 21 of the second main surface side outermost first drawn portion 25 is shorter than the length of the line segment connecting the end of the first main surface side outermost first drawn portion 24 on the first end face CA side and the end of the second main surface side outermost first drawn portion 25 on the first end face CA side.

[0061] According to this configuration, the voids can be filled more efficiently, and the electrostrictive resistance and moisture resistance can be further improved.

[0062] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0063] In the above embodiment, the apex of the bent portion 21 of the internal electrode 15 is located, for example, closer to the center T2 in the stacking direction than the portion of the dielectric layer 14 adjacent to the internal electrode 15 that constitutes the effective layer portion 10, but the apex of the bent portion 21 of the internal electrode 15 may be aligned in the length direction L with the portion of the dielectric layer 14 adjacent to the internal electrode 15 that constitutes the effective layer portion 10. However, the configuration of the above embodiment is preferable in that the desired effects can be more reliably obtained in the multilayer ceramic capacitor 1.

[0064] In the above embodiment, the structure of the multilayer ceramic capacitor 1 is generally symmetrical in the longitudinal direction L, but this is not limiting. The second lead portion 15Bb may or may not have a configuration corresponding to the bent portion 21 of the first lead portion 15Ab. However, the configuration of the above embodiment is preferable in that it can more reliably achieve the desired effects in the multilayer ceramic capacitor 1. [Explanation of symbols]

[0065] 1. Multilayer ceramic capacitors 2. Laminate 3 External electrode 10 Effective layer 14 Dielectric layer 15 Internal electrode 15a Opposite part 15b Drawer part 15Ab 1st drawer 21 Bend 22 Vertex 24 First main surface side outermost first drawer 25 outermost first drawer on second main surface side AA First principal surface AB Second principal surface BA 1st side BB 2nd side CA 1st end face CB 2nd end face

Claims

1. a laminate having an inner layer portion including a plurality of dielectric layers and a plurality of internal electrodes alternately stacked, a first main surface and a second main surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; external electrodes arranged in pairs on each of the end surfaces; A multilayer ceramic capacitor comprising: the internal electrodes each have an opposing portion opposing the internal electrode adjacent to the internal electrode in the stacking direction, and an extraction portion extracted from the opposing portion and connected to the external electrode, the laminate has an effective layer portion including each of the opposing portions and a portion of the dielectric layer sandwiched between the adjacent opposing portions, In the stacking direction, a direction from each of the main surfaces toward the center of the stacked body in the stacking direction is defined as a center side in the stacking direction, the pull-out portion has a bent portion that is bent so as to have an apex on the center side in the stacking direction, a multilayer ceramic capacitor, wherein the shortest distance in the length direction between the vertex of the bent portion and the effective layer portion is greater than a dimension of the dielectric layer in the stacking direction, and is smaller than the shortest distance in the length direction between the vertex of the bent portion and one of the end faces closest to the vertex.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the shortest distance in the length direction between the apex of the bent portion and the effective layer portion is 50 [mu]m or less.

3. the drawn-out portion drawn out from the facing portion toward the first end surface is defined as a first drawn-out portion, the first drawn portion located closest to the first main surface side among the first drawn portions is defined as a first main surface side outermost first drawn portion, When the first lead portion located closest to the second main surface among the first lead portions is defined as a second main surface side outermost first lead portion, 3. The multilayer ceramic capacitor according to claim 1, wherein a length of a line segment connecting the vertex of the bent portion of the first main surface side outermost first lead portion and the vertex of the bent portion of the second main surface side outermost first lead portion is shorter than a length of a line segment connecting an end portion of the first main surface side outermost first lead portion on the first end face side and an end portion of the second main surface side outermost first lead portion on the first end face side.

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