Monitoring circuit

Abstract

To provide a monitoring circuit capable of detecting an error in data stored in a register in real time.SOLUTION: A monitoring circuit includes: a parity generation circuit that constantly generates and outputs a parity bit for data stored in a register; a storage circuit that stores the parity bit generated by the parity generation circuit in synchronization with a clock signal and constantly outputs it; and a detection circuit that constantly detects whether the parity bit output from the parity generation circuit and the parity bit output from the storage circuit match.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed technology relates to a monitoring circuit. [Background technology]

[0002] Patent Document 1 discloses a bit phase synchronization circuit comprising: parity bit generation means for generating a parity bit of input data for each word; a memory for writing the input data and the parity bit generated by the parity bit generation means for each word according to a write address and reading out the input data according to a read address; write address generation means for generating the write address based on an input clock; read address generation means for generating the read address based on a clock having a phase independent of the input clock; parity bit detection means for generating a parity bit for data read from the memory for each word and outputting a first parity alarm when the parity bit differs from the parity bit read from the memory; and protection means for monitoring the first parity alarm output from the parity bit detection means for each address of the memory and outputting a second parity alarm when the first parity alarm for the same address has been output a predetermined number of times in succession.

[0003] Patent Document 2 discloses a bit phase synchronization circuit comprising: parity bit generation means for generating a parity bit of input data for each word; a memory for writing the input data and the parity bit generated by the parity bit generation means for each word according to a write address and reading out the input data according to a read address; write address generation means for generating the write address based on an input clock; read address generation means for generating the read address based on a clock having a phase independent of the input clock; parity bit detection means for generating a parity bit for each word of data read from the memory and outputting a first parity alarm when the parity bit differs from the parity bit read from the memory; and protection means for monitoring the first parity alarm output from the parity bit detection means for each address of the memory and outputting a second parity alarm when the first parity alarm for the same address has been output a predetermined number of times in succession.

[0004] Patent Document 3 describes a fault detection circuit for an elastic store memory (1) that writes serially transmitted data in synchronization with a write clock and sequentially reads the written data in synchronization with a read clock, and includes a first serial / parallel conversion unit (2) that is connected to a data transmission path on the write side of the elastic store memory (1) and converts data to be written to the elastic store memory (1) in parallel in predetermined bit units, a first parity generation unit (3) that generates parity bits for the parallel data converted by the first serial / parallel conversion unit (2), and a parity detection circuit (4) that temporarily stores the parity bits generated by the first parity generation unit (3). a second serial / parallel conversion unit (8) connected to a data transmission path on the read side of the elastic store memory (1) and converting data read from the elastic store memory (1) into parallel data in predetermined bit units; a second parity generation unit (9) generating a parity bit of the parallel data converted by the second serial / parallel conversion unit (8); and a parity comparison unit (10) comparing the parity bit generated by the second parity generation unit (9) with the corresponding parity bit held in the register unit (4). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-143118 [Patent Document 2] Japanese Patent Application Publication No. 10-340596 [Patent Document 3] Japanese Patent Application Publication No. 6-274313 Summary of the Invention [Problem to be solved by the invention]

[0006] Conventionally, methods have been proposed for detecting data errors by periodically reading data stored in a register such as a special function register and checking the data itself, or by checking the CRC (Cyclic Redundancy Check) of the read data.

[0007] However, the method of periodically reading and checking data from a register has the problem that it is difficult to detect data errors in real time.

[0008] The disclosed technology has been made to solve the above-mentioned problems, and aims to provide a monitoring circuit that can detect errors in data stored in a register in real time. [Means for solving the problem]

[0009] The monitoring circuit according to the first aspect includes a parity generation circuit that constantly generates and outputs a parity bit of data stored in a register, a memory circuit that stores the parity bit generated by the parity generation circuit in synchronization with a clock signal and constantly outputs it, and a detection circuit that constantly detects whether the parity bit output from the parity generation circuit matches the parity bit output from the memory circuit. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a block diagram of a monitoring circuit according to the first embodiment. [Figure 2] FIG. 10 is a block diagram of a monitoring circuit according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings.

[0012] First Embodiment

[0013] 1 is a block diagram of a monitoring circuit 10 according to this embodiment. The monitoring circuit 10 is a circuit that monitors whether data written to a register RG has changed unintentionally for some reason. Data is written to the register RG in synchronization with a clock signal CLK1. The register RG is a register that can store n-bit (n is a positive number) data, and in this embodiment, a special function register (SFR) is used as an example, but the present invention is not limited to this.

[0014] The monitoring circuit 10 includes a parity generation circuit 12, a storage circuit 14, and a detection circuit 16.

[0015] The parity generation circuit 12 constantly generates and outputs a parity bit for the data stored in the register RG. Specifically, the parity generation circuit 12 reads each bit of the register RG and calculates the number of bits in which "1" is stored. If the number of bits in which "1" is stored is odd, the parity bit is set to "1," and if the number of bits in which "1" is stored is even, the parity bit is set to "0."

[0016] Furthermore, the parity generation circuit 12 does not generate a parity bit when requested by a host device, but instead constantly generates and outputs a parity bit in synchronization with, for example, a clock signal (not shown).

[0017] The memory circuit 14 stores and constantly outputs the parity bit output from the parity generation circuit 12 in synchronization with the clock signal CLK2. That is, the memory circuit 14 does not store and constantly output the parity bit when requested by a higher-level device, but constantly stores and constantly outputs the parity bit as long as the clock signal CLK2 is input. In this embodiment, the memory circuit 14 is configured with a D flip-flop circuit, as an example.

[0018] The detection circuit 16 constantly detects whether the parity bit output from the parity generation circuit 12 matches the parity bit output from the memory circuit 14. The detection circuit 16 outputs a mismatch detection signal A that is low when the two match and high when the two do not match.

[0019] Specifically, the detection circuit 16 includes a comparison circuit 18 and a mask circuit 20 .

[0020] The comparison circuit 18 compares the parity bit output from the parity generation circuit 12 with the parity bit output from the memory circuit 14, and outputs a comparison result signal to the mask circuit 20 that is high if the two bits match and low if they do not match.

[0021] The mask circuit 20 masks the comparison result signal output from the comparison circuit 18 while data is being written to the register RG. Specifically, the mask circuit 20 is configured with an AND circuit. An inverted signal of the comparison result signal output from the comparison circuit 18 is input to one input terminal of the mask circuit 20, and an inverted mask signal obtained by inverting the mask signal MSK is input to the other input terminal of the mask circuit 20.

[0022] The mask signal MSK is a signal that is at a high level while data is being written to the register RG and at a low level otherwise. Therefore, when the mask signal MSK is at a high level, i.e., while data is being written to the register RG, the mask circuit 20 outputs a low level regardless of the comparison result signal input to one input terminal. In other words, while data is being written to the register RG, the mask circuit 20 masks the comparison result signal and fixes the output signal to a low level.

[0023] On the other hand, when the mask signal MSK is at a low level, i.e., during a period when no data is written to the register RG, the mask circuit 20 outputs a signal that is an inversion of the comparison result signal input to one input terminal. In other words, during a period when no data is written to the register RG, the mask circuit 20 outputs a mismatch detection signal A that is at a low level if the parity bit output from the parity generation circuit 12 and the parity bit output from the memory circuit 14 match, and is at a high level if they do not match.

[0024] Incidentally, a delay signal "delay" delayed by a predetermined time after a write instruction signal instructing the register RG to write data to the register RG is output to the register RG is input to the memory circuit 14. When the delay signal "delay" is input, the memory circuit 14 stores the parity bit output from the parity generation circuit 12. That is, the delay signal "delay" delayed by a predetermined time is input to the memory circuit 14, taking into consideration the time from when a write instruction signal instructing the register RG to write data to the register RG is output to the register RG until the parity bit is generated and output by the parity generation circuit 12. This allows the memory circuit 14 to reliably store and output the parity bit of the data written to the register RG.

[0025] Therefore, it is possible to prevent an erroneous mismatch detection signal A from being output from the detection circuit 16 due to a time lag occurring between the update timing of the data in the register RG and the update timing of the parity bit stored in the memory circuit 14.

[0026] As described above, in this embodiment, a parity bit for the data stored in register RG is constantly generated and stored in the memory circuit 14, and it is constantly detected whether the parity bit output from the parity generation circuit 12 matches the parity bit output from the memory circuit 14. This makes it possible to detect errors in the data of register RG in real time, even if the data stored in register RG changes for some reason. This makes it possible to quickly protect the system when the data in register RG changes unintentionally.

[0027] Second Embodiment

[0028] Next, a second embodiment will be described. Note that the same parts as those in the first embodiment are given the same reference numerals and detailed description thereof will be omitted.

[0029] 2 shows a monitoring circuit 10A according to the second embodiment. The monitoring circuit 10A has a configuration in which an inversion circuit 22 is added to the monitoring circuit 10 described in the first embodiment.

[0030] When instructed to execute a diagnostic mode for diagnosing whether the detection circuit 16 is operating normally, the inversion circuit 22 outputs a signal that is an inversion of the parity bit output from the parity generation circuit 12 to the detection circuit 16.

[0031] Specifically, the inversion circuit 22 includes a NOT circuit 24 and a multiplexer 26 .

[0032] The NOT circuit 24 inverts the parity bit output from the parity generation circuit 12 and outputs the inverted parity bit to the multiplexer 26 .

[0033] When the input mode signal "mode" indicates the diagnostic mode, the multiplexer 26 outputs the inverted parity bit output from the NOT circuit 24 to the comparison circuit 18. On the other hand, when the input mode signal "mode" indicates the normal operation mode, the multiplexer 26 outputs the parity bit output from the parity generation circuit 12 to the comparison circuit 18.

[0034] That is, in the diagnostic mode, the inversion circuit 22 intentionally outputs an incorrect parity bit to the comparison circuit 18. Therefore, when the detection circuit 16 is normal, the detection circuit 16 outputs a high level as the mismatch detection signal A indicating that the parity bits do not match. On the other hand, when some abnormality occurs in the detection circuit 16, the detection circuit 16 outputs a low level as the mismatch detection signal A indicating that the parity bits match, even though an incorrect parity bit is input to the comparison circuit 18. As a result, in the diagnostic mode, when the detection circuit 16 outputs a high level, it can be determined that the detection circuit 16 is normal, and when the detection circuit 16 outputs a low level, it can be determined that the detection circuit 16 is abnormal.

[0035] In this way, by providing the inversion circuit 22 between the parity generation circuit 12 and the detection circuit 16, an abnormality in the detection circuit 16 can be detected.

[0036] It goes without saying that the configurations, operations, etc. of the monitoring circuits described in the above embodiments are merely examples, and can be modified according to circumstances within the scope of the present disclosure.

[0037] The following additional notes are further disclosed regarding the above embodiment.

[0038] (Appendix 1) a parity generation circuit that constantly generates and outputs a parity bit of data stored in a register; a memory circuit that stores the parity bit generated by the parity generation circuit in synchronization with a clock signal and outputs the stored parity bit at all times; a detection circuit that constantly detects whether the parity bit output from the parity generation circuit and the parity bit output from the storage circuit match; A monitoring circuit comprising: (Appendix 2) The detection circuit a comparison circuit that compares the parity bit output from the parity generation circuit with the parity bit output from the storage circuit; a mask circuit that masks the comparison result output from the comparator circuit while the data is being written to the register; Contains The monitoring circuit described in Appendix 1. (Appendix 3) The storage circuit stores the parity bit output from the parity generation circuit when a delay signal delayed by a predetermined time is input after a write instruction signal instructing the register to write the data is output to the register. 1. A monitoring circuit as defined in claim 1 or 2. (Appendix 4) an inversion circuit that outputs a signal obtained by inverting the parity bit output from the parity generation circuit to the detection circuit when a diagnostic mode for diagnosing whether the detection circuit operates normally is instructed to be executed; 4. The monitoring circuit according to claim 1, further comprising: [Explanation of symbols]

[0039] 10, 10A monitoring circuit 12 Parity generation circuit 14 Memory circuit 16 Detection circuit 18 Comparison circuit 20 Mask Circuit 22 Inverting circuit 24 circuits 26 Multiplexer

Claims

1. a parity generation circuit that constantly generates and outputs a parity bit of data stored in a register; a memory circuit that stores the parity bit generated by the parity generation circuit in synchronization with a clock signal and outputs the stored parity bit at all times; a detection circuit that constantly detects whether the parity bit output from the parity generation circuit and the parity bit output from the storage circuit match; A monitoring circuit comprising:

2. The detection circuit a comparison circuit that compares the parity bit output from the parity generation circuit with the parity bit output from the storage circuit; a mask circuit that masks the comparison result output from the comparator circuit while the data is being written to the register; Contains 2. The monitoring circuit of claim 1.

3. The storage circuit stores the parity bit output from the parity generation circuit when a delay signal delayed by a predetermined time is input after a write instruction signal instructing the register to write the data is output to the register.

2. The monitoring circuit of claim 1.

4. an inversion circuit that outputs a signal obtained by inverting the parity bit output from the parity generation circuit to the detection circuit when a diagnostic mode for diagnosing whether the detection circuit operates normally is instructed to be executed; The monitoring circuit according to any one of claims 1 to 3, comprising:

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