Semiconductor device, and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of detecting peeling of a sealing resin in the vicinity of a wire joint position of a lead, even if there is an inclined surface in the sealing resin.SOLUTION: A semiconductor device A10 includes: a conductive support member 2 which includes a die pad 3 having a main surface 31 facing a first side z1 in a thickness direction z, and an input side terminal 51c that is separated from the die pad 3 and is wholly positioned on a side closer to the first side x1 in a first direction x than the die pad 3; a semiconductor element 11 mounted on the main surface 31; a wire 61 which is conductively bonded to the semiconductor element 11 and the input side terminal 51c; and a sealing resin 7. The sealing resin 7 includes: a top surface 71 facing the first side z1 in the thickness direction z; a side face 73 that faces the first side x1 in the first direction x, to which a part of the input side terminal 51c projects; and an inclined surface 77 which is connected to the top surface 71 and the side surface 73, and has an angle formed by the main surface 31 and itself larger than the top surface 71. A joint part 61a to the input side terminal 51c of the wire 61 does not overlap the inclined surface 77, when being viewed in the thickness direction z.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices equipped with semiconductor elements (such as MOSFETs and IGBTs) having switching functions have been widely known. Patent Document 1 discloses an example of such a semiconductor device. The semiconductor device disclosed in this document is packaged in a small outline package (SOP) and includes a semiconductor element, a die pad, multiple leads, and a sealing resin. The semiconductor element is mounted on the die pad. Multiple leads are arranged on both sides of the die pad, and each is electrically connected to the semiconductor element via a wire. The sealing resin covers the semiconductor element, and portions of the multiple leads protrude from both side surfaces. Since semiconductor devices are generally symmetrical in appearance, they are provided with visible marks from the exterior to prevent incorrect mounting orientation. For example, some semiconductor devices have a notch (inclined surface) in the sealing resin.

[0003] Furthermore, scanning acoustic tomography (SAT) testing may be performed to non-destructively detect peeling, voids, cracks, and the like in semiconductor devices. In SAT testing, ultrasonic waves are irradiated onto a semiconductor device, and internal information about the semiconductor device is obtained from the reflected waves. However, if the encapsulation resin of the semiconductor device has an inclined surface, the ultrasonic waves irradiated in the SAT testing are reflected by the inclined surface, making it impossible to obtain internal information about the portion overlapping the inclined surface. In this case, even if peeling occurs in the overlapping portion, it cannot be detected. If a wire is bonded to the overlapping portion, the wire may break due to undetected peeling. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-143167

[0005] [overview] SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor device that can detect peeling of the sealing resin near the wire bonding position of the lead even when the sealing resin has an inclined surface.

[0006] A semiconductor device provided by a first aspect of the present disclosure comprises: a die pad having a die pad main surface facing a first side in a thickness direction; a conductive support member spaced from the die pad and including a first terminal located entirely on a first side of the die pad in a first direction perpendicular to the thickness direction; a semiconductor element mounted on the die pad main surface; a wire conductively joined to the semiconductor element and the first terminal; and a sealing resin covering at least a portion of the conductive support member, the semiconductor element, and the wire, wherein the sealing resin comprises a resin top surface facing the first side in the thickness direction; a first resin side surface facing the first side in the first direction and exposing the first terminal; and an inclined surface connected to the resin top surface and the first resin side surface and forming an angle with the die pad main surface that is larger than the resin top surface, and when viewed in the thickness direction, a joining portion of the wire to the first terminal does not overlap the inclined surface.

[0007] A manufacturing method of a semiconductor device provided by a second aspect of the present disclosure includes an element bonding process of bonding a semiconductor element to a main surface of a lead frame facing a first side in the thickness direction of the lead frame; a wire bonding process of bonding a wire to the semiconductor element and the lead frame; a resin forming process of forming a sealing resin that covers at least a portion of the lead frame, the semiconductor element, and the wire; a bending process of bending an exposed portion of the lead frame that is exposed from the sealing resin; and a cutting process of cutting the exposed portion.In the resin forming process, the sealing resin has a resin top surface facing the first side in the thickness direction, a first resin side surface from which a portion of the lead frame is exposed, and an inclined surface that is connected to the resin top surface and the first resin side surface and forms an angle with the main surface of the lead frame that is larger than the resin top surface, and the inclined surface is formed so that it does not overlap the joint portion of the wire to the lead frame when viewed in the thickness direction.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the semiconductor device of FIG. 1, seen through the sealing resin. [Figure 3] FIG. 3 is a front view showing the semiconductor device of FIG. [Figure 4] FIG. 4 is a rear view showing the semiconductor device of FIG. [Figure 5] FIG. 5 is a left side view showing the semiconductor device of FIG. [Figure 6] FIG. 6 is a right side view showing the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9]FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a plan view showing a process according to the method for manufacturing the semiconductor device of FIG. [Figure 12] 12A to 12C are plan views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 13] 13A to 13C are plan views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] 15A to 15C are plan views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a plan view showing the semiconductor device according to the second embodiment of the present disclosure, seen through the sealing resin. [Figure 18] FIG. 18 is a plan view showing a semiconductor device according to a third embodiment of the present disclosure, seen through a sealing resin. [Figure 19] FIG. 19 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure, seen through a sealing resin. [Figure 20] FIG. 20 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 21] FIG. 21 is a plan view showing a semiconductor device according to the sixth embodiment of the present disclosure. [Figure 22] FIG. 22 is a front view showing the semiconductor device of FIG. [Figure 23] FIG. 23 is a plan view showing a semiconductor device according to the seventh embodiment of the present disclosure.

[0010] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Additionally, unless otherwise specified, "something A overlaps something B when viewed from a certain direction" includes "something A overlaps the entirety of something B" and "something A overlaps part of something B."

[0012] [First embodiment] 1 to 10 show an example of a semiconductor device according to the present disclosure. The semiconductor device A10 of this embodiment includes a semiconductor element 11, a semiconductor element 12, an insulating element 13, a conductive support member 2, a plurality of wires 61, a plurality of wires 62, a plurality of wires 63, a plurality of wires 64, and a sealing resin 7. The conductive support member 2 includes a die pad 3, a die pad 4, a plurality of input terminals 51, and a plurality of output terminals 52. The semiconductor device A10 is surface-mounted on a wiring board of an inverter device of, for example, an electric vehicle or a hybrid vehicle. The application and function of the semiconductor device A10 are not limited. The package format of the semiconductor device A10 is a small outline package (SOP). However, the package format of the semiconductor device A10 is not limited to an SOP.

[0013] FIG. 1 is a plan view showing the semiconductor device A10. FIG. 2 is a plan view showing the semiconductor device A10. In FIG. 2, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. FIG. 3 is a front view showing the semiconductor device A10. FIG. 4 is a rear view showing the semiconductor device A10. FIG. 5 is a left side view showing the semiconductor device A10. FIG. 6 is a right side view showing the semiconductor device A10. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 1. FIG. 10 is a cross-sectional view taken along line XX in FIG. 1.

[0014] The semiconductor device A10 has a rectangular shape when viewed in the thickness direction (plan view). For ease of explanation, the thickness direction (plan view) of the semiconductor device A10 is referred to as the thickness direction z, the direction along one side of the semiconductor device A10 perpendicular to the thickness direction z (the left-right direction in FIGS. 1 and 2) is referred to as the first direction x, and the direction perpendicular to the thickness direction z and the first direction x (the up-down direction in FIGS. 1 and 2) is referred to as the second direction y. Furthermore, one side of the thickness direction z (the upper side in FIGS. 3 to 8) is referred to as the first side z1, and the other side (the lower side in FIGS. 3 to 8) is referred to as the second side z2. One side of the first direction x (the left side in FIGS. 1 and 2) is referred to as the first side x1, and the other side (the right side in FIGS. 1 and 2) is referred to as the second side x2. One side of the second direction y (the upper side in FIGS. 1 and 2) is referred to as the first side y1, and the other side (the lower side in FIGS. 1 and 2) is referred to as the second side y2. The shape and dimensions of the semiconductor device A10 are not limited.

[0015] The semiconductor elements 11 and 12 are elements that are the core of the function of the semiconductor device A10.

[0016] As shown in FIG. 2 , the semiconductor element 11 is mounted on a part of the conductive support member 2 (a die pad 3 described later) and is disposed at the center of the die pad 3 in the second direction y, closer to the first side x1 than the center in the first direction x. The semiconductor element 11 has a rectangular shape that is long in the second direction y when viewed in the thickness direction z. The semiconductor element 11 is a control element and includes a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the semiconductor element 12, and a reception circuit that receives an electrical signal from the semiconductor element 12. A plurality of electrodes (not shown) are provided on the top surface of the semiconductor element 11 (the surface facing the first side z1). These electrodes are electrically connected to circuits configured in the semiconductor element 11.

[0017] As shown in FIG. 2 , the semiconductor element 12 is mounted on a portion of the conductive support member 2 (a die pad 4 described later) and is disposed at the center of the die pad 4 in the second direction y and the center in the first direction x. The semiconductor element 12 has a rectangular shape elongated in the second direction y when viewed in the thickness direction z. The semiconductor element 12 is a driving element and includes a receiving circuit that receives a PWM control signal transmitted from the semiconductor element 11, a circuit (gate driver) that performs a switching operation of a switching element (e.g., an IGBT or a MOSFET) based on the PWM control signal, and a transmitting circuit that transmits an electrical signal to the semiconductor element 11. The electrical signal may be, for example, an output signal from a temperature sensor installed near a motor. A plurality of electrodes (not shown) are provided on the upper surface (the surface facing the first side z1) of the semiconductor element 12. These electrodes are electrically connected to a circuit configured in the semiconductor element 12.

[0018] 2, the insulating element 13 is mounted on the die pad 3 and is disposed at the center of the die pad 3 in the second direction y, closer to the second side x2 than the center in the first direction x. In other words, the insulating element 13 is disposed on the second side x2 in the first direction x of the semiconductor element 11. As will be described later, the die pad 3 is disposed on the first side x1 in the first direction x of the die pad 4. Therefore, the insulating element 13 is located between the semiconductor elements 11 and 12 in the first direction x. The semiconductor element 11 has a rectangular shape that is longer in the second direction y when viewed in the thickness direction z.

[0019] Isolation element 13 is an element for transmitting PWM control signals, electrical signals, and the like in an insulated state. Isolation element 13 receives a PWM control signal from semiconductor element 11 and transmits the received PWM control signal to semiconductor element 12 in an insulated state. Isolation element 13 also receives an electrical signal from semiconductor element 12 and transmits the received electrical signal to semiconductor element 11 in an insulated state. In other words, isolation element 13 relays signal transmission and reception between semiconductor element 11 and semiconductor element 12 and insulates semiconductor element 11 from semiconductor element 12. Semiconductor element 12 (drive element) requires a higher voltage than semiconductor element 11 (control element). Isolation element 13 is necessary because a significant potential difference occurs between the input side circuit including semiconductor element 11 and the output side circuit including semiconductor element 12. Specifically, in an inverter device for an electric vehicle or a hybrid vehicle, for example, the power supply voltage supplied to semiconductor element 11 is approximately 5 V, while the power supply voltage supplied to semiconductor element 12 is approximately 600 V or higher.

[0020] In this embodiment, the insulating element 13 is an inductor-coupled insulating element. An inductor-coupled insulating element transmits electrical signals in an isolated state by inductively coupling two inductors (coils). The insulating element 13 has a substrate made of, for example, Si. An inductor made of Cu is formed on the substrate. The inductors include a transmitting inductor and a receiving inductor, which are stacked on top of each other in the thickness direction of the insulating element 13. A dielectric layer made of, for example, SiO2 is interposed between the transmitting inductor and the receiving inductor. The dielectric layer electrically insulates the transmitting inductor from the receiving inductor. In this embodiment, the insulating element 13 is an inductor-coupled insulating element, but it may also be a capacitor-coupled insulating element. One example of a capacitor-coupled insulating element is a capacitor. A plurality of electrodes (not shown) are provided on the upper surface of the insulating element 13 (the surface facing the first side z1). These electrodes are electrically connected to the inductors formed in the insulating element 13.

[0021] In the semiconductor device A10, the conductive support member 2 is a member that forms a conductive path between the semiconductor elements 11 and 12 and the wiring board of the inverter device. The conductive support member 2 is made of, for example, an alloy containing Cu. The conductive support member 2 is formed from a lead frame 81, which will be described later. The semiconductor elements 11 and 12 and the insulating element 13 are mounted on the conductive support member 2. As shown in FIG. 2 , the conductive support member 2 includes a die pad 3, a die pad 4, a plurality of input terminals 51, and a plurality of output terminals 52.

[0022] The die pad 3 is disposed at the center of the semiconductor device A10 in the second direction y, closer to the first side x1 than the center in the first direction x. The die pad 4 is disposed on the second side x2 in the first direction x relative to the die pad 3 and spaced apart from the die pad 3.

[0023] As shown in FIGS. 2 and 7, the die pad 3 has a semiconductor element 11 and an insulating element 13 mounted thereon. The die pad 3 has, for example, a substantially rectangular shape when viewed in the thickness direction z. The die pad 3 has a main surface 31 and a back surface 32. The main surface 31 and the back surface 32 are spaced apart in the thickness direction z as shown in FIGS. 7 and 8. The main surface 31 faces a first side z1, and the back surface 32 faces a second side z2. The main surface 31 and the back surface 32 are each substantially flat. The semiconductor element 11 and the insulating element 13 are bonded to the main surface 31 by a conductive bonding material (such as solder, metal paste, or sintered metal) not shown.

[0024] As shown in FIGS. 2 and 7, the die pad 4 has a semiconductor element 12 mounted thereon. The die pad 4 has, for example, a substantially rectangular shape when viewed in the thickness direction z. The die pad 4 has a main surface 41 and a back surface 42. The main surface 41 and the back surface 42 are spaced apart in the thickness direction z as shown in FIG. 7. The main surface 41 faces the first side z1, and the back surface 42 faces the second side z2. The main surface 41 and the back surface 42 are each substantially flat. The semiconductor element 12 is bonded to the main surface 41 of the die pad 4 by a conductive bonding material (not shown).

[0025] 2 and 7, the die pad 3 and the die pad 4 are spaced apart in the first direction x, and a sealing resin 7 is interposed between the die pad 3 and the die pad 4. As will be described later, the sealing resin 7 has electrical insulation properties. Therefore, the die pad 3 and the die pad 4 are electrically insulated by the insulating element 13 and the sealing resin 7.

[0026] The input terminals 51 are bonded to a wiring board of an inverter device to form a conductive path between the semiconductor device A10 and the wiring board. As shown in FIGS. 1, 2, and 5, the input terminals 51 are spaced apart from one another and arranged along the second direction y. Each of the input terminals 51 is located on a first side x1 in the first direction x with respect to the die pad 3 and protrudes from the sealing resin 7 (a side surface 73 described below) toward the first side x1 in the first direction x. The input terminals 51 include a power supply terminal to which a voltage is supplied, a ground terminal, an input terminal to which a control input signal is input, and an input terminal to which other control signals are input. In this embodiment, the semiconductor device A10 has eight input terminals 51. The number of input terminals 51 is not limited. Each input terminal 51 has a lead portion 511 and a pad portion 512.

[0027] The lead portion 511 is a substantially rectangular portion extending along the first direction x. The lead portion 511 includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIG. 7 , the portion of the lead portion 511 exposed from the sealing resin 7 is bent into a gull-wing shape. The portion of the lead portion 511 exposed from the sealing resin 7 may be plated. The plating layer formed by the plating process is made of an alloy containing Sn, such as solder, and covers the portion exposed from the sealing resin 7. The plating layer improves solder adhesion to the exposed portion and prevents erosion of the exposed portion due to soldering when the semiconductor device A10 is surface-mounted on a wiring board of an inverter device by soldering. The lead portions 511 of the multiple input terminals 51 are spaced apart from each other and arranged at equal intervals along the second direction y.

[0028] The pad portion 512 is connected to the second side x2 of the lead portion 511 in the first direction x and is wider than the lead portion 511 in the second direction y. The shape of each pad portion 512 as viewed in the thickness direction z is not limited, but is preferably such that each pad portion 512 is close to the die pad 3 and is spaced apart from each other by a predetermined distance or more. The upper surfaces of the pad portions 512 (the surfaces facing the first side z1) may be plated. A plating layer formed by this plating process is made of a metal containing Ag, for example, and covers the upper surfaces of the pad portions 512. This plating layer enhances the bonding strength of the wires 61 (described later) and protects the lead frame 81 (described later) from impacts during wire bonding of the wires 61. The entire surface of the pad portion 512 is covered with the sealing resin 7. The pad portion 512 is substantially flat. 2 and 7, in this embodiment, the pad portion 512 does not overlap a later-described inclined surface 77 of the sealing resin 7 when viewed in the thickness direction z. The dotted area in FIG. 2 and the area R shown in FIG. 7 are areas of each input terminal 51 that overlap the inclined surface 77.

[0029] The input terminals 51 include an input terminal 51a, an input terminal 51b, and a plurality of input terminals 51c. As shown in FIG. 2, the input terminal 51a is arranged fourth from the first side y1 in the second direction y among the input terminals 51. The input terminal 51a is connected to an end of the die pad 3 on the first side x1 in the first direction x by a pad portion 512. As shown in FIG. 2, the input terminal 51b is arranged closest to the second side y2 in the second direction y among the input terminals 51. The input terminal 51b is connected to an end of the die pad 3 on the second side y2 in the second direction y by a pad portion 512. The input terminal 51a and the input terminal 51b support the die pad 3. As shown in FIG. 2, the input terminal 51c is arranged third, fifth, and sixth from the first side y1 in the second direction y among the input terminals 51. Each input terminal 51c is entirely located on the first side x1 in the first direction x from the die pad 3. A wire 61 is joined to the pad portion 512 of each input terminal 51 other than the input terminal 51a. The input terminals 51 may include so-called dummy terminals to which no wire 61 is joined and which are not electrically connected to the semiconductor element 11. The shape of each input terminal 51 is not limited.

[0030] Like the input terminals 51, the output terminals 52 are bonded to a wiring board of an inverter device to form a conductive path between the semiconductor device A10 and the wiring board. As shown in FIGS. 1, 2, and 6, the output terminals 52 are spaced apart from one another and arranged along the second direction y. Each of the output terminals 52 is located on a second side x2 in the first direction x with respect to the die pad 4 and protrudes from the sealing resin 7 (a side surface 74 described below) toward the second side x2 in the first direction x. The output terminals 52 include a power supply terminal to which a voltage is supplied, a ground terminal, an output terminal, and the like. In this embodiment, the semiconductor device A10 includes eight output terminals 52. The number of output terminals 52 is not limited. Each output terminal 52 includes a lead portion 521 and a pad portion 522.

[0031] The lead portion 521 is a substantially rectangular portion extending along the first direction x. The lead portion 521 includes a portion exposed from the sealing resin 7 and a portion covered by the sealing resin 7. As shown in FIG. 7, the portion of the lead portion 521 exposed from the sealing resin 7 is bent into a gull-wing shape. Similar to the lead portion 511, a plating layer (for example, an alloy containing Sn, such as solder) may be formed on the portion of the lead portion 521 exposed from the sealing resin 7. The lead portions 521 of the multiple output-side terminals 52 are spaced apart from each other and arranged at equal intervals along the second direction y.

[0032] The pad portion 522 is connected to the first side x1 of the lead portion 521 in the first direction x and is wider than the lead portion 521 in the second direction y. The shape of each pad portion 522 as viewed in the thickness direction z is not limited, but is preferably such that each pad portion 522 is close to the die pad 4 and is spaced apart from each other by a predetermined distance or more. The upper surface of the pad portion 522 (the surface facing the first side z1) may be covered with a plating layer (e.g., a metal containing Ag), similar to the upper surface of the pad portion 512. The entire surface of the pad portion 522 is covered with the sealing resin 7. The pad portion 522 is substantially flat. In this embodiment, as shown in FIGS. 2 and 7, the pad portion 522 does not overlap a side surface 74 (described later) of the sealing resin 7 as viewed in the thickness direction z.

[0033] The multiple output terminals 52 include an output terminal 52a, an output terminal 52b, and multiple output terminals 52c. As shown in FIG. 2, the output terminal 52a is arranged closest to the first side y1 in the second direction y among the multiple output terminals 52. The output terminal 52a is connected to an end of the die pad 4 on the first side y1 in the second direction y by a pad portion 522. As shown in FIG. 2, the output terminal 52b is arranged closest to the second side y2 in the second direction y among the multiple output terminals 52. The output terminal 52b is connected to an end of the die pad 4 on the second side y2 in the second direction y by a pad portion 522. The output terminals 52a and 52b support the die pad 4. As shown in FIG. 2, the output terminal 52c is arranged second to sixth from the first side y1 in the second direction y among the multiple output terminals 52. Each output terminal 52c is entirely located on the second side x2 in the first direction x from the die pad 4. A wire 62 is joined to the pad portion 512 of each output terminal 52 other than the output terminal 52b. The multiple output terminals 52 may include so-called dummy terminals to which no wire 62 is joined and which are not electrically connected to the semiconductor element 12. The shape of each output terminal 52 is not limited.

[0034] 2 and 7, the plurality of wires 61, the plurality of wires 62, the plurality of wires 63, and the plurality of wires 64, together with the conductive support member 2, form a conductive path for the semiconductor elements 11 and 12 to perform predetermined functions. The material of each of the plurality of wires 61, the plurality of wires 62, the plurality of wires 63, and the plurality of wires 64 is a metal containing, for example, Au, Cu, or Al.

[0035] The plurality of wires 61 form conductive paths between the semiconductor element 11 and the plurality of input terminals 51. The plurality of wires 61 electrically connect the semiconductor element 11 to at least one of the plurality of input terminals 51. As shown in FIG. 2, each of the plurality of wires 61 is joined to one of the electrodes of the semiconductor element 11 and a pad portion 512 of one of the input terminals 51. As shown in FIGS. 2 and 7, the pad portion 512 does not overlap the inclined surface 77 when viewed in the thickness direction z, and therefore the joint portion 61a of the wire 61 to the pad portion 512 does not overlap the inclined surface 77.

[0036] The plurality of wires 62 form conductive paths between the semiconductor element 12 and the plurality of output terminals 52. The plurality of wires 62 electrically connect the semiconductor element 12 to at least one of the plurality of output terminals 52. As shown in FIG. 2, each of the plurality of wires 62 is joined to one of the electrodes of the semiconductor element 12 and a pad portion 522 of one of the output terminals 52. As shown in FIGS. 2 and 7, the pad portion 522 does not overlap the side surface 74 when viewed in the thickness direction z, and therefore the joint portion of the wire 62 to the pad portion 522 does not overlap the side surface 74.

[0037] The plurality of wires 63 form a conductive path between the semiconductor element 11 and the insulating element 13. The plurality of wires 63 electrically connect the semiconductor element 11 to the insulating element 13. As shown in FIG. 2 , each of the plurality of wires 63 is joined to one of the electrodes of the semiconductor element 11 and one of the electrodes of the insulating element 13.

[0038] The plurality of wires 64 form a conductive path between the insulating element 13 and the semiconductor element 12. The insulating element 13 is electrically connected to the semiconductor element 12 by the plurality of wires 64. As shown in FIG. 2 , each of the plurality of wires 64 is joined to one of the electrodes of the insulating element 13 and one of the electrodes of the semiconductor element 12.

[0039] As shown in FIG. 1, the sealing resin 7 covers the semiconductor element 11, the semiconductor element 12, the insulating element 13, the die pad 3, the die pad 4, the plurality of wires 61 to 64, and a portion of each of the plurality of input terminals 51 and output terminals 52. The sealing resin 7 has electrical insulation properties. The sealing resin 7 is made of a material containing, for example, black epoxy resin. When viewed in the thickness direction z, the sealing resin 7 has a rectangular shape that is long in the second direction y. The sealing resin 7 is formed, for example, by transfer molding using a mold.

[0040] As shown in FIGS. 3 to 6, the sealing resin 7 has a top surface 71, a bottom surface 72, side surfaces 73 to 76, and an inclined surface 77.

[0041] The top surface 71 and the bottom surface 72 are located apart from each other in the thickness direction z. The top surface 71 and the bottom surface 72 face opposite each other in the thickness direction z. The top surface 71 is located on a first side z1 in the thickness direction z and faces the first side z1, just like the main surface 31 of the die pad 3. The bottom surface 72 is located on a second side z2 in the thickness direction z and faces the second side z2, just like the back surface 32 of the die pad 3. Each of the top surface 71 and the bottom surface 72 is approximately flat.

[0042] Each of the side surfaces 73 to 76 is sandwiched between the top surface 71 and the bottom surface 72 in the thickness direction z. The side surface 73 is connected to the inclined surface 77 and the bottom surface 72. The side surfaces 74 to 76 are connected to the top surface 71 and the bottom surface 72. The side surfaces 73 and 74 are spaced apart from each other in the first direction x. The side surfaces 73 and 74 face opposite each other in the first direction x. The side surface 73 is located on a first side x1 in the first direction x and faces the first side x1 in the first direction x. The side surface 74 is located on a second side x2 in the first direction x and faces the second side x2 in the first direction x. The side surfaces 75 and 76 are spaced apart from each other in the second direction y and are connected to the side surfaces 73 and 74. The side surfaces 75 and 76 face opposite each other in the second direction y. The side surface 75 is located on a first side y1 in the second direction y and faces the first side y1 in the second direction y. The side surface 76 is located on a second side y2 in the second direction y and faces the second side y2 in the second direction y.

[0043] 1, a portion of each of the plurality of input terminals 51 protrudes from side surface 73. A portion of each of the plurality of output terminals 52 protrudes from side surface 74. The conductive support member 2 is not exposed from side surfaces 75 and 76.

[0044] The inclined surface 77 is sandwiched between the top surface 71 and the bottom surface 72 in the thickness direction z. The inclined surface 77 is connected to the top surface 71 and the side surface 73. The inclined surface 77 faces the first side z1 in the thickness direction z, but forms a larger angle with the main surface 31 of the die pad 3 than the top surface 71. In other words, the inclined surface 77 is inclined with respect to the top surface 71. The inclined surface 77 is provided as a mark to prevent the semiconductor device A10 from being mounted in the wrong orientation. As shown in FIG. 7 , the inclination angle α of the inclined surface 77 with respect to the top surface 71 is smaller than the inclination angle β of the upper region 731 of the side surface 73 with respect to the top surface 71. In this embodiment, the inclination angle α is 45 degrees. Note that the inclination angle α is not limited, but it is preferably 25 degrees or greater to function as a mark to prevent the semiconductor device A10 from being mounted in the wrong orientation. As shown in Figures 2 and 7, when viewed in the thickness direction z, the inclined surface 77 overlaps the lead portion 511 of each input side terminal 51 but does not overlap the pad portion 512 (see the dotted area in Figure 2 and area R shown in Figure 7).

[0045] As shown in FIGS. 3 to 5, the side surface 73 includes an upper region 731, a lower region 732, and a central region 733. One end of the upper region 731 in the thickness direction z is connected to the inclined surface 77, and the other end in the thickness direction z is connected to the central region 733. The upper region 731 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. The lower region 732 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. One end of the central region 733 in the thickness direction z is connected to the upper region 731, and the other end in the thickness direction z is connected to the lower region 732. The central region 733 is aligned along both the thickness direction z and the second direction y. When viewed in the thickness direction z, the central region 733 is located outward from the top surface 71, the inclined surface 77, and the bottom surface 72. From the central region 733, a portion of each of the multiple input terminals 51 is exposed.

[0046] As shown in Figures 3, 4, and 6, the side surface 74 includes an upper region 741, a lower region 742, and a central region 743. One end of the upper region 741 in the thickness direction z is connected to the top surface 71, and the other end in the thickness direction z is connected to the central region 743. The upper region 741 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. The lower region 742 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. One end of the central region 743 in the thickness direction z is connected to the upper region 741, and the other end in the thickness direction z is connected to the lower region 742. The central region 743 is aligned along both the thickness direction z and the second direction y. When viewed in the thickness direction z, the central region 743 is located outward from the top surface 71 and the bottom surface 72. From the central region 743, a portion of each of the plurality of output terminals 52 is exposed.

[0047] As shown in FIGS. 4 to 6 , the side surface 75 includes an upper region 751, a lower region 752, and a central region 753. The upper region 751 has one end in the thickness direction z connected to the top surface 71 and the other end in the thickness direction z connected to the central region 753. The upper region 751 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. The lower region 752 has one end in the thickness direction z connected to the bottom surface 72 and the other end in the thickness direction z connected to the central region 753. The lower region 752 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. The central region 753 has one end in the thickness direction z connected to the upper region 751 and the other end in the thickness direction z connected to the lower region 752. The central region 753 is aligned along both the thickness direction z and the second direction y. When viewed in the thickness direction z, the central region 753 is located outward from the top surface 71 and the bottom surface 72 .

[0048] As shown in Figures 3, 5, and 6, the side surface 76 includes an upper region 761, a lower region 762, and a central region 763. One end of the upper region 761 in the thickness direction z is connected to the top surface 71, and the other end in the thickness direction z is connected to the central region 763. The upper region 761 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. The lower region 762 is inclined so that one end in the thickness direction z is located closer to the interior of the semiconductor device A10 than the other end. One end of the central region 763 in the thickness direction z is connected to the upper region 761, and the other end in the thickness direction z is connected to the lower region 762. The central region 763 is aligned along both the thickness direction z and the second direction y. When viewed in the thickness direction z, the central region 763 is located outward from the top surface 71 and the bottom surface 72.

[0049] 9 and 10 , the surface roughness of each of the top surface 71, inclined surface 77, bottom surface 72, upper region 731 and lower region 732 of side surface 73, and upper region 741 and lower region 742 of side surface 74 of sealing resin 7 is greater than the surface roughness of the central region 733 of side surface 73 and the central region 743 of side surface 74. The surface roughness of each of the top surface 71 and bottom surface 72 is preferably 5 μmRz or more and 20 μmRz or less.

[0050] Next, an example of a method for manufacturing the semiconductor device A10 will be described below with reference to FIGS. 11 to 16. FIGS. 11 to 13 and 15 are plan views showing steps in the method for manufacturing the semiconductor device A10. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13 and corresponds to FIG. 7. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15 and corresponds to FIG. 7. The first direction x, second direction y, and thickness direction z shown in these figures indicate the same directions as those in FIGS. 1 to 10.

[0051] First, as shown in FIG. 11 , a lead frame 81 is prepared. The lead frame 81 is a plate-shaped material. In this embodiment, the base material of the lead frame 81 is Cu. The lead frame 81 may be formed by etching a metal plate or by punching a metal plate. The lead frame 81 has a main surface 81A and a back surface 81B spaced apart in the thickness direction z. The lead frame 81 also includes an outer frame 811, a die pad 812A, a die pad 812B, a plurality of first leads 813, a plurality of second leads 814, and a dam bar 816. Of these, the outer frame 811 and the dam bar 816 do not constitute the semiconductor device A10. The die pad 812A is a portion that will later become the die pad 3. The die pad 812B is a portion that will later become the die pad 4. The plurality of first leads 813 are portions that will later become the plurality of input terminals 51. The plurality of second leads 814 are portions that will later become the plurality of output terminals 52.

[0052] 12, the semiconductor element 11 and the insulating element 13 are bonded to the die pad 812A by die bonding, and the semiconductor element 12 is bonded to the die pad 812B by die bonding. After these steps, each of the plurality of wires 61 to 64 is formed by wire bonding.

[0053] In the process of forming the wire 61, first, the capillary is lowered toward the semiconductor element 11, and the tip of the wire is pressed against a predetermined electrode. At this time, the weight of the capillary and the action of ultrasonic waves emitted from the capillary cause the tip of the wire to be crimped onto the electrode, forming a first bond. Next, the capillary is raised while feeding out the wire, forming a ball bond on the electrode. Next, the capillary is moved directly above a portion of the first lead 813 that will become the pad portion 512 of one of the input terminals 51, and is further lowered, pressing the tip of the capillary against the bonding surface. As a result, the wire is sandwiched between the tip of the capillary and the bonding surface and crimped onto the bonding surface, forming a second bond. Next, the capillary is raised, and the wire is cut.

[0054] In the process of forming wire 62, first bonding is performed on the electrode of semiconductor element 12, and second bonding is performed on a portion of second lead 814 that will become pad portion 522 of output terminal 52. In the process of forming wire 63, first bonding is performed on the electrode of semiconductor element 11, and second bonding is performed on the electrode of insulating element 13. In the process of forming wire 64, first bonding is performed on the electrode of semiconductor element 12, and second bonding is performed on the electrode of insulating element 13. Note that in the processes of forming wires 63 and 64, the first bonding and second bonding may be reversed.

[0055] Next, as shown in FIGS. 13 and 14, the sealing resin 7 is formed by transfer molding. In this process, the lead frame 81 is placed in a mold having multiple cavities. At this time, the portion of the lead frame 81 that corresponds to the conductive support member 2 of the semiconductor device A10 and that is covered by the sealing resin 7 is placed in one of the multiple cavities. Then, fluidized resin is poured from a pot through a runner into each of the multiple cavities. After the fluidized sealing resin 7 solidifies in the multiple cavities, resin burrs located outside each of the multiple cavities are removed using high-pressure water or the like. This completes the formation of the sealing resin 7. The sealing resin 7 has a top surface 71 and a bottom surface 72 that face opposite each other in the thickness direction z, side surfaces 73 and 74 that face opposite each other in the first direction x, side surfaces 75 and 76 that face opposite each other in the second direction y, and an inclined surface 77 (shown in dotted lines in FIG. 13) that connects to the top surface 71 and side surfaces 73. The inclined surface 77 is formed so as not to overlap the joint portion 61a of the wire 61 to the lead frame 81 when viewed in the thickness direction z.

[0056] 15 and 16, the exposed portion of the lead frame 81 that is exposed from the sealing resin 7 is bent. Before this step, the lead frame 81 is not cut. Thereafter, the exposed portion is cut and separated into individual pieces, whereby the die pad 812A, the die pad 812B, the plurality of first leads 813, and the plurality of second leads 814 that were connected to each other by the outer frame 811 and the dam bar 816 are appropriately separated. By going through the steps described above, the semiconductor device A10 is manufactured.

[0057] Next, the effects of the semiconductor device A10 will be described.

[0058] According to this embodiment, the sealing resin 7 has an inclined surface 77 that connects to the top surface 71 and the side surface 73. The inclined surface 77 is inclined with respect to the top surface 71. The pad portion 512 to which the wire 61 is bonded does not overlap the inclined surface 77 when viewed in the thickness direction z. Therefore, the semiconductor device A10 can detect peeling of the sealing resin 7 at the pad portion 512 by SAT testing. This allows the semiconductor device A10 to suppress breakage of the wire 61 due to peeling of the sealing resin 7 at the pad portion 512.

[0059] Furthermore, according to this embodiment, the insulating element 13 relays transmission and reception of signals between the semiconductor elements 11 and 12, and also insulates the semiconductor elements 11 and 12 from each other. Therefore, even when a significant potential difference occurs between the input side circuit including the semiconductor element 11 and the output side circuit including the semiconductor element 12, the semiconductor device A10 can improve the dielectric strength between the input side circuit and the output side circuit.

[0060] Furthermore, in this embodiment, the conductive support member 2 includes a die pad 3, a die pad 4, a plurality of input terminals 51, and a plurality of output terminals 52. The plurality of input terminals 51 are exposed from a side surface 73, and the plurality of output terminals 52 are exposed from a side surface 74. On the other hand, the conductive support member 2 is not exposed from a side surface 75 or a side surface 76. Therefore, no metal portion of the conductive support member 2 exposed from the sealing resin 7 exists between the plurality of input terminals 51 and the plurality of output terminals 52, where a significant potential difference occurs. This increases the insulation distance between the plurality of input terminals 51 and the plurality of output terminals 52. This increases the dielectric strength of the semiconductor device A10 compared to when the conductive support member 2, such as a support lead, is exposed from the side surface 75 or the side surface 76.

[0061] Furthermore, according to this embodiment, in the manufacturing process of the semiconductor device A10, the exposed portion of the lead frame 81 that is exposed from the sealing resin 7 is bent, and then the exposed portion is cut and separated into individual pieces. Conversely, if the exposed portion is cut and then bent, without support leads for fixing the sealing resin 6 to the outer frame 811 of the lead frame 81, the exposed portion will be separated into individual pieces when cut. In other words, by manufacturing the semiconductor device A10 using the manufacturing method according to this embodiment, it is possible to manufacture the semiconductor device A10 without providing support leads on the lead frame 81. As a result, the semiconductor device A10 can be structured so that the conductive support member 2 is not exposed from the side surface 75 and the side surface 76.

[0062] Furthermore, according to this embodiment, the surface roughness of each of the top surface 71, inclined surface 77, bottom surface 72, upper region 731 and lower region 732 of side surface 73, and upper region 741 and lower region 742 of side surface 74 of sealing resin 7 is greater than the surface roughness of the central region 733 of side surface 73 and the central region 743 of side surface 74. Therefore, the top surface creepage distance from the input side terminal 51 to the output side terminal 52 along the upper region 731 of side surface 73, top surface 71, and upper region 741 of side surface 74 of sealing resin 7, and the bottom surface creepage distance from the input side terminal 51 to the output side terminal 52 along the lower region 732 of side surface 73, bottom surface 72, and lower region 742 of side surface 74 of sealing resin 7 can be made longer. This allows the semiconductor device A10 to have a further improved dielectric strength.

[0063] In semiconductor device A10, a voltage of 600 V or more is applied to semiconductor element 12, compared to semiconductor element 11. In this way, when a significant potential difference occurs between the input side circuit and the output side circuit, it is preferable to provide insulating element 13 and further improve the dielectric strength voltage in order to improve the reliability of semiconductor device A10.

[0064] In the present embodiment, the case where the inclined surface 77 does not overlap the pad portion 512 of each input terminal 51 as viewed in the thickness direction z has been described, but this is not limiting. The inclined surface 77 may overlap a portion of the pad portion 512 of each input terminal 51 as viewed in the thickness direction z. However, the inclined surface 77 does not overlap the joint portion 61a of the wire 61 as viewed in the thickness direction z.

[0065] Furthermore, in this embodiment, the surface roughness of each of the top surface 71, inclined surface 77, bottom surface 72, upper region 731 and lower region 732 of side surface 73, and upper region 741 and lower region 742 of side surface 74 of sealing resin 7 is described as being greater than the surface roughness of the central region 733 of side surface 73 and the central region 743 of side surface 74, but this is not limited to this. Each of the surfaces 71 to 77 of sealing resin 7 may have approximately the same surface roughness. In this case, the surface roughness of each of the surfaces 71 to 77 of sealing resin 7 may be relatively small or relatively large (for example, 5 μmRz or more and 20 μmRz or less).

[0066] In addition, in this embodiment, the case where the conductive support member 2 is not exposed from the side surface 75 and the side surface 76 has been described, but this is not limiting. The support lead may be exposed from the side surface 75 or the side surface 76.

[0067] 17 to 23 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment.

[0068] [Second embodiment] FIG. 17 is a diagram illustrating a semiconductor device A20 according to a second embodiment of the present disclosure. FIG. 17 is a plan view illustrating the semiconductor device A20, and corresponds to FIG. 2. In FIG. 17, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A20 of this embodiment differs from the first embodiment in that an insulating element 13 is mounted on the die pad 3. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first embodiment described above may be combined in any desired manner.

[0069] In this embodiment, the insulating element 13 is mounted on the die pad 4 and is disposed at the center of the die pad 4 in the second direction y, closer to the first side x1 than the center in the first direction x. That is, the insulating element 13 is disposed on the first side x1 in the first direction x of the semiconductor element 12. The die pad 4 is disposed on the second side x2 in the first direction x of the die pad 3. Therefore, in this embodiment as well, the insulating element 13 is located between the semiconductor elements 11 and 12 in the first direction x.

[0070] In this embodiment as well, the sealing resin 7 has an inclined surface 77 that is connected to the top surface 71 and the side surface 73 and is inclined relative to the top surface 71. The pad portion 512 to which the wire 61 is bonded does not overlap the inclined surface 77 when viewed in the thickness direction z, and therefore, the semiconductor device A20 can detect peeling of the sealing resin 7 at the pad portion 512 by SAT inspection. This allows the semiconductor device A20 to suppress breakage of the wire 61 due to peeling of the sealing resin 7 at the pad portion 512. Furthermore, the semiconductor device A20 has a configuration in common with the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

[0071] [Third embodiment] FIG. 18 is a diagram illustrating a semiconductor device A30 according to a third embodiment of the present disclosure. FIG. 18 is a plan view illustrating the semiconductor device A30, and corresponds to FIG. 2. In FIG. 18, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A30 of this embodiment differs from the first embodiment in the position of the inclined surface 77 in the sealing resin 7. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first and second embodiments described above may be combined in any desired manner.

[0072] In this embodiment, the inclined surface 77 is connected to the top surface 71 and the side surface 74 and is inclined with respect to the top surface 71. When viewed in the thickness direction z, the inclined surface 77 overlaps the lead portion 521 of each output terminal 52 but does not overlap the pad portion 522. The dotted areas in FIG. 18 are areas of each output terminal 52 that overlap the inclined surface 77. When viewed in the thickness direction z, the pad portion 522 does not overlap the inclined surface 77, and therefore the bonding portion of the wire 62 to the pad portion 522 does not overlap the inclined surface 77.

[0073] According to the present embodiment, the sealing resin 7 has an inclined surface 77 that is connected to the top surface 71 and the side surface 74 and is inclined relative to the top surface 71. The pad portion 522 to which the wire 62 is bonded does not overlap the inclined surface 77 when viewed in the thickness direction z, and therefore, the semiconductor device A30 can detect peeling of the sealing resin 7 at the pad portion 522 by SAT inspection. This allows the semiconductor device A30 to suppress disconnection of the wire 62 due to peeling of the sealing resin 7 at the pad portion 522. Furthermore, the semiconductor device A30 has a configuration in common with the semiconductor device A10, and thereby achieves the same effects as the semiconductor device A10.

[0074] [Fourth embodiment] FIG. 19 is a diagram illustrating a semiconductor device A40 according to a fourth embodiment of the present disclosure. FIG. 19 is a plan view showing the semiconductor device A40, and corresponds to FIG. 2. In FIG. 19, for ease of understanding, the outline of the sealing resin 7 is shown by an imaginary line (two-dot chain line) through the sealing resin 7. The semiconductor device A40 of this embodiment differs from the first embodiment in the shape of the sealing resin 7. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to third embodiments described above may be combined in any desired manner.

[0075] In this embodiment, the sealing resin 7 further includes an inclined surface 78. The inclined surface 78 is connected to the top surface 71 and the side surface 74 and is inclined with respect to the top surface 71. When viewed in the thickness direction z, the inclined surface 78 overlaps the lead portion 521 of each output terminal 52 but does not overlap the pad portion 522. The dotted areas in FIG. 19 are the areas of each input terminal 51 that overlap the inclined surface 77 or the areas of each output terminal 52 that overlap the inclined surface 78. When viewed in the thickness direction z, the pad portion 522 does not overlap the inclined surface 78, and therefore the bonding portion of the wire 62 to the pad portion 522 does not overlap the inclined surface 78.

[0076] According to the present embodiment, the sealing resin 7 has an inclined surface 77 that is connected to the top surface 71 and the side surface 73 and is inclined relative to the top surface 71, and an inclined surface 78 that is connected to the top surface 71 and the side surface 74 and is inclined relative to the top surface 71. The pad portion 512 to which the wire 61 is bonded does not overlap the inclined surface 77 as viewed in the thickness direction z, so the semiconductor device A40 can detect peeling of the sealing resin 7 at the pad portion 512 by SAT testing. This allows the semiconductor device A40 to prevent disconnection of the wire 61 due to peeling of the sealing resin 7 at the pad portion 512. Furthermore, the pad portion 522 to which the wire 62 is bonded does not overlap the inclined surface 78 as viewed in the thickness direction z, so the semiconductor device A40 can detect peeling of the sealing resin 7 at the pad portion 522 by SAT testing. This allows the semiconductor device A40 to prevent disconnection of the wire 62 due to peeling of the sealing resin 7 at the pad portion 522. Furthermore, the semiconductor device A40 has the same configuration as the semiconductor device A10, and thus provides the same effects as the semiconductor device A10.

[0077] [Fifth embodiment] FIG. 20 is a diagram illustrating a semiconductor device A50 according to a fifth embodiment of the present disclosure. FIG. 20 is a cross-sectional view showing the semiconductor device A50, and corresponds to FIG. 7. The semiconductor device A50 of this embodiment differs from the first embodiment in the dimension of the sealing resin 7 in the thickness direction z. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to fourth embodiments described above may be combined in any desired manner.

[0078] In this embodiment, the thickness dimension T1 of the sealing resin 7 on the first side z1 in the thickness direction z from the die pad 3 (the dimension from the main surface 31 of the die pad 3 to the top surface 71 of the sealing resin 7) is larger than the thickness dimension T2 on the second side z2 (the dimension from the back surface 32 of the die pad 3 to the bottom surface 72 of the sealing resin 7).

[0079] In this embodiment, the sealing resin 7 also has an inclined surface 77 that is connected to the top surface 71 and the side surface 73 and is inclined relative to the top surface 71. The pad portion 512 to which the wire 61 is bonded does not overlap the inclined surface 77 in the thickness direction z. Therefore, the semiconductor device A50 can detect peeling of the sealing resin 7 at the pad portion 512 by SAT testing. This allows the semiconductor device A50 to prevent disconnection of the wire 61 due to peeling of the sealing resin 7 at the pad portion 512. Furthermore, by sharing a configuration with the semiconductor device A10, the semiconductor device A50 achieves the same effects as the semiconductor device A10. Furthermore, in this embodiment, the thickness dimension T1 of the sealing resin 7 on the first side z1 in the thickness direction z from the die pad 3 is larger than the thickness dimension T2 of the second side z2. Therefore, even though the sealing resin 7 has the inclined surface 77, the semiconductor device A50 can prevent the top surface creepage distance from being shorter than the back surface creepage distance. Furthermore, in the semiconductor device A50, the thickness T1 is larger than the thickness T2, so that the distance between the top of the loop of each of the wires 61 to 64 and the top surface 71 can be increased.

[0080] [Sixth embodiment] 21 and 22 are diagrams illustrating a semiconductor device A60 according to a sixth embodiment of the present disclosure. FIG. 21 is a plan view showing the semiconductor device A60, and corresponds to FIG. 1. FIG. 22 is a front view showing the semiconductor device A60, and corresponds to FIG. 3. The semiconductor device A60 of this embodiment differs from the first embodiment in the shape of the sealing resin 7. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to fifth embodiments described above may be combined in any desired manner.

[0081] In this embodiment, the sealing resin 7 includes a groove 75a and a groove 76a. The groove 75a is recessed from the side surface 75 toward the second side y2 in the second direction y and extends from the top surface 71 to the bottom surface 72 in the thickness direction z. In this embodiment, the sealing resin 7 includes three grooves 75a arranged at equal intervals. The number of grooves 75a is not limited. The groove 76a is recessed from the side surface 76 toward the first side y1 in the second direction y and extends from the top surface 71 to the bottom surface 72 in the thickness direction z. In this embodiment, the sealing resin 7 includes three grooves 76a arranged at equal intervals. The number of grooves 76a is not limited. In this embodiment, the shape of each of the grooves 75a, 76a when viewed in the thickness direction z is rectangular. The shape of each of the grooves 75a, 76a when viewed in the thickness direction z is not limited and may be, for example, a semicircular shape.

[0082] In this embodiment, the sealing resin 7 also has an inclined surface 77 that is connected to the top surface 71 and the side surface 73 and is inclined relative to the top surface 71. The pad portion 512 to which the wire 61 is bonded does not overlap the inclined surface 77 when viewed in the thickness direction z. Therefore, the semiconductor device A60 can detect peeling of the sealing resin 7 at the pad portion 512 by SAT testing. This allows the semiconductor device A60 to prevent disconnection of the wire 61 due to peeling of the sealing resin 7 at the pad portion 512. Furthermore, by sharing a configuration with the semiconductor device A10, the semiconductor device A60 achieves the same effects as the semiconductor device A10. Furthermore, in this embodiment, the sealing resin 7 has a groove portion 75a recessed from the side surface 75 toward the second side y2 in the second direction y. Therefore, the creeping distance from the input terminal 51, which is closest to the first side x1 in the first direction x, along the side surfaces 73, 75, and 74 of the sealing resin 7 to the output terminal 52a is longer than in a case where the groove 75a is not provided. The sealing resin 7 also has a groove 76a recessed from the side surface 76 to the first side y1 in the second direction y. Therefore, the creeping distance from the input terminal 51b to the output terminal 52b along the side surfaces 73, 76, and 74 of the sealing resin 7 is longer than in a case where the groove 76a is not provided. This allows the semiconductor device A60 to further improve its dielectric strength.

[0083] In the present embodiment, the grooves 75a, 76a extend from the top surface 71 to the bottom surface 72 in the thickness direction z, but this is not limiting. Each groove 75a (76a) may be provided at least in the central region 753 of the side surface 75 (the central region 763 of the side surface 76). Furthermore, the semiconductor device A60 may include, instead of the grooves 75a, 76a, a first protrusion protruding from the side surface 75 to a first side y1 in the second direction y, and a second protrusion protruding from the side surface 76 to a second side y2 in the second direction y.

[0084] [Seventh embodiment] FIG. 23 is a diagram illustrating a semiconductor device A70 according to a seventh embodiment of the present disclosure. FIG. 23 is a plan view showing the semiconductor device A70, and corresponds to FIG. 1. The semiconductor device A70 of this embodiment differs from the first embodiment in the shape of the conductive support member 2 and the arrangement of the semiconductor elements. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that the parts of the first to sixth embodiments described above may be combined in any desired manner.

[0085] In this embodiment, fixing portions 39 are connected to both end portions of the die pad 3 in the first direction x. Each fixing portion 39 is a portion for fixing the die pad 3 to the lead frame, and is a so-called support lead. The outer end of each fixing portion 39 in the first direction x is exposed from the sealing resin 7 (side surface 75 or side surface 76). Semiconductor elements 14 and 15 are mounted on the die pad 3 and aligned in the first direction x.

[0086] In this embodiment as well, the sealing resin 7 has an inclined surface 77 that is connected to the top surface 71 and the side surface 73 and is inclined relative to the top surface 71. The pad portion 512 to which the wire 61 is bonded does not overlap the inclined surface 77 when viewed in the thickness direction z, and therefore, the semiconductor device A70 can detect peeling of the sealing resin 7 at the pad portion 512 by SAT inspection. This allows the semiconductor device A70 to suppress disconnection of the wire 61 due to peeling of the sealing resin 7 at the pad portion 512. Furthermore, by having a configuration in common with the semiconductor device A10, the semiconductor device A70 achieves the same effects as the semiconductor device A10.

[0087] As can be seen from the seventh embodiment, the present invention is applicable regardless of the shape of the conductive support member 2, the number, arrangement, and function of the semiconductor elements, etc. Furthermore, the present invention is applicable regardless of whether the conductive support member 2 is exposed from the side surfaces 75, 76 of the sealing resin 7.

[0088] In the first to seventh embodiments, the present invention has been described as being applied to a semiconductor device whose package format is SOP, but the present invention is not limited to this and can also be applied to semiconductor devices whose package format is other than SOP.

[0089] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the manufacturing method can be freely designed and modified in various ways.

[0090] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] a die pad (3) having a die pad main surface (31) facing a first side (z1) in a thickness direction (z); and a conductive support member (2) including a first terminal (51c) spaced apart from the die pad and entirely located on a first side (x1) in a first direction (x) perpendicular to the thickness direction relative to the die pad; a semiconductor element (11) mounted on the main surface of the die pad; a wire (61) electrically connected to the semiconductor element and the first terminal; a sealing resin (7) that covers at least a portion of the conductive support member, the semiconductor element, and the wires; Equipped with the sealing resin comprises a resin top surface (71) facing a first side in the thickness direction, a first resin side surface (73) facing the first side in the first direction and from which a portion of the first terminal protrudes, and an inclined surface (77) connected to the resin top surface and the first resin side surface and forming an angle with the die pad main surface that is larger than that of the resin top surface; When viewed in the thickness direction, a joint portion (61a) of the wire to the first terminal does not overlap the inclined surface. Semiconductor device. [Appendix 2, Figure 7] a first inclination angle (α) of the inclined surface relative to the resin top surface is 25 degrees or more; 2. The semiconductor device according to claim 1. [Appendix 3, Figure 7] a second inclination angle (β) of the first resin side surface relative to the resin top surface is greater than the first inclination angle; 3. The semiconductor device according to claim 2. [Appendix 4] the sealing resin further includes a second resin side surface (74) facing the opposite side to the first resin side surface in the first direction, The conductive support member further includes a second terminal (52c) partially protruding from the second resin side surface. 4. The semiconductor device according to any one of claims 1 to 3. [Appendix 5] Further comprising a second semiconductor element (12), the conductive support member further includes a second die pad (12) disposed at a distance from the die pad on a second side (x2) in the first direction, and on which the second semiconductor element is mounted; the second terminal is entirely located on a second side of the second die pad in the first direction; 5. The semiconductor device according to claim 4. [Appendix 6] a second wire (62) electrically connected to the second semiconductor element and the second terminal; When viewed in the thickness direction, a second joint portion of the second wire to the second terminal does not overlap with a side surface of the second resin. 6. The semiconductor device according to claim 5. [Appendix 7] the semiconductor element is a control element, The second semiconductor element is a driving element that requires a higher voltage than the control element. 7. The semiconductor device according to claim 5 or 6. [Appendix 8] The semiconductor device further includes an insulating element (13) that relays transmission and reception of signals between the semiconductor element and the second semiconductor element and insulates the semiconductor element and the second semiconductor element from each other. 8. The semiconductor device according to any one of appendixes 5 to 7. [Appendix 9] the insulating element is mounted on the die pad; 9. The semiconductor device according to claim 8. [Appendix 10, Figures 9 and 10] The sealing resin further includes a resin bottom surface (72) facing the second side in the thickness direction, the first resin side surface includes a first upper region (731) connected to the inclined surface, a first lower region (732) connected to the resin bottom surface, and a first central region (733) connected to the first upper region and the first lower region and from which the first terminal projects; the second resin side surface includes a second upper region (741) connected to the resin top surface, a second lower region (742) connected to the resin bottom surface, and a second central region (743) connected to the second upper region and the second lower region and from which the second terminal protrudes; a first surface roughness of each of the resin top surface, the inclined surface, the resin bottom surface, the first upper region, the first lower region, the second upper region, and the second lower region is greater than a second surface roughness of the first central region and the second central region; 10. The semiconductor device according to any one of appendixes 4 to 9. [Appendix 11] the sealing resin further includes a third resin side surface (75) and a fourth resin side surface (76) facing opposite sides to each other in a second direction perpendicular to the thickness direction and the first direction, the conductive support member is not exposed from the third resin side surface and the fourth resin side surface; 11. The semiconductor device according to any one of claims 1 to 10. [Appendix 12, Sixth Embodiment, Figures 21 and 22] the sealing resin further includes a first displacement portion (75a) displaced in the second direction from the third resin side surface and extending in the thickness direction; 12. The semiconductor device according to claim 11. [Appendix 13, Fifth embodiment, Figure 20] a first dimension (T1) of the sealing resin on a first side from the die pad in the thickness direction is larger than a second dimension (T2) on a second side from the die pad in the thickness direction; 13. The semiconductor device according to any one of appendices 1 to 12. [Appendix 14, Figures 12 to 16] an element bonding step of bonding a semiconductor element (11) to a lead frame main surface (81A) facing a first side in the thickness direction of the lead frame (81); a wire bonding step of bonding wires (61) to the semiconductor element and the lead frame; a resin forming step of forming a sealing resin (7) that covers at least a portion of the lead frame, the semiconductor element, and the wires; a bending step of bending an exposed portion of the lead frame exposed from the sealing resin; a cutting step of cutting the exposed portion; Equipped with In the resin forming step, the sealing resin (7) has a resin top surface (71) facing a first side in the thickness direction, a first resin side surface (73) from which a part of the lead frame protrudes, and an inclined surface (77) that is connected to the resin top surface and the first resin side surface and forms an angle with the main surface of the lead frame that is larger than the resin top surface, and is formed so that the inclined surface does not overlap a joint portion (61a) of the wire to the lead frame when viewed in the thickness direction of the lead frame. A method for manufacturing a semiconductor device. [Appendix 15, Figure 15, Figure 16] The lead frame is not cut before the bending step; The cutting step is performed after the bending step. 15. A method for manufacturing a semiconductor device according to claim 14. [Explanation of symbols]

[0091] A10, A20, A30, A40, A50, A60, A70: Semiconductor device 11, 12, 14, 15: Semiconductor elements 13: Isolation element 2: Conductive support member 3: Die pad 31: Main surface 32: Back side 39: Fixed part 4: Die pad 41: Main surface 42: Back side 51, 51a, 51b, 51c: Input terminals 511: Lead section 512: Pad section 52, 52a, 52b, 52c: Output terminals 521: Lead section 522: Pad section 61, 62, 63, 64: Wire 61a: Joint 7: Sealing resin 71:Top surface 72: Bottom 73: Side 731: Upper area 732: Lower area 733: Central area 74: Side 741: Upper area 742: Lower area 743: Central area 75: Side 751: Upper area 752: Lower area 753: Central area 75a:Groove 76: Side 761: Upper area 762:Lower area 763: Central area 76a: Groove 77,78: Inclined surface 81: Lead frame 81A: Main surface 81B: Back 811: Outer frame 812A: Die pad 812B: Die pad 813: 1st lead 814: Second Lead 816:Dambar

Claims

1. a die pad having a die pad main surface facing a first side in a thickness direction; and a conductive support member including a first terminal spaced apart from the die pad and positioned entirely on a first side of the die pad in a first direction perpendicular to the thickness direction; a semiconductor element mounted on a main surface of the die pad; a wire electrically connected to the semiconductor element and the first terminal; a sealing resin that covers at least a portion of the conductive support member, the semiconductor element, and the wires; Equipped with the sealing resin comprises a resin top surface facing a first side in the thickness direction, a first resin side surface facing the first side in the first direction and from which the first terminals are exposed, and an inclined surface connected to the resin top surface and the first resin side surface and forming an angle with the die pad main surface that is larger than that of the resin top surface; When viewed in the thickness direction, a joint portion of the wire to the first terminal does not overlap the inclined surface. Semiconductor device.

2. a first inclination angle of the inclined surface relative to the resin top surface is 25 degrees or more; The semiconductor device according to claim 1 .

3. a second inclination angle of the first resin side surface relative to the resin top surface is greater than the first inclination angle; The semiconductor device according to claim 2 .

4. the sealing resin further includes a second resin side surface facing the opposite side to the first resin side surface in the first direction, The conductive support member further includes a second terminal that partially protrudes from the second resin side surface. The semiconductor device according to claim 1 .

5. Further comprising a second semiconductor element; the conductive support member further includes a second die pad disposed at a distance from the die pad on a second side in the first direction, the second die pad having the second semiconductor element mounted thereon; the second terminal is entirely located on a second side of the second die pad in the first direction; The semiconductor device according to claim 4 .

6. a second wire electrically connected to the second semiconductor element and the second terminal; When viewed in the thickness direction, a second joint portion of the second wire to the second terminal does not overlap the second resin side surface. The semiconductor device according to claim 5 .

7. the semiconductor element is a control element, the second semiconductor element is a drive element requiring a higher voltage than the control element; The semiconductor device according to claim 5 .

8. The semiconductor device further includes an insulating element that relays transmission and reception of signals between the semiconductor element and the second semiconductor element and insulates the semiconductor element and the second semiconductor element from each other. The semiconductor device according to claim 5 .

9. the insulating element is mounted on the die pad; The semiconductor device according to claim 8 .

10. the sealing resin further includes a resin bottom surface facing a second side in the thickness direction; the first resin side surface includes a first upper region connected to the inclined surface, a first lower region connected to the resin bottom surface, and a first central region connected to the first upper region and the first lower region and from which the first terminal projects; the second resin side surface includes a second upper region connected to the resin top surface, a second lower region connected to the resin bottom surface, and a second central region connected to the second upper region and the second lower region and from which the second terminal projects, a first surface roughness of each of the resin top surface, the inclined surface, the resin bottom surface, the first upper region, the first lower region, the second upper region, and the second lower region is greater than a second surface roughness of each of the first central region and the second central region; The semiconductor device according to claim 4 .

11. the sealing resin further includes a third resin side surface and a fourth resin side surface facing opposite to each other in a second direction perpendicular to the thickness direction and the first direction, the conductive support member is not exposed from the third resin side surface and the fourth resin side surface; 11. The semiconductor device according to claim 1.

12. the sealing resin further includes a first displacement portion displaced in the second direction from the third resin side surface and extending in the thickness direction; The semiconductor device according to claim 11.

13. a first dimension of the sealing resin on a first side from the die pad in the thickness direction is larger than a second dimension of the sealing resin on a second side from the die pad in the thickness direction; The semiconductor device according to claim 1 .

14. an element bonding step of bonding a semiconductor element to a main surface of the lead frame facing a first side in a thickness direction of the lead frame; a wire bonding step of bonding wires to the semiconductor element and the lead frame; a resin forming step of forming a sealing resin that covers at least a portion of the lead frame, the semiconductor element, and the wires; a bending step of bending an exposed portion of the lead frame exposed from the sealing resin; a cutting step of cutting the exposed portion; Equipped with In the resin forming step, the sealing resin is formed so that the inclined surface does not overlap a bonding portion of the wire to the lead frame when viewed in the thickness direction, the inclined surface being connected to the resin top surface and the first resin side surface and forming an angle with the lead frame main surface that is larger than the resin top surface, and the inclined surface is connected to the resin top surface and the first resin side surface and does not overlap a bonding portion of the wire to the lead frame when viewed in the thickness direction. A method for manufacturing a semiconductor device.

15. The lead frame is not cut before the bending step; The cutting step is performed after the bending step. The method for manufacturing a semiconductor device according to claim 14.

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