Display device and electronic apparatus

Abstract

To suppress the deterioration in electric characteristic in a transistor with an oxide semiconductor layer or a semiconductor device including the transistor.SOLUTION: In a transistor including an oxide semiconductor as a channel layer, a silicon layer is provided in contact with a surface of an oxide semiconductor layer. The silicon layer is provided in contact with at least a region where a channel is formed in the oxide semiconductor layer, and a source electrode layer and a drain electrode layer are provided in contact with a region where the silicon layer is not provided in the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a transistor using an oxide semiconductor layer and a semiconductor device including the transistor. The present invention relates to a device and a method for manufacturing the same. [Background technology]

[0002] There are many types of metal oxides and they are used for various purposes. Indium oxide is well known as It is a material that has been developed and is used as a transparent electrode material required for liquid crystal displays, etc. do.

[0003] Some metal oxides exhibit semiconducting properties. Generally, metal oxides are insulators. However, it is known that metal oxides can become semiconductors depending on the combination of elements that make up the oxide. It is being done.

[0004] For example, metal oxides that exhibit semiconductor properties include tungsten oxide, tin oxide, and indium oxide. These metal oxides, which exhibit semiconducting properties, are used in the channel formation region. Thin film transistors that achieve this are already known (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO3(ZnO) with homologous phase m (m: natural number) contains In, Ga, and Zn It is known as a multi-component oxide semiconductor (Non-Patent Documents 2 to 4).

[0006] Then, the oxide semiconductor composed of the above-mentioned In-Ga-Zn-based oxide is used as a thin film transistor. It has been confirmed that it can be used as a channel layer for thin film transistors (also called TFTs). Patent document 5, non-patent documents 5 and 6).

[0007] However, oxide semiconductors are susceptible to damage caused by etching agents and plasma during the device manufacturing process. The inclusion of elements such as silicon dioxide and hydrogen can easily cause fluctuations in the semiconductor characteristics, which can lead to deterioration of the device. Variation and degradation of electrical characteristics become a problem. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-150900 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-103957 [Non-patent literature]

[0009] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-patent document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315

Non-patent document 3

Non-patent document 4

Non-patented document 5

Non-patent document 6

[0010] In view of the above problems, one embodiment of the present invention is a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a semiconductor device having a transistor, it is possible to suppress variations and deterioration of electrical characteristics. This is one of the challenges. [Means for solving the problem]

[0011] In order to solve the above problems, one embodiment of the present invention is a semiconductor device using an oxide semiconductor as a channel layer. In the transistor, a silicon layer is provided on and in contact with a surface of an oxide semiconductor layer. In this case, the silicon layer serves as a protective film that reduces the intrusion of hydrogen and the like into the oxide semiconductor layer. The insulating film functions as a protective film for the oxide semiconductor layer in the manufacturing process and also functions as a protective film for the transistor. This can suppress variations and deterioration in the electrical characteristics of the capacitors.

[0012] In one embodiment of the present invention, a silicon layer is formed such that a channel is formed at least in an oxide semiconductor layer. and the oxide semiconductor layer is provided in contact with the silicon layer. a source electrode layer and a drain electrode layer are provided in contact with at least a part of the non-transparent portion. It is possible.

[0013] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device having an oxide semiconductor layer, the method comprising: forming a first insulating film on a first insulating film; a low resistance region that functions as a source region or a drain region is provided in at least a part of the A source electrode layer and a drain electrode layer can be provided in contact with the low resistance region.

[0014] Another embodiment of the present invention is a gate electrode, a gate insulating layer provided over the gate electrode, an oxide semiconductor layer provided on the gate insulating layer and overlapping with the gate electrode; a silicon layer provided on the surface and in contact with the oxide semiconductor layer; and a source electrode electrically connected to the oxide semiconductor layer. A transistor having a silicon layer and a drain electrode layer is also provided. The source electrode layer and the drain electrode layer are connected to at least a portion of the surface of the oxide semiconductor layer that is not exposed. In addition, a source region can be provided in a region of the oxide semiconductor layer that is in contact with the source electrode layer. a first low-resistance region that functions as a drain electrode layer; A second low resistance region that functions as a drain region can be provided in the region.

[0015] Another embodiment of the present invention is a gate electrode, a gate insulating layer provided over the gate electrode, an oxide semiconductor layer provided on the gate insulating layer and overlapping with the gate electrode; A silicon layer provided in contact with a part of the surface and an oxide semiconductor layer not provided with the silicon layer A first metal oxide layer and a second metal oxide layer are provided in contact with at least a portion of the surface of the conductor layer. a source electrode layer electrically connected to the first metal oxide layer; and a second metal oxide layer. A transistor having a drain electrode layer electrically connected to the semiconductor layer is provided.

[0016] Another embodiment of the present invention is a gate electrode, a gate insulating layer provided over the gate electrode, a source electrode layer and a drain electrode layer provided on the gate insulating layer; an oxide semiconductor provided on the gate electrode layer and provided on the gate electrode via a gate insulating layer; a transistor including a silicon layer provided on and in contact with a surface of the oxide semiconductor layer; provide.

[0017] In one embodiment of the present invention, a gate electrode is formed over a substrate, and a gate insulating layer is formed over the gate electrode. an oxide semiconductor layer is formed on the gate insulating layer so as to overlap with the gate electrode; A silicon layer is formed to cover the semiconductor layer, and the silicon layer is etched to form an oxide semiconductor. A conductive film is formed over the silicon layer and the oxide semiconductor layer, and the conductive film is etched. A method for manufacturing a transistor in which a source electrode layer and a drain electrode layer are formed by etching is provided. do.

[0018] In one embodiment of the present invention, a gate electrode is formed over a substrate, and a gate insulating layer is formed over the gate electrode. an oxide semiconductor layer is formed on the gate insulating layer so as to overlap with the gate electrode; A silicon layer is formed to cover the semiconductor layer, and the silicon layer is etched to form an oxide semiconductor. A part of the oxide semiconductor layer is exposed, and plasma treatment is performed on the exposed part of the oxide semiconductor layer. A resistor region is formed, a conductive film is formed over the silicon layer and the oxide semiconductor layer, and the conductive film is etched. and forming a source electrode layer and a drain electrode layer by etching. do.

[0019] In this specification, silicon oxynitride refers to a silicon nitride having a higher oxygen content than nitrogen content. Preferably, Rutherford backscattering spectroscopy (RBS) is used. rd Backscattering Spectrometry) and hydrogen forward scattering (HFS: Hydrogen Forward Scattering) In this case, the concentration range is 50 to 70 atomic % for oxygen, 0.5 to 15 atomic % for nitrogen, and 0.5 to 15 atomic % for silicon. It refers to a material containing 25 to 35 atomic % of silicon and 0.1 to 10 atomic % of hydrogen. Silicon nitride oxide is a material whose composition contains more nitrogen than oxygen, Preferably, the oxygen concentration range is 5 to 30 when measured using RBS and HFS. atomic %, nitrogen 20-55 atomic %, silicon 25-35 atomic %, hydrogen 10-30 atomic % of silicon oxynitride or silicon nitride oxide. When the total of the atoms is 100 atomic %, the content ratio of nitrogen, oxygen, silicon and hydrogen is It is included in the above range.

[0020] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to a device that includes a display device, a semiconductor circuit, and an electronic device. In this document, the term "display device" includes a light-emitting device and a liquid crystal display device. The liquid crystal display device includes a liquid crystal element. The light-emitting element has a luminance controlled by a current or a voltage. This category includes elements that emit light, specifically inorganic EL (Electro Luminescence) These include elements such as LEDs, organic EL elements, and LED elements.

[0021] In this specification, B is formed on A, or B is formed on A. When explicitly stating "A", it is not limited to B being formed directly on A. This also includes cases where there is no direct contact between A and B, i.e., there is another object between A and B. Let's say. [Effects of the Invention]

[0022] According to one embodiment of the present invention, in a transistor having a channel layer formed of an oxide semiconductor, By providing a silicon layer on the surface of the nitride semiconductor layer, the electrical characteristics of the transistor can be improved. This can suppress deterioration of the properties. [Brief explanation of the drawings]

[0023] [Figure 1] 1A to 1C illustrate a structure of a transistor according to Embodiment 1. [Figure 2] 1A to 1C illustrate an example of a method for manufacturing a transistor according to Embodiment 1. [Figure 3] 1A to 1C illustrate a structure of a transistor according to Embodiment 1. [Figure 4] 1A to 1C illustrate a structure of a transistor according to Embodiment 1. [Figure 5] 10A to 10C illustrate an example of a method for manufacturing a transistor according to Embodiment 2. [Figure 6] 10A to 10C illustrate a structure of a transistor according to Embodiment 2. [Figure 7] 10A to 10C illustrate a structure of a transistor according to Embodiment 3. [Figure 8] 10A to 10C illustrate an example of a method for manufacturing a transistor according to Embodiment 3. [Figure 9] 10A to 10C illustrate a structure of a transistor according to Embodiment 3. [Figure 10] 10A to 10C illustrate the structure of a transistor according to Embodiment 4. [Figure 11] 10A to 10C illustrate an example of a method for manufacturing a transistor according to Embodiment 4. [Figure 12] 10A to 10C illustrate the structure of a transistor according to Embodiment 4. [Figure 13] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 5. [Figure 14] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 5. [Figure 15] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 5. [Figure 16] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 5. [Figure 17] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 5. [Figure 18] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 5. [Figure 19] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 5. [Figure 20] 10A and 10B illustrate an example of a semiconductor device according to Embodiment 6. [Figure 21] 10A to 10C illustrate an example of a semiconductor device according to Embodiment 7. [Figure 22] 10A and 10B illustrate an example of a semiconductor device according to Embodiment 8. [Figure 23] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 24] FIG. 1 is an external view showing an example of a gaming machine. [Figure 25] 1A to 1C illustrate an example of a method for manufacturing a transistor according to Embodiment 1. [Figure 26] 1A to 1C illustrate a structure of a transistor according to Embodiment 1. [Figure 27] FIG. 10 is a diagram illustrating a model used in a simulation. [Figure 28] FIG. 10 is a diagram illustrating the diffusion coefficient of hydrogen obtained by simulation. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments, and may be modified in any form without departing from the spirit of the invention. It will be apparent to those skilled in the art that various modifications and changes may be made to the embodiments and details of the present invention. It should not be construed as being limited to the description of the embodiment shown below. The configurations according to the above embodiments can be implemented in appropriate combinations. In the configuration of the present invention, the same parts or parts having similar functions are designated by the same reference numerals, and their repetition The explanation of repetition will be omitted.

[0025] (Embodiment 1) In this embodiment, an example of a structure of a transistor included in a semiconductor device will be described with reference to the drawings. This will be explained in light of the above.

[0026] The transistor 120 shown in FIG. 1 includes a gate (gate wiring and gate The gate electrode (hereinafter referred to as "gate electrode 102") is provided on the gate electrode 102. a gate insulating layer 104 formed on the insulating layer 104; and an oxide semiconductor layer 108 formed on the gate insulating layer 104. a silicon layer 112 provided on the surface of the oxide semiconductor layer 108 so as to be in contact with the surface of the oxide semiconductor layer 108; A source (including a source wiring and a source electrode (hereinafter referred to as a source electrode)) electrically connected to the compound semiconductor layer 108 The drain (the drain wiring and the drain electrode) (hereinafter referred to as "drain electrode layer 116b") (see FIG. 1).

[0027] In FIG. 1, FIG. 1(A) shows a top view, and FIG. 1(B) shows A1 in FIG. 1(A). Fig. 1(C) shows a cross section between A2 and B2 in Fig. 1(A). This shows:

[0028] At least a portion of the oxide semiconductor layer 108 is in contact with the gate electrode 10 via the gate insulating layer 104. 2, and a layer (channel) forming the channel region of the transistor 120. It functions as a channel layer.

[0029] The oxide semiconductor layer 108 may be formed using an oxide material having semiconductor properties. , InMO3(ZnO) m An oxide semiconductor having a structure represented by (m>0) can be used. In particular, it is preferable to use an In-Ga-Zn-O based oxide semiconductor. Sodium (Ga), iron (Fe), nickel (Ni), manganese (Mn) and cobalt (Co ) represents one or more metal elements selected from the group consisting of M and Ga. In addition, when the above metal elements other than Ga are contained, such as Ga and Ni or Ga and Fe, In addition to the metal element contained as M in the oxide semiconductor, impurity elements may also be contained. Those containing Fe, Ni or other transition metal elements, or oxides of said transition metals as elements In this specification, InMO3(ZnO) m Acids with structures represented by (m>0) Among oxide semiconductors, oxide semiconductors with a structure containing at least Ga as M are called In-Ga-Z The thin film is also called an In—Ga—Zn—O-based non-single-crystal film.

[0030] In addition to the above, oxide semiconductors applicable to the oxide semiconductor layer 108 include In—Sn— Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system In—O-based, Sn—O-based, and Zn—O-based oxide semiconductors can be used.

[0031] The silicon layer 112 is made of an oxide semiconductor at least in the region overlapping with the gate electrode 102. The silicon layer 112 is provided on the surface of the layer 108 so as to be in contact with the oxide semiconductor. The conductive layer 108 is provided on a part of the surface thereof so as to be in contact with the conductive layer 108. The source electrode layer 116a and the drain electrode layer 111 are formed in the area where the silicon layer 112 is not formed. Here, the oxide semiconductor layer 108 is provided with a shielding film 6b. The silicon layer 112 is not provided in the regions spaced apart from each other, and the silicon layer 112 is provided in each of the regions. 10B, the source electrode layer 116a and the drain electrode layer 116b are provided in contact with each other.

[0032] The silicon layer 112 is preferably made of i-type (intrinsic) silicon. "i-type silicon" refers to silicon that contains impurities that give it p-type or n-type properties. 1 x 10 each 17 atoms / cm 3 The oxygen and nitrogen concentrations are less than 1 x10 20 atoms / cm 3 This refers to silicon with a concentration of Impurity elements such as phosphorus (P) or boron (B) are added to the capacitor within the above range. The concentration of these impurities contained in the silicon layer 112 may be determined by the secondary ions. Secondary Ion Mass Spectrosc (SIMS) Measurements can be performed using a fluoroscopy.

[0033] The crystalline state of the silicon layer 112 may be amorphous silicon, microcrystalline silicon, or the like. The silicon layer 112 can be silicon or polycrystalline (poly)silicon. Among these crystal structures, two or more crystal structures (e.g., amorphous structure and microcrystalline structure (or The polycrystalline structure may be included.

[0034] The silicon layer 112 can be formed by a method such as CVD, sputtering, vapor deposition, or coating. The thickness of the silicon layer 112 is 1 nm or more and 500 nm or less. Preferably, it can be set to 10 nm or more and 100 nm or less.

[0035] For example, in an atmosphere that does not contain hydrogen, such as an argon atmosphere, or an atmosphere with a low hydrogen content, In this case, the silicon layer 112 is formed by sputtering, so that the film of the silicon layer 112 The hydrogen concentration in the silicon layer 112 is reduced, and the oxide is formed due to the hydrogen contained in the silicon layer 112. Fluctuations in the semiconductor characteristics of the semiconductor layer 108 can be reduced.

[0036] When the silicon layer 112 is formed by sputtering, a direct current (DC) sputtering device is used. (It is also preferable to use a pulse DC sputtering device that applies a bias in a pulsed manner.) By using a DC sputtering system, it is possible to produce a large This is because the protective layer is made of silicon oxide or silicon nitride. This is a major advantage over using an insulating layer such as a silicon oxide layer. When forming an insulating layer such as a silicon nitride layer by sputtering (using an insulating target), This is because, in the case of using RF sputtering, it is necessary to use RF sputtering, which is difficult to scale up.

[0037] When the silicon layer 112 is formed using a DC sputtering device, a silicon target, Alternatively, a silicon target doped with an impurity such as boron can be used.

[0038] As shown in FIG. 1, the back channel side of the oxide semiconductor layer 108 (opposite to the gate electrode 102) By providing the silicon layer 112 so as to contact the surface of the silicon layer 112, the silicon layer 112 is protected. The oxide semiconductor layer 108 can be prevented from being contaminated with hydrogen or the like by functioning as a protective film. As a result, the semiconductor characteristics of the oxide semiconductor layer 108 may be changed due to the inclusion of elements such as hydrogen. As a result, the electrical characteristics of the transistor having the oxide semiconductor layer 108 as a channel layer are improved. This makes it possible to suppress variations and deterioration in properties.

[0039] In addition, a source electrode layer 116a and a drain electrode layer 116b are provided over the oxide semiconductor layer 108. In this case, the silicon layer 112 functions as a channel protection layer (channel stop layer). Therefore, when the silicon layer 112 is not provided in contact with the oxide semiconductor layer 108, Compared with the case of the channel etch type, the characteristics change due to the exposure of the oxide semiconductor layer 108 is The silicon layer 112 can be made to function actively as a channel protection layer. In this case, it is preferable to form the silicon layer 112 as a dense film. By forming the silicon layer 112 using this material, a dense film can be formed.

[0040] The silicon layer 112 is formed in at least the region where a channel is formed in the oxide semiconductor layer 108. The silicon layer 112 may be provided so as to be in contact with the surface of the silicon oxide film. A silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film may be formed. The insulating film provided on the layer 112 is formed by film formation using a sputtering method or a CVD method. Alternatively, the surface of the silicon layer 112 may be oxidized (including natural oxidation) or nitrided. To oxidize or nitride the surface of the silicon layer 112, the silicon layer 112 may be oxidized or nitrided in an oxygen atmosphere or a nitrogen atmosphere. The plasma treatment may be carried out in a nitrogen atmosphere.

[0041] In addition, in FIG. 1, the source electrode layer 116a functions as the source of the transistor 120. The drain electrode layer 116b functions as the drain of the transistor 120. Depending on the driving method of the transistor 120, the source electrode layer 116a functions as a drain, In some cases, the drain electrode layer 116b may function as the source.

[0042] In the structure shown in FIG. 1, the material provided on and in contact with the surface of the oxide semiconductor layer 108 is In addition to silicon, germanium and silicon with germanium added are also available. Alternatively, germanium or silicon carbide (SiC) may be used.

[0043] Next, the effect of providing a silicon layer in contact with an oxide semiconductor layer was investigated by computer simulation. Here, we will explain the difference between amorphous silicon (a-Si) and amorphous silicon (a-Si). The hydrogen blocking effect of amorphous silicon oxide (a-SiO2) was investigated. Ta.

[0044] <Calculation method> First, classical molecular dynamics simulation was performed at a temperature of T = 27°C and a pressure of P = 1 atm. The motion of the atoms was tracked by numerically solving the equation of motion for each atom. From the mean square displacement of H obtained from the calculation results, Einstein's formula (Equation (1)) The diffusion coefficient D of H is calculated by the above formula. The larger this diffusion coefficient D, the easier it is to diffuse. do.

[0045]

number

[0046] <Calculation model and calculation conditions> a-Si:H model ( (See Figure 27(A)) and 60 atoms of H (10 atom%) in 540 atoms of a-SiO2. We prepared an a-SiO2:H model (see Figure 27(B)) with a three-dimensional periodic boundary. By imposing boundary conditions, it is a model for calculating the bulk.

[0047] In the classical molecular dynamics method used in this calculation, an empirical potential that characterizes the interatomic interactions is The force acting on each atom is evaluated by defining the following. In the a-Si:H model, Tersoff The Born-Mayer potential was used for the a-SiO2:H model. Using the r-Huggins potential and the Morse potential, a-SiO2 and hydrogen In the interaction between atoms (between silicon and hydrogen atoms, between oxygen and hydrogen atoms), Lenn The calculation program used was the Hardt-Jones potential. Simulation software "Materials Explorer 5.0" was used. .

[0048] In each calculation model, the temperature T = 27°C, the pressure P = 1 atm, and the time interval Classical molecular dynamics simulations were performed with a width of 0.2 fsec x 5 million steps.

[0049] <Calculation results and discussion> The calculated mean square displacement of H atoms in a-Si and the mean square displacement of H atoms in a-SiO2 The squared displacements are shown in Figure 28(A). In Figure 28(A), the slope of the graph is almost the same. The H atom of each calculation model obtained from the constant region (70 psec to 100 psec) The diffusion coefficient D of H atoms in a-Si is shown in Figure 28(B). The diffusion coefficient of H atoms in a-Si is smaller than that in a-SiO2. However, it was found that H atoms are less likely to diffuse than H atoms in a-SiO2. It is believed that the a-SiO2 film is more effective in preventing hydrogen contamination than the a-SiO2 film.

[0050] Next, regarding the shapes of the oxide semiconductor layer 108 and the silicon layer 112 in the structure shown in FIG. In the following description, the width (Wb) of the silicon layer 112 and the oxide semiconductor The width (Wc) of the layer 108 is the length of the silicon layer 112 in the channel width direction, It refers to the length of the oxide semiconductor layer 108. Also, it refers to the length (Lb) of the silicon layer 112, the length (Lc) of the oxide semiconductor layer 108, and the length (Ld) of the oxide semiconductor layer 108. The length (Lc) of the conductor layer 108 is the length of the silicon layer 112 in the channel length direction. The length of the oxide semiconductor layer 108 refers to the length of the oxide semiconductor layer 108. 20, the direction (between the source electrode layer 116a and the drain electrode layer 116b) is approximately parallel to the direction in which carriers move. The channel width direction refers to the direction connecting the first and second electrode layers 116b, and the channel width direction refers to the direction approximately perpendicular to the channel length direction. Point in a certain direction.

[0051] In the transistor shown in FIG. 1, the width (Wb) of the silicon layer 112 is set equal to the width (Wb) of the oxide semiconductor layer 108. (Wc) and the silicon layer 112 is made to be oxide semiconductor in the channel width direction. In this example, the insulating layer 108 is provided so as to extend over (transverse) both ends of the insulating layer 108. The length (Lb) of the silicon layer 112 is set to be smaller than the length (Lc) of the oxide semiconductor layer 108. Two regions that are not covered with the silicon layer 112 are provided in the channel length direction, and the two regions are spaced apart from each other. The source electrode layer 116a and the drain electrode layer 116b are electrically connected to the region where the gate electrode 116a is provided. By providing the oxide semiconductor layer 108 in this manner, The leakage current caused by changes in the semiconductor properties of the surface can be reduced.

[0052] Note that the structure of the transistor described in this embodiment is not limited to that shown in FIG.

[0053] In FIG. 1, the length (Lc) of the oxide semiconductor layer 108 is increased to Although the transistor 120 is shown to be configured so as to extend over the edge of the gate electrode 102, 3, the length (Lc) of the oxide semiconductor layer 108 is reduced. Alternatively, the entire oxide semiconductor layer 108 may be disposed on the gate electrode 102. In FIG. 3, FIG. 3(A) shows a top view, and FIG. 3(B) shows a top view of FIG. 3(A). 1 shows a cross-sectional view taken along line A1-B1 in FIG.

[0054] 1 and 3, in the region overlapping with the oxide semiconductor layer 108, The width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is set to the width (Wd) of the oxide semiconductor layer 108. It may be formed so that it is larger than (Wc) (see Figures 4(A) and (B)). The transistor 122 and the transistor 123 shown in FIG. 1B are formed on the silicon layer 1. The region of the oxide semiconductor layer 108 that is not in contact with the source electrode layer 116a and the drain electrode layer 116b is Since the oxide semiconductor layer 108 can be covered with the electrode layer 116b, the oxide semiconductor layer 108 is protected and reliability is improved. In addition, the oxide semiconductor layer 108 and the source electrode layer 1 The contact area between the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b is increased. The contact resistance between the source electrode layer 116a and the drain electrode layer 116b can be reduced. do.

[0055] The width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is the channel width The length of the source electrode layer 116a and the drain electrode layer 116b in the direction

[0056] The width (Wd) of the source electrode layer 116a and the drain electrode layer 116b is set to be equal to that of the silicon layer 11. 2 (Wb), or the width (Wb) of the source electrode layer 116a and the drain electrode layer 116b may be larger than the width (Wb) of the Only one width (Wd) of the oxide semiconductor layer 108 is set to the width (Wc) of the oxide semiconductor layer 108. The width (Wb) of the silicon layer 112 may be larger than the width (Wb) of the silicon layer 112.

[0057] In the structure shown in this embodiment mode, a black hole is formed above and / or below the silicon layer 112. A light-shielding portion such as a block matrix may be provided to shield the silicon layer 112 from light. By configuring the silicon layer 112 to be light-shielding, the silicon layer 112 is not irradiated with light. This can suppress variations in the electrical characteristics of the transistors caused by the gate When a light-shielding material is used for the gate electrode 102, the gate electrode 102 is formed on the upper side of the silicon layer 112 (gate electrode A light-shielding portion such as a black matrix may be provided on the opposite side to 102.

[0058] Next, an example of a method for manufacturing the transistor illustrated in FIGS. 1A to 1C will be described with reference to FIGS.

[0059] First, a gate electrode 102 is formed on a substrate 100, and then a gate electrode 103 is formed on the gate electrode 102. A gate insulating layer 104 is formed, and then an oxide semiconductor layer 106 is formed on the gate insulating layer 104. (See Figure 2(A)).

[0060] The substrate 100 may be any substrate having an insulating surface, and for example, a glass substrate may be used. Alternatively, the substrate 100 may be an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate. The surface of an insulating substrate made of an insulating material, or a semiconductor substrate made of a semiconductor material such as silicon, is covered with an insulating material. The surface of a conductive substrate made of a conductor such as metal or stainless steel is covered with an insulating material. In addition, plastic can be used as long as it can withstand the heat treatment in the manufacturing process. A block substrate can also be used.

[0061] The gate electrode 102 is formed by forming a conductive film on the entire surface of the substrate 100 and then by photolithography. The insulating film can be formed by etching the conductive film.

[0062] The gate electrode 102 is made of aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (Tungsten), or the like. It can be made of conductive materials such as stainless steel (W) and titanium (Ti). When aluminum is used as an electrode, aluminum itself has low heat resistance and is prone to corrosion. Therefore, it is preferable to form the conductive film by combining it with a heat-resistant conductive material.

[0063] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo). selected from Mo, Cr, Nd, and Sc an element, an alloy containing the above-mentioned element, an alloy containing a combination of the above-mentioned elements, or The film can be formed from a nitride containing the element. and aluminum (or copper) are laminated to form wiring and electrodes.

[0064] The gate electrode 102 is made of a material that is transparent to visible light and highly conductive. Such a material may be, for example, indium tin oxide (Indium Tin Oxide). indium tin oxide (ITO), indium tin oxide with silicon oxide (ITSO), Organic indium, organic tin, zinc oxide (ZnO), etc. can be used.

[0065] The gate insulating layer 104 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a nitride oxide film. The insulating film can be formed of a silicon oxide film, an aluminum oxide film, a tantalum oxide film, or the like. These films may be laminated by using, for example, a sputtering method. The film thickness can be formed to be 10 nm or more and 500 nm or less.

[0066] The oxide semiconductor layer 106 may be formed using an In—Ga—Zn—O-based oxide semiconductor. In this case, an oxide semiconductor target containing In, Ga, and Zn (e.g., In 2O3:Ga2O3:ZnO=1:1:1) by sputtering method. A compound semiconductor layer 106 can be formed.

[0067] The conditions for the sputtering method are, for example, a distance between the substrate 100 and the target of 30 mm or more and a distance between the substrate 100 and the target of 50 mm or more. 00mm or less, pressure between 0.01Pa and 2.0Pa, DC power supply 0.25k W or more and 5.0kW or less, temperature 20℃ or more and 200℃ or less, atmosphere argon, oxygen The atmosphere may be a mixture of argon and oxygen.

[0068] In addition, when using a pulsed direct current (DC) power supply in the sputtering method, dust can be reduced and the film thickness can be increased. The thickness of the oxide semiconductor layer 106 is preferably 5 nm to 20 nm. It can be made to be about 0 nm or less.

[0069] When an In—Ga—Zn—O-based non-single-crystal film is formed as the oxide semiconductor layer 106, The oxide semiconductor target containing In, Ga, and Zn is doped with insulating impurities. The impurities may include silicon oxide, germanium oxide, aluminum oxide, etc. Insulating oxides such as silicon nitride and aluminum nitride Nitride or insulating oxynitride such as silicon oxynitride or aluminum oxynitride is used. These insulating oxides or insulating nitrides do not impair the electrical conductivity of the oxide semiconductor. It is added at a concentration that is not too high.

[0070] By adding insulating impurities to the oxide semiconductor layer 106, the oxide semiconductor layer 106 By suppressing the crystallization of the oxide semiconductor layer 106, This makes it possible to stabilize the characteristics of thin film transistors. By including impurities such as silicon oxide in the oxide semiconductor, Even if heat treatment is performed at a temperature of 0.5° C. or less, crystallization of the oxide semiconductor or generation of microcrystalline grains can be prevented. Cut.

[0071] In addition to the above, oxide semiconductors applicable to the oxide semiconductor layer 106 include In—Sn—Zn— O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In -O-based, Sn-O-based, and Zn-O-based oxide semiconductors can be used. By adding impurities that suppress crystallization and maintain an amorphous state to the oxide semiconductor, The characteristics of the thin film transistor can be stabilized. Insulating oxides such as germanium oxide and aluminum oxide, silicon nitride, Insulating nitrides such as aluminum, silicon oxynitride, aluminum oxynitride, etc. Examples include insulating oxynitrides such as silicon dioxide.

[0072] Next, the oxide semiconductor layer 106 is etched to form an island-shaped oxide semiconductor layer 108 ( At this time, the island-shaped oxide semiconductor layer 108 is formed on at least the gate electrode 10 The oxide semiconductor layer 106 is etched so as to remain above the insulating film 2.

[0073] Next, a silicon layer 110 is formed to cover the oxide semiconductor layer 108 (see FIG. 2C). ).

[0074] The silicon layer 110 can be formed by sputtering. DC welding using a silicon target or a boron-doped silicon target under atmospheric pressure The silicon layer 110 can be formed by sputtering. However, it is not limited to this. The silicon layer 110 may be formed by a CVD method or the like. At the interface between the conductor layer 108 and the silicon layer 110, In some cases, a thin mixed layer (for example, silicon oxide) may be formed.

[0075] Next, the silicon layer 110 is etched to form island-shaped silicon layers 112 (FIG. 2(D) At this time, the island-shaped silicon layer 112 is formed in a region that overlaps at least the gate electrode 102. The silicon layer 110 is etched so as to remain in the oxide semiconductor layer 108. The silicon layer 110 is etched to expose at least a portion of the

[0076] For example, etching is performed using TMAH (Tetra Methyl Ammonium Hydroxide, tetramethylammonium hydroxide) In this case, the oxide semiconductor layer 108 and the silicon layer 110 The etching selectivity can be increased, and the oxide semiconductor layer 108 is almost entirely etched. The silicon layer 110 can be etched well without causing any oxide Damage to the semiconductor layer 108 can be reduced.

[0077] The etching selectivity is, for example, the ratio of the thickness of the A layer to the thickness of the B layer when etching the A layer and the B layer. This means the difference between the etching rate of layer A and the etching rate of layer B. A large selectivity means that there is a sufficient difference in etching rate.

[0078] Next, a conductive film 11 is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. Form 4 (see Figure 2(E)).

[0079] The conductive film 114 is formed by depositing aluminum (Al), copper (Cu) or the like by using a sputtering method or a vacuum deposition method. ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), Metals containing elements selected from chromium (Cr), neodymium (Nd), and scandium (Sc), Alloys containing the above elements or materials made of nitrides containing the above elements. It can be formed.

[0080] For example, the conductive film 114 can be formed to have a single-layer structure of a molybdenum film or a titanium film. Alternatively, the conductive film 114 may be formed to have a stacked structure, for example, an aluminum film, a titanium film, and the like. The titanium film, the aluminum film, and the titanium film may be stacked in this order. Alternatively, a three-layer structure may be formed by laminating a molybdenum film, an aluminum film, and a molybdenum film. The aluminum used in these laminated structures may be a three-layer structure. The film may be an aluminum film containing neodymium (Al-Nd). The film 114 may be a single layer structure of aluminum film containing silicon.

[0081] In addition, the conductive film 114 is formed using a material that transmits visible light and has high conductivity. Such a material may be, for example, indium tin oxide (InTnO). Tin Oxide (ITO), Indium Tin Oxide with Silicon Oxide (ITSO), Organic Indium, organic tin, zinc oxide (ZnO), etc. can be used.

[0082] Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b. At this time, the conductive film 114 is etched depending on the etching conditions. At the same time as etching, the silicon layer 112 may also be etched and reduced in thickness. This shows a case where the silicon layer 112 is also etched and reduced in thickness when the film 114 is etched. There are.

[0083] In the above process, the silicon layer 112 is formed by etching the oxide semiconductor Acts as a channel protection layer (channel stop layer) that suppresses etching of layer 108 Note that in the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided, In some cases, the oxide semiconductor layer 108 is reduced in thickness simultaneously with the etching of the conductive film 114 .

[0084] In this way, by providing the silicon layer 112 so as to be in contact with the oxide semiconductor layer 108, In this case, it is possible to prevent unintended elements such as hydrogen from entering the oxide semiconductor layer 108 from the outside. This can be done.

[0085] Through the above steps, the transistor 120 can be manufactured.

[0086] A protective insulating layer may be formed to cover the transistor 120. For example, a silicon oxide film, a silicon nitride film, an oxide film, or the like can be formed by using a CVD method or a sputtering method. Silicon oxide nitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film, oxide The aluminum oxide nitride film may be formed as a single layer or a multilayer of an aluminum nitride oxide film. After the source electrode layer 116a and the drain electrode layer 116b are formed, the silicon layer 11 The exposed portion of the source electrode layer 116a is oxidized (including natural oxidation) or nitrided. a silicon oxide film on the silicon layer 112 located in the region between the drain electrode layer 116b and the drain electrode layer 116c; A silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film may be formed.

[0087] In the step of FIG. 2, after the oxide semiconductor layer 108 is formed, In an atmosphere, 100°C to 600°C, typically 200°C to 400°C It is preferable to perform heat treatment. For example, heat treatment is performed at 350°C for 1 hour in a nitrogen atmosphere. This heat treatment causes rearrangement at the atomic level in the island-shaped oxide semiconductor layer 108. The oxide semiconductor layer 108 is advantageous in that it can release strain that inhibits carrier movement. It's important.

[0088] The timing of the heat treatment is not particularly limited as long as it is performed after the oxide semiconductor layer 106 is formed. First, the silicon layer 110 is formed, and then the island-shaped silicon layer 112 is formed. Then, the conductive film 11 After forming the source electrode layer 116a and the drain electrode layer 116b, or The heat treatment may be performed after forming a protective insulating layer. The oxide semiconductor layer 108 and the silicon layer 112 are mixed at the interface between the layer 108 and the silicon layer 112. A thin layer (eg, an oxide of silicon) may be formed.

[0089] Thereafter, various electrodes and wiring are formed to complete a semiconductor device equipped with a transistor 120. Complete.

[0090] In FIG. 2, the silicon layer 110 is formed after the oxide semiconductor layer 108 is formed. However, the oxide semiconductor layer 106 and the silicon layer 110 are stacked in succession. Then, a plurality of masks are used to pattern the silicon layer 112 and the oxide semiconductor layer 108. The manufacturing method in this case will be described with reference to FIG.

[0091] First, a gate electrode 102 is formed on a substrate 100, and then a gate electrode 103 is formed on the gate electrode 102. Then, an oxide semiconductor layer 106 and a silicon dioxide film are formed on the gate insulating layer 104. After forming the silicon layer 110 by laminating it in order, a resist mask 175 is selectively formed ( 25A). The gate insulating layer 104 to the silicon layer 110 or the oxide semiconductor layer Preferably, layers 106 through silicon layer 110 are deposited in succession.

[0092] Next, the resist mask 175 was used to remove the insulating film from the silicon layer 110 and the oxide semiconductor layer 106. The necessary portions are etched to form island-shaped oxide semiconductor layers 108 and silicon layers 111. (See FIG. 25(B)). After that, the resist mask 175 is removed.

[0093] Next, a resist mask 176 is formed on the silicon layer 111. The exposed silicon layer 111 is etched using the etching method. 12 is formed (see FIG. 25(C)).

[0094] Next, a conductive film 11 is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. After forming the conductive film 114 (see FIG. 25(D)), the conductive film 114 is etched to form the source electrode Then, a layer 116a and a drain electrode layer 116b are formed (see FIG. 25E).

[0095] Through the above steps, a transistor 124 as shown in FIG. The transistor 124 shown by 26 has a width (Wb) of the silicon layer 112 and a width (Wb) of the oxide semiconductor layer 10 26 shows the case where the widths (Wc) of the respective portions 8 are set equal to each other. 26(A) shows a top view, and FIG. 26(B) shows the area between A1 and B1 in FIG. 26(A). 26(C) shows a cross-sectional view taken along the line A2-B2 in FIG. 26(A). are.

[0096] In this way, by continuously forming the oxide semiconductor layer 106 and the silicon layer 110, The surface of the oxide semiconductor layer 106 may be damaged by an etching agent, plasma, or the like. and can be reduced.

[0097] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0098] (Embodiment 2) In this embodiment, a manufacturing method and a structure of a transistor different from those in Embodiment 1 will be described. , will be explained with reference to the drawings.

[0099] First, a method for manufacturing a transistor will be described with reference to FIGS. The manufacturing process (applicable materials, etc.) shown in this embodiment is common to those in the first embodiment. Therefore, in the following, we will omit the explanation of the overlapping parts and focus on the differences in detail. explain.

[0100] First, a gate electrode 102 is formed on a substrate 100, and then a gate electrode 103 is formed on the gate electrode 102. Then, an oxide semiconductor layer 106 and a silicon dioxide film are formed on the gate insulating layer 104. After forming the silicon layer 110 by laminating it in order, a resist mask 171 is selectively formed ( 5A). The gate insulating layer 104 to the silicon layer 110 or the oxide semiconductor layer It is preferable that the layers 106 to the silicon layer 110 are deposited successively.

[0101] Next, the silicon layer 110 is etched using the resist mask 171 to form island-shaped silicon layers. An insulating layer 111 is formed (see FIG. 5(B)). Here, an alkaline etching solution is used. By using an alkaline etching solution, the oxide semiconductor is The etching selectivity between the conductor layer 106 and the silicon layer 110 can be increased. The layer 110 can be selectively etched. For example, TMAH (Tetra Methyl Ammonium Hydroxide) ide, tetramethylammonium hydroxide) can be used.

[0102] Next, the oxide semiconductor layer 106 is etched using the resist mask 171 to form island-shaped oxide films. Then, a compound semiconductor layer 108 is formed (see FIG. 5(C)). Here, an acid-based etching solution is used. By using an acid-based etching solution, the oxide semiconductor The etching selectivity between the oxide semiconductor layer 106 and the silicon layer 111 can be increased. The layer 106 can be selectively etched. The acid-based etching solution is For example, a mixture of phosphoric acid, acetic acid, nitric acid and water (also called aluminum mixed acid) can be used. do.

[0103] Next, the silicon layer 111 is etched using the resist mask 171 to form island-shaped silicon Then, an insulating layer 112 is formed (see FIG. 5(D)). Here, an alkaline etching solution is used again. Wet etching is performed using an alkaline etching solution. The etching selectivity between the compound semiconductor layer 108 and the silicon layer 111 can be increased. The silicon layer 111 can be selectively etched. Here, the etching is isotropic. The etching proceeds, and the side surfaces of the silicon layer 111 are etched (side etching). Potassium-based etching solutions include, for example, TMAH (Tetra Methyl Ammonium Hydroxide). ammonium hydroxide, tetramethylammonium hydroxide) This can be done.

[0104] In this way, by etching the silicon layer after etching the oxide semiconductor layer, The oxide semiconductor layer and the silicon layer can be etched without adding a mask. Therefore, the process can be simplified.

[0105] Next, a conductive film is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. After forming the conductive film, the conductive film is etched to form the source electrode layer 116a and the drain electrode layer 116b. b is formed (see FIG. 5(E)).

[0106] Through the above steps, a transistor 130 as shown in FIG. 6A shows a top view, and FIG. 6B shows the A in FIG. 6A. 6(C) shows a cross section between A2 and B2 in FIG. 6(A). The figure shows:

[0107] When the manufacturing method shown in FIG. 5 is used, the width (Wb ) is smaller than the width (Wc) of the oxide semiconductor layer 108, and the length of the silicon layer 112 (Lb) is smaller than the length (Lc) of the oxide semiconductor layer 108.

[0108] In the manufacturing process of FIG. 5, the oxide semiconductor layer 106 and the silicon layer 110 are formed successively. As a result, damage caused by an etching agent, plasma, etc. is prevented from being caused on the surface of the oxide semiconductor layer 106. The oxide semiconductor layer and the edge of the oxide semiconductor layer can be formed on the oxide semiconductor layer. By providing a silicon layer that can obtain etching selectivity, etching of the oxide semiconductor layer and the silicon layer can be performed. Even when etching is performed, the process can be simplified without adding a mask. Cut.

[0109] After the transistor 130 is formed, a protective insulating layer is formed to cover the transistor 130. 5, after the oxide semiconductor layer 108 is formed, The heat treatment may be carried out in an atmosphere or in the air.

[0110] Note that the method for manufacturing the transistor 130 shown in FIG. 6 is not limited to the method shown in FIG. For example, after the process up to FIG. 5(C), the resist mask 171 is annealed with oxygen plasma. By performing etching, the resist mask 171 is isotropically shrunk to form the silicon layer 11 After exposing a portion of silicon layer 111, the exposed portion of silicon layer 111 is etched away. The silicon layer 112 may be formed by the above method.

[0111] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0112] (Embodiment 3) In this embodiment, a transistor different from those in Embodiments 1 and 2 and a manufacturing method thereof will be described. The manufacturing process (applicable materials, etc.) shown in this embodiment mode will be described with reference to the drawings. Many parts are common to the first embodiment. Therefore, in the following, overlapping parts will be omitted. The explanation of the parts that are the same will be omitted, and the differences will be explained in detail.

[0113] The transistor 140 shown in FIG. 7 includes a gate electrode 102 provided on a substrate 100 and a gate A gate insulating layer 104 is provided on the gate electrode 102, and a gate insulating layer 105 is provided on the gate insulating layer 104. The oxide semiconductor layer 108 and a silicon dioxide film provided on and in contact with the surface of the oxide semiconductor layer 108 The contact layer 112 and the source electrode layer provided on the surface of the oxide semiconductor layer 108 in contact therewith. The oxide semiconductor layer 108 has a source electrode layer 116a and a drain electrode layer 116b. The low resistance regions 109a and 109b are formed in the regions in contact with the electrode layer 116a and the drain electrode layer 116b. is provided.

[0114] That is, the transistor 140 described in this embodiment has the same structure as that described in the above embodiment. A low resistance region is formed in the region of the oxide semiconductor layer 108 where the silicon layer 112 is not provided. 7A is a diagram showing the configuration in which 109a and 109b are added. 7(B) shows a cross-sectional view taken along line A1-B1 in FIG. 7(A).

[0115] The low-resistance regions 109a and 109b are formed by oxygen vacancies (silicon vacancies) in the oxide semiconductor layer 108. The silicon layer 112 can be provided by making the silicon layer 112 in an oxygen-deficient state compared to the contact area. The oxygen vacancies occur in the oxide semiconductor layer 108 where the silicon layer 112 is not provided. By selectively treating the region with a reducing gas such as hydrogen or argon, the good.

[0116] Alternatively, hydrogen may be selectively added to the oxide semiconductor layer 108 to form the low-resistance region 109. a, 109b may be provided.

[0117] The low resistance regions 109a and 109b are the source and drain regions of the transistor 140. The source electrode layer 116a is provided in contact with the low resistance region 109a. The drain electrode layer 116b is provided in contact with the region 109b, thereby 8 and the source electrode layer 116a and the drain electrode layer 116b. This can be done.

[0118] Next, an example of a method for manufacturing the transistor illustrated in FIGS. 7A to 7C will be described with reference to FIGS.

[0119] First, the steps shown in FIGS. 2(A) to 2(D) are carried out to etch the silicon layer 112. The resist mask 172 used in the step 172 is left (see FIG. 8(A)).

[0120] Next, the oxide semiconductor layer 108 is treated with a reducing agent such as hydrogen or argon using the resist mask 172. The oxide semiconductor layer 108 is subjected to plasma treatment using a reactive gas, and the low-resistance regions 109a and 109b are formed in the oxide semiconductor layer 108. (See FIG. 8(B)).

[0121] Next, a conductive film 11 is formed on the gate insulating layer 104, the oxide semiconductor layer 108, and the silicon layer 112. 8C. Note that the conductive film 114 is formed on the oxide semiconductor layer 108 to reduce the resistance of the oxide semiconductor layer 108. It is formed so as to contact the regions 109a and 109b.

[0122] Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b. (See FIG. 8(D)).

[0123] Through the above steps, the transistor 140 can be manufactured.

[0124] After the transistor 140 is formed, a protective insulating layer is formed to cover the transistor 140. 8, after the oxide semiconductor layer 108 is formed, The heat treatment may be carried out in an atmosphere or in the air.

[0125] 7 and 8, the oxide semiconductor layer 108 is provided with low-resistance regions 109a and 109b. As a result, the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b Although the case where the contact resistance with the substrate is reduced is shown, the present invention is not limited to this.

[0126] 9A and 9B, the oxide semiconductor layer 108 and the source The first metal oxide layer 11 is formed between the drain electrode layer 116a and the drain electrode layer 116b. 9, a structure in which a second metal oxide layer 115a and a second metal oxide layer 115b are provided may be used. 9(A) shows a top view, and FIG. 9(B) shows a cross-sectional view taken along A1-B1 in FIG. 9(A). It shows.

[0127] The first metal oxide layer 115a and the second metal oxide layer 115b are made of at least an oxide semiconductor. It may be made of a metal oxide having a lower resistance than the layer 108 .

[0128] The first metal oxide layer 115a and the second metal oxide layer 115b are formed on the oxide semiconductor layer 1. The same material as the oxide semiconductor layer 08 can be used, but the deposition conditions can be different. The conductor layer 108, the first metal oxide layer 115a, and the second metal oxide layer 115b are made of In- When a Ga—Zn—O-based non-single crystal film is used, the first metal oxide layer 115a and the second metal oxide layer 115b are The oxygen gas flow rate and the deposition conditions for the In-Ga-Zn-O-based non-single-crystal film of the oxide layer 115b are The ratio of the argon gas flow rate is higher than that of the In—Ga—Zn—O-based non-single-crystal film of the oxide semiconductor layer 108. The film formation conditions are set so that the ratio of the oxygen gas flow rate is high. In—Ga—Zn—O-based non-single-crystal films of the first metal oxide layer 115a and the second metal oxide layer 115b The film formation conditions are set under a rare gas (argon, helium, etc.) atmosphere (or oxygen gas 10% Hereinafter, the gas is argon gas (90% or more), and the oxide semiconductor layer 108 is an In—Ga—Zn—O system. The film formation conditions for the non-single crystal film are set to an oxygen-mixed atmosphere (oxygen gas flow rate is higher than the rare gas flow rate). It is possible.

[0129] In this manner, the oxide semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b A first metal oxide layer 115a and a second metal oxide layer 115b are provided between the first metal oxide layer 115a and the second metal oxide layer 115b. This prevents carrier injection from the source electrode layer 116a and the drain electrode layer 116b. Since the wall can be reduced, the oxide semiconductor layer 108, the source electrode layer 116a, and the drain electrode layer The contact resistance with 116b can be reduced.

[0130] The first metal oxide layer 115a and the second metal oxide layer 115b are the same as those shown in FIGS. After the steps up to (D) are performed, a metal oxide film is formed on the silicon layer 112 and the oxide semiconductor layer 108. The conductive film 114 is then etched in the same manner as the conductive film 114. In this case, the conductive film 11 can be formed by etching under the etching conditions and the selected material. 4 and the metal oxide layer, or the conductive film 114, the metal oxide layer, and the oxide semiconductor layer 108 are simultaneously etched. It may be switched on.

[0131] 9C, a transistor 142 having a low-resistance region in the oxide semiconductor layer 108 The first metal oxide layer 115a and the second metal oxide layer 115b are formed on the surface of the substrate 109a. A layer 115b may be provided.

[0132] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0133] (Fourth embodiment) In this embodiment, a transistor different from those in Embodiments 1 to 3 and a manufacturing method thereof will be described. The manufacturing process (applicable materials, etc.) shown in this embodiment mode will be described with reference to the drawings. Many parts are common to the first embodiment. Therefore, in the following, overlapping parts will be omitted. The explanation of the parts that are the same will be omitted, and the differences will be explained in detail.

[0134] The transistor 150 shown in FIGS. 10A and 10B has a gate electrode provided on a substrate 100. a gate electrode 102, a gate insulating layer 104 provided on the gate electrode 102, and a gate insulating layer 10 The source electrode layer 116a and the drain electrode layer 116b are provided on the source electrode layer 114. 16a and the drain electrode layer 116b, and above the gate electrode 102. The gate insulating layer 116 is located in the region between the source electrode layer 116a and the drain electrode layer 116b. The oxide semiconductor layer 108 is provided on the oxide semiconductor layer 104, and the oxide semiconductor layer 108 is provided to cover the oxide semiconductor layer 108. It has a silicon layer 112 .

[0135] That is, the transistors 150 and 151 shown in this embodiment are the same as those in the above embodiment. In the structure shown in FIG. 1, the source electrode layer 116a, the drain electrode layer 116b, and the oxide semiconductor The structure shown in FIG. 10 is a board structure in which the top and bottom of the conductor layer 108 are reversed. It is also called Tom-gate bottom contact type. In Figure 10, Figure 10(A) shows the top surface. 10(B) shows a cross-sectional view taken along line A1-B1 in FIG. 10(A). .

[0136] As shown in FIGS. 10A and 10B, the oxide semiconductor layer 108 is By providing a silicon layer 112 in contact with the surface opposite to the electrode 102, Therefore, the incorporation of hydrogen into the oxide semiconductor layer 108 can be suppressed. Therefore, the change in the semiconductor characteristics of the oxide semiconductor layer 108 caused by the above-mentioned phenomenon can be suppressed. It is possible to suppress fluctuations in the characteristics of the transistor having the channel layer 108.

[0137] In addition, as in a transistor 151 shown in FIG. 10C, Between the metal electrode layer 116b and the oxide semiconductor layer 108, metal oxide layers 115a and 115b are formed. By providing the metal oxide layers 115a and 115b, the oxide The contact resistance between the compound semiconductor layer 108 and the source electrode layer 116a and the drain electrode layer 116b is The resistance can be reduced.

[0138] Next, an example of a method for manufacturing the transistors shown in FIGS. 10A and 10B will be described with reference to FIGS. 11A and 11B. and explain.

[0139] First, a gate electrode 102 is formed on a substrate 100, and then a gate electrode 103 is formed on the gate electrode 102. A gate insulating layer 104 is formed, and then a source electrode layer 116a and a drain electrode layer 116b are formed on the gate insulating layer 104. The drain electrode layer 116b is formed (see FIG. 11(A)).

[0140] Next, the oxide semiconductor layer 116 is formed on the source electrode layer 116a and the drain electrode layer 116b. 06 (see Figure 11(B)).

[0141] Next, the oxide semiconductor layer 106 is etched to form an island-shaped oxide semiconductor layer 108 ( At this time, the island-shaped oxide semiconductor layer 108 is formed on at least the gate electrode 1. The oxide semiconductor layer 106 is etched so that it remains above the oxide semiconductor layer 102.

[0142] Next, a silicon layer 110 is formed so as to cover the oxide semiconductor layer 108 (see FIG. 11(D)). (see).

[0143] Next, the silicon layer 110 is etched to form island-shaped silicon layers 112 (FIG. 11( See E).

[0144] Through the above steps, the transistor 150 can be manufactured.

[0145] After the transistor 150 is formed, a protective insulating layer is formed to cover the transistor 150. 11, after the oxide semiconductor layer 108 is formed, a nitride The heat treatment may be carried out in a nitrogen atmosphere or in an air atmosphere.

[0146] In addition, when the transistor shown in FIG. 10C is manufactured, On the gate insulating layer 104, a conductive layer constituting the source electrode layer 116a and the drain electrode layer 116b is formed. The metal oxide layers 115a and 115b are formed by laminating the metal oxide layer 115a and the metal oxide layer 115b in this order. 10C, the oxide semiconductor layer 106 is When the island-shaped oxide semiconductor layer 108 is formed by etching, the metal oxide layers 115a, 1 15b is also etched at the same time.

[0147] In FIG. 11, the island-shaped silicon layer 112 is formed so as to completely cover the oxide semiconductor layer 108. The silicon layer 112 is formed by at least oxidizing the silicon. It is sufficient to provide the layer 104 so as to be in contact with the region where the channel is formed in the compound semiconductor layer 108. For example, as in a transistor 152 illustrated in FIG. 12, In FIG. 12, the silicon layer 112 can be formed as an oxide semiconductor. The source electrode layer 116a and the drain electrode layer 116b are formed so as to be in contact with a part of the conductor layer 108. 16b), the silicon layer 112, the oxide semiconductor layer 108, the source 1 illustrates a case where a protective insulating layer 119 is provided over the electrode layer 116a and the drain electrode layer 116b. There are.

[0148] The protective insulating layer 119 is formed by depositing a silicon oxide film using, for example, a CVD method or a sputtering method. , silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitride a single layer of an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film; It may be formed by laminating layers.

[0149] In FIG. 12, FIG. 12(A) shows a top view, and FIG. 12(B) shows a bottom view. ) shows a cross-sectional view of A1-B1.

[0150] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0151] (Embodiment 5) In this embodiment, a semiconductor device including the transistor described in any of the first to fourth embodiments will be described. A manufacturing process of a display device, which is an example of a use mode, will be described with reference to the drawings. In many respects, the manufacturing process (applicable materials, etc.) shown in the embodiment is the same as that of the first embodiment. Therefore, in the following, we will omit the explanation of the overlapping parts and focus on the differences. In the following description, Figs. 15 to 19 show top views. 13 and 14 show cross-sectional views between A3-B3 and A4-B4 in FIGS. 15 to 19. are.

[0152] First, wiring and electrodes (gate wiring including a gate electrode 102) are formed on a substrate 100 having an insulating surface. Then, the gate insulating layer 104 and the oxide film 306 are formed. Then, the compound semiconductor layer 106 is formed (see FIG. 13(A) and FIG. 15).

[0153] The capacitor wiring 308 and the first terminal 321 are formed at the same time as the gate electrode 102 using the same material. It is possible.

[0154] Next, the oxide semiconductor layer 106 is etched to form an island-shaped oxide semiconductor layer 108. (see FIG. 16), a silicon layer 110 is formed to cover the oxide semiconductor layer 108 (see FIG. 1 3(B)). At this time, the island-shaped oxide semiconductor layer 108 is formed on at least the gate electrode 102. The oxide semiconductor layer 106 is etched so as to remain above the oxide semiconductor layer 106.

[0155] Next, the silicon layer 110 is etched to form island-shaped silicon layers 112 (FIG. 13( At this time, the island-shaped silicon layer 112 is formed on at least the gate electrode 102. The silicon layer 110 is etched so as to remain in the area overlapping with the oxide semiconductor. Silicon layer 110 is etched to expose at least a portion of body layer 108 .

[0156] Next, a contact hole 31 is formed in the gate insulating layer 104 so as to expose the first terminal 321. After forming the gate insulating layer 104, the oxide semiconductor layer 108 and the silicon layer 112, The conductive film 114 is formed in this manner (see FIG. 13D). The first terminal 321 is electrically connected via a contact hole 313 .

[0157] Next, the conductive film 114 is etched to form the source electrode layer 116a and the drain electrode layer 116b. Then, a connection electrode 320 and a second terminal 322 are formed (see FIG. 14(A) and FIG. 18). The silicon layer 112 functions as a channel protection layer for the oxide semiconductor layer 108 .

[0158] The second terminal 322 is electrically connected to the source wiring (the source wiring including the source electrode layer 116a). The connection electrode 320 can be directly connected to the first terminal 321. The configuration can be such that the two are connected.

[0159] Through the above steps, the transistor 160 can be manufactured.

[0160] Next, heat treatment is performed at 200°C or higher and 600°C or lower, typically 300°C or higher and 500°C or lower. For example, heat treatment is performed at 350° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer 108 is formed by the In-Ga-Zn-O-based non-single crystal film. This heat treatment releases the distortion that inhibits carrier movement, The heat treatment (including optical annealing) is effective. The timing for the heat treatment is as follows: There are no particular limitations on the method as long as it is after the oxide semiconductor layer 106 is formed. For example, This may be done after the formation of the poles.

[0161] Next, a protective insulating layer 340 is formed to cover the transistor 160. 0 is selectively etched to form a contact hole 325 reaching the drain electrode layer 116b, A contact hole 326 reaching the connection electrode 320 and a contact hole 328 reaching the second terminal 322 are formed. A hole 327 is formed (see FIG. 14(B)).

[0162] Next, a transparent conductive layer 310 electrically connected to the drain electrode layer 116b and a connection electrode 320 are A transparent conductive layer 328 electrically connected to the second terminal 322 329 is formed (see FIG. 14(C) and FIG. 19).

[0163] The transparent conductive layer 310 functions as a pixel electrode, and the transparent conductive layers 328 and 329 are for connection with the FPC. More specifically, the transparent conductive layer formed on the connection electrode 320 serves as an electrode or wiring used for the connection electrode 320. The transparent conductive layer 328 is used as a terminal electrode for connection that functions as an input terminal of the gate wiring. The transparent conductive layer 329 formed on the terminal 322 of the second electrode functions as an input terminal of the source wiring. It can be used as a terminal electrode for connection.

[0164] In addition, the capacitance wiring 308, the gate insulating layer 104, the protective insulating layer 340, and the transparent conductive layer 310 In this case, the capacitor wiring 308 and the transparent conductive layer 310 The gate insulating layer 104 and the protective insulating layer 340 serve as dielectrics.

[0165] The transparent conductive layers 310, 328, and 329 are made of indium oxide (In2O3), indium oxide Tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy Gold (In2O3-ZnO) can be formed using sputtering or vacuum deposition. For example, after forming a transparent conductive film, a resist mask is formed on the transparent conductive film, and an etching Transparent conductive layers 310, 328, and 329 are formed by removing unnecessary portions by etching. It is possible.

[0166] By the above process, elements such as bottom gate n-channel thin film transistors and storage capacitors can be fabricated. These elements are then arranged in a matrix to correspond to the individual pixels. By disposing the organic EL element in this manner, an active matrix display device can be manufactured.

[0167] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0168] (Embodiment 6) In this embodiment mode, a liquid crystal display device is exemplified as a semiconductor device including a thin film transistor. First, the appearance and cross section of a liquid crystal display panel, which is one type of semiconductor device, are shown in Figure 2. 20(A1) and 20(A2) show the structure of an oxide film formed on a first substrate 4001. thin film transistors 4010 and 4011 having a nitride semiconductor layer and a liquid crystal element 4013, FIG. 4 is a top view of a panel sealed between a second substrate 4006 and the panel by a sealant 4005; FIG. 20(B) corresponds to a cross-sectional view taken along line MN in FIGS. 20(A1) and 20(A2).

[0169] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0170] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 20(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0171] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 20B, the thin film transistor included in the pixel portion 4002 is a thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 The insulating layers 4020 and 4011 are formed on the thin film transistors 4010 and 4011. 21 is provided.

[0172] The thin film transistors 4010 and 4011 can be formed using the structure shown in the above embodiment mode. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. It is a membrane transistor.

[0173] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0174] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically stainless steel). Materials that can be used include FR, ceramics, and plastics. P (Fiberglass-Reinforced Plastics) plate, PVF (Polymer glass) vinyl fluoride film, polyester film or acrylic resin film Aluminum foil can also be used as a PVF film or polyester film. It is also possible to use a sheet sandwiched between two sheets.

[0175] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031, A spherical spacer may be used. 1 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 4 to the substrate via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 4 to the common potential line. Included in 005.

[0176] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs to It is optically isotropic, requiring no alignment treatment, and has little viewing angle dependency. stomach.

[0177] The liquid crystal display device shown in this embodiment is an example of a transmission type liquid crystal display device. The device can be applied to both reflective and semi-transmissive liquid crystal display devices.

[0178] In addition, in the liquid crystal display device described in this embodiment mode, a polarizing plate is provided on the outer side (viewing side) of the substrate, and In this example, a colored layer and an electrode layer for a display element are provided on the side of the substrate in this order. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and the polarizing plate may be provided on the The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding film that functions as a light shielding film may be provided.

[0179] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, To improve the reliability of thin film transistors, the film functions as a protective film and a planarizing insulating film. The insulating layer 4020 and the insulating layer 4021 are used to cover the insulating layer 4020 and the insulating layer 4021. is intended to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective film is preferably a silicon oxide film, a silicon nitride film, or the like, which is formed by sputtering. Silicon film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride Aluminum nitride film, aluminum oxide nitride film, or aluminum nitride oxide film, or a single layer or laminated layer. In this embodiment, an example in which the protective film is formed by sputtering is shown, but the method is not particularly limited. The insulating film may be formed by various methods.

[0180] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. When a silicon film is used, the aluminum film used as the source electrode layer and the drain electrode layer can be It is effective in preventing locking.

[0181] In addition, an insulating layer is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. When this happens, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent the problem of

[0182] After forming the protective film, the semiconductor layer is annealed (at 200°C or higher and 400°C or lower). That's fine.

[0183] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking a plurality of insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0184] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0185] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, The semiconductor layer may be annealed (at 200°C to 400°C) at the same time as the annealing process. By combining the baking process of the insulating layer 4021 with the annealing process of the semiconductor layer, the semiconductor device can be efficiently manufactured. It is possible to create the following.

[0186] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide Conductive materials can be used.

[0187] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The formed pixel electrode preferably has a light transmittance of 70% or more at a wavelength of 550 nm. In addition, the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less. preferable.

[0188] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0189] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0190] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 40 The source electrode layer and the drain electrode layer 11 are formed of the same conductive film.

[0191] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0192] In FIG. 20, a signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0193] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0194] (Embodiment 7) In this embodiment, electronic paper is shown as an example of a semiconductor device including a transistor. .

[0195] FIG. 21 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device may be the thin film transistor shown in any one of the first to fifth embodiments. It can be fabricated in the same way as a transistor.

[0196] The electronic paper in Figure 21 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of controlling the orientation of spherical particles and performing display by generating a

[0197] The thin film transistor 581 provided on the substrate 580 is a thin film transistor of a bottom gate structure. The source electrode layer or the drain electrode layer is a first electrode layer 587 and an insulating layer 583. The first electrode 84 is electrically connected to the second electrode 585 through contact holes formed therein. Between the layer 587 and the second electrode layer 588, there are black areas 590a and white areas 590b. and a spherical particle 589 containing a cavity 594 filled with liquid therearound. The spherical particles 589 are surrounded by a filler 595 such as resin (see FIG. 21). In the LCD panel 21, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is provided over the same substrate as the thin film transistor 581. The common connection portion shown in the above embodiment is used to electrically connect a pair of A second electrode layer 588 provided on the substrate 596 is connected to the substrate 596 via conductive particles disposed between the substrates. It can be electrically connected to a common potential line.

[0198] It is also possible to use an electrophoretic element instead of the twist ball. A transparent liquid, positively charged white particles, and negatively charged black particles are enclosed in a 10 mm diameter container. Microcapsules of about 200 μm are used. Between the first electrode layer and the second electrode layer The microcapsules provided on the substrate are subjected to an electric field by the first electrode layer and the second electrode layer. When the screen is turned on, the white particles and black particles move in opposite directions, allowing the screen to display either white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary light It does not require a battery, consumes little power, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the image that has been displayed can be maintained. Therefore, it is possible to transmit the signal from the radio wave source to the semiconductor device with a display function (simply a display device, or a display The displayed image is preserved even if the device (also called a semiconductor device) is moved away. It becomes possible to keep

[0199] As described above, electronic paper with high reliability as a semiconductor device can be manufactured.

[0200] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0201] (Embodiment 8) In this embodiment mode, a light-emitting display device will be described as an example of a semiconductor device including a transistor. The display device has a display element that uses electroluminescence. The light-emitting element that uses electroluminescence is an organic light-emitting material. Generally, the former is used in organic EL devices, The latter is called an inorganic EL element.

[0202] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0203] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. It is a localized emission that uses

[0204] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be described with reference to FIG. 22. FIG. 22(A) shows a cross section of a semiconductor device formed on a first substrate 4501. The thin film transistors 4509 and 4510 and the light emitting element 4511 are mounted on a second substrate 450. 22(B) is a top view of the panel sealed with a sealant 4505 between the panel and the substrate 6. This corresponds to a cross-sectional view taken along line HI in FIG. 22(A). An explanation will be given using an organic EL element.

[0205] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0206] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 22B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0207] The thin film transistors 4509 and 4510 can be formed using the structure described in the above embodiment mode. In this embodiment mode, the thin film transistors 4509 and 4510 are n-channel thin film transistors. It is a membrane transistor.

[0208] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0209] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0210] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0211] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon nitride oxide film, a DLC film, etc.

[0212] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0213] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film.

[0214] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0215] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 must be light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0216] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used.

[0217] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0218] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0219] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0220] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0221] (Embodiment 9) The semiconductor device including the transistor described in the above embodiment can be used in various electronic devices (play equipment, etc.). The present invention can be applied to electronic devices such as television sets ( Televisions (also called televisions or television receivers), computer monitors, digital Cameras, digital video cameras, digital photo frames, mobile phones (mobile phones) mobile phones, mobile phone devices), portable game consoles, personal digital assistants, sound reproducing devices, pachinko machines, Examples include large game machines such as prank machines.

[0222] FIG. 23A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0223] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0224] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0225] FIG. 23B shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0226] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0227] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0228] FIG. 24(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 24(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least the semiconductor device It is sufficient that the system is equipped with the above-mentioned equipment, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in FIG. 24(A) uses a program or data recorded on a recording medium. It has the function of reading the information and displaying it on the display, and sharing information with other portable gaming machines via wireless communication. The functions of the portable gaming machine shown in FIG. 24(A) are not limited to these. It can have a variety of functions.

[0229] FIG. 24(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is It is not limited to the above, but may be configured to include at least a semiconductor device, and other accessories may be included. The configuration can be appropriately provided.

[0230] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0231] 100 boards 102 gate electrode 104 Gate insulating layer 106 Oxide semiconductor layer 108 Oxide semiconductor layer 109a Low resistance region 109b Low resistance region 110 Silicon layer 111 Silicon layer 112 Silicon Layer 114 Conductive film 115a Metal oxide layer 115b Metal oxide layer 116a Source electrode layer 116b Drain electrode layer 119 Protective Insulation Layer 120 transistors 121 Transistor 122 transistors 123 Transistor 124 transistors 130 transistors 140 transistors 141 transistors 142 transistors 150 transistors 151 transistors 152 transistors 160 transistors 171 Resist mask 172 Resist mask 175 Resist Mask 176 Resist Mask 308 Capacitance wiring 310 Transparent conductive layer 313 Contact Hole 320 connecting electrode 321 First Terminal 322 Second Terminal 325 Contact Hole 326 Contact Hole 327 Contact Hole 328 Transparent conductive layer 329 Transparent conductive layer 340 Protective Insulation Layer 580 board 581 Thin-film transistor 583 Insulating Layer 587 First electrode layer 588 Second electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 PCB 4001 First substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Second board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4501 First board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 Second board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Second electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 First electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 590a black area 590b White area 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

[Claim 1] a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer and overlapping the gate electrode; a silicon layer provided on and in contact with a surface of the oxide semiconductor layer; a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer, the silicon layer is provided in contact with a portion of a surface of the oxide semiconductor layer, the source electrode layer and the drain electrode layer are provided in contact with a surface of the oxide semiconductor layer on which the silicon layer is not provided, a first low-resistance region functioning as a source region is provided in a region of the oxide semiconductor layer that is in contact with the source electrode layer; a second low-resistance region functioning as a drain region in a region of the oxide semiconductor layer that is in contact with the drain electrode layer;

Images