Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide technology capable of enhancing the insulation reliability of a semiconductor device.SOLUTION: A semiconductor device comprises an impurity region of a first conductivity type formed on a well region, an electrode formed on the inner insulating film of a trench extending from the upper surface of the impurity region through the well region to a drift layer, and an interlayer insulating film provided on the electrode, and the end portion of the insulating film, which faces the impurity region, and the end portion of the electrode, which faces the impurity region, are lower than the upper surface of the impurity region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In recent years, a technology has been proposed to suppress a decrease in the breakdown voltage of a semiconductor device by making the depth of the trench in the termination structure the same as the depth of the trench in the active region, thereby aligning the depth of the depletion layer in the drift layer (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-165364 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional technology, etching conditions for forming trenches can sometimes cause the condition of the gate insulating film above the trench to deteriorate, and operating the semiconductor device in such a case can cause the gate insulating film above the trench to deteriorate, reducing the insulation reliability of the semiconductor device.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that can improve the insulation reliability of a semiconductor device. [Means for solving the problem]

[0006] A first semiconductor device according to the present disclosure includes a drift layer of a first conductivity type, a well region of a second conductivity type provided on the drift layer, an impurity region of the first conductivity type provided on the well region, an electrode provided on an insulating film inside a gate trench that extends from an upper surface of the impurity region through the well region to the drift layer, and an interlayer insulating film provided on the electrode, wherein an insulating film end portion, which is an end portion of the insulating film inside the gate trench that faces the impurity region, and an electrode end portion, which is an end portion of the electrode inside the gate trench that faces the impurity region, are lower than the upper surface of the impurity region, and the gate trench provided in the active region is provided in a termination region and is directly connected to an external trench that does not have a periodic structure in a plan view.

[0007] a gate trench provided in the active region and directly connected to an external trench that does not have a periodic structure in a plan view; an insulating film provided on the gate trench, the insulating film being an end portion of the insulating film inside the gate trench that faces the impurity region and an electrode end portion of the electrode inside the gate trench that faces the impurity region; and an interlayer insulating film provided on the electrode. [Effects of the Invention]

[0008] According to the present disclosure, the insulating film edge and the electrode edge are lower than the top surface of the impurity region, and this configuration can improve the insulation reliability of the semiconductor device.

[0009] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 3] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 4] 3 is a flowchart showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 5] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first modification of the first embodiment. [Figure 6] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a first modification of the first embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a second modification of the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a second modification of the first embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a first modification of the third embodiment. [Figure 12] FIG. 10 is a plan view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a first modification of the fourth embodiment. [Figure 15] FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device according to a first modification of the fourth embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In the following description, specific positions and directions, such as "top," "bottom," "left," "right," "front," or "back," may not necessarily correspond to the positions and directions in actual implementation. A higher concentration in one portion may mean, for example, that the average concentration in one portion is higher than the average concentration in another portion. Conversely, a lower concentration in one portion may mean, for example, that the average concentration in one portion is lower than the average concentration in another portion. In the following description, the first conductivity type is n-type and the second conductivity type is p-type; however, the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0012] <First Embodiment> Fig. 1 is a plan view showing the configuration of a semiconductor device according to the first embodiment, and Fig. 2 is a cross-sectional view showing the configuration of the semiconductor device taken along lines AA and BB in Fig. 1. In the following, a case will be described in which the semiconductor device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it may also be an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting - IGBT).

[0013] As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor substrate 1, a gate insulating film 7 which is an insulating film, a gate electrode 8 which is an electrode, an interlayer insulating film 9, a drain electrode 14, and a source electrode 15.

[0014] The semiconductor substrate 1 includes at least one of a normal semiconductor wafer and an epitaxially grown layer. In this specification, for example, "at least one of A, B, C, ..., and Z" means any one of all combinations of one or more types selected from the group A, B, C, ..., and Z.

[0015] The semiconductor substrate 1 may be made of ordinary silicon (Si), or may be made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), diamond, etc. When the semiconductor substrate 1 is made of a wide bandgap semiconductor, stable operation of the semiconductor device under high temperatures and high voltages and high switching speed can be achieved.

[0016] An active region 51 and a termination region 52 are defined in the semiconductor substrate 1. The active region 51 according to the first embodiment is essentially a region through which a current flows between the source and drain, i.e., a main current of the semiconductor device. The termination region 52 is a region adjacent to the active region 51, and is provided with termination structures such as a junction termination extension (JTE), a guard ring (GR), and a field limiting ring (FLR), not shown, on the right side of the dotted line in FIG.

[0017] 1, the n-type drift layer 2, the p-type well region 3, the n-type source region 4 which is an impurity region, the p-type electric field relaxation region 11, and the p-type high concentration region 12. Note that the contact region 5, the electric field relaxation region 11, and the high concentration region 12 are not essential.

[0018] The well region 3 is provided on the drift layer 2, and the source region 4 is provided on the well region 3. The contact region 5 in FIG. 1 is provided on the well region 3, similar to the source region 4, and realizes ohmic contact with the source electrode 15.

[0019] 2, a trench is provided that extends from the upper surface of the source region 4, passing through the well region 3, and reaching the drift layer 2. In the first embodiment, the trench includes a gate trench 6 provided in the active region 51 and an external trench 13 provided in the termination region 52. In the following description, when there is no need to distinguish between the gate trench 6 and the external trench 13, they may be simply referred to as a "trench."

[0020] It is preferable that the depth of the gate trench 6 and the depth of the external trench 13 are the same or substantially the same. With this configuration, the depth of the depletion layer in the drift layer 2 can be made uniform, thereby suppressing a decrease in the breakdown voltage of the semiconductor device due to electric field concentration at the outer periphery of the active region 51.

[0021] A gate electrode 8 is provided on the gate insulating film 7 inside each of the gate trench 6 and the external trench 13. The gate electrode 8 is made of, for example, a polysilicon film, and is electrically connected to a gate pad, which is an external gate electrode (not shown). When a gate voltage equal to or higher than the threshold voltage is applied from the outside to the gate electrode 8 via the gate pad, a channel through which a main current can pass is formed in a portion of the well region 3 close to the gate electrode 8.

[0022] 1 , in the first embodiment, the external trench 13 is connected to the gate trench 6, and the gate electrode 8 of the external trench 13 is connected to the gate electrode 8 of the gate trench 6. Therefore, the gate electrode 8 of the external trench 13 has the function of forming a channel, similar to the gate electrode 8 of the gate trench 6. However, as in a first modified example of the fourth embodiment described later, the external trench 13 may be separated from the gate trench 6, and the gate electrode 8 of the external trench 13 may not have the function of forming a channel.

[0023] 2, an insulating film end 7a, which is an end of the gate insulating film 7 facing the source region 4, and an electrode end 8a, which is an end of the gate electrode 8 facing the source region 4, are lower than the upper surface 4a of the source region 4. The insulating film end 7a directly faces the source region 4, and the electrode end 8a indirectly faces the source region 4.

[0024] The electric field relaxation region 11 is a region for relaxing the electric field strength applied to the gate insulating film 7, and is provided below the gate trench 6 and the external trench 13. Note that a termination structure such as a JTE is provided in the termination region 52, continuing to the electric field relaxation region 11.

[0025] 3, a p-type high concentration region 18 may be provided at a deep position in the mesa portion between the gate trenches 6 to relieve the electric field at the bottom of the gate trench 6. The impurity concentration of the p-type high concentration region 18 may be equal to or higher than the impurity concentration of the p-type well region 3.

[0026] 2 is provided between external trench 13 and electric field relaxation region 11. High concentration region 12 is a region for reducing sheet resistance, and the p-type impurity concentration of high concentration region 12 is higher than the p-type impurity concentration of electric field relaxation region 11. Note that electric field relaxation region 11 may be in contact with external trench 13 without providing high concentration region 12.

[0027] The interlayer insulating film 9 is provided on the gate electrode 8. The interlayer insulating film 9 may be made up of one insulating layer, or may be made up of multiple insulating layers made of different materials.

[0028] 2, the interlayer insulating film 9 provided on the gate electrode 8 of the gate trench 6 is provided only inside the gate trench 6, and is provided at a position lower than the upper surface 4a of the source region 4. On the other hand, the interlayer insulating film 9 provided on the gate electrode 8 of the external trench 13 is provided across the inside and outside of the external trench 13, and a part of the interlayer insulating film 9 is provided at a position higher than the upper surface 4a of the source region 4.

[0029] The source electrode 15 is provided on the source region 4 of the active region 51 and the interlayer insulating film 9 , and the drain electrode 14 is provided on the lower surface of the drift layer 2 .

[0030] <Manufacturing process> 4 is a flowchart showing the manufacturing process of the semiconductor device according to the present embodiment 1. The following mainly describes the main components of the semiconductor device according to the present embodiment 1.

[0031] In step S1, a semiconductor substrate 1 including a drift layer 2, a well region 3, and a source region 4 is formed by, for example, photolithography and ion implantation. In step S2, a gate trench 6 and an external trench 13 are formed on the upper surface of the semiconductor substrate 1 by, for example, photolithography and etching. In step S3, a gate insulating film 7 is formed inside the gate trench 6 and the external trench 13 by, for example, thermal oxidation.

[0032] In step S4, a polysilicon film, which is a conductive film, is formed, and then, for example, photolithography and etching back of the polysilicon film are performed to form a gate electrode 8 having an electrode end 8a lower than the upper surface 4a of the source region 4. In step S5, for example, wet etching is performed on a portion of the gate insulating film 7 to make the insulating film end 7a lower than the upper surface 4a of the source region 4. In step S6, an interlayer insulating film 9 is formed on the gate electrode 8. The interlayer insulating film 9 may be formed by, for example, CVD (Chemical Vapor Deposition), photolithography, and dry etching, or by other methods.

[0033] <Summary of the First Embodiment> In semiconductor devices of the prior art, a gate insulating film is formed on the upper part of the trench (e.g., the portion between the upper end of the trench and a position approximately 100 nm in depth from the upper end of the trench). In this configuration, depending on the etching conditions used to form the trench, unevenness may be formed on the gate insulating film due to the formation of unevenness on the upper part of the trench, which may deteriorate the condition of the gate insulating film. In such a case, when the semiconductor device is operated, an electric field may concentrate around the corner 4c between the upper surface 4a and the side surface 4b of the source region 4, i.e., around the upper part of the trench, degrading the gate insulating film at the upper part of the trench and reducing the insulating reliability of the semiconductor device. In particular, the external trench 13 does not have a periodic structure in plan view like the gate trench 6, and the electric field distribution at the upper part of the trench is likely to differ from that of the gate trench 6, making it more likely for the electric field to concentrate at the upper part of the trench. Therefore, in the external trench 13, the gate insulating film is likely to deteriorate as described above, reducing the insulating reliability of the semiconductor device.

[0034] In contrast to this, in the present embodiment 1, the electrode end 8a of the gate electrode 8 is lower than the upper surface 4a of the source region 4. With such a configuration, the application of a voltage to the upper part of the trench is suppressed, and therefore the insulation reliability of the semiconductor device can be improved.

[0035] In addition, in the first embodiment, the insulating film end portion 7a of the gate insulating film 7 is also lower than the upper surface 4a of the source region 4. With this configuration, the corner portion 4c of the source region 4 is not in contact with the gate insulating film 7, which is relatively thin and has low insulating reliability, but is in contact with the interlayer insulating film 9, which is relatively thick and has high insulating reliability, thereby improving the insulating reliability of the semiconductor device. Furthermore, by replacing the portion where the gate insulating film of the conventional technology was provided with the interlayer insulating film 9, the interlayer insulating film 9 can be made thicker, thereby improving the insulating reliability of the semiconductor device.

[0036] Furthermore, in the first embodiment, the interlayer insulating film 9 provided on the gate electrode 8 of the external trench 13 is provided across the inside and outside of the external trench 13. With this configuration, not only the side but also the top of the corner 4c of the source region 4 on the external trench 13 side is covered with the interlayer insulating film 9, thereby improving the insulation reliability of the semiconductor device.

[0037] In particular, when semiconductor substrate 1 is made of silicon carbide and corners 4c of source region 4 require high dielectric breakdown field strength, it is effective to improve the insulation reliability of the semiconductor device.

[0038] <First Modification of First Embodiment> 5 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 1. In Modification 1, the gate electrodes 8 of the gate trench 6 and the external trench 13 each include a protruding portion 8b. The protruding portion 8b is provided in a portion other than the electrode end portion 8a and is higher than the upper surface 4a of the source region 4.

[0039] 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to Modification 1, specifically, the process of forming the gate electrode 8 (i.e., the process of step S4 in FIG. 4). The manufacturing process of the gate electrode 8 of the external trench 13 will be described below, but the manufacturing process of the gate electrode 8 of the gate trench 6 is also the same as the following description.

[0040] 6, a polysilicon film 81 is formed facing the source region 4 and having a portion higher than the upper surface 4a of the source region 4. Next, a resist 61 is formed on the polysilicon film 81, exposing a facing portion 81a of the polysilicon film 81 facing the source region 4. Then, the exposed facing portion 81a is removed to form a gate electrode 8 including a protrusion 8b.

[0041] When forming gate electrode 8 from polysilicon film 81, depending on the accuracy of photolithography, the opening in resist 61 exposing opposing portion 81a may be misaligned, resulting in the opposing portion 81a of the end of polysilicon film 81 facing source region 4 being exposed, as shown in FIG. 6. Even with gate electrode 8 including protrusion 8b formed in such a case, the effect of embodiment 1 can be obtained to some extent, as with gate electrode 8 not including protrusion 8b. According to this first modification, the degree of freedom in the shape of gate electrode 8 can be increased.

[0042] <Second Modification of First Embodiment> 7 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 2. In Modification 2, insulating film end 7a is higher than electrode end 8a. This configuration can be formed by, without performing step S5 of FIG. 4, depositing interlayer insulating film 9 and performing photolithography in step S6, and then performing dry etching to pattern interlayer insulating film 9 while removing a portion of gate insulating film 7. With this configuration, dry etching can be performed on a portion of gate insulating film 7, making it easier to control the amount of etching.

[0043] 7, the insulating film end 7a is higher than the electrode end 8a in the gate trench 6, but the insulating film end 7a may also be higher than the electrode end 8a in the external trench 13. As shown in Fig. 8, the interlayer insulating film 9 may include a first interlayer insulating film 9a having the same height as the insulating film end 7a, and a second interlayer insulating film 9b provided on the insulating film end 7a and the first interlayer insulating film 9a.

[0044] <Embodiment 2> 9 is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment. In the first embodiment, as shown in FIG. 2, the interlayer insulating film 9 provided on the gate electrode 8 of the gate trench 6 is provided only inside the gate trench 6. In contrast, in the second embodiment, the interlayer insulating film 9 provided on the gate electrode 8 of the gate trench 6 is provided across the inside and outside of the gate trench 6, and is also provided on the source region 4.

[0045] According to the semiconductor device of the second embodiment, it is not necessary to fill the interlayer insulating film 9 in the gate trench 6 with good control, which simplifies the manufacturing process of the semiconductor device. In FIG. 9, the interlayer insulating film 9 includes a first interlayer insulating film 9a provided on the insulating film end portion 7a and the gate electrode 8, and a second interlayer insulating film 9b provided on the first interlayer insulating film 9a, but it may be made up of one layer or three or more layers.

[0046] <Third Embodiment> 10 is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment. In the third embodiment, a gate wiring electrode 10a is provided on the external trench 13 side. The gate wiring electrode 10a is provided on an interlayer insulating film 9 provided on the gate electrode 8 in the external trench 13, and similar to the interlayer insulating film 9, the gate wiring electrode 10a is provided across the inside and outside of the external trench 13. The interlayer insulating film 9 has a contact hole that exposes the gate electrode 8 in the external trench 13, and the gate wiring electrode 10a is connected to the gate electrode 8 in the external trench 13 that is exposed from the interlayer insulating film 9.

[0047] When the gate electrode 8 of the gate trench 6 and the gate electrode 8 of the external trench 13 are formed simultaneously by etching, the external trench 13 generally has a larger resist opening area during etching than the gate trench 6. For this reason, the gate electrode 8 of the external trench 13 is etched faster and becomes thinner than the gate electrode 8 of the gate trench 6, and as a result, the gate wiring resistance is likely to decrease. In contrast, in the third embodiment, the gate wiring electrode 10a is provided, so that the decrease in gate wiring resistance can be suppressed even if the thickness of the gate electrode 8 becomes thinner.

[0048] <First Modification of Third Embodiment> 11 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 1. The configuration of Modification 1 is similar to that of Modification 1 of Embodiment 1, in which the gate wiring electrode 10a described in Embodiment 3 is added. With this configuration, it is possible to increase the degree of freedom in the shape of the gate electrode 8 while suppressing a decrease in the gate wiring resistance.

[0049] <Fourth Embodiment> Fig. 12 is a plan view showing the configuration of a semiconductor device according to the fourth embodiment, and Fig. 13 is a cross-sectional view showing the configuration of the semiconductor device taken along line CC in Fig. 12. In the fourth embodiment, a gate wiring electrode 10b is provided on the gate trench 6 side. As shown in Fig. 13, the gate wiring electrode 10b is provided on an interlayer insulating film 9 provided on a gate electrode 8 in the gate trench 6. The interlayer insulating film 9 has a contact hole that exposes the gate electrode 8 in the gate trench 6, and the gate wiring electrode 10b is connected to the gate electrode 8 in the gate trench 6 that is exposed from the interlayer insulating film 9.

[0050] 12, the external trench 13 is not connected to the gate trench 6 in a plan view, and they are separated from each other. Although not shown, in the fourth embodiment, the gate wiring electrode 10b is electrically connected to the gate pad, and is also electrically connected to the gate electrode 8 of the external trench 13 via a trench other than the external trench 13. According to this configuration, as in the first embodiment, the gate electrode 8 of the external trench 13 has the function of forming a channel, and therefore the degree of freedom in design layout of the trench can be increased.

[0051] <First Modification of Fourth Embodiment> The gate electrode 8 of the external trench 13 does not have to be electrically connected to the gate wiring electrode 10b. For example, the gate electrode 8 of the external trench 13 may have a floating potential without being electrically connected to the gate pad and the gate wiring electrode 10b, or only the gate wiring electrode 10b of the gate trench 6 may be electrically connected to the gate pad. Furthermore, when the gate electrode 8 of the external trench 13 is a floating electrode, the gate electrode 8 of the external trench 13 may be formed only on the side surface of the external trench 13, as shown in FIGS. 14 and 15 .

[0052] <Fifth Embodiment> 16 is a cross-sectional view showing the configuration of a semiconductor device according to the fifth embodiment. In the fifth embodiment, in a cross-sectional view, a recess 4d is provided between the upper surface 4a and the side surface 4b of the source region 4, which is each of the side surfaces of the gate trench 6 and the external trench 13. The interlayer insulating film 9 covers at least a part of the recess 4d.

[0053] In the fifth embodiment, the angle θ between an extension of the top surface 4a of the source region 4 and the upper inner wall of the recess 4d is equal to or greater than 1° and less than 90°. The insulating film end 7a and the electrode end 8a are lower than the recess 4d. The recess 4d may have a curved shape or a tapered shape. The recess 4d may be provided as a secondary step during etching to form a trench.

[0054] In the semiconductor device according to the fifth embodiment, the recess 4d is provided between the side surface 4b and the upper surface 4a of the source region 4, and therefore, electric field concentration in the portion between the side surface 4b and the upper surface 4a of the source region 4 can be suppressed. Furthermore, when the recess 4d includes a plurality of irregularities over a part or the entirety thereof, forming the gate insulating film 7 on the recess 4d tends to result in the formation of irregularities in the gate insulating film 7. However, in the fifth embodiment, the interlayer insulating film 9 covers at least a part of the recess 4d, and therefore, the influence of the electric field concentration on the gate insulating film 7 can be suppressed, and the insulation reliability of the semiconductor device can be improved.

[0055] In the fifth embodiment, the configuration in which the recess 4d is provided in the first embodiment has been described, but the present invention is not limited to this. For example, the recess 4d may be provided in a configuration in which the interlayer insulating film 9 provided on the gate electrode 8 of the external trench 13 does not straddle both the inside and outside of the external trench 13. Furthermore, the recess 4d may be provided in the second to fifth embodiments and their modifications, regardless of whether the interlayer insulating film 9 provided on the gate electrode 8 of the external trench 13 straddles both the inside and outside of the external trench 13.

[0056] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0057] The above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned. [Explanation of symbols]

[0058] 1 semiconductor substrate, 2 drift layer, 3 well region, 4 source region, 4a upper surface, 4b side surface, 4c corner portion, 4d recess portion, 6 gate trench, 7 gate insulating film, 7a insulating film edge portion, 8 gate electrode, 8a electrode edge portion, 8b protrusion portion, 9 interlayer insulating film, 10a, 10b gate wiring electrode, 13 external trench, 51 active region, 52 termination region, 61 resist, 81 polysilicon film, 81a opposing portion, θ angle.

Claims

1. a drift layer of a first conductivity type; a second conductivity type well region provided on the drift layer; an impurity region of the first conductivity type provided on the well region; an electrode provided on an insulating film inside a gate trench that extends from an upper surface of the impurity region through the well region to the drift layer; an interlayer insulating film provided on the electrode; Equipped with an insulating film end portion, which is an end portion of the insulating film inside the gate trench facing the impurity region, and an electrode end portion, which is an end portion of the electrode inside the gate trench facing the impurity region, are lower than the top surface of the impurity region; The semiconductor device, wherein the gate trench provided in the active region is directly connected to an external trench provided in the termination region and not having a periodic structure in plan view.

2. 2. The semiconductor device according to claim 1, an electrode provided on the insulating film inside the external trench and electrically connected to the electrode provided on the insulating film inside the gate trench includes a portion that is higher than the top surface of the impurity region.

3. 3. The semiconductor device according to claim 1, the interlayer insulating film provided on the electrode of the external trench is provided across the inside and outside of the external trench.

4. 2. The semiconductor device according to claim 1, the interlayer insulating film provided on the electrode of the external trench is also provided on the impurity region.

5. 3. The semiconductor device according to claim 1, a gate wiring electrode provided on the interlayer insulating film provided on the electrode in the external trench, the gate wiring electrode being provided across the inside and outside of the external trench; the gate wiring electrode is connected to the electrode of the external trench exposed from the interlayer insulating film.

6. 2. The semiconductor device according to claim 1, a gate wiring electrode provided on the interlayer insulating film provided on the electrode in the gate trench; the gate wiring electrode is connected to the electrode of the gate trench exposed from the interlayer insulating film.

7. 2. The semiconductor device according to claim 1, an end of the interlayer insulating film provided on the electrode of the gate trench, the end facing the impurity region, is lower than the top surface of the impurity region.

8. 2. The semiconductor device according to claim 1, a portion of an end of the interlayer insulating film provided on the electrode of the gate trench, the end facing the impurity region, includes a portion higher than the top surface of the impurity region.

9. 10. The semiconductor device according to claim 1, The interlayer insulating film of the semiconductor device is made up of a plurality of layers.

10. a drift layer of a first conductivity type; a second conductivity type well region provided on the drift layer; an impurity region of the first conductivity type provided on the well region; an electrode provided on an insulating film inside a gate trench that extends from an upper surface of the impurity region through the well region to the drift layer; an interlayer insulating film provided on the electrode; Equipped with an insulating film end portion, which is an end portion of the insulating film inside the gate trench facing the impurity region, and an electrode end portion, which is an end portion of the electrode inside the gate trench facing the impurity region, are lower than the top surface of the impurity region; a recess is provided between a side surface of the gate trench and the upper surface of the impurity region in a cross-sectional view; The semiconductor device, wherein the gate trench provided in the active region is directly connected to an external trench provided in the termination region and not having a periodic structure in plan view.

11. 11. The semiconductor device according to claim 10, The semiconductor device, wherein the insulating film edge and the electrode edge are lower than the recess.

12. 11. The semiconductor device according to claim 10, The interlayer insulating film covers at least a part of the recess.

13. 11. The semiconductor device according to claim 10, an angle θ formed between an extension of the top surface of the impurity region and an upper inner wall of the recess is equal to or greater than 1° and less than 90°.

14. 11. The semiconductor device according to claim 10, The recess has a curved or tapered shape.

15. 11. The semiconductor device according to claim 10, an electrode provided on the insulating film inside the external trench and electrically connected to the electrode provided on the insulating film inside the gate trench includes a portion that is higher than the top surface of the impurity region.

16. 12. The semiconductor device according to claim 10, the interlayer insulating film provided on the electrode of the external trench is provided across the inside and outside of the external trench.

17. 11. The semiconductor device according to claim 10, the interlayer insulating film provided on the electrode of the external trench is also provided on the impurity region.

18. 12. The semiconductor device according to claim 10, a gate wiring electrode provided on the interlayer insulating film provided on the electrode in the external trench, the gate wiring electrode being provided across the inside and outside of the external trench; the gate wiring electrode is connected to the electrode of the external trench exposed from the interlayer insulating film.

19. 11. The semiconductor device according to claim 10, a gate wiring electrode provided on the interlayer insulating film provided on the electrode in the gate trench; the gate wiring electrode is connected to the electrode of the gate trench exposed from the interlayer insulating film.

20. forming a semiconductor substrate including a drift layer of a first conductivity type, a well region of a second conductivity type provided on the drift layer, and an impurity region of the first conductivity type provided on the well region; forming an electrode on an insulating film inside a gate trench that extends from an upper surface of the impurity region through the well region to the drift layer; forming an interlayer insulating film on the electrode; an insulating film end portion, which is an end portion of the insulating film inside the gate trench facing the impurity region, and an electrode end portion, which is an end portion of the electrode inside the gate trench facing the impurity region, are lower than the top surface of the impurity region; The method for manufacturing a semiconductor device, wherein the gate trench provided in the active region is directly connected to an external trench provided in the termination region and not having a periodic structure in plan view.

21. forming a semiconductor substrate including a drift layer of a first conductivity type, a well region of a second conductivity type provided on the drift layer, and an impurity region of the first conductivity type provided on the well region; forming an electrode on an insulating film inside a gate trench that extends from an upper surface of the impurity region through the well region to the drift layer; forming an interlayer insulating film on the electrode; an insulating film end portion, which is an end portion of the insulating film inside the gate trench facing the impurity region, and an electrode end portion, which is an end portion of the electrode inside the gate trench facing the impurity region, are lower than the top surface of the impurity region; a recess is provided between a side surface of the gate trench and the upper surface of the impurity region in a cross-sectional view; The method for manufacturing a semiconductor device, wherein the gate trench provided in the active region is directly connected to an external trench provided in the termination region and not having a periodic structure in plan view.

Images